linux/drivers/net/ethernet/intel/e1000/e1000_hw.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 1999 - 2006 Intel Corporation. */
   3
   4/* e1000_hw.h
   5 * Structures, enums, and macros for the MAC
   6 */
   7
   8#ifndef _E1000_HW_H_
   9#define _E1000_HW_H_
  10
  11#include "e1000_osdep.h"
  12
  13
  14/* Forward declarations of structures used by the shared code */
  15struct e1000_hw;
  16struct e1000_hw_stats;
  17
  18/* Enumerated types specific to the e1000 hardware */
  19/* Media Access Controllers */
  20typedef enum {
  21        e1000_undefined = 0,
  22        e1000_82542_rev2_0,
  23        e1000_82542_rev2_1,
  24        e1000_82543,
  25        e1000_82544,
  26        e1000_82540,
  27        e1000_82545,
  28        e1000_82545_rev_3,
  29        e1000_82546,
  30        e1000_ce4100,
  31        e1000_82546_rev_3,
  32        e1000_82541,
  33        e1000_82541_rev_2,
  34        e1000_82547,
  35        e1000_82547_rev_2,
  36        e1000_num_macs
  37} e1000_mac_type;
  38
  39typedef enum {
  40        e1000_eeprom_uninitialized = 0,
  41        e1000_eeprom_spi,
  42        e1000_eeprom_microwire,
  43        e1000_eeprom_flash,
  44        e1000_eeprom_none,      /* No NVM support */
  45        e1000_num_eeprom_types
  46} e1000_eeprom_type;
  47
  48/* Media Types */
  49typedef enum {
  50        e1000_media_type_copper = 0,
  51        e1000_media_type_fiber = 1,
  52        e1000_media_type_internal_serdes = 2,
  53        e1000_num_media_types
  54} e1000_media_type;
  55
  56typedef enum {
  57        e1000_10_half = 0,
  58        e1000_10_full = 1,
  59        e1000_100_half = 2,
  60        e1000_100_full = 3
  61} e1000_speed_duplex_type;
  62
  63/* Flow Control Settings */
  64typedef enum {
  65        E1000_FC_NONE = 0,
  66        E1000_FC_RX_PAUSE = 1,
  67        E1000_FC_TX_PAUSE = 2,
  68        E1000_FC_FULL = 3,
  69        E1000_FC_DEFAULT = 0xFF
  70} e1000_fc_type;
  71
  72struct e1000_shadow_ram {
  73        u16 eeprom_word;
  74        bool modified;
  75};
  76
  77/* PCI bus types */
  78typedef enum {
  79        e1000_bus_type_unknown = 0,
  80        e1000_bus_type_pci,
  81        e1000_bus_type_pcix,
  82        e1000_bus_type_reserved
  83} e1000_bus_type;
  84
  85/* PCI bus speeds */
  86typedef enum {
  87        e1000_bus_speed_unknown = 0,
  88        e1000_bus_speed_33,
  89        e1000_bus_speed_66,
  90        e1000_bus_speed_100,
  91        e1000_bus_speed_120,
  92        e1000_bus_speed_133,
  93        e1000_bus_speed_reserved
  94} e1000_bus_speed;
  95
  96/* PCI bus widths */
  97typedef enum {
  98        e1000_bus_width_unknown = 0,
  99        e1000_bus_width_32,
 100        e1000_bus_width_64,
 101        e1000_bus_width_reserved
 102} e1000_bus_width;
 103
 104/* PHY status info structure and supporting enums */
 105typedef enum {
 106        e1000_cable_length_50 = 0,
 107        e1000_cable_length_50_80,
 108        e1000_cable_length_80_110,
 109        e1000_cable_length_110_140,
 110        e1000_cable_length_140,
 111        e1000_cable_length_undefined = 0xFF
 112} e1000_cable_length;
 113
 114typedef enum {
 115        e1000_gg_cable_length_60 = 0,
 116        e1000_gg_cable_length_60_115 = 1,
 117        e1000_gg_cable_length_115_150 = 2,
 118        e1000_gg_cable_length_150 = 4
 119} e1000_gg_cable_length;
 120
 121typedef enum {
 122        e1000_igp_cable_length_10 = 10,
 123        e1000_igp_cable_length_20 = 20,
 124        e1000_igp_cable_length_30 = 30,
 125        e1000_igp_cable_length_40 = 40,
 126        e1000_igp_cable_length_50 = 50,
 127        e1000_igp_cable_length_60 = 60,
 128        e1000_igp_cable_length_70 = 70,
 129        e1000_igp_cable_length_80 = 80,
 130        e1000_igp_cable_length_90 = 90,
 131        e1000_igp_cable_length_100 = 100,
 132        e1000_igp_cable_length_110 = 110,
 133        e1000_igp_cable_length_115 = 115,
 134        e1000_igp_cable_length_120 = 120,
 135        e1000_igp_cable_length_130 = 130,
 136        e1000_igp_cable_length_140 = 140,
 137        e1000_igp_cable_length_150 = 150,
 138        e1000_igp_cable_length_160 = 160,
 139        e1000_igp_cable_length_170 = 170,
 140        e1000_igp_cable_length_180 = 180
 141} e1000_igp_cable_length;
 142
 143typedef enum {
 144        e1000_10bt_ext_dist_enable_normal = 0,
 145        e1000_10bt_ext_dist_enable_lower,
 146        e1000_10bt_ext_dist_enable_undefined = 0xFF
 147} e1000_10bt_ext_dist_enable;
 148
 149typedef enum {
 150        e1000_rev_polarity_normal = 0,
 151        e1000_rev_polarity_reversed,
 152        e1000_rev_polarity_undefined = 0xFF
 153} e1000_rev_polarity;
 154
 155typedef enum {
 156        e1000_downshift_normal = 0,
 157        e1000_downshift_activated,
 158        e1000_downshift_undefined = 0xFF
 159} e1000_downshift;
 160
 161typedef enum {
 162        e1000_smart_speed_default = 0,
 163        e1000_smart_speed_on,
 164        e1000_smart_speed_off
 165} e1000_smart_speed;
 166
 167typedef enum {
 168        e1000_polarity_reversal_enabled = 0,
 169        e1000_polarity_reversal_disabled,
 170        e1000_polarity_reversal_undefined = 0xFF
 171} e1000_polarity_reversal;
 172
 173typedef enum {
 174        e1000_auto_x_mode_manual_mdi = 0,
 175        e1000_auto_x_mode_manual_mdix,
 176        e1000_auto_x_mode_auto1,
 177        e1000_auto_x_mode_auto2,
 178        e1000_auto_x_mode_undefined = 0xFF
 179} e1000_auto_x_mode;
 180
 181typedef enum {
 182        e1000_1000t_rx_status_not_ok = 0,
 183        e1000_1000t_rx_status_ok,
 184        e1000_1000t_rx_status_undefined = 0xFF
 185} e1000_1000t_rx_status;
 186
 187typedef enum {
 188        e1000_phy_m88 = 0,
 189        e1000_phy_igp,
 190        e1000_phy_8211,
 191        e1000_phy_8201,
 192        e1000_phy_undefined = 0xFF
 193} e1000_phy_type;
 194
 195typedef enum {
 196        e1000_ms_hw_default = 0,
 197        e1000_ms_force_master,
 198        e1000_ms_force_slave,
 199        e1000_ms_auto
 200} e1000_ms_type;
 201
 202typedef enum {
 203        e1000_ffe_config_enabled = 0,
 204        e1000_ffe_config_active,
 205        e1000_ffe_config_blocked
 206} e1000_ffe_config;
 207
 208typedef enum {
 209        e1000_dsp_config_disabled = 0,
 210        e1000_dsp_config_enabled,
 211        e1000_dsp_config_activated,
 212        e1000_dsp_config_undefined = 0xFF
 213} e1000_dsp_config;
 214
 215struct e1000_phy_info {
 216        e1000_cable_length cable_length;
 217        e1000_10bt_ext_dist_enable extended_10bt_distance;
 218        e1000_rev_polarity cable_polarity;
 219        e1000_downshift downshift;
 220        e1000_polarity_reversal polarity_correction;
 221        e1000_auto_x_mode mdix_mode;
 222        e1000_1000t_rx_status local_rx;
 223        e1000_1000t_rx_status remote_rx;
 224};
 225
 226struct e1000_phy_stats {
 227        u32 idle_errors;
 228        u32 receive_errors;
 229};
 230
 231struct e1000_eeprom_info {
 232        e1000_eeprom_type type;
 233        u16 word_size;
 234        u16 opcode_bits;
 235        u16 address_bits;
 236        u16 delay_usec;
 237        u16 page_size;
 238};
 239
 240/* Flex ASF Information */
 241#define E1000_HOST_IF_MAX_SIZE  2048
 242
 243typedef enum {
 244        e1000_byte_align = 0,
 245        e1000_word_align = 1,
 246        e1000_dword_align = 2
 247} e1000_align_type;
 248
 249/* Error Codes */
 250#define E1000_SUCCESS      0
 251#define E1000_ERR_EEPROM   1
 252#define E1000_ERR_PHY      2
 253#define E1000_ERR_CONFIG   3
 254#define E1000_ERR_PARAM    4
 255#define E1000_ERR_MAC_TYPE 5
 256#define E1000_ERR_PHY_TYPE 6
 257#define E1000_ERR_RESET   9
 258#define E1000_ERR_MASTER_REQUESTS_PENDING 10
 259#define E1000_ERR_HOST_INTERFACE_COMMAND 11
 260#define E1000_BLK_PHY_RESET   12
 261
 262#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
 263                                     (((_value) & 0xff00) >> 8))
 264
 265/* Function prototypes */
 266/* Initialization */
 267s32 e1000_reset_hw(struct e1000_hw *hw);
 268s32 e1000_init_hw(struct e1000_hw *hw);
 269s32 e1000_set_mac_type(struct e1000_hw *hw);
 270void e1000_set_media_type(struct e1000_hw *hw);
 271
 272/* Link Configuration */
 273s32 e1000_setup_link(struct e1000_hw *hw);
 274s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
 275void e1000_config_collision_dist(struct e1000_hw *hw);
 276s32 e1000_check_for_link(struct e1000_hw *hw);
 277s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
 278s32 e1000_force_mac_fc(struct e1000_hw *hw);
 279
 280/* PHY */
 281s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
 282s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
 283s32 e1000_phy_hw_reset(struct e1000_hw *hw);
 284s32 e1000_phy_reset(struct e1000_hw *hw);
 285s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
 286s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
 287
 288/* EEPROM Functions */
 289s32 e1000_init_eeprom_params(struct e1000_hw *hw);
 290
 291/* MNG HOST IF functions */
 292u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
 293
 294#define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64
 295#define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8   /* Host Interface data length */
 296
 297#define E1000_MNG_DHCP_COMMAND_TIMEOUT  10      /* Time in ms to process MNG command */
 298#define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0   /* Cookie offset */
 299#define E1000_MNG_DHCP_COOKIE_LENGTH    0x10    /* Cookie length */
 300#define E1000_MNG_IAMT_MODE             0x3
 301#define E1000_MNG_ICH_IAMT_MODE         0x2
 302#define E1000_IAMT_SIGNATURE            0x544D4149      /* Intel(R) Active Management Technology signature */
 303
 304#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1        /* DHCP parsing enabled */
 305#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT    0x2        /* DHCP parsing enabled */
 306#define E1000_VFTA_ENTRY_SHIFT                       0x5
 307#define E1000_VFTA_ENTRY_MASK                        0x7F
 308#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK              0x1F
 309
 310struct e1000_host_mng_command_header {
 311        u8 command_id;
 312        u8 checksum;
 313        u16 reserved1;
 314        u16 reserved2;
 315        u16 command_length;
 316};
 317
 318struct e1000_host_mng_command_info {
 319        struct e1000_host_mng_command_header command_header;    /* Command Head/Command Result Head has 4 bytes */
 320        u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];  /* Command data can length 0..0x658 */
 321};
 322#ifdef __BIG_ENDIAN
 323struct e1000_host_mng_dhcp_cookie {
 324        u32 signature;
 325        u16 vlan_id;
 326        u8 reserved0;
 327        u8 status;
 328        u32 reserved1;
 329        u8 checksum;
 330        u8 reserved3;
 331        u16 reserved2;
 332};
 333#else
 334struct e1000_host_mng_dhcp_cookie {
 335        u32 signature;
 336        u8 status;
 337        u8 reserved0;
 338        u16 vlan_id;
 339        u32 reserved1;
 340        u16 reserved2;
 341        u8 reserved3;
 342        u8 checksum;
 343};
 344#endif
 345
 346bool e1000_check_mng_mode(struct e1000_hw *hw);
 347s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
 348s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
 349s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
 350s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
 351s32 e1000_read_mac_addr(struct e1000_hw *hw);
 352
 353/* Filters (multicast, vlan, receive) */
 354u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
 355void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
 356void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);
 357void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
 358
 359/* LED functions */
 360s32 e1000_setup_led(struct e1000_hw *hw);
 361s32 e1000_cleanup_led(struct e1000_hw *hw);
 362s32 e1000_led_on(struct e1000_hw *hw);
 363s32 e1000_led_off(struct e1000_hw *hw);
 364s32 e1000_blink_led_start(struct e1000_hw *hw);
 365
 366/* Adaptive IFS Functions */
 367
 368/* Everything else */
 369void e1000_reset_adaptive(struct e1000_hw *hw);
 370void e1000_update_adaptive(struct e1000_hw *hw);
 371void e1000_get_bus_info(struct e1000_hw *hw);
 372void e1000_pci_set_mwi(struct e1000_hw *hw);
 373void e1000_pci_clear_mwi(struct e1000_hw *hw);
 374void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
 375int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
 376/* Port I/O is only supported on 82544 and newer */
 377void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
 378
 379#define E1000_READ_REG_IO(a, reg) \
 380    e1000_read_reg_io((a), E1000_##reg)
 381#define E1000_WRITE_REG_IO(a, reg, val) \
 382    e1000_write_reg_io((a), E1000_##reg, val)
 383
 384/* PCI Device IDs */
 385#define E1000_DEV_ID_82542               0x1000
 386#define E1000_DEV_ID_82543GC_FIBER       0x1001
 387#define E1000_DEV_ID_82543GC_COPPER      0x1004
 388#define E1000_DEV_ID_82544EI_COPPER      0x1008
 389#define E1000_DEV_ID_82544EI_FIBER       0x1009
 390#define E1000_DEV_ID_82544GC_COPPER      0x100C
 391#define E1000_DEV_ID_82544GC_LOM         0x100D
 392#define E1000_DEV_ID_82540EM             0x100E
 393#define E1000_DEV_ID_82540EM_LOM         0x1015
 394#define E1000_DEV_ID_82540EP_LOM         0x1016
 395#define E1000_DEV_ID_82540EP             0x1017
 396#define E1000_DEV_ID_82540EP_LP          0x101E
 397#define E1000_DEV_ID_82545EM_COPPER      0x100F
 398#define E1000_DEV_ID_82545EM_FIBER       0x1011
 399#define E1000_DEV_ID_82545GM_COPPER      0x1026
 400#define E1000_DEV_ID_82545GM_FIBER       0x1027
 401#define E1000_DEV_ID_82545GM_SERDES      0x1028
 402#define E1000_DEV_ID_82546EB_COPPER      0x1010
 403#define E1000_DEV_ID_82546EB_FIBER       0x1012
 404#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
 405#define E1000_DEV_ID_82541EI             0x1013
 406#define E1000_DEV_ID_82541EI_MOBILE      0x1018
 407#define E1000_DEV_ID_82541ER_LOM         0x1014
 408#define E1000_DEV_ID_82541ER             0x1078
 409#define E1000_DEV_ID_82547GI             0x1075
 410#define E1000_DEV_ID_82541GI             0x1076
 411#define E1000_DEV_ID_82541GI_MOBILE      0x1077
 412#define E1000_DEV_ID_82541GI_LF          0x107C
 413#define E1000_DEV_ID_82546GB_COPPER      0x1079
 414#define E1000_DEV_ID_82546GB_FIBER       0x107A
 415#define E1000_DEV_ID_82546GB_SERDES      0x107B
 416#define E1000_DEV_ID_82546GB_PCIE        0x108A
 417#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
 418#define E1000_DEV_ID_82547EI             0x1019
 419#define E1000_DEV_ID_82547EI_MOBILE      0x101A
 420#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
 421#define E1000_DEV_ID_INTEL_CE4100_GBE    0x2E6E
 422
 423#define NODE_ADDRESS_SIZE 6
 424
 425/* MAC decode size is 128K - This is the size of BAR0 */
 426#define MAC_DECODE_SIZE (128 * 1024)
 427
 428#define E1000_82542_2_0_REV_ID 2
 429#define E1000_82542_2_1_REV_ID 3
 430#define E1000_REVISION_0       0
 431#define E1000_REVISION_1       1
 432#define E1000_REVISION_2       2
 433#define E1000_REVISION_3       3
 434
 435#define SPEED_10    10
 436#define SPEED_100   100
 437#define SPEED_1000  1000
 438#define HALF_DUPLEX 1
 439#define FULL_DUPLEX 2
 440
 441/* The sizes (in bytes) of a ethernet packet */
 442#define ENET_HEADER_SIZE             14
 443#define MINIMUM_ETHERNET_FRAME_SIZE  64 /* With FCS */
 444#define ETHERNET_FCS_SIZE            4
 445#define MINIMUM_ETHERNET_PACKET_SIZE \
 446    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 447#define CRC_LENGTH                   ETHERNET_FCS_SIZE
 448#define MAX_JUMBO_FRAME_SIZE         0x3F00
 449
 450/* 802.1q VLAN Packet Sizes */
 451#define VLAN_TAG_SIZE  4        /* 802.3ac tag (not DMAed) */
 452
 453/* Ethertype field values */
 454#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 455#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
 456#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
 457
 458/* Packet Header defines */
 459#define IP_PROTOCOL_TCP    6
 460#define IP_PROTOCOL_UDP    0x11
 461
 462/* This defines the bits that are set in the Interrupt Mask
 463 * Set/Read Register.  Each bit is documented below:
 464 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 465 *   o RXSEQ  = Receive Sequence Error
 466 */
 467#define POLL_IMS_ENABLE_MASK ( \
 468    E1000_IMS_RXDMT0 |         \
 469    E1000_IMS_RXSEQ)
 470
 471/* This defines the bits that are set in the Interrupt Mask
 472 * Set/Read Register.  Each bit is documented below:
 473 *   o RXT0   = Receiver Timer Interrupt (ring 0)
 474 *   o TXDW   = Transmit Descriptor Written Back
 475 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 476 *   o RXSEQ  = Receive Sequence Error
 477 *   o LSC    = Link Status Change
 478 */
 479#define IMS_ENABLE_MASK ( \
 480    E1000_IMS_RXT0   |    \
 481    E1000_IMS_TXDW   |    \
 482    E1000_IMS_RXDMT0 |    \
 483    E1000_IMS_RXSEQ  |    \
 484    E1000_IMS_LSC)
 485
 486/* Number of high/low register pairs in the RAR. The RAR (Receive Address
 487 * Registers) holds the directed and multicast addresses that we monitor. We
 488 * reserve one of these spots for our directed address, allowing us room for
 489 * E1000_RAR_ENTRIES - 1 multicast addresses.
 490 */
 491#define E1000_RAR_ENTRIES 15
 492
 493#define MIN_NUMBER_OF_DESCRIPTORS  8
 494#define MAX_NUMBER_OF_DESCRIPTORS  0xFFF8
 495
 496/* Receive Descriptor */
 497struct e1000_rx_desc {
 498        __le64 buffer_addr;     /* Address of the descriptor's data buffer */
 499        __le16 length;          /* Length of data DMAed into data buffer */
 500        __le16 csum;            /* Packet checksum */
 501        u8 status;              /* Descriptor status */
 502        u8 errors;              /* Descriptor Errors */
 503        __le16 special;
 504};
 505
 506/* Receive Descriptor - Extended */
 507union e1000_rx_desc_extended {
 508        struct {
 509                __le64 buffer_addr;
 510                __le64 reserved;
 511        } read;
 512        struct {
 513                struct {
 514                        __le32 mrq;     /* Multiple Rx Queues */
 515                        union {
 516                                __le32 rss;     /* RSS Hash */
 517                                struct {
 518                                        __le16 ip_id;   /* IP id */
 519                                        __le16 csum;    /* Packet Checksum */
 520                                } csum_ip;
 521                        } hi_dword;
 522                } lower;
 523                struct {
 524                        __le32 status_error;    /* ext status/error */
 525                        __le16 length;
 526                        __le16 vlan;    /* VLAN tag */
 527                } upper;
 528        } wb;                   /* writeback */
 529};
 530
 531#define MAX_PS_BUFFERS 4
 532/* Receive Descriptor - Packet Split */
 533union e1000_rx_desc_packet_split {
 534        struct {
 535                /* one buffer for protocol header(s), three data buffers */
 536                __le64 buffer_addr[MAX_PS_BUFFERS];
 537        } read;
 538        struct {
 539                struct {
 540                        __le32 mrq;     /* Multiple Rx Queues */
 541                        union {
 542                                __le32 rss;     /* RSS Hash */
 543                                struct {
 544                                        __le16 ip_id;   /* IP id */
 545                                        __le16 csum;    /* Packet Checksum */
 546                                } csum_ip;
 547                        } hi_dword;
 548                } lower;
 549                struct {
 550                        __le32 status_error;    /* ext status/error */
 551                        __le16 length0; /* length of buffer 0 */
 552                        __le16 vlan;    /* VLAN tag */
 553                } middle;
 554                struct {
 555                        __le16 header_status;
 556                        __le16 length[3];       /* length of buffers 1-3 */
 557                } upper;
 558                __le64 reserved;
 559        } wb;                   /* writeback */
 560};
 561
 562/* Receive Descriptor bit definitions */
 563#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 564#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
 565#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 566#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 567#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
 568#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 569#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
 570#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
 571#define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
 572#define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
 573#define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
 574#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
 575#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
 576#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
 577#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
 578#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
 579#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
 580#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
 581#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
 582#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
 583#define E1000_RXD_SPC_PRI_SHIFT 13
 584#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
 585#define E1000_RXD_SPC_CFI_SHIFT 12
 586
 587#define E1000_RXDEXT_STATERR_CE    0x01000000
 588#define E1000_RXDEXT_STATERR_SE    0x02000000
 589#define E1000_RXDEXT_STATERR_SEQ   0x04000000
 590#define E1000_RXDEXT_STATERR_CXE   0x10000000
 591#define E1000_RXDEXT_STATERR_TCPE  0x20000000
 592#define E1000_RXDEXT_STATERR_IPE   0x40000000
 593#define E1000_RXDEXT_STATERR_RXE   0x80000000
 594
 595#define E1000_RXDPS_HDRSTAT_HDRSP        0x00008000
 596#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK  0x000003FF
 597
 598/* mask to determine if packets should be dropped due to frame errors */
 599#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
 600    E1000_RXD_ERR_CE  |                \
 601    E1000_RXD_ERR_SE  |                \
 602    E1000_RXD_ERR_SEQ |                \
 603    E1000_RXD_ERR_CXE |                \
 604    E1000_RXD_ERR_RXE)
 605
 606/* Same mask, but for extended and packet split descriptors */
 607#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
 608    E1000_RXDEXT_STATERR_CE  |            \
 609    E1000_RXDEXT_STATERR_SE  |            \
 610    E1000_RXDEXT_STATERR_SEQ |            \
 611    E1000_RXDEXT_STATERR_CXE |            \
 612    E1000_RXDEXT_STATERR_RXE)
 613
 614/* Transmit Descriptor */
 615struct e1000_tx_desc {
 616        __le64 buffer_addr;     /* Address of the descriptor's data buffer */
 617        union {
 618                __le32 data;
 619                struct {
 620                        __le16 length;  /* Data buffer length */
 621                        u8 cso; /* Checksum offset */
 622                        u8 cmd; /* Descriptor control */
 623                } flags;
 624        } lower;
 625        union {
 626                __le32 data;
 627                struct {
 628                        u8 status;      /* Descriptor status */
 629                        u8 css; /* Checksum start */
 630                        __le16 special;
 631                } fields;
 632        } upper;
 633};
 634
 635/* Transmit Descriptor bit definitions */
 636#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
 637#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
 638#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 639#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 640#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 641#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 642#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
 643#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 644#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
 645#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 646#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
 647#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
 648#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 649#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
 650#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
 651#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
 652#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
 653#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
 654#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
 655#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
 656
 657/* Offload Context Descriptor */
 658struct e1000_context_desc {
 659        union {
 660                __le32 ip_config;
 661                struct {
 662                        u8 ipcss;       /* IP checksum start */
 663                        u8 ipcso;       /* IP checksum offset */
 664                        __le16 ipcse;   /* IP checksum end */
 665                } ip_fields;
 666        } lower_setup;
 667        union {
 668                __le32 tcp_config;
 669                struct {
 670                        u8 tucss;       /* TCP checksum start */
 671                        u8 tucso;       /* TCP checksum offset */
 672                        __le16 tucse;   /* TCP checksum end */
 673                } tcp_fields;
 674        } upper_setup;
 675        __le32 cmd_and_length;  /* */
 676        union {
 677                __le32 data;
 678                struct {
 679                        u8 status;      /* Descriptor status */
 680                        u8 hdr_len;     /* Header length */
 681                        __le16 mss;     /* Maximum segment size */
 682                } fields;
 683        } tcp_seg_setup;
 684};
 685
 686/* Offload data descriptor */
 687struct e1000_data_desc {
 688        __le64 buffer_addr;     /* Address of the descriptor's buffer address */
 689        union {
 690                __le32 data;
 691                struct {
 692                        __le16 length;  /* Data buffer length */
 693                        u8 typ_len_ext; /* */
 694                        u8 cmd; /* */
 695                } flags;
 696        } lower;
 697        union {
 698                __le32 data;
 699                struct {
 700                        u8 status;      /* Descriptor status */
 701                        u8 popts;       /* Packet Options */
 702                        __le16 special; /* */
 703                } fields;
 704        } upper;
 705};
 706
 707/* Filters */
 708#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
 709#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
 710#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 711
 712/* Receive Address Register */
 713struct e1000_rar {
 714        volatile __le32 low;    /* receive address low */
 715        volatile __le32 high;   /* receive address high */
 716};
 717
 718/* Number of entries in the Multicast Table Array (MTA). */
 719#define E1000_NUM_MTA_REGISTERS 128
 720
 721/* IPv4 Address Table Entry */
 722struct e1000_ipv4_at_entry {
 723        volatile u32 ipv4_addr; /* IP Address (RW) */
 724        volatile u32 reserved;
 725};
 726
 727/* Four wakeup IP addresses are supported */
 728#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
 729#define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
 730#define E1000_IP6AT_SIZE                  1
 731
 732/* IPv6 Address Table Entry */
 733struct e1000_ipv6_at_entry {
 734        volatile u8 ipv6_addr[16];
 735};
 736
 737/* Flexible Filter Length Table Entry */
 738struct e1000_fflt_entry {
 739        volatile u32 length;    /* Flexible Filter Length (RW) */
 740        volatile u32 reserved;
 741};
 742
 743/* Flexible Filter Mask Table Entry */
 744struct e1000_ffmt_entry {
 745        volatile u32 mask;      /* Flexible Filter Mask (RW) */
 746        volatile u32 reserved;
 747};
 748
 749/* Flexible Filter Value Table Entry */
 750struct e1000_ffvt_entry {
 751        volatile u32 value;     /* Flexible Filter Value (RW) */
 752        volatile u32 reserved;
 753};
 754
 755/* Four Flexible Filters are supported */
 756#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
 757
 758/* Each Flexible Filter is at most 128 (0x80) bytes in length */
 759#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
 760
 761#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
 762#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 763#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 764
 765#define E1000_DISABLE_SERDES_LOOPBACK   0x0400
 766
 767/* Register Set. (82543, 82544)
 768 *
 769 * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
 770 * These registers are physically located on the NIC, but are mapped into the
 771 * host memory address space.
 772 *
 773 * RW - register is both readable and writable
 774 * RO - register is read only
 775 * WO - register is write only
 776 * R/clr - register is read only and is cleared when read
 777 * A - register array
 778 */
 779#define E1000_CTRL     0x00000  /* Device Control - RW */
 780#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
 781#define E1000_STATUS   0x00008  /* Device Status - RO */
 782#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
 783#define E1000_EERD     0x00014  /* EEPROM Read - RW */
 784#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
 785#define E1000_FLA      0x0001C  /* Flash Access - RW */
 786#define E1000_MDIC     0x00020  /* MDI Control - RW */
 787
 788#define INTEL_CE_GBE_MDIO_RCOMP_BASE    (hw->ce4100_gbe_mdio_base_virt)
 789#define E1000_MDIO_STS  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0)
 790#define E1000_MDIO_CMD  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 4)
 791#define E1000_MDIO_DRV  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 8)
 792#define E1000_MDC_CMD   (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0xC)
 793#define E1000_RCOMP_CTL (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x20)
 794#define E1000_RCOMP_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x24)
 795
 796#define E1000_SCTL     0x00024  /* SerDes Control - RW */
 797#define E1000_FEXTNVM  0x00028  /* Future Extended NVM register */
 798#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
 799#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
 800#define E1000_FCT      0x00030  /* Flow Control Type - RW */
 801#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
 802#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
 803#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
 804#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
 805#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
 806#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
 807#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
 808
 809/* Auxiliary Control Register. This register is CE4100 specific,
 810 * RMII/RGMII function is switched by this register - RW
 811 * Following are bits definitions of the Auxiliary Control Register
 812 */
 813#define E1000_CTL_AUX  0x000E0
 814#define E1000_CTL_AUX_END_SEL_SHIFT     10
 815#define E1000_CTL_AUX_ENDIANESS_SHIFT   8
 816#define E1000_CTL_AUX_RGMII_RMII_SHIFT  0
 817
 818/* descriptor and packet transfer use CTL_AUX.ENDIANESS */
 819#define E1000_CTL_AUX_DES_PKT   (0x0 << E1000_CTL_AUX_END_SEL_SHIFT)
 820/* descriptor use CTL_AUX.ENDIANESS, packet use default */
 821#define E1000_CTL_AUX_DES       (0x1 << E1000_CTL_AUX_END_SEL_SHIFT)
 822/* descriptor use default, packet use CTL_AUX.ENDIANESS */
 823#define E1000_CTL_AUX_PKT       (0x2 << E1000_CTL_AUX_END_SEL_SHIFT)
 824/* all use CTL_AUX.ENDIANESS */
 825#define E1000_CTL_AUX_ALL       (0x3 << E1000_CTL_AUX_END_SEL_SHIFT)
 826
 827#define E1000_CTL_AUX_RGMII     (0x0 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
 828#define E1000_CTL_AUX_RMII      (0x1 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
 829
 830/* LW little endian, Byte big endian */
 831#define E1000_CTL_AUX_LWLE_BBE  (0x0 << E1000_CTL_AUX_ENDIANESS_SHIFT)
 832#define E1000_CTL_AUX_LWLE_BLE  (0x1 << E1000_CTL_AUX_ENDIANESS_SHIFT)
 833#define E1000_CTL_AUX_LWBE_BBE  (0x2 << E1000_CTL_AUX_ENDIANESS_SHIFT)
 834#define E1000_CTL_AUX_LWBE_BLE  (0x3 << E1000_CTL_AUX_ENDIANESS_SHIFT)
 835
 836#define E1000_RCTL     0x00100  /* RX Control - RW */
 837#define E1000_RDTR1    0x02820  /* RX Delay Timer (1) - RW */
 838#define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
 839#define E1000_RDBAH1   0x02904  /* RX Descriptor Base Address High (1) - RW */
 840#define E1000_RDLEN1   0x02908  /* RX Descriptor Length (1) - RW */
 841#define E1000_RDH1     0x02910  /* RX Descriptor Head (1) - RW */
 842#define E1000_RDT1     0x02918  /* RX Descriptor Tail (1) - RW */
 843#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
 844#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
 845#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
 846#define E1000_TCTL     0x00400  /* TX Control - RW */
 847#define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
 848#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
 849#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
 850#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
 851#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
 852#define E1000_EXTCNF_CTRL  0x00F00      /* Extended Configuration Control */
 853#define E1000_EXTCNF_SIZE  0x00F08      /* Extended Configuration Size */
 854#define E1000_PHY_CTRL     0x00F10      /* PHY Control Register in CSR */
 855#define FEXTNVM_SW_CONFIG  0x0001
 856#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
 857#define E1000_PBS      0x01008  /* Packet Buffer Size */
 858#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
 859#define E1000_FLASH_UPDATES 1000
 860#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
 861#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
 862#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
 863#define E1000_FLSWCTL  0x01030  /* FLASH control register */
 864#define E1000_FLSWDATA 0x01034  /* FLASH data register */
 865#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
 866#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
 867#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
 868#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
 869#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
 870#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
 871#define E1000_RDFH     0x02410  /* RX Data FIFO Head - RW */
 872#define E1000_RDFT     0x02418  /* RX Data FIFO Tail - RW */
 873#define E1000_RDFHS    0x02420  /* RX Data FIFO Head Saved - RW */
 874#define E1000_RDFTS    0x02428  /* RX Data FIFO Tail Saved - RW */
 875#define E1000_RDFPC    0x02430  /* RX Data FIFO Packet Count - RW */
 876#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
 877#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
 878#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
 879#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
 880#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
 881#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
 882#define E1000_RDBAL0   E1000_RDBAL      /* RX Desc Base Address Low (0) - RW */
 883#define E1000_RDBAH0   E1000_RDBAH      /* RX Desc Base Address High (0) - RW */
 884#define E1000_RDLEN0   E1000_RDLEN      /* RX Desc Length (0) - RW */
 885#define E1000_RDH0     E1000_RDH        /* RX Desc Head (0) - RW */
 886#define E1000_RDT0     E1000_RDT        /* RX Desc Tail (0) - RW */
 887#define E1000_RDTR0    E1000_RDTR       /* RX Delay Timer (0) - RW */
 888#define E1000_RXDCTL   0x02828  /* RX Descriptor Control queue 0 - RW */
 889#define E1000_RXDCTL1  0x02928  /* RX Descriptor Control queue 1 - RW */
 890#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
 891#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
 892#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
 893#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
 894#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
 895#define E1000_TDFH     0x03410  /* TX Data FIFO Head - RW */
 896#define E1000_TDFT     0x03418  /* TX Data FIFO Tail - RW */
 897#define E1000_TDFHS    0x03420  /* TX Data FIFO Head Saved - RW */
 898#define E1000_TDFTS    0x03428  /* TX Data FIFO Tail Saved - RW */
 899#define E1000_TDFPC    0x03430  /* TX Data FIFO Packet Count - RW */
 900#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
 901#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
 902#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
 903#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
 904#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
 905#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
 906#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
 907#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
 908#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
 909#define E1000_TARC0    0x03840  /* TX Arbitration Count (0) */
 910#define E1000_TDBAL1   0x03900  /* TX Desc Base Address Low (1) - RW */
 911#define E1000_TDBAH1   0x03904  /* TX Desc Base Address High (1) - RW */
 912#define E1000_TDLEN1   0x03908  /* TX Desc Length (1) - RW */
 913#define E1000_TDH1     0x03910  /* TX Desc Head (1) - RW */
 914#define E1000_TDT1     0x03918  /* TX Desc Tail (1) - RW */
 915#define E1000_TXDCTL1  0x03928  /* TX Descriptor Control (1) - RW */
 916#define E1000_TARC1    0x03940  /* TX Arbitration Count (1) */
 917#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
 918#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
 919#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
 920#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
 921#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
 922#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
 923#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
 924#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
 925#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
 926#define E1000_COLC     0x04028  /* Collision Count - R/clr */
 927#define E1000_DC       0x04030  /* Defer Count - R/clr */
 928#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
 929#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
 930#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
 931#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
 932#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
 933#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
 934#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
 935#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
 936#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
 937#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
 938#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
 939#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
 940#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
 941#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
 942#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
 943#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
 944#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
 945#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
 946#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
 947#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
 948#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
 949#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
 950#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
 951#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
 952#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
 953#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
 954#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
 955#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
 956#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
 957#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
 958#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
 959#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
 960#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
 961#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
 962#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
 963#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
 964#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
 965#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
 966#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
 967#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
 968#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
 969#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
 970#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
 971#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
 972#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
 973#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
 974#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
 975#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
 976#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Packet Timer Expire Count */
 977#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Absolute Timer Expire Count */
 978#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Packet Timer Expire Count */
 979#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Absolute Timer Expire Count */
 980#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
 981#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Minimum Threshold Count */
 982#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
 983#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
 984#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
 985#define E1000_RFCTL    0x05008  /* Receive Filter Control */
 986#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
 987#define E1000_RA       0x05400  /* Receive Address - RW Array */
 988#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
 989#define E1000_WUC      0x05800  /* Wakeup Control - RW */
 990#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
 991#define E1000_WUS      0x05810  /* Wakeup Status - RO */
 992#define E1000_MANC     0x05820  /* Management Control - RW */
 993#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
 994#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
 995#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
 996#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
 997#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
 998#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
 999#define E1000_HOST_IF  0x08800  /* Host Interface */
1000#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */

1001#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
1002
1003#define E1000_KUMCTRLSTA 0x00034        /* MAC-PHY interface - RW */
1004#define E1000_MDPHYA     0x0003C        /* PHY address - RW */
1005#define E1000_MANC2H     0x05860        /* Management Control To Host - RW */
1006#define E1000_SW_FW_SYNC 0x05B5C        /* Software-Firmware Synchronization - RW */
1007
1008#define E1000_GCR       0x05B00 /* PCI-Ex Control */
1009#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
1010#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
1011#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
1012#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
1013#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
1014#define E1000_SWSM      0x05B50 /* SW Semaphore */
1015#define E1000_FWSM      0x05B54 /* FW Semaphore */
1016#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
1017#define E1000_HICR      0x08F00 /* Host Interface Control */
1018
1019/* RSS registers */
1020#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
1021#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
1022#define E1000_RETA      0x05C00 /* Redirection Table - RW Array */
1023#define E1000_RSSRK     0x05C80 /* RSS Random Key - RW Array */
1024#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
1025#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
1026/* Register Set (82542)
1027 *
1028 * Some of the 82542 registers are located at different offsets than they are
1029 * in more current versions of the 8254x. Despite the difference in location,
1030 * the registers function in the same manner.
1031 */
1032#define E1000_82542_CTL_AUX  E1000_CTL_AUX
1033#define E1000_82542_CTRL     E1000_CTRL
1034#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1035#define E1000_82542_STATUS   E1000_STATUS
1036#define E1000_82542_EECD     E1000_EECD
1037#define E1000_82542_EERD     E1000_EERD
1038#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1039#define E1000_82542_FLA      E1000_FLA
1040#define E1000_82542_MDIC     E1000_MDIC
1041#define E1000_82542_SCTL     E1000_SCTL
1042#define E1000_82542_FEXTNVM  E1000_FEXTNVM
1043#define E1000_82542_FCAL     E1000_FCAL
1044#define E1000_82542_FCAH     E1000_FCAH
1045#define E1000_82542_FCT      E1000_FCT
1046#define E1000_82542_VET      E1000_VET
1047#define E1000_82542_RA       0x00040
1048#define E1000_82542_ICR      E1000_ICR
1049#define E1000_82542_ITR      E1000_ITR
1050#define E1000_82542_ICS      E1000_ICS
1051#define E1000_82542_IMS      E1000_IMS
1052#define E1000_82542_IMC      E1000_IMC
1053#define E1000_82542_RCTL     E1000_RCTL
1054#define E1000_82542_RDTR     0x00108
1055#define E1000_82542_RDFH     E1000_RDFH
1056#define E1000_82542_RDFT     E1000_RDFT
1057#define E1000_82542_RDFHS    E1000_RDFHS
1058#define E1000_82542_RDFTS    E1000_RDFTS
1059#define E1000_82542_RDFPC    E1000_RDFPC
1060#define E1000_82542_RDBAL    0x00110
1061#define E1000_82542_RDBAH    0x00114
1062#define E1000_82542_RDLEN    0x00118
1063#define E1000_82542_RDH      0x00120
1064#define E1000_82542_RDT      0x00128
1065#define E1000_82542_RDTR0    E1000_82542_RDTR
1066#define E1000_82542_RDBAL0   E1000_82542_RDBAL
1067#define E1000_82542_RDBAH0   E1000_82542_RDBAH
1068#define E1000_82542_RDLEN0   E1000_82542_RDLEN
1069#define E1000_82542_RDH0     E1000_82542_RDH
1070#define E1000_82542_RDT0     E1000_82542_RDT
1071#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8))   /* Split and Replication
1072                                                         * RX Control - RW */
1073#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1074#define E1000_82542_RDBAH3   0x02B04    /* RX Desc Base High Queue 3 - RW */
1075#define E1000_82542_RDBAL3   0x02B00    /* RX Desc Low Queue 3 - RW */
1076#define E1000_82542_RDLEN3   0x02B08    /* RX Desc Length Queue 3 - RW */
1077#define E1000_82542_RDH3     0x02B10    /* RX Desc Head Queue 3 - RW */
1078#define E1000_82542_RDT3     0x02B18    /* RX Desc Tail Queue 3 - RW */
1079#define E1000_82542_RDBAL2   0x02A00    /* RX Desc Base Low Queue 2 - RW */
1080#define E1000_82542_RDBAH2   0x02A04    /* RX Desc Base High Queue 2 - RW */
1081#define E1000_82542_RDLEN2   0x02A08    /* RX Desc Length Queue 2 - RW */
1082#define E1000_82542_RDH2     0x02A10    /* RX Desc Head Queue 2 - RW */
1083#define E1000_82542_RDT2     0x02A18    /* RX Desc Tail Queue 2 - RW */
1084#define E1000_82542_RDTR1    0x00130
1085#define E1000_82542_RDBAL1   0x00138
1086#define E1000_82542_RDBAH1   0x0013C
1087#define E1000_82542_RDLEN1   0x00140
1088#define E1000_82542_RDH1     0x00148
1089#define E1000_82542_RDT1     0x00150
1090#define E1000_82542_FCRTH    0x00160
1091#define E1000_82542_FCRTL    0x00168
1092#define E1000_82542_FCTTV    E1000_FCTTV
1093#define E1000_82542_TXCW     E1000_TXCW
1094#define E1000_82542_RXCW     E1000_RXCW
1095#define E1000_82542_MTA      0x00200
1096#define E1000_82542_TCTL     E1000_TCTL
1097#define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1098#define E1000_82542_TIPG     E1000_TIPG
1099#define E1000_82542_TDBAL    0x00420
1100#define E1000_82542_TDBAH    0x00424
1101#define E1000_82542_TDLEN    0x00428
1102#define E1000_82542_TDH      0x00430
1103#define E1000_82542_TDT      0x00438
1104#define E1000_82542_TIDV     0x00440
1105#define E1000_82542_TBT      E1000_TBT
1106#define E1000_82542_AIT      E1000_AIT
1107#define E1000_82542_VFTA     0x00600
1108#define E1000_82542_LEDCTL   E1000_LEDCTL
1109#define E1000_82542_PBA      E1000_PBA
1110#define E1000_82542_PBS      E1000_PBS
1111#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1112#define E1000_82542_EEARBC   E1000_EEARBC
1113#define E1000_82542_FLASHT   E1000_FLASHT
1114#define E1000_82542_EEWR     E1000_EEWR
1115#define E1000_82542_FLSWCTL  E1000_FLSWCTL
1116#define E1000_82542_FLSWDATA E1000_FLSWDATA
1117#define E1000_82542_FLSWCNT  E1000_FLSWCNT
1118#define E1000_82542_FLOP     E1000_FLOP
1119#define E1000_82542_EXTCNF_CTRL  E1000_EXTCNF_CTRL
1120#define E1000_82542_EXTCNF_SIZE  E1000_EXTCNF_SIZE
1121#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1122#define E1000_82542_ERT      E1000_ERT
1123#define E1000_82542_RXDCTL   E1000_RXDCTL
1124#define E1000_82542_RXDCTL1  E1000_RXDCTL1
1125#define E1000_82542_RADV     E1000_RADV
1126#define E1000_82542_RSRPD    E1000_RSRPD
1127#define E1000_82542_TXDMAC   E1000_TXDMAC
1128#define E1000_82542_KABGTXD  E1000_KABGTXD
1129#define E1000_82542_TDFHS    E1000_TDFHS
1130#define E1000_82542_TDFTS    E1000_TDFTS
1131#define E1000_82542_TDFPC    E1000_TDFPC
1132#define E1000_82542_TXDCTL   E1000_TXDCTL
1133#define E1000_82542_TADV     E1000_TADV
1134#define E1000_82542_TSPMT    E1000_TSPMT
1135#define E1000_82542_CRCERRS  E1000_CRCERRS
1136#define E1000_82542_ALGNERRC E1000_ALGNERRC
1137#define E1000_82542_SYMERRS  E1000_SYMERRS
1138#define E1000_82542_RXERRC   E1000_RXERRC
1139#define E1000_82542_MPC      E1000_MPC
1140#define E1000_82542_SCC      E1000_SCC
1141#define E1000_82542_ECOL     E1000_ECOL
1142#define E1000_82542_MCC      E1000_MCC
1143#define E1000_82542_LATECOL  E1000_LATECOL
1144#define E1000_82542_COLC     E1000_COLC
1145#define E1000_82542_DC       E1000_DC
1146#define E1000_82542_TNCRS    E1000_TNCRS
1147#define E1000_82542_SEC      E1000_SEC
1148#define E1000_82542_CEXTERR  E1000_CEXTERR
1149#define E1000_82542_RLEC     E1000_RLEC
1150#define E1000_82542_XONRXC   E1000_XONRXC
1151#define E1000_82542_XONTXC   E1000_XONTXC
1152#define E1000_82542_XOFFRXC  E1000_XOFFRXC
1153#define E1000_82542_XOFFTXC  E1000_XOFFTXC
1154#define E1000_82542_FCRUC    E1000_FCRUC
1155#define E1000_82542_PRC64    E1000_PRC64
1156#define E1000_82542_PRC127   E1000_PRC127
1157#define E1000_82542_PRC255   E1000_PRC255
1158#define E1000_82542_PRC511   E1000_PRC511
1159#define E1000_82542_PRC1023  E1000_PRC1023
1160#define E1000_82542_PRC1522  E1000_PRC1522
1161#define E1000_82542_GPRC     E1000_GPRC
1162#define E1000_82542_BPRC     E1000_BPRC
1163#define E1000_82542_MPRC     E1000_MPRC
1164#define E1000_82542_GPTC     E1000_GPTC
1165#define E1000_82542_GORCL    E1000_GORCL
1166#define E1000_82542_GORCH    E1000_GORCH
1167#define E1000_82542_GOTCL    E1000_GOTCL
1168#define E1000_82542_GOTCH    E1000_GOTCH
1169#define E1000_82542_RNBC     E1000_RNBC
1170#define E1000_82542_RUC      E1000_RUC
1171#define E1000_82542_RFC      E1000_RFC
1172#define E1000_82542_ROC      E1000_ROC
1173#define E1000_82542_RJC      E1000_RJC
1174#define E1000_82542_MGTPRC   E1000_MGTPRC
1175#define E1000_82542_MGTPDC   E1000_MGTPDC
1176#define E1000_82542_MGTPTC   E1000_MGTPTC
1177#define E1000_82542_TORL     E1000_TORL
1178#define E1000_82542_TORH     E1000_TORH
1179#define E1000_82542_TOTL     E1000_TOTL
1180#define E1000_82542_TOTH     E1000_TOTH
1181#define E1000_82542_TPR      E1000_TPR
1182#define E1000_82542_TPT      E1000_TPT
1183#define E1000_82542_PTC64    E1000_PTC64
1184#define E1000_82542_PTC127   E1000_PTC127
1185#define E1000_82542_PTC255   E1000_PTC255
1186#define E1000_82542_PTC511   E1000_PTC511
1187#define E1000_82542_PTC1023  E1000_PTC1023
1188#define E1000_82542_PTC1522  E1000_PTC1522
1189#define E1000_82542_MPTC     E1000_MPTC
1190#define E1000_82542_BPTC     E1000_BPTC
1191#define E1000_82542_TSCTC    E1000_TSCTC
1192#define E1000_82542_TSCTFC   E1000_TSCTFC
1193#define E1000_82542_RXCSUM   E1000_RXCSUM
1194#define E1000_82542_WUC      E1000_WUC
1195#define E1000_82542_WUFC     E1000_WUFC
1196#define E1000_82542_WUS      E1000_WUS
1197#define E1000_82542_MANC     E1000_MANC
1198#define E1000_82542_IPAV     E1000_IPAV
1199#define E1000_82542_IP4AT    E1000_IP4AT
1200#define E1000_82542_IP6AT    E1000_IP6AT
1201#define E1000_82542_WUPL     E1000_WUPL
1202#define E1000_82542_WUPM     E1000_WUPM
1203#define E1000_82542_FFLT     E1000_FFLT
1204#define E1000_82542_TDFH     0x08010
1205#define E1000_82542_TDFT     0x08018
1206#define E1000_82542_FFMT     E1000_FFMT
1207#define E1000_82542_FFVT     E1000_FFVT
1208#define E1000_82542_HOST_IF  E1000_HOST_IF
1209#define E1000_82542_IAM         E1000_IAM
1210#define E1000_82542_EEMNGCTL    E1000_EEMNGCTL
1211#define E1000_82542_PSRCTL      E1000_PSRCTL
1212#define E1000_82542_RAID        E1000_RAID
1213#define E1000_82542_TARC0       E1000_TARC0
1214#define E1000_82542_TDBAL1      E1000_TDBAL1
1215#define E1000_82542_TDBAH1      E1000_TDBAH1
1216#define E1000_82542_TDLEN1      E1000_TDLEN1
1217#define E1000_82542_TDH1        E1000_TDH1
1218#define E1000_82542_TDT1        E1000_TDT1
1219#define E1000_82542_TXDCTL1     E1000_TXDCTL1
1220#define E1000_82542_TARC1       E1000_TARC1
1221#define E1000_82542_RFCTL       E1000_RFCTL
1222#define E1000_82542_GCR         E1000_GCR
1223#define E1000_82542_GSCL_1      E1000_GSCL_1
1224#define E1000_82542_GSCL_2      E1000_GSCL_2
1225#define E1000_82542_GSCL_3      E1000_GSCL_3
1226#define E1000_82542_GSCL_4      E1000_GSCL_4
1227#define E1000_82542_FACTPS      E1000_FACTPS
1228#define E1000_82542_SWSM        E1000_SWSM
1229#define E1000_82542_FWSM        E1000_FWSM
1230#define E1000_82542_FFLT_DBG    E1000_FFLT_DBG
1231#define E1000_82542_IAC         E1000_IAC
1232#define E1000_82542_ICRXPTC     E1000_ICRXPTC
1233#define E1000_82542_ICRXATC     E1000_ICRXATC
1234#define E1000_82542_ICTXPTC     E1000_ICTXPTC
1235#define E1000_82542_ICTXATC     E1000_ICTXATC
1236#define E1000_82542_ICTXQEC     E1000_ICTXQEC
1237#define E1000_82542_ICTXQMTC    E1000_ICTXQMTC
1238#define E1000_82542_ICRXDMTC    E1000_ICRXDMTC
1239#define E1000_82542_ICRXOC      E1000_ICRXOC
1240#define E1000_82542_HICR        E1000_HICR
1241
1242#define E1000_82542_CPUVEC      E1000_CPUVEC
1243#define E1000_82542_MRQC        E1000_MRQC
1244#define E1000_82542_RETA        E1000_RETA
1245#define E1000_82542_RSSRK       E1000_RSSRK
1246#define E1000_82542_RSSIM       E1000_RSSIM
1247#define E1000_82542_RSSIR       E1000_RSSIR
1248#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1249#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
1250
1251/* Statistics counters collected by the MAC */
1252struct e1000_hw_stats {
1253        u64 crcerrs;
1254        u64 algnerrc;
1255        u64 symerrs;
1256        u64 rxerrc;
1257        u64 txerrc;
1258        u64 mpc;
1259        u64 scc;
1260        u64 ecol;
1261        u64 mcc;
1262        u64 latecol;
1263        u64 colc;
1264        u64 dc;
1265        u64 tncrs;
1266        u64 sec;
1267        u64 cexterr;
1268        u64 rlec;
1269        u64 xonrxc;
1270        u64 xontxc;
1271        u64 xoffrxc;
1272        u64 xofftxc;
1273        u64 fcruc;
1274        u64 prc64;
1275        u64 prc127;
1276        u64 prc255;
1277        u64 prc511;
1278        u64 prc1023;
1279        u64 prc1522;
1280        u64 gprc;
1281        u64 bprc;
1282        u64 mprc;
1283        u64 gptc;
1284        u64 gorcl;
1285        u64 gorch;
1286        u64 gotcl;
1287        u64 gotch;
1288        u64 rnbc;
1289        u64 ruc;
1290        u64 rfc;
1291        u64 roc;
1292        u64 rlerrc;
1293        u64 rjc;
1294        u64 mgprc;
1295        u64 mgpdc;
1296        u64 mgptc;
1297        u64 torl;
1298        u64 torh;
1299        u64 totl;
1300        u64 toth;
1301        u64 tpr;
1302        u64 tpt;
1303        u64 ptc64;
1304        u64 ptc127;
1305        u64 ptc255;
1306        u64 ptc511;
1307        u64 ptc1023;
1308        u64 ptc1522;
1309        u64 mptc;
1310        u64 bptc;
1311        u64 tsctc;
1312        u64 tsctfc;
1313        u64 iac;
1314        u64 icrxptc;
1315        u64 icrxatc;
1316        u64 ictxptc;
1317        u64 ictxatc;
1318        u64 ictxqec;
1319        u64 ictxqmtc;
1320        u64 icrxdmtc;
1321        u64 icrxoc;
1322};
1323
1324/* Structure containing variables used by the shared code (e1000_hw.c) */
1325struct e1000_hw {
1326        u8 __iomem *hw_addr;
1327        u8 __iomem *flash_address;
1328        void __iomem *ce4100_gbe_mdio_base_virt;
1329        e1000_mac_type mac_type;
1330        e1000_phy_type phy_type;
1331        u32 phy_init_script;
1332        e1000_media_type media_type;
1333        void *back;
1334        struct e1000_shadow_ram *eeprom_shadow_ram;
1335        u32 flash_bank_size;
1336        u32 flash_base_addr;
1337        e1000_fc_type fc;
1338        e1000_bus_speed bus_speed;
1339        e1000_bus_width bus_width;
1340        e1000_bus_type bus_type;
1341        struct e1000_eeprom_info eeprom;
1342        e1000_ms_type master_slave;
1343        e1000_ms_type original_master_slave;
1344        e1000_ffe_config ffe_config_state;
1345        u32 asf_firmware_present;
1346        u32 eeprom_semaphore_present;
1347        unsigned long io_base;
1348        u32 phy_id;
1349        u32 phy_revision;
1350        u32 phy_addr;
1351        u32 original_fc;
1352        u32 txcw;
1353        u32 autoneg_failed;
1354        u32 max_frame_size;
1355        u32 min_frame_size;
1356        u32 mc_filter_type;
1357        u32 num_mc_addrs;
1358        u32 collision_delta;
1359        u32 tx_packet_delta;
1360        u32 ledctl_default;
1361        u32 ledctl_mode1;
1362        u32 ledctl_mode2;
1363        bool tx_pkt_filtering;
1364        struct e1000_host_mng_dhcp_cookie mng_cookie;
1365        u16 phy_spd_default;
1366        u16 autoneg_advertised;
1367        u16 pci_cmd_word;
1368        u16 fc_high_water;
1369        u16 fc_low_water;
1370        u16 fc_pause_time;
1371        u16 current_ifs_val;
1372        u16 ifs_min_val;
1373        u16 ifs_max_val;
1374        u16 ifs_step_size;
1375        u16 ifs_ratio;
1376        u16 device_id;
1377        u16 vendor_id;
1378        u16 subsystem_id;
1379        u16 subsystem_vendor_id;
1380        u8 revision_id;
1381        u8 autoneg;
1382        u8 mdix;
1383        u8 forced_speed_duplex;
1384        u8 wait_autoneg_complete;
1385        u8 dma_fairness;
1386        u8 mac_addr[NODE_ADDRESS_SIZE];
1387        u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1388        bool disable_polarity_correction;
1389        bool speed_downgraded;
1390        e1000_smart_speed smart_speed;
1391        e1000_dsp_config dsp_config_state;
1392        bool get_link_status;
1393        bool serdes_has_link;
1394        bool tbi_compatibility_en;
1395        bool tbi_compatibility_on;
1396        bool laa_is_present;
1397        bool phy_reset_disable;
1398        bool initialize_hw_bits_disable;
1399        bool fc_send_xon;
1400        bool fc_strict_ieee;
1401        bool report_tx_early;
1402        bool adaptive_ifs;
1403        bool ifs_params_forced;
1404        bool in_ifs_mode;
1405        bool mng_reg_access_disabled;
1406        bool leave_av_bit_off;
1407        bool bad_tx_carr_stats_fd;
1408        bool has_smbus;
1409};
1410
1411#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
1412#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
1413#define E1000_EEPROM_RW_REG_DATA   16   /* Offset to data in EEPROM read/write registers */
1414#define E1000_EEPROM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
1415#define E1000_EEPROM_RW_REG_START  1    /* First bit for telling part to start operation */
1416#define E1000_EEPROM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
1417#define E1000_EEPROM_POLL_WRITE    1    /* Flag for polling for write complete */
1418#define E1000_EEPROM_POLL_READ     0    /* Flag for polling for read complete */
1419/* Register Bit Masks */
1420/* Device Control */
1421#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
1422#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
1423#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
1424#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004        /*Blocks new Master requests */
1425#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
1426#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
1427#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
1428#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
1429#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
1430#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
1431#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
1432#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
1433#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
1434#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
1435#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
1436#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
1437#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
1438#define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
1439#define E1000_CTRL_D_UD_POLARITY 0x00004000     /* Defined polarity of Dock/Undock indication in SDP[0] */
1440#define E1000_CTRL_FORCE_PHY_RESET 0x00008000   /* Reset both PHY ports, through PHYRST_N pin */
1441#define E1000_CTRL_EXT_LINK_EN 0x00010000       /* enable link status from external LINK_0 and LINK_1 pins */
1442#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
1443#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
1444#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
1445#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
1446#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
1447#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
1448#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
1449#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
1450#define E1000_CTRL_RST      0x04000000  /* Global reset */
1451#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
1452#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
1453#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
1454#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
1455#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
1456#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1457
1458/* Device Status */
1459#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
1460#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
1461#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
1462#define E1000_STATUS_FUNC_SHIFT 2
1463#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
1464#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
1465#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
1466#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
1467#define E1000_STATUS_SPEED_MASK 0x000000C0
1468#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
1469#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
1470#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
1471#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion
1472                                                   by EEPROM/Flash */
1473#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
1474#define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state. Clear on write '0'. */
1475#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000       /* Status of Master requests. */
1476#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
1477#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
1478#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
1479#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
1480#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
1481#define E1000_STATUS_BMC_SKU_0  0x00100000      /* BMC USB redirect disabled */
1482#define E1000_STATUS_BMC_SKU_1  0x00200000      /* BMC SRAM disabled */
1483#define E1000_STATUS_BMC_SKU_2  0x00400000      /* BMC SDRAM disabled */
1484#define E1000_STATUS_BMC_CRYPTO 0x00800000      /* BMC crypto disabled */
1485#define E1000_STATUS_BMC_LITE   0x01000000      /* BMC external code execution disabled */
1486#define E1000_STATUS_RGMII_ENABLE 0x02000000    /* RGMII disabled */
1487#define E1000_STATUS_FUSE_8       0x04000000
1488#define E1000_STATUS_FUSE_9       0x08000000
1489#define E1000_STATUS_SERDES0_DIS  0x10000000    /* SERDES disabled on port 0 */
1490#define E1000_STATUS_SERDES1_DIS  0x20000000    /* SERDES disabled on port 1 */
1491
1492/* Constants used to interpret the masked PCI-X bus speed. */
1493#define E1000_STATUS_PCIX_SPEED_66  0x00000000  /* PCI-X bus speed  50-66 MHz */
1494#define E1000_STATUS_PCIX_SPEED_100 0x00004000  /* PCI-X bus speed  66-100 MHz */
1495#define E1000_STATUS_PCIX_SPEED_133 0x00008000  /* PCI-X bus speed 100-133 MHz */
1496
1497/* EEPROM/Flash Control */
1498#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
1499#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
1500#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
1501#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
1502#define E1000_EECD_FWE_MASK  0x00000030
1503#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
1504#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
1505#define E1000_EECD_FWE_SHIFT 4
1506#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
1507#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
1508#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
1509#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1510#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1511                                         * (0-small, 1-large) */
1512#define E1000_EECD_TYPE      0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1513#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1514#define E1000_EEPROM_GRANT_ATTEMPTS 1000        /* EEPROM # attempts to gain grant */
1515#endif
1516#define E1000_EECD_AUTO_RD          0x00000200  /* EEPROM Auto Read done */
1517#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* EEprom Size */
1518#define E1000_EECD_SIZE_EX_SHIFT    11
1519#define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
1520#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
1521#define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
1522#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
1523#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
1524#define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
1525#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
1526#define E1000_EECD_SECVAL_SHIFT      22
1527#define E1000_STM_OPCODE     0xDB00
1528#define E1000_HICR_FW_RESET  0xC0
1529
1530#define E1000_SHADOW_RAM_WORDS     2048
1531#define E1000_ICH_NVM_SIG_WORD     0x13
1532#define E1000_ICH_NVM_SIG_MASK     0xC0
1533
1534/* EEPROM Read */
1535#define E1000_EERD_START      0x00000001        /* Start Read */
1536#define E1000_EERD_DONE       0x00000010        /* Read Done */
1537#define E1000_EERD_ADDR_SHIFT 8
1538#define E1000_EERD_ADDR_MASK  0x0000FF00        /* Read Address */
1539#define E1000_EERD_DATA_SHIFT 16
1540#define E1000_EERD_DATA_MASK  0xFFFF0000        /* Read Data */
1541
1542/* SPI EEPROM Status Register */
1543#define EEPROM_STATUS_RDY_SPI  0x01
1544#define EEPROM_STATUS_WEN_SPI  0x02
1545#define EEPROM_STATUS_BP0_SPI  0x04
1546#define EEPROM_STATUS_BP1_SPI  0x08
1547#define EEPROM_STATUS_WPEN_SPI 0x80
1548
1549/* Extended Device Control */
1550#define E1000_CTRL_EXT_GPI0_EN   0x00000001     /* Maps SDP4 to GPI0 */
1551#define E1000_CTRL_EXT_GPI1_EN   0x00000002     /* Maps SDP5 to GPI1 */
1552#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1553#define E1000_CTRL_EXT_GPI2_EN   0x00000004     /* Maps SDP6 to GPI2 */
1554#define E1000_CTRL_EXT_GPI3_EN   0x00000008     /* Maps SDP7 to GPI3 */
1555#define E1000_CTRL_EXT_SDP4_DATA 0x00000010     /* Value of SW Defineable Pin 4 */
1556#define E1000_CTRL_EXT_SDP5_DATA 0x00000020     /* Value of SW Defineable Pin 5 */
1557#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
1558#define E1000_CTRL_EXT_SDP6_DATA 0x00000040     /* Value of SW Defineable Pin 6 */
1559#define E1000_CTRL_EXT_SDP7_DATA 0x00000080     /* Value of SW Defineable Pin 7 */
1560#define E1000_CTRL_EXT_SDP4_DIR  0x00000100     /* Direction of SDP4 0=in 1=out */
1561#define E1000_CTRL_EXT_SDP5_DIR  0x00000200     /* Direction of SDP5 0=in 1=out */
1562#define E1000_CTRL_EXT_SDP6_DIR  0x00000400     /* Direction of SDP6 0=in 1=out */
1563#define E1000_CTRL_EXT_SDP7_DIR  0x00000800     /* Direction of SDP7 0=in 1=out */
1564#define E1000_CTRL_EXT_ASDCHK    0x00001000     /* Initiate an ASD sequence */
1565#define E1000_CTRL_EXT_EE_RST    0x00002000     /* Reinitialize from EEPROM */
1566#define E1000_CTRL_EXT_IPS       0x00004000     /* Invert Power State */
1567#define E1000_CTRL_EXT_SPD_BYPS  0x00008000     /* Speed Select Bypass */
1568#define E1000_CTRL_EXT_RO_DIS    0x00020000     /* Relaxed Ordering disable */
1569#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1570#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1571#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
1572#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
1573#define E1000_CTRL_EXT_LINK_MODE_SERDES  0x00C00000
1574#define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
1575#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
1576#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
1577#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
1578#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
1579#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
1580#define E1000_CTRL_EXT_DRV_LOAD       0x10000000        /* Driver loaded bit for FW */
1581#define E1000_CTRL_EXT_IAME           0x08000000        /* Interrupt acknowledge Auto-mask */
1582#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000        /* Clear Interrupt timers after IMS clear */
1583#define E1000_CRTL_EXT_PB_PAREN       0x01000000        /* packet buffer parity error detection enabled */
1584#define E1000_CTRL_EXT_DF_PAREN       0x02000000        /* descriptor FIFO parity error detection enable */
1585#define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
1586
1587/* MDI Control */
1588#define E1000_MDIC_DATA_MASK 0x0000FFFF
1589#define E1000_MDIC_REG_MASK  0x001F0000
1590#define E1000_MDIC_REG_SHIFT 16
1591#define E1000_MDIC_PHY_MASK  0x03E00000
1592#define E1000_MDIC_PHY_SHIFT 21
1593#define E1000_MDIC_OP_WRITE  0x04000000
1594#define E1000_MDIC_OP_READ   0x08000000
1595#define E1000_MDIC_READY     0x10000000
1596#define E1000_MDIC_INT_EN    0x20000000
1597#define E1000_MDIC_ERROR     0x40000000
1598
1599#define INTEL_CE_GBE_MDIC_OP_WRITE      0x04000000
1600#define INTEL_CE_GBE_MDIC_OP_READ       0x00000000
1601#define INTEL_CE_GBE_MDIC_GO            0x80000000
1602#define INTEL_CE_GBE_MDIC_READ_ERROR    0x80000000
1603
1604#define E1000_KUMCTRLSTA_MASK           0x0000FFFF
1605#define E1000_KUMCTRLSTA_OFFSET         0x001F0000
1606#define E1000_KUMCTRLSTA_OFFSET_SHIFT   16
1607#define E1000_KUMCTRLSTA_REN            0x00200000
1608
1609#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL      0x00000000
1610#define E1000_KUMCTRLSTA_OFFSET_CTRL           0x00000001
1611#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL       0x00000002
1612#define E1000_KUMCTRLSTA_OFFSET_DIAG           0x00000003
1613#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS       0x00000004
1614#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM      0x00000009
1615#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL        0x00000010
1616#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES     0x0000001E
1617#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES      0x0000001F
1618
1619/* FIFO Control */
1620#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS   0x00000008
1621#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS   0x00000800
1622
1623/* In-Band Control */
1624#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT    0x00000500
1625#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING  0x00000010
1626
1627/* Half-Duplex Control */
1628#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1629#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT  0x00000000
1630
1631#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL       0x0000001E
1632
1633#define E1000_KUMCTRLSTA_DIAG_FELPBK           0x2000
1634#define E1000_KUMCTRLSTA_DIAG_NELPBK           0x1000
1635
1636#define E1000_KUMCTRLSTA_K0S_100_EN            0x2000
1637#define E1000_KUMCTRLSTA_K0S_GBE_EN            0x1000
1638#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK   0x0003
1639
1640#define E1000_KABGTXD_BGSQLBIAS                0x00050000
1641
1642#define E1000_PHY_CTRL_SPD_EN                  0x00000001
1643#define E1000_PHY_CTRL_D0A_LPLU                0x00000002
1644#define E1000_PHY_CTRL_NOND0A_LPLU             0x00000004
1645#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE      0x00000008
1646#define E1000_PHY_CTRL_GBE_DISABLE             0x00000040
1647#define E1000_PHY_CTRL_B2B_EN                  0x00000080
1648
1649/* LED Control */
1650#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
1651#define E1000_LEDCTL_LED0_MODE_SHIFT      0
1652#define E1000_LEDCTL_LED0_BLINK_RATE      0x0000020
1653#define E1000_LEDCTL_LED0_IVRT            0x00000040
1654#define E1000_LEDCTL_LED0_BLINK           0x00000080
1655#define E1000_LEDCTL_LED1_MODE_MASK       0x00000F00
1656#define E1000_LEDCTL_LED1_MODE_SHIFT      8
1657#define E1000_LEDCTL_LED1_BLINK_RATE      0x0002000
1658#define E1000_LEDCTL_LED1_IVRT            0x00004000
1659#define E1000_LEDCTL_LED1_BLINK           0x00008000
1660#define E1000_LEDCTL_LED2_MODE_MASK       0x000F0000
1661#define E1000_LEDCTL_LED2_MODE_SHIFT      16
1662#define E1000_LEDCTL_LED2_BLINK_RATE      0x00200000
1663#define E1000_LEDCTL_LED2_IVRT            0x00400000
1664#define E1000_LEDCTL_LED2_BLINK           0x00800000
1665#define E1000_LEDCTL_LED3_MODE_MASK       0x0F000000
1666#define E1000_LEDCTL_LED3_MODE_SHIFT      24
1667#define E1000_LEDCTL_LED3_BLINK_RATE      0x20000000
1668#define E1000_LEDCTL_LED3_IVRT            0x40000000
1669#define E1000_LEDCTL_LED3_BLINK           0x80000000
1670
1671#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
1672#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1673#define E1000_LEDCTL_MODE_LINK_UP       0x2
1674#define E1000_LEDCTL_MODE_ACTIVITY      0x3
1675#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1676#define E1000_LEDCTL_MODE_LINK_10       0x5
1677#define E1000_LEDCTL_MODE_LINK_100      0x6
1678#define E1000_LEDCTL_MODE_LINK_1000     0x7
1679#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
1680#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
1681#define E1000_LEDCTL_MODE_COLLISION     0xA
1682#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
1683#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
1684#define E1000_LEDCTL_MODE_PAUSED        0xD
1685#define E1000_LEDCTL_MODE_LED_ON        0xE
1686#define E1000_LEDCTL_MODE_LED_OFF       0xF
1687
1688/* Receive Address */
1689#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
1690
1691/* Interrupt Cause Read */
1692#define E1000_ICR_TXDW          0x00000001      /* Transmit desc written back */
1693#define E1000_ICR_TXQE          0x00000002      /* Transmit Queue empty */
1694#define E1000_ICR_LSC           0x00000004      /* Link Status Change */
1695#define E1000_ICR_RXSEQ         0x00000008      /* rx sequence error */
1696#define E1000_ICR_RXDMT0        0x00000010      /* rx desc min. threshold (0) */
1697#define E1000_ICR_RXO           0x00000040      /* rx overrun */
1698#define E1000_ICR_RXT0          0x00000080      /* rx timer intr (ring 0) */
1699#define E1000_ICR_MDAC          0x00000200      /* MDIO access complete */
1700#define E1000_ICR_RXCFG         0x00000400      /* RX /c/ ordered set */
1701#define E1000_ICR_GPI_EN0       0x00000800      /* GP Int 0 */
1702#define E1000_ICR_GPI_EN1       0x00001000      /* GP Int 1 */
1703#define E1000_ICR_GPI_EN2       0x00002000      /* GP Int 2 */
1704#define E1000_ICR_GPI_EN3       0x00004000      /* GP Int 3 */
1705#define E1000_ICR_TXD_LOW       0x00008000
1706#define E1000_ICR_SRPD          0x00010000
1707#define E1000_ICR_ACK           0x00020000      /* Receive Ack frame */
1708#define E1000_ICR_MNG           0x00040000      /* Manageability event */
1709#define E1000_ICR_DOCK          0x00080000      /* Dock/Undock */
1710#define E1000_ICR_INT_ASSERTED  0x80000000      /* If this bit asserted, the driver should claim the interrupt */
1711#define E1000_ICR_RXD_FIFO_PAR0 0x00100000      /* queue 0 Rx descriptor FIFO parity error */
1712#define E1000_ICR_TXD_FIFO_PAR0 0x00200000      /* queue 0 Tx descriptor FIFO parity error */
1713#define E1000_ICR_HOST_ARB_PAR  0x00400000      /* host arb read buffer parity error */
1714#define E1000_ICR_PB_PAR        0x00800000      /* packet buffer parity error */
1715#define E1000_ICR_RXD_FIFO_PAR1 0x01000000      /* queue 1 Rx descriptor FIFO parity error */
1716#define E1000_ICR_TXD_FIFO_PAR1 0x02000000      /* queue 1 Tx descriptor FIFO parity error */
1717#define E1000_ICR_ALL_PARITY    0x03F00000      /* all parity error bits */
1718#define E1000_ICR_DSW           0x00000020      /* FW changed the status of DISSW bit in the FWSM */
1719#define E1000_ICR_PHYINT        0x00001000      /* LAN connected device generates an interrupt */
1720#define E1000_ICR_EPRST         0x00100000      /* ME hardware reset occurs */
1721
1722/* Interrupt Cause Set */
1723#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
1724#define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
1725#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
1726#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
1727#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
1728#define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
1729#define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
1730#define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
1731#define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
1732#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
1733#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
1734#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
1735#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
1736#define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
1737#define E1000_ICS_SRPD      E1000_ICR_SRPD
1738#define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
1739#define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
1740#define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
1741#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1742#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1743#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
1744#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
1745#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1746#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1747#define E1000_ICS_DSW       E1000_ICR_DSW
1748#define E1000_ICS_PHYINT    E1000_ICR_PHYINT
1749#define E1000_ICS_EPRST     E1000_ICR_EPRST
1750
1751/* Interrupt Mask Set */
1752#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
1753#define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
1754#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
1755#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
1756#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
1757#define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
1758#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
1759#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
1760#define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
1761#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
1762#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
1763#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
1764#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
1765#define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
1766#define E1000_IMS_SRPD      E1000_ICR_SRPD
1767#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
1768#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
1769#define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
1770#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1771#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1772#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
1773#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
1774#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1775#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1776#define E1000_IMS_DSW       E1000_ICR_DSW
1777#define E1000_IMS_PHYINT    E1000_ICR_PHYINT
1778#define E1000_IMS_EPRST     E1000_ICR_EPRST
1779
1780/* Interrupt Mask Clear */
1781#define E1000_IMC_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
1782#define E1000_IMC_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
1783#define E1000_IMC_LSC       E1000_ICR_LSC       /* Link Status Change */
1784#define E1000_IMC_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
1785#define E1000_IMC_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
1786#define E1000_IMC_RXO       E1000_ICR_RXO       /* rx overrun */
1787#define E1000_IMC_RXT0      E1000_ICR_RXT0      /* rx timer intr */
1788#define E1000_IMC_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
1789#define E1000_IMC_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
1790#define E1000_IMC_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
1791#define E1000_IMC_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
1792#define E1000_IMC_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
1793#define E1000_IMC_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
1794#define E1000_IMC_TXD_LOW   E1000_ICR_TXD_LOW
1795#define E1000_IMC_SRPD      E1000_ICR_SRPD
1796#define E1000_IMC_ACK       E1000_ICR_ACK       /* Receive Ack frame */
1797#define E1000_IMC_MNG       E1000_ICR_MNG       /* Manageability event */
1798#define E1000_IMC_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
1799#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1800#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1801#define E1000_IMC_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
1802#define E1000_IMC_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
1803#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1804#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1805#define E1000_IMC_DSW       E1000_ICR_DSW
1806#define E1000_IMC_PHYINT    E1000_ICR_PHYINT
1807#define E1000_IMC_EPRST     E1000_ICR_EPRST
1808
1809/* Receive Control */
1810#define E1000_RCTL_RST            0x00000001    /* Software reset */
1811#define E1000_RCTL_EN             0x00000002    /* enable */
1812#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
1813#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
1814#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
1815#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
1816#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
1817#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
1818#define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
1819#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
1820#define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
1821#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
1822#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
1823#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min threshold size */
1824#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min threshold size */
1825#define E1000_RCTL_MO_SHIFT       12    /* multicast offset shift */
1826#define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
1827#define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
1828#define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
1829#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
1830#define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
1831#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
1832/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1833#define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
1834#define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
1835#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
1836#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
1837/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1838#define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
1839#define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
1840#define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
1841#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
1842#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
1843#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
1844#define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
1845#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
1846#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
1847#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
1848#define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
1849#define E1000_RCTL_FLXBUF_SHIFT   27    /* Flexible buffer shift */
1850
1851/* Use byte values for the following shift parameters
1852 * Usage:
1853 *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1854 *                  E1000_PSRCTL_BSIZE0_MASK) |
1855 *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1856 *                  E1000_PSRCTL_BSIZE1_MASK) |
1857 *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1858 *                  E1000_PSRCTL_BSIZE2_MASK) |
1859 *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1860 *                  E1000_PSRCTL_BSIZE3_MASK))
1861 * where value0 = [128..16256],  default=256
1862 *       value1 = [1024..64512], default=4096
1863 *       value2 = [0..64512],    default=4096
1864 *       value3 = [0..64512],    default=0
1865 */
1866
1867#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
1868#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
1869#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
1870#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
1871
1872#define E1000_PSRCTL_BSIZE0_SHIFT  7    /* Shift _right_ 7 */
1873#define E1000_PSRCTL_BSIZE1_SHIFT  2    /* Shift _right_ 2 */
1874#define E1000_PSRCTL_BSIZE2_SHIFT  6    /* Shift _left_ 6 */
1875#define E1000_PSRCTL_BSIZE3_SHIFT 14    /* Shift _left_ 14 */
1876
1877/* SW_W_SYNC definitions */
1878#define E1000_SWFW_EEP_SM     0x0001
1879#define E1000_SWFW_PHY0_SM    0x0002
1880#define E1000_SWFW_PHY1_SM    0x0004
1881#define E1000_SWFW_MAC_CSR_SM 0x0008
1882
1883/* Receive Descriptor */
1884#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
1885#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
1886#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
1887#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
1888#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
1889
1890/* Flow Control */
1891#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
1892#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
1893#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
1894#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
1895
1896/* Header split receive */
1897#define E1000_RFCTL_ISCSI_DIS           0x00000001
1898#define E1000_RFCTL_ISCSI_DWC_MASK      0x0000003E
1899#define E1000_RFCTL_ISCSI_DWC_SHIFT     1
1900#define E1000_RFCTL_NFSW_DIS            0x00000040
1901#define E1000_RFCTL_NFSR_DIS            0x00000080
1902#define E1000_RFCTL_NFS_VER_MASK        0x00000300
1903#define E1000_RFCTL_NFS_VER_SHIFT       8
1904#define E1000_RFCTL_IPV6_DIS            0x00000400
1905#define E1000_RFCTL_IPV6_XSUM_DIS       0x00000800
1906#define E1000_RFCTL_ACK_DIS             0x00001000
1907#define E1000_RFCTL_ACKD_DIS            0x00002000
1908#define E1000_RFCTL_IPFRSP_DIS          0x00004000
1909#define E1000_RFCTL_EXTEN               0x00008000
1910#define E1000_RFCTL_IPV6_EX_DIS         0x00010000
1911#define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
1912
1913/* Receive Descriptor Control */
1914#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1915#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1916#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1917#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
1918
1919/* Transmit Descriptor Control */
1920#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1921#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1922#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1923#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
1924#define E1000_TXDCTL_LWTHRESH 0xFE000000        /* TXDCTL Low Threshold */
1925#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1926#define E1000_TXDCTL_COUNT_DESC 0x00400000      /* Enable the counting of desc.
1927                                                   still to be processed. */
1928/* Transmit Configuration Word */
1929#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
1930#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
1931#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
1932#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
1933#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
1934#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
1935#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
1936#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
1937#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
1938#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
1939
1940/* Receive Configuration Word */
1941#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
1942#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
1943#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
1944#define E1000_RXCW_CC    0x10000000     /* Receive config change */
1945#define E1000_RXCW_C     0x20000000     /* Receive config */
1946#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
1947#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
1948
1949/* Transmit Control */
1950#define E1000_TCTL_RST    0x00000001    /* software reset */
1951#define E1000_TCTL_EN     0x00000002    /* enable tx */
1952#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
1953#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
1954#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
1955#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
1956#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
1957#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
1958#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
1959#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
1960#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
1961/* Extended Transmit Control */
1962#define E1000_TCTL_EXT_BST_MASK  0x000003FF     /* Backoff Slot Time */
1963#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00     /* Gigabit Carry Extend Padding */
1964
1965/* Receive Checksum Control */
1966#define E1000_RXCSUM_PCSS_MASK 0x000000FF       /* Packet Checksum Start */
1967#define E1000_RXCSUM_IPOFL     0x00000100       /* IPv4 checksum offload */
1968#define E1000_RXCSUM_TUOFL     0x00000200       /* TCP / UDP checksum offload */
1969#define E1000_RXCSUM_IPV6OFL   0x00000400       /* IPv6 checksum offload */
1970#define E1000_RXCSUM_IPPCSE    0x00001000       /* IP payload checksum enable */
1971#define E1000_RXCSUM_PCSD      0x00002000       /* packet checksum disabled */
1972
1973/* Multiple Receive Queue Control */
1974#define E1000_MRQC_ENABLE_MASK              0x00000003
1975#define E1000_MRQC_ENABLE_RSS_2Q            0x00000001
1976#define E1000_MRQC_ENABLE_RSS_INT           0x00000004
1977#define E1000_MRQC_RSS_FIELD_MASK           0xFFFF0000
1978#define E1000_MRQC_RSS_FIELD_IPV4_TCP       0x00010000
1979#define E1000_MRQC_RSS_FIELD_IPV4           0x00020000
1980#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX    0x00040000
1981#define E1000_MRQC_RSS_FIELD_IPV6_EX        0x00080000
1982#define E1000_MRQC_RSS_FIELD_IPV6           0x00100000
1983#define E1000_MRQC_RSS_FIELD_IPV6_TCP       0x00200000
1984
1985/* Definitions for power management and wakeup registers */
1986/* Wake Up Control */
1987#define E1000_WUC_APME       0x00000001 /* APM Enable */
1988#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
1989#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1990#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
1991#define E1000_WUC_SPM        0x80000000 /* Enable SPM */
1992
1993/* Wake Up Filter Control */
1994#define E1000_WUFC_LNKC 0x00000001      /* Link Status Change Wakeup Enable */
1995#define E1000_WUFC_MAG  0x00000002      /* Magic Packet Wakeup Enable */
1996#define E1000_WUFC_EX   0x00000004      /* Directed Exact Wakeup Enable */
1997#define E1000_WUFC_MC   0x00000008      /* Directed Multicast Wakeup Enable */
1998#define E1000_WUFC_BC   0x00000010      /* Broadcast Wakeup Enable */
1999#define E1000_WUFC_ARP  0x00000020      /* ARP Request Packet Wakeup Enable */
2000#define E1000_WUFC_IPV4 0x00000040      /* Directed IPv4 Packet Wakeup Enable */

2001#define E1000_WUFC_IPV6 0x00000080      /* Directed IPv6 Packet Wakeup Enable */
2002#define E1000_WUFC_IGNORE_TCO      0x00008000   /* Ignore WakeOn TCO packets */
2003#define E1000_WUFC_FLX0 0x00010000      /* Flexible Filter 0 Enable */
2004#define E1000_WUFC_FLX1 0x00020000      /* Flexible Filter 1 Enable */
2005#define E1000_WUFC_FLX2 0x00040000      /* Flexible Filter 2 Enable */
2006#define E1000_WUFC_FLX3 0x00080000      /* Flexible Filter 3 Enable */
2007#define E1000_WUFC_ALL_FILTERS 0x000F00FF       /* Mask for all wakeup filters */
2008#define E1000_WUFC_FLX_OFFSET 16        /* Offset to the Flexible Filters bits */
2009#define E1000_WUFC_FLX_FILTERS 0x000F0000       /* Mask for the 4 flexible filters */
2010
2011/* Wake Up Status */
2012#define E1000_WUS_LNKC 0x00000001       /* Link Status Changed */
2013#define E1000_WUS_MAG  0x00000002       /* Magic Packet Received */
2014#define E1000_WUS_EX   0x00000004       /* Directed Exact Received */
2015#define E1000_WUS_MC   0x00000008       /* Directed Multicast Received */
2016#define E1000_WUS_BC   0x00000010       /* Broadcast Received */
2017#define E1000_WUS_ARP  0x00000020       /* ARP Request Packet Received */
2018#define E1000_WUS_IPV4 0x00000040       /* Directed IPv4 Packet Wakeup Received */
2019#define E1000_WUS_IPV6 0x00000080       /* Directed IPv6 Packet Wakeup Received */
2020#define E1000_WUS_FLX0 0x00010000       /* Flexible Filter 0 Match */
2021#define E1000_WUS_FLX1 0x00020000       /* Flexible Filter 1 Match */
2022#define E1000_WUS_FLX2 0x00040000       /* Flexible Filter 2 Match */
2023#define E1000_WUS_FLX3 0x00080000       /* Flexible Filter 3 Match */
2024#define E1000_WUS_FLX_FILTERS 0x000F0000        /* Mask for the 4 flexible filters */
2025
2026/* Management Control */
2027#define E1000_MANC_SMBUS_EN      0x00000001     /* SMBus Enabled - RO */
2028#define E1000_MANC_ASF_EN        0x00000002     /* ASF Enabled - RO */
2029#define E1000_MANC_R_ON_FORCE    0x00000004     /* Reset on Force TCO - RO */
2030#define E1000_MANC_RMCP_EN       0x00000100     /* Enable RCMP 026Fh Filtering */
2031#define E1000_MANC_0298_EN       0x00000200     /* Enable RCMP 0298h Filtering */
2032#define E1000_MANC_IPV4_EN       0x00000400     /* Enable IPv4 */
2033#define E1000_MANC_IPV6_EN       0x00000800     /* Enable IPv6 */
2034#define E1000_MANC_SNAP_EN       0x00001000     /* Accept LLC/SNAP */
2035#define E1000_MANC_ARP_EN        0x00002000     /* Enable ARP Request Filtering */
2036#define E1000_MANC_NEIGHBOR_EN   0x00004000     /* Enable Neighbor Discovery
2037                                                 * Filtering */
2038#define E1000_MANC_ARP_RES_EN    0x00008000     /* Enable ARP response Filtering */
2039#define E1000_MANC_TCO_RESET     0x00010000     /* TCO Reset Occurred */
2040#define E1000_MANC_RCV_TCO_EN    0x00020000     /* Receive TCO Packets Enabled */
2041#define E1000_MANC_REPORT_STATUS 0x00040000     /* Status Reporting Enabled */
2042#define E1000_MANC_RCV_ALL       0x00080000     /* Receive All Enabled */
2043#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000      /* Block phy resets */
2044#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000      /* Enable MAC address
2045                                                         * filtering */
2046#define E1000_MANC_EN_MNG2HOST   0x00200000     /* Enable MNG packets to host
2047                                                 * memory */
2048#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000      /* Enable IP address
2049                                                         * filtering */
2050#define E1000_MANC_EN_XSUM_FILTER   0x00800000  /* Enable checksum filtering */
2051#define E1000_MANC_BR_EN         0x01000000     /* Enable broadcast filtering */
2052#define E1000_MANC_SMB_REQ       0x01000000     /* SMBus Request */
2053#define E1000_MANC_SMB_GNT       0x02000000     /* SMBus Grant */
2054#define E1000_MANC_SMB_CLK_IN    0x04000000     /* SMBus Clock In */
2055#define E1000_MANC_SMB_DATA_IN   0x08000000     /* SMBus Data In */
2056#define E1000_MANC_SMB_DATA_OUT  0x10000000     /* SMBus Data Out */
2057#define E1000_MANC_SMB_CLK_OUT   0x20000000     /* SMBus Clock Out */
2058
2059#define E1000_MANC_SMB_DATA_OUT_SHIFT  28       /* SMBus Data Out Shift */
2060#define E1000_MANC_SMB_CLK_OUT_SHIFT   29       /* SMBus Clock Out Shift */
2061
2062/* SW Semaphore Register */
2063#define E1000_SWSM_SMBI         0x00000001      /* Driver Semaphore bit */
2064#define E1000_SWSM_SWESMBI      0x00000002      /* FW Semaphore bit */
2065#define E1000_SWSM_WMNG         0x00000004      /* Wake MNG Clock */
2066#define E1000_SWSM_DRV_LOAD     0x00000008      /* Driver Loaded Bit */
2067
2068/* FW Semaphore Register */
2069#define E1000_FWSM_MODE_MASK    0x0000000E      /* FW mode */
2070#define E1000_FWSM_MODE_SHIFT            1
2071#define E1000_FWSM_FW_VALID     0x00008000      /* FW established a valid mode */
2072
2073#define E1000_FWSM_RSPCIPHY        0x00000040   /* Reset PHY on PCI reset */
2074#define E1000_FWSM_DISSW           0x10000000   /* FW disable SW Write Access */
2075#define E1000_FWSM_SKUSEL_MASK     0x60000000   /* LAN SKU select */
2076#define E1000_FWSM_SKUEL_SHIFT     29
2077#define E1000_FWSM_SKUSEL_EMB      0x0  /* Embedded SKU */
2078#define E1000_FWSM_SKUSEL_CONS     0x1  /* Consumer SKU */
2079#define E1000_FWSM_SKUSEL_PERF_100 0x2  /* Perf & Corp 10/100 SKU */
2080#define E1000_FWSM_SKUSEL_PERF_GBE 0x3  /* Perf & Copr GbE SKU */
2081
2082/* FFLT Debug Register */
2083#define E1000_FFLT_DBG_INVC     0x00100000      /* Invalid /C/ code handling */
2084
2085typedef enum {
2086        e1000_mng_mode_none = 0,
2087        e1000_mng_mode_asf,
2088        e1000_mng_mode_pt,
2089        e1000_mng_mode_ipmi,
2090        e1000_mng_mode_host_interface_only
2091} e1000_mng_mode;
2092
2093/* Host Interface Control Register */
2094#define E1000_HICR_EN           0x00000001      /* Enable Bit - RO */
2095#define E1000_HICR_C            0x00000002      /* Driver sets this bit when done
2096                                                 * to put command in RAM */
2097#define E1000_HICR_SV           0x00000004      /* Status Validity */
2098#define E1000_HICR_FWR          0x00000080      /* FW reset. Set by the Host */
2099
2100/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2101#define E1000_HI_MAX_DATA_LENGTH         252    /* Host Interface data length */
2102#define E1000_HI_MAX_BLOCK_BYTE_LENGTH  1792    /* Number of bytes in range */
2103#define E1000_HI_MAX_BLOCK_DWORD_LENGTH  448    /* Number of dwords in range */
2104#define E1000_HI_COMMAND_TIMEOUT         500    /* Time in ms to process HI command */
2105
2106struct e1000_host_command_header {
2107        u8 command_id;
2108        u8 command_length;
2109        u8 command_options;     /* I/F bits for command, status for return */
2110        u8 checksum;
2111};
2112struct e1000_host_command_info {
2113        struct e1000_host_command_header command_header;        /* Command Head/Command Result Head has 4 bytes */
2114        u8 command_data[E1000_HI_MAX_DATA_LENGTH];      /* Command data can length 0..252 */
2115};
2116
2117/* Host SMB register #0 */
2118#define E1000_HSMC0R_CLKIN      0x00000001      /* SMB Clock in */
2119#define E1000_HSMC0R_DATAIN     0x00000002      /* SMB Data in */
2120#define E1000_HSMC0R_DATAOUT    0x00000004      /* SMB Data out */
2121#define E1000_HSMC0R_CLKOUT     0x00000008      /* SMB Clock out */
2122
2123/* Host SMB register #1 */
2124#define E1000_HSMC1R_CLKIN      E1000_HSMC0R_CLKIN
2125#define E1000_HSMC1R_DATAIN     E1000_HSMC0R_DATAIN
2126#define E1000_HSMC1R_DATAOUT    E1000_HSMC0R_DATAOUT
2127#define E1000_HSMC1R_CLKOUT     E1000_HSMC0R_CLKOUT
2128
2129/* FW Status Register */
2130#define E1000_FWSTS_FWS_MASK    0x000000FF      /* FW Status */
2131
2132/* Wake Up Packet Length */
2133#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
2134
2135#define E1000_MDALIGN          4096
2136
2137/* PCI-Ex registers*/
2138
2139/* PCI-Ex Control Register */
2140#define E1000_GCR_RXD_NO_SNOOP          0x00000001
2141#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
2142#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
2143#define E1000_GCR_TXD_NO_SNOOP          0x00000008
2144#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
2145#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
2146
2147#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
2148                             E1000_GCR_RXDSCW_NO_SNOOP      | \
2149                             E1000_GCR_RXDSCR_NO_SNOOP      | \
2150                             E1000_GCR_TXD_NO_SNOOP         | \
2151                             E1000_GCR_TXDSCW_NO_SNOOP      | \
2152                             E1000_GCR_TXDSCR_NO_SNOOP)
2153
2154#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2155
2156#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2157/* Function Active and Power State to MNG */
2158#define E1000_FACTPS_FUNC0_POWER_STATE_MASK         0x00000003
2159#define E1000_FACTPS_LAN0_VALID                     0x00000004
2160#define E1000_FACTPS_FUNC0_AUX_EN                   0x00000008
2161#define E1000_FACTPS_FUNC1_POWER_STATE_MASK         0x000000C0
2162#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT        6
2163#define E1000_FACTPS_LAN1_VALID                     0x00000100
2164#define E1000_FACTPS_FUNC1_AUX_EN                   0x00000200
2165#define E1000_FACTPS_FUNC2_POWER_STATE_MASK         0x00003000
2166#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT        12
2167#define E1000_FACTPS_IDE_ENABLE                     0x00004000
2168#define E1000_FACTPS_FUNC2_AUX_EN                   0x00008000
2169#define E1000_FACTPS_FUNC3_POWER_STATE_MASK         0x000C0000
2170#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT        18
2171#define E1000_FACTPS_SP_ENABLE                      0x00100000
2172#define E1000_FACTPS_FUNC3_AUX_EN                   0x00200000
2173#define E1000_FACTPS_FUNC4_POWER_STATE_MASK         0x03000000
2174#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT        24
2175#define E1000_FACTPS_IPMI_ENABLE                    0x04000000
2176#define E1000_FACTPS_FUNC4_AUX_EN                   0x08000000
2177#define E1000_FACTPS_MNGCG                          0x20000000
2178#define E1000_FACTPS_LAN_FUNC_SEL                   0x40000000
2179#define E1000_FACTPS_PM_STATE_CHANGED               0x80000000
2180
2181/* PCI-Ex Config Space */
2182#define PCI_EX_LINK_STATUS           0x12
2183#define PCI_EX_LINK_WIDTH_MASK       0x3F0
2184#define PCI_EX_LINK_WIDTH_SHIFT      4
2185
2186/* EEPROM Commands - Microwire */
2187#define EEPROM_READ_OPCODE_MICROWIRE  0x6       /* EEPROM read opcode */
2188#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5       /* EEPROM write opcode */
2189#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7       /* EEPROM erase opcode */
2190#define EEPROM_EWEN_OPCODE_MICROWIRE  0x13      /* EEPROM erase/write enable */
2191#define EEPROM_EWDS_OPCODE_MICROWIRE  0x10      /* EEPROM erase/write disable */
2192
2193/* EEPROM Commands - SPI */
2194#define EEPROM_MAX_RETRY_SPI        5000        /* Max wait of 5ms, for RDY signal */
2195#define EEPROM_READ_OPCODE_SPI      0x03        /* EEPROM read opcode */
2196#define EEPROM_WRITE_OPCODE_SPI     0x02        /* EEPROM write opcode */
2197#define EEPROM_A8_OPCODE_SPI        0x08        /* opcode bit-3 = address bit-8 */
2198#define EEPROM_WREN_OPCODE_SPI      0x06        /* EEPROM set Write Enable latch */
2199#define EEPROM_WRDI_OPCODE_SPI      0x04        /* EEPROM reset Write Enable latch */
2200#define EEPROM_RDSR_OPCODE_SPI      0x05        /* EEPROM read Status register */
2201#define EEPROM_WRSR_OPCODE_SPI      0x01        /* EEPROM write Status register */
2202#define EEPROM_ERASE4K_OPCODE_SPI   0x20        /* EEPROM ERASE 4KB */
2203#define EEPROM_ERASE64K_OPCODE_SPI  0xD8        /* EEPROM ERASE 64KB */
2204#define EEPROM_ERASE256_OPCODE_SPI  0xDB        /* EEPROM ERASE 256B */
2205
2206/* EEPROM Size definitions */
2207#define EEPROM_WORD_SIZE_SHIFT  6
2208#define EEPROM_SIZE_SHIFT       10
2209#define EEPROM_SIZE_MASK        0x1C00
2210
2211/* EEPROM Word Offsets */
2212#define EEPROM_COMPAT                 0x0003
2213#define EEPROM_ID_LED_SETTINGS        0x0004
2214#define EEPROM_VERSION                0x0005
2215#define EEPROM_SERDES_AMPLITUDE       0x0006    /* For SERDES output amplitude adjustment. */
2216#define EEPROM_PHY_CLASS_WORD         0x0007
2217#define EEPROM_INIT_CONTROL1_REG      0x000A
2218#define EEPROM_INIT_CONTROL2_REG      0x000F
2219#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2220#define EEPROM_INIT_CONTROL3_PORT_B   0x0014
2221#define EEPROM_INIT_3GIO_3            0x001A
2222#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2223#define EEPROM_INIT_CONTROL3_PORT_A   0x0024
2224#define EEPROM_CFG                    0x0012
2225#define EEPROM_FLASH_VERSION          0x0032
2226#define EEPROM_CHECKSUM_REG           0x003F
2227
2228#define E1000_EEPROM_CFG_DONE         0x00040000        /* MNG config cycle done */
2229#define E1000_EEPROM_CFG_DONE_PORT_1  0x00080000        /* ...for second port */
2230
2231/* Word definitions for ID LED Settings */
2232#define ID_LED_RESERVED_0000 0x0000
2233#define ID_LED_RESERVED_FFFF 0xFFFF
2234#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
2235                              (ID_LED_OFF1_OFF2 << 8) | \
2236                              (ID_LED_DEF1_DEF2 << 4) | \
2237                              (ID_LED_DEF1_DEF2))
2238#define ID_LED_DEF1_DEF2     0x1
2239#define ID_LED_DEF1_ON2      0x2
2240#define ID_LED_DEF1_OFF2     0x3
2241#define ID_LED_ON1_DEF2      0x4
2242#define ID_LED_ON1_ON2       0x5
2243#define ID_LED_ON1_OFF2      0x6
2244#define ID_LED_OFF1_DEF2     0x7
2245#define ID_LED_OFF1_ON2      0x8
2246#define ID_LED_OFF1_OFF2     0x9
2247
2248#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
2249#define IGP_ACTIVITY_LED_ENABLE 0x0300
2250#define IGP_LED3_MODE           0x07000000
2251
2252/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2253#define EEPROM_SERDES_AMPLITUDE_MASK  0x000F
2254
2255/* Mask bit for PHY class in Word 7 of the EEPROM */
2256#define EEPROM_PHY_CLASS_A   0x8000
2257
2258/* Mask bits for fields in Word 0x0a of the EEPROM */
2259#define EEPROM_WORD0A_ILOS   0x0010
2260#define EEPROM_WORD0A_SWDPIO 0x01E0
2261#define EEPROM_WORD0A_LRST   0x0200
2262#define EEPROM_WORD0A_FD     0x0400
2263#define EEPROM_WORD0A_66MHZ  0x0800
2264
2265/* Mask bits for fields in Word 0x0f of the EEPROM */
2266#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2267#define EEPROM_WORD0F_PAUSE      0x1000
2268#define EEPROM_WORD0F_ASM_DIR    0x2000
2269#define EEPROM_WORD0F_ANE        0x0800
2270#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2271#define EEPROM_WORD0F_LPLU       0x0001
2272
2273/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2274#define EEPROM_WORD1020_GIGA_DISABLE         0x0010
2275#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2276
2277/* Mask bits for fields in Word 0x1a of the EEPROM */
2278#define EEPROM_WORD1A_ASPM_MASK  0x000C
2279
2280/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2281#define EEPROM_SUM 0xBABA
2282
2283/* EEPROM Map defines (WORD OFFSETS)*/
2284#define EEPROM_NODE_ADDRESS_BYTE_0 0
2285#define EEPROM_PBA_BYTE_1          8
2286
2287#define EEPROM_RESERVED_WORD          0xFFFF
2288
2289/* EEPROM Map Sizes (Byte Counts) */
2290#define PBA_SIZE 4
2291
2292/* Collision related configuration parameters */
2293#define E1000_COLLISION_THRESHOLD       15
2294#define E1000_CT_SHIFT                  4
2295/* Collision distance is a 0-based value that applies to
2296 * half-duplex-capable hardware only. */
2297#define E1000_COLLISION_DISTANCE        63
2298#define E1000_COLLISION_DISTANCE_82542  64
2299#define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
2300#define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
2301#define E1000_COLD_SHIFT                12
2302
2303/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2304#define REQ_TX_DESCRIPTOR_MULTIPLE  8
2305#define REQ_RX_DESCRIPTOR_MULTIPLE  8
2306
2307/* Default values for the transmit IPG register */
2308#define DEFAULT_82542_TIPG_IPGT        10
2309#define DEFAULT_82543_TIPG_IPGT_FIBER  9
2310#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2311
2312#define E1000_TIPG_IPGT_MASK  0x000003FF
2313#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2314#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2315
2316#define DEFAULT_82542_TIPG_IPGR1 2
2317#define DEFAULT_82543_TIPG_IPGR1 8
2318#define E1000_TIPG_IPGR1_SHIFT  10
2319
2320#define DEFAULT_82542_TIPG_IPGR2 10
2321#define DEFAULT_82543_TIPG_IPGR2 6
2322#define E1000_TIPG_IPGR2_SHIFT  20
2323
2324#define E1000_TXDMAC_DPP 0x00000001
2325
2326/* Adaptive IFS defines */
2327#define TX_THRESHOLD_START     8
2328#define TX_THRESHOLD_INCREMENT 10
2329#define TX_THRESHOLD_DECREMENT 1
2330#define TX_THRESHOLD_STOP      190
2331#define TX_THRESHOLD_DISABLE   0
2332#define TX_THRESHOLD_TIMER_MS  10000
2333#define MIN_NUM_XMITS          1000
2334#define IFS_MAX                80
2335#define IFS_STEP               10
2336#define IFS_MIN                40
2337#define IFS_RATIO              4
2338
2339/* Extended Configuration Control and Size */
2340#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2341#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE  0x00000002
2342#define E1000_EXTCNF_CTRL_D_UD_ENABLE       0x00000004
2343#define E1000_EXTCNF_CTRL_D_UD_LATENCY      0x00000008
2344#define E1000_EXTCNF_CTRL_D_UD_OWNER        0x00000010
2345#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2346#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2347#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER   0x0FFF0000
2348
2349#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH    0x000000FF
2350#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH   0x0000FF00
2351#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH   0x00FF0000
2352#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE  0x00000001
2353#define E1000_EXTCNF_CTRL_SWFLAG            0x00000020
2354
2355/* PBA constants */
2356#define E1000_PBA_8K 0x0008     /* 8KB, default Rx allocation */
2357#define E1000_PBA_12K 0x000C    /* 12KB, default Rx allocation */
2358#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
2359#define E1000_PBA_20K 0x0014
2360#define E1000_PBA_22K 0x0016
2361#define E1000_PBA_24K 0x0018
2362#define E1000_PBA_30K 0x001E
2363#define E1000_PBA_32K 0x0020
2364#define E1000_PBA_34K 0x0022
2365#define E1000_PBA_38K 0x0026
2366#define E1000_PBA_40K 0x0028
2367#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
2368
2369#define E1000_PBS_16K E1000_PBA_16K
2370
2371/* Flow Control Constants */
2372#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
2373#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2374#define FLOW_CONTROL_TYPE         0x8808
2375
2376/* The historical defaults for the flow control values are given below. */
2377#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
2378#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
2379#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
2380
2381/* PCIX Config space */
2382#define PCIX_COMMAND_REGISTER    0xE6
2383#define PCIX_STATUS_REGISTER_LO  0xE8
2384#define PCIX_STATUS_REGISTER_HI  0xEA
2385
2386#define PCIX_COMMAND_MMRBC_MASK      0x000C
2387#define PCIX_COMMAND_MMRBC_SHIFT     0x2
2388#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
2389#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
2390#define PCIX_STATUS_HI_MMRBC_4K      0x3
2391#define PCIX_STATUS_HI_MMRBC_2K      0x2
2392
2393/* Number of bits required to shift right the "pause" bits from the
2394 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2395 */
2396#define PAUSE_SHIFT 5
2397
2398/* Number of bits required to shift left the "SWDPIO" bits from the
2399 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2400 */
2401#define SWDPIO_SHIFT 17
2402
2403/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2404 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2405 */
2406#define SWDPIO__EXT_SHIFT 4
2407
2408/* Number of bits required to shift left the "ILOS" bit from the EEPROM
2409 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2410 */
2411#define ILOS_SHIFT  3
2412
2413#define RECEIVE_BUFFER_ALIGN_SIZE  (256)
2414
2415/* Number of milliseconds we wait for auto-negotiation to complete */
2416#define LINK_UP_TIMEOUT             500
2417
2418/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2419#define AUTO_READ_DONE_TIMEOUT      10
2420/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2421#define PHY_CFG_TIMEOUT             100
2422
2423#define E1000_TX_BUFFER_SIZE ((u32)1514)
2424
2425/* The carrier extension symbol, as received by the NIC. */
2426#define CARRIER_EXTENSION   0x0F
2427
2428/* TBI_ACCEPT macro definition:
2429 *
2430 * This macro requires:
2431 *      adapter = a pointer to struct e1000_hw
2432 *      status = the 8 bit status field of the RX descriptor with EOP set
2433 *      error = the 8 bit error field of the RX descriptor with EOP set
2434 *      length = the sum of all the length fields of the RX descriptors that
2435 *               make up the current frame
2436 *      last_byte = the last byte of the frame DMAed by the hardware
2437 *      max_frame_length = the maximum frame length we want to accept.
2438 *      min_frame_length = the minimum frame length we want to accept.
2439 *
2440 * This macro is a conditional that should be used in the interrupt
2441 * handler's Rx processing routine when RxErrors have been detected.
2442 *
2443 * Typical use:
2444 *  ...
2445 *  if (TBI_ACCEPT) {
2446 *      accept_frame = true;
2447 *      e1000_tbi_adjust_stats(adapter, MacAddress);
2448 *      frame_length--;
2449 *  } else {
2450 *      accept_frame = false;
2451 *  }
2452 *  ...
2453 */
2454
2455#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2456    ((adapter)->tbi_compatibility_on && \
2457     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2458     ((last_byte) == CARRIER_EXTENSION) && \
2459     (((status) & E1000_RXD_STAT_VP) ? \
2460          (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2461           ((length) <= ((adapter)->max_frame_size + 1))) : \
2462          (((length) > (adapter)->min_frame_size) && \
2463           ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2464
2465/* Structures, enums, and macros for the PHY */
2466
2467/* Bit definitions for the Management Data IO (MDIO) and Management Data
2468 * Clock (MDC) pins in the Device Control Register.
2469 */
2470#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
2471#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
2472#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
2473#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
2474#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
2475#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
2476#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2477#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
2478
2479/* PHY 1000 MII Register/Bit Definitions */
2480/* PHY Registers defined by IEEE */
2481#define PHY_CTRL         0x00   /* Control Register */
2482#define PHY_STATUS       0x01   /* Status Register */
2483#define PHY_ID1          0x02   /* Phy Id Reg (word 1) */
2484#define PHY_ID2          0x03   /* Phy Id Reg (word 2) */
2485#define PHY_AUTONEG_ADV  0x04   /* Autoneg Advertisement */
2486#define PHY_LP_ABILITY   0x05   /* Link Partner Ability (Base Page) */
2487#define PHY_AUTONEG_EXP  0x06   /* Autoneg Expansion Reg */
2488#define PHY_NEXT_PAGE_TX 0x07   /* Next Page TX */
2489#define PHY_LP_NEXT_PAGE 0x08   /* Link Partner Next Page */
2490#define PHY_1000T_CTRL   0x09   /* 1000Base-T Control Reg */
2491#define PHY_1000T_STATUS 0x0A   /* 1000Base-T Status Reg */
2492#define PHY_EXT_STATUS   0x0F   /* Extended Status Reg */
2493
2494#define MAX_PHY_REG_ADDRESS        0x1F /* 5 bit address bus (0-0x1F) */
2495#define MAX_PHY_MULTI_PAGE_REG     0xF  /* Registers equal on all pages */
2496
2497/* M88E1000 Specific Registers */
2498#define M88E1000_PHY_SPEC_CTRL     0x10 /* PHY Specific Control Register */
2499#define M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */
2500#define M88E1000_INT_ENABLE        0x12 /* Interrupt Enable Register */
2501#define M88E1000_INT_STATUS        0x13 /* Interrupt Status Register */
2502#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2503#define M88E1000_RX_ERR_CNTR       0x15 /* Receive Error Counter */
2504
2505#define M88E1000_PHY_EXT_CTRL      0x1A /* PHY extend control register */
2506#define M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */
2507#define M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */
2508#define M88E1000_PHY_VCO_REG_BIT8  0x100        /* Bits 8 & 11 are adjusted for */
2509#define M88E1000_PHY_VCO_REG_BIT11 0x800        /* improved BER performance */
2510
2511#define IGP01E1000_IEEE_REGS_PAGE  0x0000
2512#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2513#define IGP01E1000_IEEE_FORCE_GIGA      0x0140
2514
2515/* IGP01E1000 Specific Registers */
2516#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2517#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2518#define IGP01E1000_PHY_PORT_CTRL   0x12 /* PHY Specific Control Register */
2519#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2520#define IGP01E1000_GMII_FIFO       0x14 /* GMII FIFO Register */
2521#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15     /* PHY Channel Quality Register */
2522#define IGP02E1000_PHY_POWER_MGMT      0x19
2523#define IGP01E1000_PHY_PAGE_SELECT     0x1F     /* PHY Page Select Core Register */
2524
2525/* IGP01E1000 AGC Registers - stores the cable length values*/
2526#define IGP01E1000_PHY_AGC_A        0x1172
2527#define IGP01E1000_PHY_AGC_B        0x1272
2528#define IGP01E1000_PHY_AGC_C        0x1472
2529#define IGP01E1000_PHY_AGC_D        0x1872
2530
2531/* IGP02E1000 AGC Registers for cable length values */
2532#define IGP02E1000_PHY_AGC_A        0x11B1
2533#define IGP02E1000_PHY_AGC_B        0x12B1
2534#define IGP02E1000_PHY_AGC_C        0x14B1
2535#define IGP02E1000_PHY_AGC_D        0x18B1
2536
2537/* IGP01E1000 DSP Reset Register */
2538#define IGP01E1000_PHY_DSP_RESET   0x1F33
2539#define IGP01E1000_PHY_DSP_SET     0x1F71
2540#define IGP01E1000_PHY_DSP_FFE     0x1F35
2541
2542#define IGP01E1000_PHY_CHANNEL_NUM    4
2543#define IGP02E1000_PHY_CHANNEL_NUM    4
2544
2545#define IGP01E1000_PHY_AGC_PARAM_A    0x1171
2546#define IGP01E1000_PHY_AGC_PARAM_B    0x1271
2547#define IGP01E1000_PHY_AGC_PARAM_C    0x1471
2548#define IGP01E1000_PHY_AGC_PARAM_D    0x1871
2549
2550#define IGP01E1000_PHY_EDAC_MU_INDEX        0xC000
2551#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2552
2553#define IGP01E1000_PHY_ANALOG_TX_STATE      0x2890
2554#define IGP01E1000_PHY_ANALOG_CLASS_A       0x2000
2555#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE  0x0004
2556#define IGP01E1000_PHY_DSP_FFE_CM_CP        0x0069
2557
2558#define IGP01E1000_PHY_DSP_FFE_DEFAULT      0x002A
2559/* IGP01E1000 PCS Initialization register - stores the polarity status when
2560 * speed = 1000 Mbps. */
2561#define IGP01E1000_PHY_PCS_INIT_REG  0x00B4
2562#define IGP01E1000_PHY_PCS_CTRL_REG  0x00B5
2563
2564#define IGP01E1000_ANALOG_REGS_PAGE  0x20C0
2565
2566/* PHY Control Register */
2567#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
2568#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
2569#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
2570#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
2571#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
2572#define MII_CR_POWER_DOWN       0x0800  /* Power down */
2573#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
2574#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
2575#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
2576#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
2577
2578/* PHY Status Register */
2579#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
2580#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
2581#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
2582#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
2583#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
2584#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
2585#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2586#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
2587#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
2588#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
2589#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
2590#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
2591#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
2592#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
2593#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
2594
2595/* Autoneg Advertisement Register */
2596#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
2597#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
2598#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
2599#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
2600#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
2601#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
2602#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
2603#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
2604#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
2605#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
2606
2607/* Link Partner Ability Register (Base Page) */
2608#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2609#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
2610#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
2611#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
2612#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
2613#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
2614#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
2615#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
2616#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
2617#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
2618#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
2619
2620/* Autoneg Expansion Register */
2621#define NWAY_ER_LP_NWAY_CAPS      0x0001        /* LP has Auto Neg Capability */
2622#define NWAY_ER_PAGE_RXD          0x0002        /* LP is 10T   Half Duplex Capable */
2623#define NWAY_ER_NEXT_PAGE_CAPS    0x0004        /* LP is 10T   Full Duplex Capable */
2624#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008        /* LP is 100TX Half Duplex Capable */
2625#define NWAY_ER_PAR_DETECT_FAULT  0x0010        /* LP is 100TX Full Duplex Capable */
2626
2627/* Next Page TX Register */
2628#define NPTX_MSG_CODE_FIELD 0x0001      /* NP msg code or unformatted data */
2629#define NPTX_TOGGLE         0x0800      /* Toggles between exchanges
2630                                         * of different NP
2631                                         */
2632#define NPTX_ACKNOWLDGE2    0x1000      /* 1 = will comply with msg
2633                                         * 0 = cannot comply with msg
2634                                         */
2635#define NPTX_MSG_PAGE       0x2000      /* formatted(1)/unformatted(0) pg */
2636#define NPTX_NEXT_PAGE      0x8000      /* 1 = addition NP will follow
2637                                         * 0 = sending last NP
2638                                         */
2639
2640/* Link Partner Next Page Register */
2641#define LP_RNPR_MSG_CODE_FIELD 0x0001   /* NP msg code or unformatted data */
2642#define LP_RNPR_TOGGLE         0x0800   /* Toggles between exchanges
2643                                         * of different NP
2644                                         */
2645#define LP_RNPR_ACKNOWLDGE2    0x1000   /* 1 = will comply with msg
2646                                         * 0 = cannot comply with msg
2647                                         */
2648#define LP_RNPR_MSG_PAGE       0x2000   /* formatted(1)/unformatted(0) pg */
2649#define LP_RNPR_ACKNOWLDGE     0x4000   /* 1 = ACK / 0 = NO ACK */
2650#define LP_RNPR_NEXT_PAGE      0x8000   /* 1 = addition NP will follow
2651                                         * 0 = sending last NP
2652                                         */
2653
2654/* 1000BASE-T Control Register */
2655#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
2656#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
2657#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
2658#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
2659                                        /* 0=DTE device */
2660#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
2661                                        /* 0=Configure PHY as Slave */
2662#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
2663                                        /* 0=Automatic Master/Slave config */
2664#define CR_1000T_TEST_MODE_NORMAL 0x0000        /* Normal Operation */
2665#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
2666#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
2667#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
2668#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
2669
2670/* 1000BASE-T Status Register */
2671#define SR_1000T_IDLE_ERROR_CNT   0x00FF        /* Num idle errors since last read */
2672#define SR_1000T_ASYM_PAUSE_DIR   0x0100        /* LP asymmetric pause direction bit */
2673#define SR_1000T_LP_HD_CAPS       0x0400        /* LP is 1000T HD capable */
2674#define SR_1000T_LP_FD_CAPS       0x0800        /* LP is 1000T FD capable */
2675#define SR_1000T_REMOTE_RX_STATUS 0x1000        /* Remote receiver OK */
2676#define SR_1000T_LOCAL_RX_STATUS  0x2000        /* Local receiver OK */
2677#define SR_1000T_MS_CONFIG_RES    0x4000        /* 1=Local TX is Master, 0=Slave */
2678#define SR_1000T_MS_CONFIG_FAULT  0x8000        /* Master/Slave config fault */
2679#define SR_1000T_REMOTE_RX_STATUS_SHIFT          12
2680#define SR_1000T_LOCAL_RX_STATUS_SHIFT           13
2681#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT    5
2682#define FFE_IDLE_ERR_COUNT_TIMEOUT_20            20
2683#define FFE_IDLE_ERR_COUNT_TIMEOUT_100           100
2684
2685/* Extended Status Register */
2686#define IEEE_ESR_1000T_HD_CAPS 0x1000   /* 1000T HD capable */
2687#define IEEE_ESR_1000T_FD_CAPS 0x2000   /* 1000T FD capable */
2688#define IEEE_ESR_1000X_HD_CAPS 0x4000   /* 1000X HD capable */
2689#define IEEE_ESR_1000X_FD_CAPS 0x8000   /* 1000X FD capable */
2690
2691#define PHY_TX_POLARITY_MASK   0x0100   /* register 10h bit 8 (polarity bit) */
2692#define PHY_TX_NORMAL_POLARITY 0        /* register 10h bit 8 (normal polarity) */
2693
2694#define AUTO_POLARITY_DISABLE  0x0010   /* register 11h bit 4 */
2695                                      /* (0=enable, 1=disable) */
2696
2697/* M88E1000 PHY Specific Control Register */
2698#define M88E1000_PSCR_JABBER_DISABLE    0x0001  /* 1=Jabber Function disabled */
2699#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002  /* 1=Polarity Reversal enabled */
2700#define M88E1000_PSCR_SQE_TEST          0x0004  /* 1=SQE Test enabled */
2701#define M88E1000_PSCR_CLK125_DISABLE    0x0010  /* 1=CLK125 low,
2702                                                 * 0=CLK125 toggling
2703                                                 */
2704#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000   /* MDI Crossover Mode bits 6:5 */
2705                                               /* Manual MDI configuration */
2706#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020   /* Manual MDIX configuration */
2707#define M88E1000_PSCR_AUTO_X_1000T     0x0040   /* 1000BASE-T: Auto crossover,
2708                                                 *  100BASE-TX/10BASE-T:
2709                                                 *  MDI Mode
2710                                                 */
2711#define M88E1000_PSCR_AUTO_X_MODE      0x0060   /* Auto crossover enabled
2712                                                 * all speeds.
2713                                                 */
2714#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2715                                        /* 1=Enable Extended 10BASE-T distance
2716                                         * (Lower 10BASE-T RX Threshold)
2717                                         * 0=Normal 10BASE-T RX Threshold */
2718#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
2719                                        /* 1=5-Bit interface in 100BASE-TX
2720                                         * 0=MII interface in 100BASE-TX */
2721#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200       /* 1=Scrambler disable */
2722#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400       /* 1=Force link good */
2723#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800       /* 1=Assert CRS on Transmit */
2724
2725#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
2726#define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
2727#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2728
2729/* M88E1000 PHY Specific Status Register */
2730#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
2731#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
2732#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
2733#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
2734#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2735                                                 * 3=110-140M;4=>140M */
2736#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
2737#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
2738#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
2739#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
2740#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
2741#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
2742#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
2743#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
2744
2745#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2746#define M88E1000_PSSR_DOWNSHIFT_SHIFT    5
2747#define M88E1000_PSSR_MDIX_SHIFT         6
2748#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2749
2750/* M88E1000 Extended PHY Specific Control Register */
2751#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000    /* 1=Fiber loopback */
2752#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000    /* 1=Lost lock detect enabled.
2753                                                 * Will assert lost lock and bring
2754                                                 * link down if idle not seen
2755                                                 * within 1ms in 1000BASE-T
2756                                                 */
2757/* Number of times we will attempt to autonegotiate before downshifting if we
2758 * are the master */
2759#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2760#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
2761#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
2762#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
2763#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
2764/* Number of times we will attempt to autonegotiate before downshifting if we
2765 * are the slave */
2766#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
2767#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
2768#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
2769#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
2770#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
2771#define M88E1000_EPSCR_TX_CLK_2_5     0x0060    /* 2.5 MHz TX_CLK */
2772#define M88E1000_EPSCR_TX_CLK_25      0x0070    /* 25  MHz TX_CLK */
2773#define M88E1000_EPSCR_TX_CLK_0       0x0000    /* NO  TX_CLK */
2774
2775/* M88EC018 Rev 2 specific DownShift settings */
2776#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
2777#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X    0x0000
2778#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X    0x0200
2779#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X    0x0400
2780#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X    0x0600
2781#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
2782#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X    0x0A00
2783#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X    0x0C00
2784#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X    0x0E00
2785
2786/* IGP01E1000 Specific Port Config Register - R/W */
2787#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT  0x0010
2788#define IGP01E1000_PSCFR_PRE_EN                0x0020
2789#define IGP01E1000_PSCFR_SMART_SPEED           0x0080
2790#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK    0x0100
2791#define IGP01E1000_PSCFR_DISABLE_JABBER        0x0400
2792#define IGP01E1000_PSCFR_DISABLE_TRANSMIT      0x2000
2793
2794/* IGP01E1000 Specific Port Status Register - R/O */
2795#define IGP01E1000_PSSR_AUTONEG_FAILED         0x0001   /* RO LH SC */
2796#define IGP01E1000_PSSR_POLARITY_REVERSED      0x0002
2797#define IGP01E1000_PSSR_CABLE_LENGTH           0x007C
2798#define IGP01E1000_PSSR_FULL_DUPLEX            0x0200
2799#define IGP01E1000_PSSR_LINK_UP                0x0400
2800#define IGP01E1000_PSSR_MDIX                   0x0800
2801#define IGP01E1000_PSSR_SPEED_MASK             0xC000   /* speed bits mask */
2802#define IGP01E1000_PSSR_SPEED_10MBPS           0x4000
2803#define IGP01E1000_PSSR_SPEED_100MBPS          0x8000
2804#define IGP01E1000_PSSR_SPEED_1000MBPS         0xC000
2805#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT     0x0002   /* shift right 2 */
2806#define IGP01E1000_PSSR_MDIX_SHIFT             0x000B   /* shift right 11 */
2807
2808/* IGP01E1000 Specific Port Control Register - R/W */
2809#define IGP01E1000_PSCR_TP_LOOPBACK            0x0010
2810#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR      0x0200
2811#define IGP01E1000_PSCR_TEN_CRS_SELECT         0x0400
2812#define IGP01E1000_PSCR_FLIP_CHIP              0x0800
2813#define IGP01E1000_PSCR_AUTO_MDIX              0x1000
2814#define IGP01E1000_PSCR_FORCE_MDI_MDIX         0x2000   /* 0-MDI, 1-MDIX */
2815
2816/* IGP01E1000 Specific Port Link Health Register */
2817#define IGP01E1000_PLHR_SS_DOWNGRADE           0x8000
2818#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR    0x4000
2819#define IGP01E1000_PLHR_MASTER_FAULT           0x2000
2820#define IGP01E1000_PLHR_MASTER_RESOLUTION      0x1000
2821#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK       0x0800   /* LH */
2822#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW   0x0400   /* LH */
2823#define IGP01E1000_PLHR_DATA_ERR_1             0x0200   /* LH */
2824#define IGP01E1000_PLHR_DATA_ERR_0             0x0100
2825#define IGP01E1000_PLHR_AUTONEG_FAULT          0x0040
2826#define IGP01E1000_PLHR_AUTONEG_ACTIVE         0x0010
2827#define IGP01E1000_PLHR_VALID_CHANNEL_D        0x0008
2828#define IGP01E1000_PLHR_VALID_CHANNEL_C        0x0004
2829#define IGP01E1000_PLHR_VALID_CHANNEL_B        0x0002
2830#define IGP01E1000_PLHR_VALID_CHANNEL_A        0x0001
2831
2832/* IGP01E1000 Channel Quality Register */
2833#define IGP01E1000_MSE_CHANNEL_D        0x000F
2834#define IGP01E1000_MSE_CHANNEL_C        0x00F0
2835#define IGP01E1000_MSE_CHANNEL_B        0x0F00
2836#define IGP01E1000_MSE_CHANNEL_A        0xF000
2837
2838#define IGP02E1000_PM_SPD                         0x0001        /* Smart Power Down */
2839#define IGP02E1000_PM_D3_LPLU                     0x0004        /* Enable LPLU in non-D0a modes */
2840#define IGP02E1000_PM_D0_LPLU                     0x0002        /* Enable LPLU in D0a mode */
2841
2842/* IGP01E1000 DSP reset macros */
2843#define DSP_RESET_ENABLE     0x0
2844#define DSP_RESET_DISABLE    0x2
2845#define E1000_MAX_DSP_RESETS 10
2846
2847/* IGP01E1000 & IGP02E1000 AGC Registers */
2848
2849#define IGP01E1000_AGC_LENGTH_SHIFT 7   /* Coarse - 13:11, Fine - 10:7 */
2850#define IGP02E1000_AGC_LENGTH_SHIFT 9   /* Coarse - 15:13, Fine - 12:9 */
2851
2852/* IGP02E1000 AGC Register Length 9-bit mask */
2853#define IGP02E1000_AGC_LENGTH_MASK  0x7F
2854
2855/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2856#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2857#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
2858
2859/* The precision error of the cable length is +/- 10 meters */
2860#define IGP01E1000_AGC_RANGE    10
2861#define IGP02E1000_AGC_RANGE    15
2862
2863/* IGP01E1000 PCS Initialization register */
2864/* bits 3:6 in the PCS registers stores the channels polarity */
2865#define IGP01E1000_PHY_POLARITY_MASK    0x0078
2866
2867/* IGP01E1000 GMII FIFO Register */
2868#define IGP01E1000_GMII_FLEX_SPD               0x10     /* Enable flexible speed
2869                                                         * on Link-Up */
2870#define IGP01E1000_GMII_SPD                    0x20     /* Enable SPD */
2871
2872/* IGP01E1000 Analog Register */
2873#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS       0x20D1
2874#define IGP01E1000_ANALOG_FUSE_STATUS             0x20D0
2875#define IGP01E1000_ANALOG_FUSE_CONTROL            0x20DC
2876#define IGP01E1000_ANALOG_FUSE_BYPASS             0x20DE
2877
2878#define IGP01E1000_ANALOG_FUSE_POLY_MASK            0xF000
2879#define IGP01E1000_ANALOG_FUSE_FINE_MASK            0x0F80
2880#define IGP01E1000_ANALOG_FUSE_COARSE_MASK          0x0070
2881#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED        0x0100
2882#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL    0x0002
2883
2884#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH        0x0040
2885#define IGP01E1000_ANALOG_FUSE_COARSE_10            0x0010
2886#define IGP01E1000_ANALOG_FUSE_FINE_1               0x0080
2887#define IGP01E1000_ANALOG_FUSE_FINE_10              0x0500
2888
2889/* Bit definitions for valid PHY IDs. */
2890/* I = Integrated
2891 * E = External
2892 */
2893#define M88_VENDOR         0x0141
2894#define M88E1000_E_PHY_ID  0x01410C50
2895#define M88E1000_I_PHY_ID  0x01410C30
2896#define M88E1011_I_PHY_ID  0x01410C20
2897#define IGP01E1000_I_PHY_ID  0x02A80380
2898#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2899#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2900#define M88E1011_I_REV_4   0x04
2901#define M88E1111_I_PHY_ID  0x01410CC0
2902#define M88E1118_E_PHY_ID  0x01410E40
2903#define L1LXT971A_PHY_ID   0x001378E0
2904
2905#define RTL8211B_PHY_ID    0x001CC910
2906#define RTL8201N_PHY_ID    0x8200
2907#define RTL_PHY_CTRL_FD    0x0100 /* Full duplex.0=half; 1=full */
2908#define RTL_PHY_CTRL_SPD_100    0x200000 /* Force 100Mb */
2909
2910/* Bits...
2911 * 15-5: page
2912 * 4-0: register offset
2913 */
2914#define PHY_PAGE_SHIFT        5
2915#define PHY_REG(page, reg)    \
2916        (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2917
2918#define IGP3_PHY_PORT_CTRL           \
2919        PHY_REG(769, 17)        /* Port General Configuration */
2920#define IGP3_PHY_RATE_ADAPT_CTRL \
2921        PHY_REG(769, 25)        /* Rate Adapter Control Register */
2922
2923#define IGP3_KMRN_FIFO_CTRL_STATS \
2924        PHY_REG(770, 16)        /* KMRN FIFO's control/status register */
2925#define IGP3_KMRN_POWER_MNG_CTRL \
2926        PHY_REG(770, 17)        /* KMRN Power Management Control Register */
2927#define IGP3_KMRN_INBAND_CTRL \
2928        PHY_REG(770, 18)        /* KMRN Inband Control Register */
2929#define IGP3_KMRN_DIAG \
2930        PHY_REG(770, 19)        /* KMRN Diagnostic register */
2931#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002     /* RX PCS is not synced */
2932#define IGP3_KMRN_ACK_TIMEOUT \
2933        PHY_REG(770, 20)        /* KMRN Acknowledge Timeouts register */
2934
2935#define IGP3_VR_CTRL \
2936        PHY_REG(776, 18)        /* Voltage regulator control register */
2937#define IGP3_VR_CTRL_MODE_SHUT       0x0200     /* Enter powerdown, shutdown VRs */
2938#define IGP3_VR_CTRL_MODE_MASK       0x0300     /* Shutdown VR Mask */
2939
2940#define IGP3_CAPABILITY \
2941        PHY_REG(776, 19)        /* IGP3 Capability Register */
2942
2943/* Capabilities for SKU Control  */
2944#define IGP3_CAP_INITIATE_TEAM       0x0001     /* Able to initiate a team */
2945#define IGP3_CAP_WFM                 0x0002     /* Support WoL and PXE */
2946#define IGP3_CAP_ASF                 0x0004     /* Support ASF */
2947#define IGP3_CAP_LPLU                0x0008     /* Support Low Power Link Up */
2948#define IGP3_CAP_DC_AUTO_SPEED       0x0010     /* Support AC/DC Auto Link Speed */
2949#define IGP3_CAP_SPD                 0x0020     /* Support Smart Power Down */
2950#define IGP3_CAP_MULT_QUEUE          0x0040     /* Support 2 tx & 2 rx queues */
2951#define IGP3_CAP_RSS                 0x0080     /* Support RSS */
2952#define IGP3_CAP_8021PQ              0x0100     /* Support 802.1Q & 802.1p */
2953#define IGP3_CAP_AMT_CB              0x0200     /* Support active manageability and circuit breaker */
2954
2955#define IGP3_PPC_JORDAN_EN           0x0001
2956#define IGP3_PPC_JORDAN_GIGA_SPEED   0x0002
2957
2958#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS         0x0001
2959#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK   0x001E
2960#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA        0x0020
2961#define IGP3_KMRN_PMC_K0S_MODE1_EN_100         0x0040
2962
2963#define IGP3E1000_PHY_MISC_CTRL                0x1B     /* Misc. Ctrl register */
2964#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET        0x1000   /* Duplex Manual Set */
2965
2966#define IGP3_KMRN_EXT_CTRL  PHY_REG(770, 18)
2967#define IGP3_KMRN_EC_DIS_INBAND    0x0080
2968
2969#define IGP03E1000_E_PHY_ID  0x02A80390
2970#define IFE_E_PHY_ID         0x02A80330 /* 10/100 PHY */
2971#define IFE_PLUS_E_PHY_ID    0x02A80320
2972#define IFE_C_E_PHY_ID       0x02A80310
2973
2974#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10  /* 100BaseTx Extended Status, Control and Address */
2975#define IFE_PHY_SPECIAL_CONTROL           0x11  /* 100BaseTx PHY special control register */
2976#define IFE_PHY_RCV_FALSE_CARRIER         0x13  /* 100BaseTx Receive False Carrier Counter */
2977#define IFE_PHY_RCV_DISCONNECT            0x14  /* 100BaseTx Receive Disconnect Counter */
2978#define IFE_PHY_RCV_ERROT_FRAME           0x15  /* 100BaseTx Receive Error Frame Counter */
2979#define IFE_PHY_RCV_SYMBOL_ERR            0x16  /* Receive Symbol Error Counter */
2980#define IFE_PHY_PREM_EOF_ERR              0x17  /* 100BaseTx Receive Premature End Of Frame Error Counter */
2981#define IFE_PHY_RCV_EOF_ERR               0x18  /* 10BaseT Receive End Of Frame Error Counter */
2982#define IFE_PHY_TX_JABBER_DETECT          0x19  /* 10BaseT Transmit Jabber Detect Counter */
2983#define IFE_PHY_EQUALIZER                 0x1A  /* PHY Equalizer Control and Status */
2984#define IFE_PHY_SPECIAL_CONTROL_LED       0x1B  /* PHY special control and LED configuration */
2985#define IFE_PHY_MDIX_CONTROL              0x1C  /* MDI/MDI-X Control register */
2986#define IFE_PHY_HWI_CONTROL               0x1D  /* Hardware Integrity Control (HWI) */
2987
2988#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE  0x2000     /* Default 1 = Disable auto reduced power down */
2989#define IFE_PESC_100BTX_POWER_DOWN           0x0400     /* Indicates the power state of 100BASE-TX */
2990#define IFE_PESC_10BTX_POWER_DOWN            0x0200     /* Indicates the power state of 10BASE-T */
2991#define IFE_PESC_POLARITY_REVERSED           0x0100     /* Indicates 10BASE-T polarity */
2992#define IFE_PESC_PHY_ADDR_MASK               0x007C     /* Bit 6:2 for sampled PHY address */
2993#define IFE_PESC_SPEED                       0x0002     /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
2994#define IFE_PESC_DUPLEX                      0x0001     /* Auto-negotiation duplex result 1=Full, 0=Half */
2995#define IFE_PESC_POLARITY_REVERSED_SHIFT     8
2996
2997#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN   0x0100     /* 1 = Dynamic Power Down disabled */
2998#define IFE_PSC_FORCE_POLARITY               0x0020     /* 1=Reversed Polarity, 0=Normal */
2999#define IFE_PSC_AUTO_POLARITY_DISABLE        0x0010     /* 1=Auto Polarity Disabled, 0=Enabled */
3000#define IFE_PSC_JABBER_FUNC_DISABLE          0x0001     /* 1=Jabber Disabled, 0=Normal Jabber Operation */

3001#define IFE_PSC_FORCE_POLARITY_SHIFT         5
3002#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT  4
3003
3004#define IFE_PMC_AUTO_MDIX                    0x0080     /* 1=enable MDI/MDI-X feature, default 0=disabled */
3005#define IFE_PMC_FORCE_MDIX                   0x0040     /* 1=force MDIX-X, 0=force MDI */
3006#define IFE_PMC_MDIX_STATUS                  0x0020     /* 1=MDI-X, 0=MDI */
3007#define IFE_PMC_AUTO_MDIX_COMPLETE           0x0010     /* Resolution algorithm is completed */
3008#define IFE_PMC_MDIX_MODE_SHIFT              6
3009#define IFE_PHC_MDIX_RESET_ALL_MASK          0x0000     /* Disable auto MDI-X */
3010
3011#define IFE_PHC_HWI_ENABLE                   0x8000     /* Enable the HWI feature */
3012#define IFE_PHC_ABILITY_CHECK                0x4000     /* 1= Test Passed, 0=failed */
3013#define IFE_PHC_TEST_EXEC                    0x2000     /* PHY launch test pulses on the wire */
3014#define IFE_PHC_HIGHZ                        0x0200     /* 1 = Open Circuit */
3015#define IFE_PHC_LOWZ                         0x0400     /* 1 = Short Circuit */
3016#define IFE_PHC_LOW_HIGH_Z_MASK              0x0600     /* Mask for indication type of problem on the line */
3017#define IFE_PHC_DISTANCE_MASK                0x01FF     /* Mask for distance to the cable problem, in 80cm granularity */
3018#define IFE_PHC_RESET_ALL_MASK               0x0000     /* Disable HWI */
3019#define IFE_PSCL_PROBE_MODE                  0x0020     /* LED Probe mode */
3020#define IFE_PSCL_PROBE_LEDS_OFF              0x0006     /* Force LEDs 0 and 2 off */
3021#define IFE_PSCL_PROBE_LEDS_ON               0x0007     /* Force LEDs 0 and 2 on */
3022
3023#define ICH_FLASH_COMMAND_TIMEOUT            5000       /* 5000 uSecs - adjusted */
3024#define ICH_FLASH_ERASE_TIMEOUT              3000000    /* Up to 3 seconds - worst case */
3025#define ICH_FLASH_CYCLE_REPEAT_COUNT         10 /* 10 cycles */
3026#define ICH_FLASH_SEG_SIZE_256               256
3027#define ICH_FLASH_SEG_SIZE_4K                4096
3028#define ICH_FLASH_SEG_SIZE_64K               65536
3029
3030#define ICH_CYCLE_READ                       0x0
3031#define ICH_CYCLE_RESERVED                   0x1
3032#define ICH_CYCLE_WRITE                      0x2
3033#define ICH_CYCLE_ERASE                      0x3
3034
3035#define ICH_FLASH_GFPREG   0x0000
3036#define ICH_FLASH_HSFSTS   0x0004
3037#define ICH_FLASH_HSFCTL   0x0006
3038#define ICH_FLASH_FADDR    0x0008
3039#define ICH_FLASH_FDATA0   0x0010
3040#define ICH_FLASH_FRACC    0x0050
3041#define ICH_FLASH_FREG0    0x0054
3042#define ICH_FLASH_FREG1    0x0058
3043#define ICH_FLASH_FREG2    0x005C
3044#define ICH_FLASH_FREG3    0x0060
3045#define ICH_FLASH_FPR0     0x0074
3046#define ICH_FLASH_FPR1     0x0078
3047#define ICH_FLASH_SSFSTS   0x0090
3048#define ICH_FLASH_SSFCTL   0x0092
3049#define ICH_FLASH_PREOP    0x0094
3050#define ICH_FLASH_OPTYPE   0x0096
3051#define ICH_FLASH_OPMENU   0x0098
3052
3053#define ICH_FLASH_REG_MAPSIZE      0x00A0
3054#define ICH_FLASH_SECTOR_SIZE      4096
3055#define ICH_GFPREG_BASE_MASK       0x1FFF
3056#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3057
3058/* Miscellaneous PHY bit definitions. */
3059#define PHY_PREAMBLE        0xFFFFFFFF
3060#define PHY_SOF             0x01
3061#define PHY_OP_READ         0x02
3062#define PHY_OP_WRITE        0x01
3063#define PHY_TURNAROUND      0x02
3064#define PHY_PREAMBLE_SIZE   32
3065#define MII_CR_SPEED_1000   0x0040
3066#define MII_CR_SPEED_100    0x2000
3067#define MII_CR_SPEED_10     0x0000
3068#define E1000_PHY_ADDRESS   0x01
3069#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
3070#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
3071#define PHY_REVISION_MASK   0xFFFFFFF0
3072#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
3073#define REG4_SPEED_MASK     0x01E0
3074#define REG9_SPEED_MASK     0x0300
3075#define ADVERTISE_10_HALF   0x0001
3076#define ADVERTISE_10_FULL   0x0002
3077#define ADVERTISE_100_HALF  0x0004
3078#define ADVERTISE_100_FULL  0x0008
3079#define ADVERTISE_1000_HALF 0x0010
3080#define ADVERTISE_1000_FULL 0x0020
3081#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
3082#define AUTONEG_ADVERTISE_10_100_ALL    0x000F  /* All 10/100 speeds */
3083#define AUTONEG_ADVERTISE_10_ALL        0x0003  /* 10Mbps Full & Half speeds */
3084
3085#endif /* _E1000_HW_H_ */
3086
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.