LXR linux/drivers/net/ethernet/intel/i40e/i40e_adminq

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4#ifndef _I40E_ADMINQ_CMD_H_
   5#define _I40E_ADMINQ_CMD_H_
   6
   7/* This header file defines the i40e Admin Queue commands and is shared between
   8 * i40e Firmware and Software.
   9 *
  10 * This file needs to comply with the Linux Kernel coding style.
  11 */
  12
  13#define I40E_FW_API_VERSION_MAJOR       0x0001
  14#define I40E_FW_API_VERSION_MINOR_X722  0x0008
  15#define I40E_FW_API_VERSION_MINOR_X710  0x0008
  16
  17#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
  18                                        I40E_FW_API_VERSION_MINOR_X710 : \
  19                                        I40E_FW_API_VERSION_MINOR_X722)
  20
  21/* API version 1.7 implements additional link and PHY-specific APIs  */
  22#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
  23/* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
  24#define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
  25
  26struct i40e_aq_desc {
  27        __le16 flags;
  28        __le16 opcode;
  29        __le16 datalen;
  30        __le16 retval;
  31        __le32 cookie_high;
  32        __le32 cookie_low;
  33        union {
  34                struct {
  35                        __le32 param0;
  36                        __le32 param1;
  37                        __le32 param2;
  38                        __le32 param3;
  39                } internal;
  40                struct {
  41                        __le32 param0;
  42                        __le32 param1;
  43                        __le32 addr_high;
  44                        __le32 addr_low;
  45                } external;
  46                u8 raw[16];
  47        } params;
  48};
  49
  50/* Flags sub-structure
  51 * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
  52 * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  53 */
  54
  55/* command flags and offsets*/
  56#define I40E_AQ_FLAG_DD_SHIFT   0
  57#define I40E_AQ_FLAG_CMP_SHIFT  1
  58#define I40E_AQ_FLAG_ERR_SHIFT  2
  59#define I40E_AQ_FLAG_VFE_SHIFT  3
  60#define I40E_AQ_FLAG_LB_SHIFT   9
  61#define I40E_AQ_FLAG_RD_SHIFT   10
  62#define I40E_AQ_FLAG_VFC_SHIFT  11
  63#define I40E_AQ_FLAG_BUF_SHIFT  12
  64#define I40E_AQ_FLAG_SI_SHIFT   13
  65#define I40E_AQ_FLAG_EI_SHIFT   14
  66#define I40E_AQ_FLAG_FE_SHIFT   15
  67
  68#define I40E_AQ_FLAG_DD         BIT(I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
  69#define I40E_AQ_FLAG_CMP        BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
  70#define I40E_AQ_FLAG_ERR        BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
  71#define I40E_AQ_FLAG_VFE        BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
  72#define I40E_AQ_FLAG_LB         BIT(I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
  73#define I40E_AQ_FLAG_RD         BIT(I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
  74#define I40E_AQ_FLAG_VFC        BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
  75#define I40E_AQ_FLAG_BUF        BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
  76#define I40E_AQ_FLAG_SI         BIT(I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
  77#define I40E_AQ_FLAG_EI         BIT(I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
  78#define I40E_AQ_FLAG_FE         BIT(I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
  79
  80/* error codes */
  81enum i40e_admin_queue_err {
  82        I40E_AQ_RC_OK           = 0,  /* success */
  83        I40E_AQ_RC_EPERM        = 1,  /* Operation not permitted */
  84        I40E_AQ_RC_ENOENT       = 2,  /* No such element */
  85        I40E_AQ_RC_ESRCH        = 3,  /* Bad opcode */
  86        I40E_AQ_RC_EINTR        = 4,  /* operation interrupted */
  87        I40E_AQ_RC_EIO          = 5,  /* I/O error */
  88        I40E_AQ_RC_ENXIO        = 6,  /* No such resource */
  89        I40E_AQ_RC_E2BIG        = 7,  /* Arg too long */
  90        I40E_AQ_RC_EAGAIN       = 8,  /* Try again */
  91        I40E_AQ_RC_ENOMEM       = 9,  /* Out of memory */
  92        I40E_AQ_RC_EACCES       = 10, /* Permission denied */
  93        I40E_AQ_RC_EFAULT       = 11, /* Bad address */
  94        I40E_AQ_RC_EBUSY        = 12, /* Device or resource busy */
  95        I40E_AQ_RC_EEXIST       = 13, /* object already exists */
  96        I40E_AQ_RC_EINVAL       = 14, /* Invalid argument */
  97        I40E_AQ_RC_ENOTTY       = 15, /* Not a typewriter */
  98        I40E_AQ_RC_ENOSPC       = 16, /* No space left or alloc failure */
  99        I40E_AQ_RC_ENOSYS       = 17, /* Function not implemented */
 100        I40E_AQ_RC_ERANGE       = 18, /* Parameter out of range */
 101        I40E_AQ_RC_EFLUSHED     = 19, /* Cmd flushed due to prev cmd error */
 102        I40E_AQ_RC_BAD_ADDR     = 20, /* Descriptor contains a bad pointer */
 103        I40E_AQ_RC_EMODE        = 21, /* Op not allowed in current dev mode */
 104        I40E_AQ_RC_EFBIG        = 22, /* File too large */
 105};
 106
 107/* Admin Queue command opcodes */
 108enum i40e_admin_queue_opc {
 109        /* aq commands */
 110        i40e_aqc_opc_get_version        = 0x0001,
 111        i40e_aqc_opc_driver_version     = 0x0002,
 112        i40e_aqc_opc_queue_shutdown     = 0x0003,
 113        i40e_aqc_opc_set_pf_context     = 0x0004,
 114
 115        /* resource ownership */
 116        i40e_aqc_opc_request_resource   = 0x0008,
 117        i40e_aqc_opc_release_resource   = 0x0009,
 118
 119        i40e_aqc_opc_list_func_capabilities     = 0x000A,
 120        i40e_aqc_opc_list_dev_capabilities      = 0x000B,
 121
 122        /* Proxy commands */
 123        i40e_aqc_opc_set_proxy_config           = 0x0104,
 124        i40e_aqc_opc_set_ns_proxy_table_entry   = 0x0105,
 125
 126        /* LAA */
 127        i40e_aqc_opc_mac_address_read   = 0x0107,
 128        i40e_aqc_opc_mac_address_write  = 0x0108,
 129
 130        /* PXE */
 131        i40e_aqc_opc_clear_pxe_mode     = 0x0110,
 132
 133        /* WoL commands */
 134        i40e_aqc_opc_set_wol_filter     = 0x0120,
 135        i40e_aqc_opc_get_wake_reason    = 0x0121,
 136
 137        /* internal switch commands */
 138        i40e_aqc_opc_get_switch_config          = 0x0200,
 139        i40e_aqc_opc_add_statistics             = 0x0201,
 140        i40e_aqc_opc_remove_statistics          = 0x0202,
 141        i40e_aqc_opc_set_port_parameters        = 0x0203,
 142        i40e_aqc_opc_get_switch_resource_alloc  = 0x0204,
 143        i40e_aqc_opc_set_switch_config          = 0x0205,
 144        i40e_aqc_opc_rx_ctl_reg_read            = 0x0206,
 145        i40e_aqc_opc_rx_ctl_reg_write           = 0x0207,
 146
 147        i40e_aqc_opc_add_vsi                    = 0x0210,
 148        i40e_aqc_opc_update_vsi_parameters      = 0x0211,
 149        i40e_aqc_opc_get_vsi_parameters         = 0x0212,
 150
 151        i40e_aqc_opc_add_pv                     = 0x0220,
 152        i40e_aqc_opc_update_pv_parameters       = 0x0221,
 153        i40e_aqc_opc_get_pv_parameters          = 0x0222,
 154
 155        i40e_aqc_opc_add_veb                    = 0x0230,
 156        i40e_aqc_opc_update_veb_parameters      = 0x0231,
 157        i40e_aqc_opc_get_veb_parameters         = 0x0232,
 158
 159        i40e_aqc_opc_delete_element             = 0x0243,
 160
 161        i40e_aqc_opc_add_macvlan                = 0x0250,
 162        i40e_aqc_opc_remove_macvlan             = 0x0251,
 163        i40e_aqc_opc_add_vlan                   = 0x0252,
 164        i40e_aqc_opc_remove_vlan                = 0x0253,
 165        i40e_aqc_opc_set_vsi_promiscuous_modes  = 0x0254,
 166        i40e_aqc_opc_add_tag                    = 0x0255,
 167        i40e_aqc_opc_remove_tag                 = 0x0256,
 168        i40e_aqc_opc_add_multicast_etag         = 0x0257,
 169        i40e_aqc_opc_remove_multicast_etag      = 0x0258,
 170        i40e_aqc_opc_update_tag                 = 0x0259,
 171        i40e_aqc_opc_add_control_packet_filter  = 0x025A,
 172        i40e_aqc_opc_remove_control_packet_filter       = 0x025B,
 173        i40e_aqc_opc_add_cloud_filters          = 0x025C,
 174        i40e_aqc_opc_remove_cloud_filters       = 0x025D,
 175        i40e_aqc_opc_clear_wol_switch_filters   = 0x025E,
 176
 177        i40e_aqc_opc_add_mirror_rule    = 0x0260,
 178        i40e_aqc_opc_delete_mirror_rule = 0x0261,
 179
 180        /* Dynamic Device Personalization */
 181        i40e_aqc_opc_write_personalization_profile      = 0x0270,
 182        i40e_aqc_opc_get_personalization_profile_list   = 0x0271,
 183
 184        /* DCB commands */
 185        i40e_aqc_opc_dcb_ignore_pfc     = 0x0301,
 186        i40e_aqc_opc_dcb_updated        = 0x0302,
 187        i40e_aqc_opc_set_dcb_parameters = 0x0303,
 188
 189        /* TX scheduler */
 190        i40e_aqc_opc_configure_vsi_bw_limit             = 0x0400,
 191        i40e_aqc_opc_configure_vsi_ets_sla_bw_limit     = 0x0406,
 192        i40e_aqc_opc_configure_vsi_tc_bw                = 0x0407,
 193        i40e_aqc_opc_query_vsi_bw_config                = 0x0408,
 194        i40e_aqc_opc_query_vsi_ets_sla_config           = 0x040A,
 195        i40e_aqc_opc_configure_switching_comp_bw_limit  = 0x0410,
 196
 197        i40e_aqc_opc_enable_switching_comp_ets                  = 0x0413,
 198        i40e_aqc_opc_modify_switching_comp_ets                  = 0x0414,
 199        i40e_aqc_opc_disable_switching_comp_ets                 = 0x0415,
 200        i40e_aqc_opc_configure_switching_comp_ets_bw_limit      = 0x0416,
 201        i40e_aqc_opc_configure_switching_comp_bw_config         = 0x0417,
 202        i40e_aqc_opc_query_switching_comp_ets_config            = 0x0418,
 203        i40e_aqc_opc_query_port_ets_config                      = 0x0419,
 204        i40e_aqc_opc_query_switching_comp_bw_config             = 0x041A,
 205        i40e_aqc_opc_suspend_port_tx                            = 0x041B,
 206        i40e_aqc_opc_resume_port_tx                             = 0x041C,
 207        i40e_aqc_opc_configure_partition_bw                     = 0x041D,
 208        /* hmc */
 209        i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
 210        i40e_aqc_opc_set_hmc_resource_profile   = 0x0501,
 211
 212        /* phy commands*/
 213        i40e_aqc_opc_get_phy_abilities          = 0x0600,
 214        i40e_aqc_opc_set_phy_config             = 0x0601,
 215        i40e_aqc_opc_set_mac_config             = 0x0603,
 216        i40e_aqc_opc_set_link_restart_an        = 0x0605,
 217        i40e_aqc_opc_get_link_status            = 0x0607,
 218        i40e_aqc_opc_set_phy_int_mask           = 0x0613,
 219        i40e_aqc_opc_get_local_advt_reg         = 0x0614,
 220        i40e_aqc_opc_set_local_advt_reg         = 0x0615,
 221        i40e_aqc_opc_get_partner_advt           = 0x0616,
 222        i40e_aqc_opc_set_lb_modes               = 0x0618,
 223        i40e_aqc_opc_get_phy_wol_caps           = 0x0621,
 224        i40e_aqc_opc_set_phy_debug              = 0x0622,
 225        i40e_aqc_opc_upload_ext_phy_fm          = 0x0625,
 226        i40e_aqc_opc_run_phy_activity           = 0x0626,
 227        i40e_aqc_opc_set_phy_register           = 0x0628,
 228        i40e_aqc_opc_get_phy_register           = 0x0629,
 229
 230        /* NVM commands */
 231        i40e_aqc_opc_nvm_read                   = 0x0701,
 232        i40e_aqc_opc_nvm_erase                  = 0x0702,
 233        i40e_aqc_opc_nvm_update                 = 0x0703,
 234        i40e_aqc_opc_nvm_config_read            = 0x0704,
 235        i40e_aqc_opc_nvm_config_write           = 0x0705,
 236        i40e_aqc_opc_oem_post_update            = 0x0720,
 237        i40e_aqc_opc_thermal_sensor             = 0x0721,
 238
 239        /* virtualization commands */
 240        i40e_aqc_opc_send_msg_to_pf             = 0x0801,
 241        i40e_aqc_opc_send_msg_to_vf             = 0x0802,
 242        i40e_aqc_opc_send_msg_to_peer           = 0x0803,
 243
 244        /* alternate structure */
 245        i40e_aqc_opc_alternate_write            = 0x0900,
 246        i40e_aqc_opc_alternate_write_indirect   = 0x0901,
 247        i40e_aqc_opc_alternate_read             = 0x0902,
 248        i40e_aqc_opc_alternate_read_indirect    = 0x0903,
 249        i40e_aqc_opc_alternate_write_done       = 0x0904,
 250        i40e_aqc_opc_alternate_set_mode         = 0x0905,
 251        i40e_aqc_opc_alternate_clear_port       = 0x0906,
 252
 253        /* LLDP commands */
 254        i40e_aqc_opc_lldp_get_mib       = 0x0A00,
 255        i40e_aqc_opc_lldp_update_mib    = 0x0A01,
 256        i40e_aqc_opc_lldp_add_tlv       = 0x0A02,
 257        i40e_aqc_opc_lldp_update_tlv    = 0x0A03,
 258        i40e_aqc_opc_lldp_delete_tlv    = 0x0A04,
 259        i40e_aqc_opc_lldp_stop          = 0x0A05,
 260        i40e_aqc_opc_lldp_start         = 0x0A06,
 261        i40e_aqc_opc_get_cee_dcb_cfg    = 0x0A07,
 262        i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
 263        i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
 264        i40e_aqc_opc_lldp_restore               = 0x0A0A,
 265
 266        /* Tunnel commands */
 267        i40e_aqc_opc_add_udp_tunnel     = 0x0B00,
 268        i40e_aqc_opc_del_udp_tunnel     = 0x0B01,
 269        i40e_aqc_opc_set_rss_key        = 0x0B02,
 270        i40e_aqc_opc_set_rss_lut        = 0x0B03,
 271        i40e_aqc_opc_get_rss_key        = 0x0B04,
 272        i40e_aqc_opc_get_rss_lut        = 0x0B05,
 273
 274        /* Async Events */
 275        i40e_aqc_opc_event_lan_overflow         = 0x1001,
 276
 277        /* OEM commands */
 278        i40e_aqc_opc_oem_parameter_change       = 0xFE00,
 279        i40e_aqc_opc_oem_device_status_change   = 0xFE01,
 280        i40e_aqc_opc_oem_ocsd_initialize        = 0xFE02,
 281        i40e_aqc_opc_oem_ocbb_initialize        = 0xFE03,
 282
 283        /* debug commands */
 284        i40e_aqc_opc_debug_read_reg             = 0xFF03,
 285        i40e_aqc_opc_debug_write_reg            = 0xFF04,
 286        i40e_aqc_opc_debug_modify_reg           = 0xFF07,
 287        i40e_aqc_opc_debug_dump_internals       = 0xFF08,
 288};
 289
 290/* command structures and indirect data structures */
 291
 292/* Structure naming conventions:
 293 * - no suffix for direct command descriptor structures
 294 * - _data for indirect sent data
 295 * - _resp for indirect return data (data which is both will use _data)
 296 * - _completion for direct return data
 297 * - _element_ for repeated elements (may also be _data or _resp)
 298 *
 299 * Command structures are expected to overlay the params.raw member of the basic
 300 * descriptor, and as such cannot exceed 16 bytes in length.
 301 */
 302
 303/* This macro is used to generate a compilation error if a structure
 304 * is not exactly the correct length. It gives a divide by zero error if the
 305 * structure is not of the correct size, otherwise it creates an enum that is
 306 * never used.
 307 */
 308#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
 309        { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
 310
 311/* This macro is used extensively to ensure that command structures are 16
 312 * bytes in length as they have to map to the raw array of that size.
 313 */
 314#define I40E_CHECK_CMD_LENGTH(X)        I40E_CHECK_STRUCT_LEN(16, X)
 315
 316/* internal (0x00XX) commands */
 317
 318/* Get version (direct 0x0001) */
 319struct i40e_aqc_get_version {
 320        __le32 rom_ver;
 321        __le32 fw_build;
 322        __le16 fw_major;
 323        __le16 fw_minor;
 324        __le16 api_major;
 325        __le16 api_minor;
 326};
 327
 328I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
 329
 330/* Send driver version (indirect 0x0002) */
 331struct i40e_aqc_driver_version {
 332        u8      driver_major_ver;
 333        u8      driver_minor_ver;
 334        u8      driver_build_ver;
 335        u8      driver_subbuild_ver;
 336        u8      reserved[4];
 337        __le32  address_high;
 338        __le32  address_low;
 339};
 340
 341I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
 342
 343/* Queue Shutdown (direct 0x0003) */
 344struct i40e_aqc_queue_shutdown {
 345        __le32  driver_unloading;
 346#define I40E_AQ_DRIVER_UNLOADING        0x1
 347        u8      reserved[12];
 348};
 349
 350I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
 351
 352/* Set PF context (0x0004, direct) */
 353struct i40e_aqc_set_pf_context {
 354        u8      pf_id;
 355        u8      reserved[15];
 356};
 357
 358I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
 359
 360/* Request resource ownership (direct 0x0008)
 361 * Release resource ownership (direct 0x0009)
 362 */
 363#define I40E_AQ_RESOURCE_NVM                    1
 364#define I40E_AQ_RESOURCE_SDP                    2
 365#define I40E_AQ_RESOURCE_ACCESS_READ            1
 366#define I40E_AQ_RESOURCE_ACCESS_WRITE           2
 367#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT       3000
 368#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT      180000
 369
 370struct i40e_aqc_request_resource {
 371        __le16  resource_id;
 372        __le16  access_type;
 373        __le32  timeout;
 374        __le32  resource_number;
 375        u8      reserved[4];
 376};
 377
 378I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
 379
 380/* Get function capabilities (indirect 0x000A)
 381 * Get device capabilities (indirect 0x000B)
 382 */
 383struct i40e_aqc_list_capabilites {
 384        u8 command_flags;
 385#define I40E_AQ_LIST_CAP_PF_INDEX_EN    1
 386        u8 pf_index;
 387        u8 reserved[2];
 388        __le32 count;
 389        __le32 addr_high;
 390        __le32 addr_low;
 391};
 392
 393I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
 394
 395struct i40e_aqc_list_capabilities_element_resp {
 396        __le16  id;
 397        u8      major_rev;
 398        u8      minor_rev;
 399        __le32  number;
 400        __le32  logical_id;
 401        __le32  phys_id;
 402        u8      reserved[16];
 403};
 404
 405/* list of caps */
 406
 407#define I40E_AQ_CAP_ID_SWITCH_MODE      0x0001
 408#define I40E_AQ_CAP_ID_MNG_MODE         0x0002
 409#define I40E_AQ_CAP_ID_NPAR_ACTIVE      0x0003
 410#define I40E_AQ_CAP_ID_OS2BMC_CAP       0x0004
 411#define I40E_AQ_CAP_ID_FUNCTIONS_VALID  0x0005
 412#define I40E_AQ_CAP_ID_ALTERNATE_RAM    0x0006
 413#define I40E_AQ_CAP_ID_WOL_AND_PROXY    0x0008
 414#define I40E_AQ_CAP_ID_SRIOV            0x0012
 415#define I40E_AQ_CAP_ID_VF               0x0013
 416#define I40E_AQ_CAP_ID_VMDQ             0x0014
 417#define I40E_AQ_CAP_ID_8021QBG          0x0015
 418#define I40E_AQ_CAP_ID_8021QBR          0x0016
 419#define I40E_AQ_CAP_ID_VSI              0x0017
 420#define I40E_AQ_CAP_ID_DCB              0x0018
 421#define I40E_AQ_CAP_ID_FCOE             0x0021
 422#define I40E_AQ_CAP_ID_ISCSI            0x0022
 423#define I40E_AQ_CAP_ID_RSS              0x0040
 424#define I40E_AQ_CAP_ID_RXQ              0x0041
 425#define I40E_AQ_CAP_ID_TXQ              0x0042
 426#define I40E_AQ_CAP_ID_MSIX             0x0043
 427#define I40E_AQ_CAP_ID_VF_MSIX          0x0044
 428#define I40E_AQ_CAP_ID_FLOW_DIRECTOR    0x0045
 429#define I40E_AQ_CAP_ID_1588             0x0046
 430#define I40E_AQ_CAP_ID_IWARP            0x0051
 431#define I40E_AQ_CAP_ID_LED              0x0061
 432#define I40E_AQ_CAP_ID_SDP              0x0062
 433#define I40E_AQ_CAP_ID_MDIO             0x0063
 434#define I40E_AQ_CAP_ID_WSR_PROT         0x0064
 435#define I40E_AQ_CAP_ID_NVM_MGMT         0x0080
 436#define I40E_AQ_CAP_ID_FLEX10           0x00F1
 437#define I40E_AQ_CAP_ID_CEM              0x00F2
 438
 439/* Set CPPM Configuration (direct 0x0103) */
 440struct i40e_aqc_cppm_configuration {
 441        __le16  command_flags;
 442#define I40E_AQ_CPPM_EN_LTRC    0x0800
 443#define I40E_AQ_CPPM_EN_DMCTH   0x1000
 444#define I40E_AQ_CPPM_EN_DMCTLX  0x2000
 445#define I40E_AQ_CPPM_EN_HPTC    0x4000
 446#define I40E_AQ_CPPM_EN_DMARC   0x8000
 447        __le16  ttlx;
 448        __le32  dmacr;
 449        __le16  dmcth;
 450        u8      hptc;
 451        u8      reserved;
 452        __le32  pfltrc;
 453};
 454
 455I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
 456
 457/* Set ARP Proxy command / response (indirect 0x0104) */
 458struct i40e_aqc_arp_proxy_data {
 459        __le16  command_flags;
 460#define I40E_AQ_ARP_INIT_IPV4   0x0800
 461#define I40E_AQ_ARP_UNSUP_CTL   0x1000
 462#define I40E_AQ_ARP_ENA         0x2000
 463#define I40E_AQ_ARP_ADD_IPV4    0x4000
 464#define I40E_AQ_ARP_DEL_IPV4    0x8000
 465        __le16  table_id;
 466        __le32  enabled_offloads;
 467#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE     0x00000020
 468#define I40E_AQ_ARP_OFFLOAD_ENABLE              0x00000800
 469        __le32  ip_addr;
 470        u8      mac_addr[6];
 471        u8      reserved[2];
 472};
 473
 474I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
 475
 476/* Set NS Proxy Table Entry Command (indirect 0x0105) */
 477struct i40e_aqc_ns_proxy_data {
 478        __le16  table_idx_mac_addr_0;
 479        __le16  table_idx_mac_addr_1;
 480        __le16  table_idx_ipv6_0;
 481        __le16  table_idx_ipv6_1;
 482        __le16  control;
 483#define I40E_AQ_NS_PROXY_ADD_0          0x0001
 484#define I40E_AQ_NS_PROXY_DEL_0          0x0002
 485#define I40E_AQ_NS_PROXY_ADD_1          0x0004
 486#define I40E_AQ_NS_PROXY_DEL_1          0x0008
 487#define I40E_AQ_NS_PROXY_ADD_IPV6_0     0x0010
 488#define I40E_AQ_NS_PROXY_DEL_IPV6_0     0x0020
 489#define I40E_AQ_NS_PROXY_ADD_IPV6_1     0x0040
 490#define I40E_AQ_NS_PROXY_DEL_IPV6_1     0x0080
 491#define I40E_AQ_NS_PROXY_COMMAND_SEQ    0x0100
 492#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL  0x0200
 493#define I40E_AQ_NS_PROXY_INIT_MAC_TBL   0x0400
 494#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
 495#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE        0x1000
 496        u8      mac_addr_0[6];
 497        u8      mac_addr_1[6];
 498        u8      local_mac_addr[6];
 499        u8      ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
 500        u8      ipv6_addr_1[16];
 501};
 502
 503I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
 504
 505/* Manage LAA Command (0x0106) - obsolete */
 506struct i40e_aqc_mng_laa {
 507        __le16  command_flags;
 508#define I40E_AQ_LAA_FLAG_WR     0x8000
 509        u8      reserved[2];
 510        __le32  sal;
 511        __le16  sah;
 512        u8      reserved2[6];
 513};
 514
 515I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
 516
 517/* Manage MAC Address Read Command (indirect 0x0107) */
 518struct i40e_aqc_mac_address_read {
 519        __le16  command_flags;
 520#define I40E_AQC_LAN_ADDR_VALID         0x10
 521#define I40E_AQC_SAN_ADDR_VALID         0x20
 522#define I40E_AQC_PORT_ADDR_VALID        0x40
 523#define I40E_AQC_WOL_ADDR_VALID         0x80
 524#define I40E_AQC_MC_MAG_EN_VALID        0x100
 525#define I40E_AQC_ADDR_VALID_MASK        0x3F0
 526        u8      reserved[6];
 527        __le32  addr_high;
 528        __le32  addr_low;
 529};
 530
 531I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
 532
 533struct i40e_aqc_mac_address_read_data {
 534        u8 pf_lan_mac[6];
 535        u8 pf_san_mac[6];
 536        u8 port_mac[6];
 537        u8 pf_wol_mac[6];
 538};
 539
 540I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
 541
 542/* Manage MAC Address Write Command (0x0108) */
 543struct i40e_aqc_mac_address_write {
 544        __le16  command_flags;
 545#define I40E_AQC_MC_MAG_EN              0x0100
 546#define I40E_AQC_WOL_PRESERVE_ON_PFR    0x0200
 547#define I40E_AQC_WRITE_TYPE_LAA_ONLY    0x0000
 548#define I40E_AQC_WRITE_TYPE_LAA_WOL     0x4000
 549#define I40E_AQC_WRITE_TYPE_PORT        0x8000
 550#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG       0xC000
 551#define I40E_AQC_WRITE_TYPE_MASK        0xC000
 552
 553        __le16  mac_sah;
 554        __le32  mac_sal;
 555        u8      reserved[8];
 556};
 557
 558I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
 559
 560/* PXE commands (0x011x) */
 561
 562/* Clear PXE Command and response  (direct 0x0110) */
 563struct i40e_aqc_clear_pxe {
 564        u8      rx_cnt;
 565        u8      reserved[15];
 566};
 567
 568I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
 569
 570/* Set WoL Filter (0x0120) */
 571
 572struct i40e_aqc_set_wol_filter {
 573        __le16 filter_index;
 574#define I40E_AQC_MAX_NUM_WOL_FILTERS    8
 575#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT        15
 576#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
 577                I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
 578
 579#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT             0
 580#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK      (0x7 << \
 581                I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
 582        __le16 cmd_flags;
 583#define I40E_AQC_SET_WOL_FILTER                         0x8000
 584#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL              0x4000
 585#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR            0
 586#define I40E_AQC_SET_WOL_FILTER_ACTION_SET              1
 587        __le16 valid_flags;
 588#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID            0x8000
 589#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID     0x4000
 590        u8 reserved[2];
 591        __le32  address_high;
 592        __le32  address_low;
 593};
 594
 595I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
 596
 597struct i40e_aqc_set_wol_filter_data {
 598        u8 filter[128];
 599        u8 mask[16];
 600};
 601
 602I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
 603
 604/* Get Wake Reason (0x0121) */
 605
 606struct i40e_aqc_get_wake_reason_completion {
 607        u8 reserved_1[2];
 608        __le16 wake_reason;
 609#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT      0
 610#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
 611                I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
 612#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT   8
 613#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK    (0xFF << \
 614                I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
 615        u8 reserved_2[12];
 616};
 617
 618I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
 619
 620/* Switch configuration commands (0x02xx) */
 621
 622/* Used by many indirect commands that only pass an seid and a buffer in the
 623 * command
 624 */
 625struct i40e_aqc_switch_seid {
 626        __le16  seid;
 627        u8      reserved[6];
 628        __le32  addr_high;
 629        __le32  addr_low;
 630};
 631
 632I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
 633
 634/* Get Switch Configuration command (indirect 0x0200)
 635 * uses i40e_aqc_switch_seid for the descriptor
 636 */
 637struct i40e_aqc_get_switch_config_header_resp {
 638        __le16  num_reported;
 639        __le16  num_total;
 640        u8      reserved[12];
 641};
 642
 643I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
 644
 645struct i40e_aqc_switch_config_element_resp {
 646        u8      element_type;
 647#define I40E_AQ_SW_ELEM_TYPE_MAC        1
 648#define I40E_AQ_SW_ELEM_TYPE_PF         2
 649#define I40E_AQ_SW_ELEM_TYPE_VF         3
 650#define I40E_AQ_SW_ELEM_TYPE_EMP        4
 651#define I40E_AQ_SW_ELEM_TYPE_BMC        5
 652#define I40E_AQ_SW_ELEM_TYPE_PV         16
 653#define I40E_AQ_SW_ELEM_TYPE_VEB        17
 654#define I40E_AQ_SW_ELEM_TYPE_PA         18
 655#define I40E_AQ_SW_ELEM_TYPE_VSI        19
 656        u8      revision;
 657#define I40E_AQ_SW_ELEM_REV_1           1
 658        __le16  seid;
 659        __le16  uplink_seid;
 660        __le16  downlink_seid;
 661        u8      reserved[3];
 662        u8      connection_type;
 663#define I40E_AQ_CONN_TYPE_REGULAR       0x1
 664#define I40E_AQ_CONN_TYPE_DEFAULT       0x2
 665#define I40E_AQ_CONN_TYPE_CASCADED      0x3
 666        __le16  scheduler_id;
 667        __le16  element_info;
 668};
 669
 670I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
 671
 672/* Get Switch Configuration (indirect 0x0200)
 673 *    an array of elements are returned in the response buffer
 674 *    the first in the array is the header, remainder are elements
 675 */
 676struct i40e_aqc_get_switch_config_resp {
 677        struct i40e_aqc_get_switch_config_header_resp   header;
 678        struct i40e_aqc_switch_config_element_resp      element[1];
 679};
 680
 681I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
 682
 683/* Add Statistics (direct 0x0201)
 684 * Remove Statistics (direct 0x0202)
 685 */
 686struct i40e_aqc_add_remove_statistics {
 687        __le16  seid;
 688        __le16  vlan;
 689        __le16  stat_index;
 690        u8      reserved[10];
 691};
 692
 693I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
 694
 695/* Set Port Parameters command (direct 0x0203) */
 696struct i40e_aqc_set_port_parameters {
 697        __le16  command_flags;
 698#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS   1
 699#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS  2 /* must set! */
 700#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA    4
 701        __le16  bad_frame_vsi;
 702#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT  0x0
 703#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK   0x3FF
 704        __le16  default_seid;        /* reserved for command */
 705        u8      reserved[10];
 706};
 707
 708I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
 709
 710/* Get Switch Resource Allocation (indirect 0x0204) */
 711struct i40e_aqc_get_switch_resource_alloc {
 712        u8      num_entries;         /* reserved for command */
 713        u8      reserved[7];
 714        __le32  addr_high;
 715        __le32  addr_low;
 716};
 717
 718I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
 719
 720/* expect an array of these structs in the response buffer */
 721struct i40e_aqc_switch_resource_alloc_element_resp {
 722        u8      resource_type;
 723#define I40E_AQ_RESOURCE_TYPE_VEB               0x0
 724#define I40E_AQ_RESOURCE_TYPE_VSI               0x1
 725#define I40E_AQ_RESOURCE_TYPE_MACADDR           0x2
 726#define I40E_AQ_RESOURCE_TYPE_STAG              0x3
 727#define I40E_AQ_RESOURCE_TYPE_ETAG              0x4
 728#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH    0x5
 729#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH      0x6
 730#define I40E_AQ_RESOURCE_TYPE_VLAN              0x7
 731#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY    0x8
 732#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY   0x9
 733#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL    0xA
 734#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE       0xB
 735#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS        0xC
 736#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS      0xD
 737#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
 738#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS        0x10
 739#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS       0x11
 740#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS          0x12
 741#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS      0x13
 742        u8      reserved1;
 743        __le16  guaranteed;
 744        __le16  total;
 745        __le16  used;
 746        __le16  total_unalloced;
 747        u8      reserved2[6];
 748};
 749
 750I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
 751
 752/* Set Switch Configuration (direct 0x0205) */
 753struct i40e_aqc_set_switch_config {
 754        __le16  flags;
 755/* flags used for both fields below */
 756#define I40E_AQ_SET_SWITCH_CFG_PROMISC          0x0001
 757#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER        0x0002
 758        __le16  valid_flags;
 759        /* The ethertype in switch_tag is dropped on ingress and used
 760         * internally by the switch. Set this to zero for the default
 761         * of 0x88a8 (802.1ad). Should be zero for firmware API
 762         * versions lower than 1.7.
 763         */
 764        __le16  switch_tag;
 765        /* The ethertypes in first_tag and second_tag are used to
 766         * match the outer and inner VLAN tags (respectively) when HW
 767         * double VLAN tagging is enabled via the set port parameters
 768         * AQ command. Otherwise these are both ignored. Set them to
 769         * zero for their defaults of 0x8100 (802.1Q). Should be zero
 770         * for firmware API versions lower than 1.7.
 771         */
 772        __le16  first_tag;
 773        __le16  second_tag;
 774        /* Next byte is split into following:
 775         * Bit 7    : 0 : No action, 1: Switch to mode defined by bits 6:0
 776         * Bit 6    : 0 : Destination Port, 1: source port
 777         * Bit 5..4 : L4 type
 778         * 0: rsvd
 779         * 1: TCP
 780         * 2: UDP
 781         * 3: Both TCP and UDP
 782         * Bits 3:0 Mode
 783         * 0: default mode
 784         * 1: L4 port only mode
 785         * 2: non-tunneled mode
 786         * 3: tunneled mode
 787         */
 788#define I40E_AQ_SET_SWITCH_BIT7_VALID           0x80
 789
 790#define I40E_AQ_SET_SWITCH_L4_SRC_PORT          0x40
 791
 792#define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD         0x00
 793#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP          0x10
 794#define I40E_AQ_SET_SWITCH_L4_TYPE_UDP          0x20
 795#define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH         0x30
 796
 797#define I40E_AQ_SET_SWITCH_MODE_DEFAULT         0x00
 798#define I40E_AQ_SET_SWITCH_MODE_L4_PORT         0x01
 799#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL      0x02
 800#define I40E_AQ_SET_SWITCH_MODE_TUNNEL          0x03
 801        u8      mode;
 802        u8      rsvd5[5];
 803};
 804
 805I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
 806
 807/* Read Receive control registers  (direct 0x0206)
 808 * Write Receive control registers (direct 0x0207)
 809 *     used for accessing Rx control registers that can be
 810 *     slow and need special handling when under high Rx load
 811 */
 812struct i40e_aqc_rx_ctl_reg_read_write {
 813        __le32 reserved1;
 814        __le32 address;
 815        __le32 reserved2;
 816        __le32 value;
 817};
 818
 819I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
 820
 821/* Add VSI (indirect 0x0210)
 822 *    this indirect command uses struct i40e_aqc_vsi_properties_data
 823 *    as the indirect buffer (128 bytes)
 824 *
 825 * Update VSI (indirect 0x211)
 826 *     uses the same data structure as Add VSI
 827 *
 828 * Get VSI (indirect 0x0212)
 829 *     uses the same completion and data structure as Add VSI
 830 */
 831struct i40e_aqc_add_get_update_vsi {
 832        __le16  uplink_seid;
 833        u8      connection_type;
 834#define I40E_AQ_VSI_CONN_TYPE_NORMAL    0x1
 835#define I40E_AQ_VSI_CONN_TYPE_DEFAULT   0x2
 836#define I40E_AQ_VSI_CONN_TYPE_CASCADED  0x3
 837        u8      reserved1;
 838        u8      vf_id;
 839        u8      reserved2;
 840        __le16  vsi_flags;
 841#define I40E_AQ_VSI_TYPE_SHIFT          0x0
 842#define I40E_AQ_VSI_TYPE_MASK           (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
 843#define I40E_AQ_VSI_TYPE_VF             0x0
 844#define I40E_AQ_VSI_TYPE_VMDQ2          0x1
 845#define I40E_AQ_VSI_TYPE_PF             0x2
 846#define I40E_AQ_VSI_TYPE_EMP_MNG        0x3
 847#define I40E_AQ_VSI_FLAG_CASCADED_PV    0x4
 848        __le32  addr_high;
 849        __le32  addr_low;
 850};
 851
 852I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
 853
 854struct i40e_aqc_add_get_update_vsi_completion {
 855        __le16 seid;
 856        __le16 vsi_number;
 857        __le16 vsi_used;
 858        __le16 vsi_free;
 859        __le32 addr_high;
 860        __le32 addr_low;
 861};
 862
 863I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
 864
 865struct i40e_aqc_vsi_properties_data {
 866        /* first 96 byte are written by SW */
 867        __le16  valid_sections;
 868#define I40E_AQ_VSI_PROP_SWITCH_VALID           0x0001
 869#define I40E_AQ_VSI_PROP_SECURITY_VALID         0x0002
 870#define I40E_AQ_VSI_PROP_VLAN_VALID             0x0004
 871#define I40E_AQ_VSI_PROP_CAS_PV_VALID           0x0008
 872#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID       0x0010
 873#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID        0x0020
 874#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID        0x0040
 875#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID        0x0080
 876#define I40E_AQ_VSI_PROP_OUTER_UP_VALID         0x0100
 877#define I40E_AQ_VSI_PROP_SCHED_VALID            0x0200
 878        /* switch section */
 879        __le16  switch_id; /* 12bit id combined with flags below */
 880#define I40E_AQ_VSI_SW_ID_SHIFT         0x0000
 881#define I40E_AQ_VSI_SW_ID_MASK          (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
 882#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
 883#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
 884#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
 885        u8      sw_reserved[2];
 886        /* security section */
 887        u8      sec_flags;
 888#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01
 889#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02
 890#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK     0x04
 891        u8      sec_reserved;
 892        /* VLAN section */
 893        __le16  pvid; /* VLANS include priority bits */
 894        __le16  fcoe_pvid;
 895        u8      port_vlan_flags;
 896#define I40E_AQ_VSI_PVLAN_MODE_SHIFT    0x00
 897#define I40E_AQ_VSI_PVLAN_MODE_MASK     (0x03 << \
 898                                         I40E_AQ_VSI_PVLAN_MODE_SHIFT)
 899#define I40E_AQ_VSI_PVLAN_MODE_TAGGED   0x01
 900#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
 901#define I40E_AQ_VSI_PVLAN_MODE_ALL      0x03
 902#define I40E_AQ_VSI_PVLAN_INSERT_PVID   0x04
 903#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT    0x03
 904#define I40E_AQ_VSI_PVLAN_EMOD_MASK     (0x3 << \
 905                                         I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
 906#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
 907#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP   0x08
 908#define I40E_AQ_VSI_PVLAN_EMOD_STR      0x10
 909#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING  0x18
 910        u8      pvlan_reserved[3];
 911        /* ingress egress up sections */
 912        __le32  ingress_table; /* bitmap, 3 bits per up */
 913#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT  0
 914#define I40E_AQ_VSI_UP_TABLE_UP0_MASK   (0x7 << \
 915                                         I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
 916#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT  3
 917#define I40E_AQ_VSI_UP_TABLE_UP1_MASK   (0x7 << \
 918                                         I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
 919#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT  6
 920#define I40E_AQ_VSI_UP_TABLE_UP2_MASK   (0x7 << \
 921                                         I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
 922#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT  9
 923#define I40E_AQ_VSI_UP_TABLE_UP3_MASK   (0x7 << \
 924                                         I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
 925#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT  12
 926#define I40E_AQ_VSI_UP_TABLE_UP4_MASK   (0x7 << \
 927                                         I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
 928#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT  15
 929#define I40E_AQ_VSI_UP_TABLE_UP5_MASK   (0x7 << \
 930                                         I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
 931#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT  18
 932#define I40E_AQ_VSI_UP_TABLE_UP6_MASK   (0x7 << \
 933                                         I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
 934#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT  21
 935#define I40E_AQ_VSI_UP_TABLE_UP7_MASK   (0x7 << \
 936                                         I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
 937        __le32  egress_table;   /* same defines as for ingress table */
 938        /* cascaded PV section */
 939        __le16  cas_pv_tag;
 940        u8      cas_pv_flags;
 941#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT           0x00
 942#define I40E_AQ_VSI_CAS_PV_TAGX_MASK            (0x03 << \
 943                                                 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
 944#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE           0x00
 945#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE          0x01
 946#define I40E_AQ_VSI_CAS_PV_TAGX_COPY            0x02
 947#define I40E_AQ_VSI_CAS_PV_INSERT_TAG           0x10
 948#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE           0x20
 949#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG      0x40
 950        u8      cas_pv_reserved;
 951        /* queue mapping section */
 952        __le16  mapping_flags;
 953#define I40E_AQ_VSI_QUE_MAP_CONTIG      0x0
 954#define I40E_AQ_VSI_QUE_MAP_NONCONTIG   0x1
 955        __le16  queue_mapping[16];
 956#define I40E_AQ_VSI_QUEUE_SHIFT         0x0
 957#define I40E_AQ_VSI_QUEUE_MASK          (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
 958        __le16  tc_mapping[8];
 959#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
 960#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK  (0x1FF << \
 961                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 962#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
 963#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK  (0x7 << \
 964                                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 965        /* queueing option section */
 966        u8      queueing_opt_flags;
 967#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA   0x04
 968#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA     0x08
 969#define I40E_AQ_VSI_QUE_OPT_TCP_ENA     0x10
 970#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA    0x20
 971#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF  0x00
 972#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
 973        u8      queueing_opt_reserved[3];
 974        /* scheduler section */
 975        u8      up_enable_bits;
 976        u8      sched_reserved;
 977        /* outer up section */
 978        __le32  outer_up_table; /* same structure and defines as ingress tbl */
 979        u8      cmd_reserved[8];
 980        /* last 32 bytes are written by FW */
 981        __le16  qs_handle[8];
 982#define I40E_AQ_VSI_QS_HANDLE_INVALID   0xFFFF
 983        __le16  stat_counter_idx;
 984        __le16  sched_id;
 985        u8      resp_reserved[12];
 986};
 987
 988I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
 989
 990/* Add Port Virtualizer (direct 0x0220)
 991 * also used for update PV (direct 0x0221) but only flags are used
 992 * (IS_CTRL_PORT only works on add PV)
 993 */
 994struct i40e_aqc_add_update_pv {
 995        __le16  command_flags;
 996#define I40E_AQC_PV_FLAG_PV_TYPE                0x1
 997#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN    0x2
 998#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN    0x4
 999#define I40E_AQC_PV_FLAG_IS_CTRL_PORT           0x8
1000        __le16  uplink_seid;

1001        __le16  connected_seid;
1002        u8      reserved[10];
1003};
1004
1005I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1006
1007struct i40e_aqc_add_update_pv_completion {
1008        /* reserved for update; for add also encodes error if rc == ENOSPC */
1009        __le16  pv_seid;
1010#define I40E_AQC_PV_ERR_FLAG_NO_PV      0x1
1011#define I40E_AQC_PV_ERR_FLAG_NO_SCHED   0x2
1012#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1013#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY   0x8
1014        u8      reserved[14];
1015};
1016
1017I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1018
1019/* Get PV Params (direct 0x0222)
1020 * uses i40e_aqc_switch_seid for the descriptor
1021 */
1022
1023struct i40e_aqc_get_pv_params_completion {
1024        __le16  seid;
1025        __le16  default_stag;
1026        __le16  pv_flags; /* same flags as add_pv */
1027#define I40E_AQC_GET_PV_PV_TYPE                 0x1
1028#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG       0x2
1029#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG       0x4
1030        u8      reserved[8];
1031        __le16  default_port_seid;
1032};
1033
1034I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1035
1036/* Add VEB (direct 0x0230) */
1037struct i40e_aqc_add_veb {
1038        __le16  uplink_seid;
1039        __le16  downlink_seid;
1040        __le16  veb_flags;
1041#define I40E_AQC_ADD_VEB_FLOATING               0x1
1042#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT        1
1043#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK         (0x3 << \
1044                                        I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1045#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT      0x2
1046#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA         0x4
1047#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER       0x8     /* deprecated */
1048#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS   0x10
1049        u8      enable_tcs;
1050        u8      reserved[9];
1051};
1052
1053I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1054
1055struct i40e_aqc_add_veb_completion {
1056        u8      reserved[6];
1057        __le16  switch_seid;
1058        /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1059        __le16  veb_seid;
1060#define I40E_AQC_VEB_ERR_FLAG_NO_VEB            0x1
1061#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED          0x2
1062#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER        0x4
1063#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY          0x8
1064        __le16  statistic_index;
1065        __le16  vebs_used;
1066        __le16  vebs_free;
1067};
1068
1069I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1070
1071/* Get VEB Parameters (direct 0x0232)
1072 * uses i40e_aqc_switch_seid for the descriptor
1073 */
1074struct i40e_aqc_get_veb_parameters_completion {
1075        __le16  seid;
1076        __le16  switch_id;
1077        __le16  veb_flags; /* only the first/last flags from 0x0230 is valid */
1078        __le16  statistic_index;
1079        __le16  vebs_used;
1080        __le16  vebs_free;
1081        u8      reserved[4];
1082};
1083
1084I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1085
1086/* Delete Element (direct 0x0243)
1087 * uses the generic i40e_aqc_switch_seid
1088 */
1089
1090/* Add MAC-VLAN (indirect 0x0250) */
1091
1092/* used for the command for most vlan commands */
1093struct i40e_aqc_macvlan {
1094        __le16  num_addresses;
1095        __le16  seid[3];
1096#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT     0
1097#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK      (0x3FF << \
1098                                        I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1099#define I40E_AQC_MACVLAN_CMD_SEID_VALID         0x8000
1100        __le32  addr_high;
1101        __le32  addr_low;
1102};
1103
1104I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1105
1106/* indirect data for command and response */
1107struct i40e_aqc_add_macvlan_element_data {
1108        u8      mac_addr[6];
1109        __le16  vlan_tag;
1110        __le16  flags;
1111#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH      0x0001
1112#define I40E_AQC_MACVLAN_ADD_HASH_MATCH         0x0002
1113#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN        0x0004
1114#define I40E_AQC_MACVLAN_ADD_TO_QUEUE           0x0008
1115#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC     0x0010
1116        __le16  queue_number;
1117#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT        0
1118#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK         (0x7FF << \
1119                                        I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1120        /* response section */
1121        u8      match_method;
1122#define I40E_AQC_MM_PERFECT_MATCH       0x01
1123#define I40E_AQC_MM_HASH_MATCH          0x02
1124#define I40E_AQC_MM_ERR_NO_RES          0xFF
1125        u8      reserved1[3];
1126};
1127
1128struct i40e_aqc_add_remove_macvlan_completion {
1129        __le16 perfect_mac_used;
1130        __le16 perfect_mac_free;
1131        __le16 unicast_hash_free;
1132        __le16 multicast_hash_free;
1133        __le32 addr_high;
1134        __le32 addr_low;
1135};
1136
1137I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1138
1139/* Remove MAC-VLAN (indirect 0x0251)
1140 * uses i40e_aqc_macvlan for the descriptor
1141 * data points to an array of num_addresses of elements
1142 */
1143
1144struct i40e_aqc_remove_macvlan_element_data {
1145        u8      mac_addr[6];
1146        __le16  vlan_tag;
1147        u8      flags;
1148#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH      0x01
1149#define I40E_AQC_MACVLAN_DEL_HASH_MATCH         0x02
1150#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN        0x08
1151#define I40E_AQC_MACVLAN_DEL_ALL_VSIS           0x10
1152        u8      reserved[3];
1153        /* reply section */
1154        u8      error_code;
1155#define I40E_AQC_REMOVE_MACVLAN_SUCCESS         0x0
1156#define I40E_AQC_REMOVE_MACVLAN_FAIL            0xFF
1157        u8      reply_reserved[3];
1158};
1159
1160/* Add VLAN (indirect 0x0252)
1161 * Remove VLAN (indirect 0x0253)
1162 * use the generic i40e_aqc_macvlan for the command
1163 */
1164struct i40e_aqc_add_remove_vlan_element_data {
1165        __le16  vlan_tag;
1166        u8      vlan_flags;
1167/* flags for add VLAN */
1168#define I40E_AQC_ADD_VLAN_LOCAL                 0x1
1169#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT           1
1170#define I40E_AQC_ADD_PVLAN_TYPE_MASK    (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1171#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR         0x0
1172#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY         0x2
1173#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY       0x4
1174#define I40E_AQC_VLAN_PTYPE_SHIFT               3
1175#define I40E_AQC_VLAN_PTYPE_MASK        (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1176#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI         0x0
1177#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI         0x8
1178#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI       0x10
1179#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI        0x18
1180/* flags for remove VLAN */
1181#define I40E_AQC_REMOVE_VLAN_ALL        0x1
1182        u8      reserved;
1183        u8      result;
1184/* flags for add VLAN */
1185#define I40E_AQC_ADD_VLAN_SUCCESS       0x0
1186#define I40E_AQC_ADD_VLAN_FAIL_REQUEST  0xFE
1187#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1188/* flags for remove VLAN */
1189#define I40E_AQC_REMOVE_VLAN_SUCCESS    0x0
1190#define I40E_AQC_REMOVE_VLAN_FAIL       0xFF
1191        u8      reserved1[3];
1192};
1193
1194struct i40e_aqc_add_remove_vlan_completion {
1195        u8      reserved[4];
1196        __le16  vlans_used;
1197        __le16  vlans_free;
1198        __le32  addr_high;
1199        __le32  addr_low;
1200};
1201
1202/* Set VSI Promiscuous Modes (direct 0x0254) */
1203struct i40e_aqc_set_vsi_promiscuous_modes {
1204        __le16  promiscuous_flags;
1205        __le16  valid_flags;
1206/* flags used for both fields above */
1207#define I40E_AQC_SET_VSI_PROMISC_UNICAST        0x01
1208#define I40E_AQC_SET_VSI_PROMISC_MULTICAST      0x02
1209#define I40E_AQC_SET_VSI_PROMISC_BROADCAST      0x04
1210#define I40E_AQC_SET_VSI_DEFAULT                0x08
1211#define I40E_AQC_SET_VSI_PROMISC_VLAN           0x10
1212#define I40E_AQC_SET_VSI_PROMISC_TX             0x8000
1213        __le16  seid;
1214#define I40E_AQC_VSI_PROM_CMD_SEID_MASK         0x3FF
1215        __le16  vlan_tag;
1216#define I40E_AQC_SET_VSI_VLAN_MASK              0x0FFF
1217#define I40E_AQC_SET_VSI_VLAN_VALID             0x8000
1218        u8      reserved[8];
1219};
1220
1221I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1222
1223/* Add S/E-tag command (direct 0x0255)
1224 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1225 */
1226struct i40e_aqc_add_tag {
1227        __le16  flags;
1228#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE          0x0001
1229        __le16  seid;
1230#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT     0
1231#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK      (0x3FF << \
1232                                        I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1233        __le16  tag;
1234        __le16  queue_number;
1235        u8      reserved[8];
1236};
1237
1238I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1239
1240struct i40e_aqc_add_remove_tag_completion {
1241        u8      reserved[12];
1242        __le16  tags_used;
1243        __le16  tags_free;
1244};
1245
1246I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1247
1248/* Remove S/E-tag command (direct 0x0256)
1249 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1250 */
1251struct i40e_aqc_remove_tag {
1252        __le16  seid;
1253#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT  0
1254#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1255                                        I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1256        __le16  tag;
1257        u8      reserved[12];
1258};
1259
1260I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1261
1262/* Add multicast E-Tag (direct 0x0257)
1263 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1264 * and no external data
1265 */
1266struct i40e_aqc_add_remove_mcast_etag {
1267        __le16  pv_seid;
1268        __le16  etag;
1269        u8      num_unicast_etags;
1270        u8      reserved[3];
1271        __le32  addr_high;          /* address of array of 2-byte s-tags */
1272        __le32  addr_low;
1273};
1274
1275I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1276
1277struct i40e_aqc_add_remove_mcast_etag_completion {
1278        u8      reserved[4];
1279        __le16  mcast_etags_used;
1280        __le16  mcast_etags_free;
1281        __le32  addr_high;
1282        __le32  addr_low;
1283
1284};
1285
1286I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1287
1288/* Update S/E-Tag (direct 0x0259) */
1289struct i40e_aqc_update_tag {
1290        __le16  seid;
1291#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT  0
1292#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1293                                        I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1294        __le16  old_tag;
1295        __le16  new_tag;
1296        u8      reserved[10];
1297};
1298
1299I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1300
1301struct i40e_aqc_update_tag_completion {
1302        u8      reserved[12];
1303        __le16  tags_used;
1304        __le16  tags_free;
1305};
1306
1307I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1308
1309/* Add Control Packet filter (direct 0x025A)
1310 * Remove Control Packet filter (direct 0x025B)
1311 * uses the i40e_aqc_add_oveb_cloud,
1312 * and the generic direct completion structure
1313 */
1314struct i40e_aqc_add_remove_control_packet_filter {
1315        u8      mac[6];
1316        __le16  etype;
1317        __le16  flags;
1318#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC    0x0001
1319#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP          0x0002
1320#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE      0x0004
1321#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX            0x0008
1322#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX            0x0000
1323        __le16  seid;
1324#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT  0
1325#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK   (0x3FF << \
1326                                I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1327        __le16  queue;
1328        u8      reserved[2];
1329};
1330
1331I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1332
1333struct i40e_aqc_add_remove_control_packet_filter_completion {
1334        __le16  mac_etype_used;
1335        __le16  etype_used;
1336        __le16  mac_etype_free;
1337        __le16  etype_free;
1338        u8      reserved[8];
1339};
1340
1341I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1342
1343/* Add Cloud filters (indirect 0x025C)
1344 * Remove Cloud filters (indirect 0x025D)
1345 * uses the i40e_aqc_add_remove_cloud_filters,
1346 * and the generic indirect completion structure
1347 */
1348struct i40e_aqc_add_remove_cloud_filters {
1349        u8      num_filters;
1350        u8      reserved;
1351        __le16  seid;
1352#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT   0
1353#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK    (0x3FF << \
1354                                        I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1355        u8      big_buffer_flag;
1356#define I40E_AQC_ADD_CLOUD_CMD_BB       1
1357        u8      reserved2[3];
1358        __le32  addr_high;
1359        __le32  addr_low;
1360};
1361
1362I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1363
1364struct i40e_aqc_cloud_filters_element_data {
1365        u8      outer_mac[6];
1366        u8      inner_mac[6];
1367        __le16  inner_vlan;
1368        union {
1369                struct {
1370                        u8 reserved[12];
1371                        u8 data[4];
1372                } v4;
1373                struct {
1374                        u8 data[16];
1375                } v6;
1376                struct {
1377                        __le16 data[8];
1378                } raw_v6;
1379        } ipaddr;
1380        __le16  flags;
1381#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT                 0
1382#define I40E_AQC_ADD_CLOUD_FILTER_MASK  (0x3F << \
1383                                        I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1384/* 0x0000 reserved */
1385#define I40E_AQC_ADD_CLOUD_FILTER_OIP                   0x0001
1386/* 0x0002 reserved */
1387#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN            0x0003
1388#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID     0x0004
1389/* 0x0005 reserved */
1390#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID           0x0006
1391/* 0x0007 reserved */
1392/* 0x0008 reserved */
1393#define I40E_AQC_ADD_CLOUD_FILTER_OMAC                  0x0009
1394#define I40E_AQC_ADD_CLOUD_FILTER_IMAC                  0x000A
1395#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC      0x000B
1396#define I40E_AQC_ADD_CLOUD_FILTER_IIP                   0x000C
1397/* 0x0010 to 0x0017 is for custom filters */
1398#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT               0x0010 /* Dest IP + L4 Port */
1399#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT              0x0011 /* Dest MAC + L4 Port */
1400#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT         0x0012 /* Dest MAC + VLAN + L4 Port */
1401
1402#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE               0x0080
1403#define I40E_AQC_ADD_CLOUD_VNK_SHIFT                    6
1404#define I40E_AQC_ADD_CLOUD_VNK_MASK                     0x00C0
1405#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4                   0
1406#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6                   0x0100
1407
1408#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT               9
1409#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK                0x1E00
1410#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN               0
1411#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC          1
1412#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE              2
1413#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP                  3
1414#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED            4
1415#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE           5
1416
1417#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC       0x2000
1418#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC       0x4000
1419#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP        0x8000
1420
1421        __le32  tenant_id;
1422        u8      reserved[4];
1423        __le16  queue_number;
1424#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT          0
1425#define I40E_AQC_ADD_CLOUD_QUEUE_MASK           (0x7FF << \
1426                                                 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1427        u8      reserved2[14];
1428        /* response section */
1429        u8      allocation_result;
1430#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS       0x0
1431#define I40E_AQC_ADD_CLOUD_FILTER_FAIL          0xFF
1432        u8      response_reserved[7];
1433};
1434
1435I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1436
1437/* i40e_aqc_cloud_filters_element_bb is used when
1438 * I40E_AQC_CLOUD_CMD_BB flag is set.
1439 */
1440struct i40e_aqc_cloud_filters_element_bb {
1441        struct i40e_aqc_cloud_filters_element_data element;
1442        u16     general_fields[32];
1443#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0    0
1444#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1    1
1445#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2    2
1446#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0    3
1447#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1    4
1448#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2    5
1449#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0    6
1450#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1    7
1451#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2    8
1452#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0    9
1453#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1    10
1454#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2    11
1455#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0    12
1456#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1    13
1457#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2    14
1458#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0    15
1459#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1    16
1460#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2    17
1461#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3    18
1462#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4    19
1463#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5    20
1464#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6    21
1465#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7    22
1466#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0    23
1467#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1    24
1468#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2    25
1469#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3    26
1470#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4    27
1471#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5    28
1472#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6    29
1473#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7    30
1474};
1475
1476I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1477
1478struct i40e_aqc_remove_cloud_filters_completion {
1479        __le16 perfect_ovlan_used;
1480        __le16 perfect_ovlan_free;
1481        __le16 vlan_used;
1482        __le16 vlan_free;
1483        __le32 addr_high;
1484        __le32 addr_low;
1485};
1486
1487I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1488
1489/* Replace filter Command 0x025F
1490 * uses the i40e_aqc_replace_cloud_filters,
1491 * and the generic indirect completion structure
1492 */
1493struct i40e_filter_data {
1494        u8 filter_type;
1495        u8 input[3];
1496};
1497
1498I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1499
1500struct i40e_aqc_replace_cloud_filters_cmd {
1501        u8      valid_flags;
1502#define I40E_AQC_REPLACE_L1_FILTER              0x0
1503#define I40E_AQC_REPLACE_CLOUD_FILTER           0x1
1504#define I40E_AQC_GET_CLOUD_FILTERS              0x2
1505#define I40E_AQC_MIRROR_CLOUD_FILTER            0x4
1506#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER     0x8
1507        u8      old_filter_type;
1508        u8      new_filter_type;
1509        u8      tr_bit;
1510        u8      reserved[4];
1511        __le32 addr_high;
1512        __le32 addr_low;
1513};
1514
1515I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1516
1517struct i40e_aqc_replace_cloud_filters_cmd_buf {
1518        u8      data[32];
1519/* Filter type INPUT codes*/
1520#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX    3
1521#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED      BIT(7)
1522
1523/* Field Vector offsets */
1524#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA      0
1525#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH    6
1526#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG        7
1527#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN        8
1528#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN  9
1529#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN  10
1530#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY  11
1531#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC        12
1532/* big FLU */
1533#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA       14
1534/* big FLU */
1535#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA      15
1536
1537#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN  37
1538        struct i40e_filter_data filters[8];
1539};
1540
1541I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1542
1543/* Add Mirror Rule (indirect or direct 0x0260)
1544 * Delete Mirror Rule (indirect or direct 0x0261)
1545 * note: some rule types (4,5) do not use an external buffer.
1546 *       take care to set the flags correctly.
1547 */
1548struct i40e_aqc_add_delete_mirror_rule {
1549        __le16 seid;
1550        __le16 rule_type;
1551#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT         0
1552#define I40E_AQC_MIRROR_RULE_TYPE_MASK          (0x7 << \
1553                                                I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1554#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1555#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS  2
1556#define I40E_AQC_MIRROR_RULE_TYPE_VLAN          3
1557#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS   4
1558#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS    5
1559        __le16 num_entries;
1560        __le16 destination;  /* VSI for add, rule id for delete */
1561        __le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1562        __le32 addr_low;
1563};
1564
1565I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1566
1567struct i40e_aqc_add_delete_mirror_rule_completion {
1568        u8      reserved[2];
1569        __le16  rule_id;  /* only used on add */
1570        __le16  mirror_rules_used;
1571        __le16  mirror_rules_free;
1572        __le32  addr_high;
1573        __le32  addr_low;
1574};
1575
1576I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1577
1578/* Dynamic Device Personalization */
1579struct i40e_aqc_write_personalization_profile {
1580        u8      flags;
1581        u8      reserved[3];
1582        __le32  profile_track_id;
1583        __le32  addr_high;
1584        __le32  addr_low;
1585};
1586
1587I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1588
1589struct i40e_aqc_write_ddp_resp {
1590        __le32 error_offset;
1591        __le32 error_info;
1592        __le32 addr_high;
1593        __le32 addr_low;
1594};
1595
1596struct i40e_aqc_get_applied_profiles {
1597        u8      flags;
1598#define I40E_AQC_GET_DDP_GET_CONF       0x1
1599#define I40E_AQC_GET_DDP_GET_RDPU_CONF  0x2
1600        u8      rsv[3];
1601        __le32  reserved;
1602        __le32  addr_high;
1603        __le32  addr_low;
1604};
1605
1606I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1607
1608/* DCB 0x03xx*/
1609
1610/* PFC Ignore (direct 0x0301)
1611 *    the command and response use the same descriptor structure
1612 */
1613struct i40e_aqc_pfc_ignore {
1614        u8      tc_bitmap;
1615        u8      command_flags; /* unused on response */
1616#define I40E_AQC_PFC_IGNORE_SET         0x80
1617#define I40E_AQC_PFC_IGNORE_CLEAR       0x0
1618        u8      reserved[14];
1619};
1620
1621I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1622
1623/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1624 * with no parameters
1625 */
1626
1627/* TX scheduler 0x04xx */
1628
1629/* Almost all the indirect commands use
1630 * this generic struct to pass the SEID in param0
1631 */
1632struct i40e_aqc_tx_sched_ind {
1633        __le16  vsi_seid;
1634        u8      reserved[6];
1635        __le32  addr_high;
1636        __le32  addr_low;
1637};
1638
1639I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1640
1641/* Several commands respond with a set of queue set handles */
1642struct i40e_aqc_qs_handles_resp {
1643        __le16 qs_handles[8];
1644};
1645
1646/* Configure VSI BW limits (direct 0x0400) */
1647struct i40e_aqc_configure_vsi_bw_limit {
1648        __le16  vsi_seid;
1649        u8      reserved[2];
1650        __le16  credit;
1651        u8      reserved1[2];
1652        u8      max_credit; /* 0-3, limit = 2^max */
1653        u8      reserved2[7];
1654};
1655
1656I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1657
1658/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1659 *    responds with i40e_aqc_qs_handles_resp
1660 */
1661struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1662        u8      tc_valid_bits;
1663        u8      reserved[15];
1664        __le16  tc_bw_credits[8]; /* FW writesback QS handles here */
1665
1666        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1667        __le16  tc_bw_max[2];
1668        u8      reserved1[28];
1669};
1670
1671I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1672
1673/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1674 *    responds with i40e_aqc_qs_handles_resp
1675 */
1676struct i40e_aqc_configure_vsi_tc_bw_data {
1677        u8      tc_valid_bits;
1678        u8      reserved[3];
1679        u8      tc_bw_credits[8];
1680        u8      reserved1[4];
1681        __le16  qs_handles[8];
1682};
1683
1684I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1685
1686/* Query vsi bw configuration (indirect 0x0408) */
1687struct i40e_aqc_query_vsi_bw_config_resp {
1688        u8      tc_valid_bits;
1689        u8      tc_suspended_bits;
1690        u8      reserved[14];
1691        __le16  qs_handles[8];
1692        u8      reserved1[4];
1693        __le16  port_bw_limit;
1694        u8      reserved2[2];
1695        u8      max_bw; /* 0-3, limit = 2^max */
1696        u8      reserved3[23];
1697};
1698
1699I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1700
1701/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1702struct i40e_aqc_query_vsi_ets_sla_config_resp {
1703        u8      tc_valid_bits;
1704        u8      reserved[3];
1705        u8      share_credits[8];
1706        __le16  credits[8];
1707
1708        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1709        __le16  tc_bw_max[2];
1710};
1711
1712I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1713
1714/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1715struct i40e_aqc_configure_switching_comp_bw_limit {
1716        __le16  seid;
1717        u8      reserved[2];
1718        __le16  credit;
1719        u8      reserved1[2];
1720        u8      max_bw; /* 0-3, limit = 2^max */
1721        u8      reserved2[7];
1722};
1723
1724I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1725
1726/* Enable  Physical Port ETS (indirect 0x0413)
1727 * Modify  Physical Port ETS (indirect 0x0414)
1728 * Disable Physical Port ETS (indirect 0x0415)
1729 */
1730struct i40e_aqc_configure_switching_comp_ets_data {
1731        u8      reserved[4];
1732        u8      tc_valid_bits;
1733        u8      seepage;
1734#define I40E_AQ_ETS_SEEPAGE_EN_MASK     0x1
1735        u8      tc_strict_priority_flags;
1736        u8      reserved1[17];
1737        u8      tc_bw_share_credits[8];
1738        u8      reserved2[96];
1739};
1740
1741I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1742
1743/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1744struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1745        u8      tc_valid_bits;
1746        u8      reserved[15];
1747        __le16  tc_bw_credit[8];
1748
1749        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1750        __le16  tc_bw_max[2];
1751        u8      reserved1[28];
1752};
1753
1754I40E_CHECK_STRUCT_LEN(0x40,
1755                      i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1756
1757/* Configure Switching Component Bandwidth Allocation per Tc
1758 * (indirect 0x0417)
1759 */
1760struct i40e_aqc_configure_switching_comp_bw_config_data {
1761        u8      tc_valid_bits;
1762        u8      reserved[2];
1763        u8      absolute_credits; /* bool */
1764        u8      tc_bw_share_credits[8];
1765        u8      reserved1[20];
1766};
1767
1768I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1769
1770/* Query Switching Component Configuration (indirect 0x0418) */
1771struct i40e_aqc_query_switching_comp_ets_config_resp {
1772        u8      tc_valid_bits;
1773        u8      reserved[35];
1774        __le16  port_bw_limit;
1775        u8      reserved1[2];
1776        u8      tc_bw_max; /* 0-3, limit = 2^max */
1777        u8      reserved2[23];
1778};
1779
1780I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1781
1782/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1783struct i40e_aqc_query_port_ets_config_resp {
1784        u8      reserved[4];
1785        u8      tc_valid_bits;
1786        u8      reserved1;
1787        u8      tc_strict_priority_bits;
1788        u8      reserved2;
1789        u8      tc_bw_share_credits[8];
1790        __le16  tc_bw_limits[8];
1791
1792        /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1793        __le16  tc_bw_max[2];
1794        u8      reserved3[32];
1795};
1796
1797I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1798
1799/* Query Switching Component Bandwidth Allocation per Traffic Type
1800 * (indirect 0x041A)
1801 */
1802struct i40e_aqc_query_switching_comp_bw_config_resp {
1803        u8      tc_valid_bits;
1804        u8      reserved[2];
1805        u8      absolute_credits_enable; /* bool */
1806        u8      tc_bw_share_credits[8];
1807        __le16  tc_bw_limits[8];
1808
1809        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1810        __le16  tc_bw_max[2];
1811};
1812
1813I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1814
1815/* Suspend/resume port TX traffic
1816 * (direct 0x041B and 0x041C) uses the generic SEID struct
1817 */
1818
1819/* Configure partition BW
1820 * (indirect 0x041D)
1821 */
1822struct i40e_aqc_configure_partition_bw_data {
1823        __le16  pf_valid_bits;
1824        u8      min_bw[16];      /* guaranteed bandwidth */
1825        u8      max_bw[16];      /* bandwidth limit */
1826};
1827
1828I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1829
1830/* Get and set the active HMC resource profile and status.
1831 * (direct 0x0500) and (direct 0x0501)
1832 */
1833struct i40e_aq_get_set_hmc_resource_profile {
1834        u8      pm_profile;
1835        u8      pe_vf_enabled;
1836        u8      reserved[14];
1837};
1838
1839I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1840
1841enum i40e_aq_hmc_profile {
1842        /* I40E_HMC_PROFILE_NO_CHANGE   = 0, reserved */
1843        I40E_HMC_PROFILE_DEFAULT        = 1,
1844        I40E_HMC_PROFILE_FAVOR_VF       = 2,
1845        I40E_HMC_PROFILE_EQUAL          = 3,
1846};
1847
1848/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1849
1850/* set in param0 for get phy abilities to report qualified modules */
1851#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES    0x0001
1852#define I40E_AQ_PHY_REPORT_INITIAL_VALUES       0x0002
1853
1854enum i40e_aq_phy_type {
1855        I40E_PHY_TYPE_SGMII                     = 0x0,
1856        I40E_PHY_TYPE_1000BASE_KX               = 0x1,
1857        I40E_PHY_TYPE_10GBASE_KX4               = 0x2,
1858        I40E_PHY_TYPE_10GBASE_KR                = 0x3,
1859        I40E_PHY_TYPE_40GBASE_KR4               = 0x4,
1860        I40E_PHY_TYPE_XAUI                      = 0x5,
1861        I40E_PHY_TYPE_XFI                       = 0x6,
1862        I40E_PHY_TYPE_SFI                       = 0x7,
1863        I40E_PHY_TYPE_XLAUI                     = 0x8,
1864        I40E_PHY_TYPE_XLPPI                     = 0x9,
1865        I40E_PHY_TYPE_40GBASE_CR4_CU            = 0xA,
1866        I40E_PHY_TYPE_10GBASE_CR1_CU            = 0xB,
1867        I40E_PHY_TYPE_10GBASE_AOC               = 0xC,
1868        I40E_PHY_TYPE_40GBASE_AOC               = 0xD,
1869        I40E_PHY_TYPE_UNRECOGNIZED              = 0xE,
1870        I40E_PHY_TYPE_UNSUPPORTED               = 0xF,
1871        I40E_PHY_TYPE_100BASE_TX                = 0x11,
1872        I40E_PHY_TYPE_1000BASE_T                = 0x12,
1873        I40E_PHY_TYPE_10GBASE_T                 = 0x13,
1874        I40E_PHY_TYPE_10GBASE_SR                = 0x14,
1875        I40E_PHY_TYPE_10GBASE_LR                = 0x15,
1876        I40E_PHY_TYPE_10GBASE_SFPP_CU           = 0x16,
1877        I40E_PHY_TYPE_10GBASE_CR1               = 0x17,
1878        I40E_PHY_TYPE_40GBASE_CR4               = 0x18,
1879        I40E_PHY_TYPE_40GBASE_SR4               = 0x19,
1880        I40E_PHY_TYPE_40GBASE_LR4               = 0x1A,
1881        I40E_PHY_TYPE_1000BASE_SX               = 0x1B,
1882        I40E_PHY_TYPE_1000BASE_LX               = 0x1C,
1883        I40E_PHY_TYPE_1000BASE_T_OPTICAL        = 0x1D,
1884        I40E_PHY_TYPE_20GBASE_KR2               = 0x1E,
1885        I40E_PHY_TYPE_25GBASE_KR                = 0x1F,
1886        I40E_PHY_TYPE_25GBASE_CR                = 0x20,
1887        I40E_PHY_TYPE_25GBASE_SR                = 0x21,
1888        I40E_PHY_TYPE_25GBASE_LR                = 0x22,
1889        I40E_PHY_TYPE_25GBASE_AOC               = 0x23,
1890        I40E_PHY_TYPE_25GBASE_ACC               = 0x24,
1891        I40E_PHY_TYPE_2_5GBASE_T                = 0x30,
1892        I40E_PHY_TYPE_5GBASE_T                  = 0x31,
1893        I40E_PHY_TYPE_MAX,
1894        I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP   = 0xFD,
1895        I40E_PHY_TYPE_EMPTY                     = 0xFE,
1896        I40E_PHY_TYPE_DEFAULT                   = 0xFF,
1897};
1898
1899#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1900                                BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1901                                BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1902                                BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1903                                BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1904                                BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1905                                BIT_ULL(I40E_PHY_TYPE_XFI) | \
1906                                BIT_ULL(I40E_PHY_TYPE_SFI) | \
1907                                BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1908                                BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1909                                BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1910                                BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1911                                BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1912                                BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1913                                BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1914                                BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1915                                BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1916                                BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1917                                BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1918                                BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1919                                BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1920                                BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1921                                BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1922                                BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1923                                BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1924                                BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1925                                BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1926                                BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1927                                BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1928                                BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1929                                BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1930                                BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1931                                BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1932                                BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1933                                BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1934                                BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1935                                BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1936                                BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1937
1938#define I40E_LINK_SPEED_2_5GB_SHIFT     0x0
1939#define I40E_LINK_SPEED_100MB_SHIFT     0x1
1940#define I40E_LINK_SPEED_1000MB_SHIFT    0x2
1941#define I40E_LINK_SPEED_10GB_SHIFT      0x3
1942#define I40E_LINK_SPEED_40GB_SHIFT      0x4
1943#define I40E_LINK_SPEED_20GB_SHIFT      0x5
1944#define I40E_LINK_SPEED_25GB_SHIFT      0x6
1945#define I40E_LINK_SPEED_5GB_SHIFT       0x7
1946
1947enum i40e_aq_link_speed {
1948        I40E_LINK_SPEED_UNKNOWN = 0,
1949        I40E_LINK_SPEED_100MB   = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1950        I40E_LINK_SPEED_1GB     = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1951        I40E_LINK_SPEED_2_5GB   = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1952        I40E_LINK_SPEED_5GB     = (1 << I40E_LINK_SPEED_5GB_SHIFT),
1953        I40E_LINK_SPEED_10GB    = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1954        I40E_LINK_SPEED_40GB    = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1955        I40E_LINK_SPEED_20GB    = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1956        I40E_LINK_SPEED_25GB    = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1957};
1958
1959struct i40e_aqc_module_desc {
1960        u8 oui[3];
1961        u8 reserved1;
1962        u8 part_number[16];
1963        u8 revision[4];
1964        u8 reserved2[8];
1965};
1966
1967I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1968
1969struct i40e_aq_get_phy_abilities_resp {
1970        __le32  phy_type;       /* bitmap using the above enum for offsets */
1971        u8      link_speed;     /* bitmap using the above enum bit patterns */
1972        u8      abilities;
1973#define I40E_AQ_PHY_FLAG_PAUSE_TX       0x01
1974#define I40E_AQ_PHY_FLAG_PAUSE_RX       0x02
1975#define I40E_AQ_PHY_FLAG_LOW_POWER      0x04
1976#define I40E_AQ_PHY_LINK_ENABLED        0x08
1977#define I40E_AQ_PHY_AN_ENABLED          0x10
1978#define I40E_AQ_PHY_FLAG_MODULE_QUAL    0x20
1979#define I40E_AQ_PHY_FEC_ABILITY_KR      0x40
1980#define I40E_AQ_PHY_FEC_ABILITY_RS      0x80
1981        __le16  eee_capability;
1982#define I40E_AQ_EEE_100BASE_TX          0x0002
1983#define I40E_AQ_EEE_1000BASE_T          0x0004
1984#define I40E_AQ_EEE_10GBASE_T           0x0008
1985#define I40E_AQ_EEE_1000BASE_KX         0x0010
1986#define I40E_AQ_EEE_10GBASE_KX4         0x0020
1987#define I40E_AQ_EEE_10GBASE_KR          0x0040
1988        __le32  eeer_val;
1989        u8      d3_lpan;
1990#define I40E_AQ_SET_PHY_D3_LPAN_ENA     0x01
1991        u8      phy_type_ext;
1992#define I40E_AQ_PHY_TYPE_EXT_25G_KR     0X01
1993#define I40E_AQ_PHY_TYPE_EXT_25G_CR     0X02
1994#define I40E_AQ_PHY_TYPE_EXT_25G_SR     0x04
1995#define I40E_AQ_PHY_TYPE_EXT_25G_LR     0x08
1996#define I40E_AQ_PHY_TYPE_EXT_25G_AOC    0x10
1997#define I40E_AQ_PHY_TYPE_EXT_25G_ACC    0x20
1998#define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40
1999#define I40E_AQ_PHY_TYPE_EXT_5GBASE_T   0x80
2000        u8      fec_cfg_curr_mod_ext_info;

2001#define I40E_AQ_ENABLE_FEC_KR           0x01
2002#define I40E_AQ_ENABLE_FEC_RS           0x02
2003#define I40E_AQ_REQUEST_FEC_KR          0x04
2004#define I40E_AQ_REQUEST_FEC_RS          0x08
2005#define I40E_AQ_ENABLE_FEC_AUTO         0x10
2006#define I40E_AQ_FEC
2007#define I40E_AQ_MODULE_TYPE_EXT_MASK    0xE0
2008#define I40E_AQ_MODULE_TYPE_EXT_SHIFT   5
2009
2010        u8      ext_comp_code;
2011        u8      phy_id[4];
2012        u8      module_type[3];
2013        u8      qualified_module_count;
2014#define I40E_AQ_PHY_MAX_QMS             16
2015        struct i40e_aqc_module_desc     qualified_module[I40E_AQ_PHY_MAX_QMS];
2016};
2017
2018I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
2019
2020/* Set PHY Config (direct 0x0601) */
2021struct i40e_aq_set_phy_config { /* same bits as above in all */
2022        __le32  phy_type;
2023        u8      link_speed;
2024        u8      abilities;
2025/* bits 0-2 use the values from get_phy_abilities_resp */
2026#define I40E_AQ_PHY_ENABLE_LINK         0x08
2027#define I40E_AQ_PHY_ENABLE_AN           0x10
2028#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK  0x20
2029        __le16  eee_capability;
2030        __le32  eeer;
2031        u8      low_power_ctrl;
2032        u8      phy_type_ext;
2033#define I40E_AQ_PHY_TYPE_EXT_25G_KR     0X01
2034#define I40E_AQ_PHY_TYPE_EXT_25G_CR     0X02
2035#define I40E_AQ_PHY_TYPE_EXT_25G_SR     0x04
2036#define I40E_AQ_PHY_TYPE_EXT_25G_LR     0x08
2037        u8      fec_config;
2038#define I40E_AQ_SET_FEC_ABILITY_KR      BIT(0)
2039#define I40E_AQ_SET_FEC_ABILITY_RS      BIT(1)
2040#define I40E_AQ_SET_FEC_REQUEST_KR      BIT(2)
2041#define I40E_AQ_SET_FEC_REQUEST_RS      BIT(3)
2042#define I40E_AQ_SET_FEC_AUTO            BIT(4)
2043#define I40E_AQ_PHY_FEC_CONFIG_SHIFT    0x0
2044#define I40E_AQ_PHY_FEC_CONFIG_MASK     (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2045        u8      reserved;
2046};
2047
2048I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
2049
2050/* Set MAC Config command data structure (direct 0x0603) */
2051struct i40e_aq_set_mac_config {
2052        __le16  max_frame_size;
2053        u8      params;
2054#define I40E_AQ_SET_MAC_CONFIG_CRC_EN           0x04
2055#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK      0x78
2056#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT     3
2057#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE      0x0
2058#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX   0xF
2059#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX   0x9
2060#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX   0x8
2061#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX   0x7
2062#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX   0x6
2063#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX   0x5
2064#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX   0x4
2065#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX   0x3
2066#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX   0x2
2067#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX   0x1
2068        u8      tx_timer_priority; /* bitmap */
2069        __le16  tx_timer_value;
2070        __le16  fc_refresh_threshold;
2071        u8      reserved[8];
2072};
2073
2074I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2075
2076/* Restart Auto-Negotiation (direct 0x605) */
2077struct i40e_aqc_set_link_restart_an {
2078        u8      command;
2079#define I40E_AQ_PHY_RESTART_AN  0x02
2080#define I40E_AQ_PHY_LINK_ENABLE 0x04
2081        u8      reserved[15];
2082};
2083
2084I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2085
2086/* Get Link Status cmd & response data structure (direct 0x0607) */
2087struct i40e_aqc_get_link_status {
2088        __le16  command_flags; /* only field set on command */
2089#define I40E_AQ_LSE_MASK                0x3
2090#define I40E_AQ_LSE_NOP                 0x0
2091#define I40E_AQ_LSE_DISABLE             0x2
2092#define I40E_AQ_LSE_ENABLE              0x3
2093/* only response uses this flag */
2094#define I40E_AQ_LSE_IS_ENABLED          0x1
2095        u8      phy_type;    /* i40e_aq_phy_type   */
2096        u8      link_speed;  /* i40e_aq_link_speed */
2097        u8      link_info;
2098#define I40E_AQ_LINK_UP                 0x01    /* obsolete */
2099#define I40E_AQ_LINK_UP_FUNCTION        0x01
2100#define I40E_AQ_LINK_FAULT              0x02
2101#define I40E_AQ_LINK_FAULT_TX           0x04
2102#define I40E_AQ_LINK_FAULT_RX           0x08
2103#define I40E_AQ_LINK_FAULT_REMOTE       0x10
2104#define I40E_AQ_LINK_UP_PORT            0x20
2105#define I40E_AQ_MEDIA_AVAILABLE         0x40
2106#define I40E_AQ_SIGNAL_DETECT           0x80
2107        u8      an_info;
2108#define I40E_AQ_AN_COMPLETED            0x01
2109#define I40E_AQ_LP_AN_ABILITY           0x02
2110#define I40E_AQ_PD_FAULT                0x04
2111#define I40E_AQ_FEC_EN                  0x08
2112#define I40E_AQ_PHY_LOW_POWER           0x10
2113#define I40E_AQ_LINK_PAUSE_TX           0x20
2114#define I40E_AQ_LINK_PAUSE_RX           0x40
2115#define I40E_AQ_QUALIFIED_MODULE        0x80
2116        u8      ext_info;
2117#define I40E_AQ_LINK_PHY_TEMP_ALARM     0x01
2118#define I40E_AQ_LINK_XCESSIVE_ERRORS    0x02
2119#define I40E_AQ_LINK_TX_SHIFT           0x02
2120#define I40E_AQ_LINK_TX_MASK            (0x03 << I40E_AQ_LINK_TX_SHIFT)
2121#define I40E_AQ_LINK_TX_ACTIVE          0x00
2122#define I40E_AQ_LINK_TX_DRAINED         0x01
2123#define I40E_AQ_LINK_TX_FLUSHED         0x03
2124#define I40E_AQ_LINK_FORCED_40G         0x10
2125/* 25G Error Codes */
2126#define I40E_AQ_25G_NO_ERR              0X00
2127#define I40E_AQ_25G_NOT_PRESENT         0X01
2128#define I40E_AQ_25G_NVM_CRC_ERR         0X02
2129#define I40E_AQ_25G_SBUS_UCODE_ERR      0X03
2130#define I40E_AQ_25G_SERDES_UCODE_ERR    0X04
2131#define I40E_AQ_25G_NIMB_UCODE_ERR      0X05
2132        u8      loopback; /* use defines from i40e_aqc_set_lb_mode */
2133/* Since firmware API 1.7 loopback field keeps power class info as well */
2134#define I40E_AQ_LOOPBACK_MASK           0x07
2135#define I40E_AQ_PWR_CLASS_SHIFT_LB      6
2136#define I40E_AQ_PWR_CLASS_MASK_LB       (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2137        __le16  max_frame_size;
2138        u8      config;
2139#define I40E_AQ_CONFIG_FEC_KR_ENA       0x01
2140#define I40E_AQ_CONFIG_FEC_RS_ENA       0x02
2141#define I40E_AQ_CONFIG_CRC_ENA          0x04
2142#define I40E_AQ_CONFIG_PACING_MASK      0x78
2143        union {
2144                struct {
2145                        u8      power_desc;
2146#define I40E_AQ_LINK_POWER_CLASS_1      0x00
2147#define I40E_AQ_LINK_POWER_CLASS_2      0x01
2148#define I40E_AQ_LINK_POWER_CLASS_3      0x02
2149#define I40E_AQ_LINK_POWER_CLASS_4      0x03
2150#define I40E_AQ_PWR_CLASS_MASK          0x03
2151                        u8      reserved[4];
2152                };
2153                struct {
2154                        u8      link_type[4];
2155                        u8      link_type_ext;
2156                };
2157        };
2158};
2159
2160I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2161
2162/* Set event mask command (direct 0x613) */
2163struct i40e_aqc_set_phy_int_mask {
2164        u8      reserved[8];
2165        __le16  event_mask;
2166#define I40E_AQ_EVENT_LINK_UPDOWN       0x0002
2167#define I40E_AQ_EVENT_MEDIA_NA          0x0004
2168#define I40E_AQ_EVENT_LINK_FAULT        0x0008
2169#define I40E_AQ_EVENT_PHY_TEMP_ALARM    0x0010
2170#define I40E_AQ_EVENT_EXCESSIVE_ERRORS  0x0020
2171#define I40E_AQ_EVENT_SIGNAL_DETECT     0x0040
2172#define I40E_AQ_EVENT_AN_COMPLETED      0x0080
2173#define I40E_AQ_EVENT_MODULE_QUAL_FAIL  0x0100
2174#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2175        u8      reserved1[6];
2176};
2177
2178I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2179
2180/* Get Local AN advt register (direct 0x0614)
2181 * Set Local AN advt register (direct 0x0615)
2182 * Get Link Partner AN advt register (direct 0x0616)
2183 */
2184struct i40e_aqc_an_advt_reg {
2185        __le32  local_an_reg0;
2186        __le16  local_an_reg1;
2187        u8      reserved[10];
2188};
2189
2190I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2191
2192/* Set Loopback mode (0x0618) */
2193struct i40e_aqc_set_lb_mode {
2194        __le16  lb_mode;
2195#define I40E_AQ_LB_PHY_LOCAL    0x01
2196#define I40E_AQ_LB_PHY_REMOTE   0x02
2197#define I40E_AQ_LB_MAC_LOCAL    0x04
2198        u8      reserved[14];
2199};
2200
2201I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2202
2203/* Set PHY Debug command (0x0622) */
2204struct i40e_aqc_set_phy_debug {
2205        u8      command_flags;
2206#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL        0x02
2207#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT  2
2208#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK   (0x03 << \
2209                                        I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2210#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE   0x00
2211#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD   0x01
2212#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT   0x02
2213/* Disable link manageability on a single port */
2214#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW       0x10
2215/* Disable link manageability on all ports */
2216#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW   0x20
2217        u8      reserved[15];
2218};
2219
2220I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2221
2222enum i40e_aq_phy_reg_type {
2223        I40E_AQC_PHY_REG_INTERNAL       = 0x1,
2224        I40E_AQC_PHY_REG_EXERNAL_BASET  = 0x2,
2225        I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2226};
2227
2228/* Run PHY Activity (0x0626) */
2229struct i40e_aqc_run_phy_activity {
2230        __le16  activity_id;
2231        u8      flags;
2232        u8      reserved1;
2233        __le32  control;
2234        __le32  data;
2235        u8      reserved2[4];
2236};
2237
2238I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2239
2240/* Set PHY Register command (0x0628) */
2241/* Get PHY Register command (0x0629) */
2242struct i40e_aqc_phy_register_access {
2243        u8      phy_interface;
2244#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2245#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2246#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE  2
2247        u8      dev_address;
2248        u8      reserved1[2];
2249        __le32  reg_address;
2250        __le32  reg_value;
2251        u8      reserved2[4];
2252};
2253
2254I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2255
2256/* NVM Read command (indirect 0x0701)
2257 * NVM Erase commands (direct 0x0702)
2258 * NVM Update commands (indirect 0x0703)
2259 */
2260struct i40e_aqc_nvm_update {
2261        u8      command_flags;
2262#define I40E_AQ_NVM_LAST_CMD                    0x01
2263#define I40E_AQ_NVM_REARRANGE_TO_FLAT           0x20
2264#define I40E_AQ_NVM_REARRANGE_TO_STRUCT         0x40
2265#define I40E_AQ_NVM_FLASH_ONLY                  0x80
2266#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT    1
2267#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK     0x03
2268#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2269#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL      0x01
2270        u8      module_pointer;
2271        __le16  length;
2272        __le32  offset;
2273        __le32  addr_high;
2274        __le32  addr_low;
2275};
2276
2277I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2278
2279/* NVM Config Read (indirect 0x0704) */
2280struct i40e_aqc_nvm_config_read {
2281        __le16  cmd_flags;
2282#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK   1 
2283#define I40E_AQ_ANVM_READ_SINGLE_FEATURE                0 
2284#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES             1
2285        __le16  element_count;
2286        __le16  element_id;     /* Feature/field ID */
2287        __le16  element_id_msw; /* MSWord of field ID */
2288        __le32  address_high;
2289        __le32  address_low;
2290};
2291
2292I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2293
2294/* NVM Config Write (indirect 0x0705) */
2295struct i40e_aqc_nvm_config_write {
2296        __le16  cmd_flags;
2297        __le16  element_count;
2298        u8      reserved[4];
2299        __le32  address_high;
2300        __le32  address_low;
2301};
2302
2303I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2304
2305/* Used for 0x0704 as well as for 0x0705 commands */
2306#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT         1
2307#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2308                                BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2309#define I40E_AQ_ANVM_FEATURE            0
2310#define I40E_AQ_ANVM_IMMEDIATE_FIELD    BIT(FEATURE_OR_IMMEDIATE_SHIFT)
2311struct i40e_aqc_nvm_config_data_feature {
2312        __le16 feature_id;
2313#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY            0x01
2314#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP           0x08
2315#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR             0x10
2316        __le16 feature_options;
2317        __le16 feature_selection;
2318};
2319
2320I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2321
2322struct i40e_aqc_nvm_config_data_immediate_field {
2323        __le32 field_id;
2324        __le32 field_value;
2325        __le16 field_options;
2326        __le16 reserved;
2327};
2328
2329I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2330
2331/* OEM Post Update (indirect 0x0720)
2332 * no command data struct used
2333 */
2334struct i40e_aqc_nvm_oem_post_update {
2335#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA       0x01
2336        u8 sel_data;
2337        u8 reserved[7];
2338};
2339
2340I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2341
2342struct i40e_aqc_nvm_oem_post_update_buffer {
2343        u8 str_len;
2344        u8 dev_addr;
2345        __le16 eeprom_addr;
2346        u8 data[36];
2347};
2348
2349I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2350
2351/* Thermal Sensor (indirect 0x0721)
2352 *     read or set thermal sensor configs and values
2353 *     takes a sensor and command specific data buffer, not detailed here
2354 */
2355struct i40e_aqc_thermal_sensor {
2356        u8 sensor_action;
2357#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG      0
2358#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG       1
2359#define I40E_AQ_THERMAL_SENSOR_READ_TEMP        2
2360        u8 reserved[7];
2361        __le32  addr_high;
2362        __le32  addr_low;
2363};
2364
2365I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2366
2367/* Send to PF command (indirect 0x0801) id is only used by PF
2368 * Send to VF command (indirect 0x0802) id is only used by PF
2369 * Send to Peer PF command (indirect 0x0803)
2370 */
2371struct i40e_aqc_pf_vf_message {
2372        __le32  id;
2373        u8      reserved[4];
2374        __le32  addr_high;
2375        __le32  addr_low;
2376};
2377
2378I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2379
2380/* Alternate structure */
2381
2382/* Direct write (direct 0x0900)
2383 * Direct read (direct 0x0902)
2384 */
2385struct i40e_aqc_alternate_write {
2386        __le32 address0;
2387        __le32 data0;
2388        __le32 address1;
2389        __le32 data1;
2390};
2391
2392I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2393
2394/* Indirect write (indirect 0x0901)
2395 * Indirect read (indirect 0x0903)
2396 */
2397
2398struct i40e_aqc_alternate_ind_write {
2399        __le32 address;
2400        __le32 length;
2401        __le32 addr_high;
2402        __le32 addr_low;
2403};
2404
2405I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2406
2407/* Done alternate write (direct 0x0904)
2408 * uses i40e_aq_desc
2409 */
2410struct i40e_aqc_alternate_write_done {
2411        __le16  cmd_flags;
2412#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK        1
2413#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY      0
2414#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI        1
2415#define I40E_AQ_ALTERNATE_RESET_NEEDED          2
2416        u8      reserved[14];
2417};
2418
2419I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2420
2421/* Set OEM mode (direct 0x0905) */
2422struct i40e_aqc_alternate_set_mode {
2423        __le32  mode;
2424#define I40E_AQ_ALTERNATE_MODE_NONE     0
2425#define I40E_AQ_ALTERNATE_MODE_OEM      1
2426        u8      reserved[12];
2427};
2428
2429I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2430
2431/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2432
2433/* async events 0x10xx */
2434
2435/* Lan Queue Overflow Event (direct, 0x1001) */
2436struct i40e_aqc_lan_overflow {
2437        __le32  prtdcb_rupto;
2438        __le32  otx_ctl;
2439        u8      reserved[8];
2440};
2441
2442I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2443
2444/* Get LLDP MIB (indirect 0x0A00) */
2445struct i40e_aqc_lldp_get_mib {
2446        u8      type;
2447        u8      reserved1;
2448#define I40E_AQ_LLDP_MIB_TYPE_MASK              0x3
2449#define I40E_AQ_LLDP_MIB_LOCAL                  0x0
2450#define I40E_AQ_LLDP_MIB_REMOTE                 0x1
2451#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE       0x2
2452#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK           0xC
2453#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT          0x2
2454#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2455#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR       0x1
2456#define I40E_AQ_LLDP_TX_SHIFT                   0x4
2457#define I40E_AQ_LLDP_TX_MASK                    (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2458/* TX pause flags use I40E_AQ_LINK_TX_* above */
2459        __le16  local_len;
2460        __le16  remote_len;
2461        u8      reserved2[2];
2462        __le32  addr_high;
2463        __le32  addr_low;
2464};
2465
2466I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2467
2468/* Configure LLDP MIB Change Event (direct 0x0A01)
2469 * also used for the event (with type in the command field)
2470 */
2471struct i40e_aqc_lldp_update_mib {
2472        u8      command;
2473#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE  0x0
2474#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2475        u8      reserved[7];
2476        __le32  addr_high;
2477        __le32  addr_low;
2478};
2479
2480I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2481
2482/* Add LLDP TLV (indirect 0x0A02)
2483 * Delete LLDP TLV (indirect 0x0A04)
2484 */
2485struct i40e_aqc_lldp_add_tlv {
2486        u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2487        u8      reserved1[1];
2488        __le16  len;
2489        u8      reserved2[4];
2490        __le32  addr_high;
2491        __le32  addr_low;
2492};
2493
2494I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2495
2496/* Update LLDP TLV (indirect 0x0A03) */
2497struct i40e_aqc_lldp_update_tlv {
2498        u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2499        u8      reserved;
2500        __le16  old_len;
2501        __le16  new_offset;
2502        __le16  new_len;
2503        __le32  addr_high;
2504        __le32  addr_low;
2505};
2506
2507I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2508
2509/* Stop LLDP (direct 0x0A05) */
2510struct i40e_aqc_lldp_stop {
2511        u8      command;
2512#define I40E_AQ_LLDP_AGENT_STOP                 0x0
2513#define I40E_AQ_LLDP_AGENT_SHUTDOWN             0x1
2514#define I40E_AQ_LLDP_AGENT_STOP_PERSIST         0x2
2515        u8      reserved[15];
2516};
2517
2518I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2519
2520/* Start LLDP (direct 0x0A06) */
2521struct i40e_aqc_lldp_start {
2522        u8      command;
2523#define I40E_AQ_LLDP_AGENT_START                0x1
2524#define I40E_AQ_LLDP_AGENT_START_PERSIST        0x2
2525        u8      reserved[15];
2526};
2527
2528I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2529
2530/* Set DCB (direct 0x0303) */
2531struct i40e_aqc_set_dcb_parameters {
2532        u8 command;
2533#define I40E_AQ_DCB_SET_AGENT   0x1
2534#define I40E_DCB_VALID          0x1
2535        u8 valid_flags;
2536        u8 reserved[14];
2537};
2538
2539I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2540
2541/* Get CEE DCBX Oper Config (0x0A07)
2542 * uses the generic descriptor struct
2543 * returns below as indirect response
2544 */
2545
2546#define I40E_AQC_CEE_APP_FCOE_SHIFT     0x0
2547#define I40E_AQC_CEE_APP_FCOE_MASK      (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2548#define I40E_AQC_CEE_APP_ISCSI_SHIFT    0x3
2549#define I40E_AQC_CEE_APP_ISCSI_MASK     (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2550#define I40E_AQC_CEE_APP_FIP_SHIFT      0x8
2551#define I40E_AQC_CEE_APP_FIP_MASK       (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2552
2553#define I40E_AQC_CEE_PG_STATUS_SHIFT    0x0
2554#define I40E_AQC_CEE_PG_STATUS_MASK     (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2555#define I40E_AQC_CEE_PFC_STATUS_SHIFT   0x3
2556#define I40E_AQC_CEE_PFC_STATUS_MASK    (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2557#define I40E_AQC_CEE_APP_STATUS_SHIFT   0x8
2558#define I40E_AQC_CEE_APP_STATUS_MASK    (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2559#define I40E_AQC_CEE_FCOE_STATUS_SHIFT  0x8
2560#define I40E_AQC_CEE_FCOE_STATUS_MASK   (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2561#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2562#define I40E_AQC_CEE_ISCSI_STATUS_MASK  (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2563#define I40E_AQC_CEE_FIP_STATUS_SHIFT   0x10
2564#define I40E_AQC_CEE_FIP_STATUS_MASK    (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2565
2566/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2567 * word boundary layout issues, which the Linux compilers silently deal
2568 * with by adding padding, making the actual struct larger than designed.
2569 * However, the FW compiler for the NIC is less lenient and complains
2570 * about the struct.  Hence, the struct defined here has an extra byte in
2571 * fields reserved3 and reserved4 to directly acknowledge that padding,
2572 * and the new length is used in the length check macro.
2573 */
2574struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2575        u8      reserved1;
2576        u8      oper_num_tc;
2577        u8      oper_prio_tc[4];
2578        u8      reserved2;
2579        u8      oper_tc_bw[8];
2580        u8      oper_pfc_en;
2581        u8      reserved3[2];
2582        __le16  oper_app_prio;
2583        u8      reserved4[2];
2584        __le16  tlv_status;
2585};
2586
2587I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2588
2589struct i40e_aqc_get_cee_dcb_cfg_resp {
2590        u8      oper_num_tc;
2591        u8      oper_prio_tc[4];
2592        u8      oper_tc_bw[8];
2593        u8      oper_pfc_en;
2594        __le16  oper_app_prio;
2595#define I40E_AQC_CEE_APP_FCOE_SHIFT     0x0
2596#define I40E_AQC_CEE_APP_FCOE_MASK      (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2597#define I40E_AQC_CEE_APP_ISCSI_SHIFT    0x3
2598#define I40E_AQC_CEE_APP_ISCSI_MASK     (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2599#define I40E_AQC_CEE_APP_FIP_SHIFT      0x8
2600#define I40E_AQC_CEE_APP_FIP_MASK       (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2601#define I40E_AQC_CEE_APP_FIP_MASK       (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2602        __le32  tlv_status;
2603#define I40E_AQC_CEE_PG_STATUS_SHIFT    0x0
2604#define I40E_AQC_CEE_PG_STATUS_MASK     (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2605#define I40E_AQC_CEE_PFC_STATUS_SHIFT   0x3
2606#define I40E_AQC_CEE_PFC_STATUS_MASK    (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2607#define I40E_AQC_CEE_APP_STATUS_SHIFT   0x8
2608#define I40E_AQC_CEE_APP_STATUS_MASK    (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2609        u8      reserved[12];
2610};
2611
2612I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2613
2614/*      Set Local LLDP MIB (indirect 0x0A08)
2615 *      Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2616 */
2617struct i40e_aqc_lldp_set_local_mib {
2618#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT        0
2619#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2620#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2621#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT    (1)
2622#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \
2623                        BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2624#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS          0x1
2625        u8      type;
2626        u8      reserved0;
2627        __le16  length;
2628        u8      reserved1[4];
2629        __le32  address_high;
2630        __le32  address_low;
2631};
2632
2633I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2634
2635/*      Stop/Start LLDP Agent (direct 0x0A09)
2636 *      Used for stopping/starting specific LLDP agent. e.g. DCBx
2637 */
2638struct i40e_aqc_lldp_stop_start_specific_agent {
2639#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT     0
2640#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2641                                BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2642        u8      command;
2643        u8      reserved[15];
2644};
2645
2646I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2647
2648/* Restore LLDP Agent factory settings (direct 0x0A0A) */
2649struct i40e_aqc_lldp_restore {
2650        u8      command;
2651#define I40E_AQ_LLDP_AGENT_RESTORE_NOT          0x0
2652#define I40E_AQ_LLDP_AGENT_RESTORE              0x1
2653        u8      reserved[15];
2654};
2655
2656I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2657
2658/* Add Udp Tunnel command and completion (direct 0x0B00) */
2659struct i40e_aqc_add_udp_tunnel {
2660        __le16  udp_port;
2661        u8      reserved0[3];
2662        u8      protocol_type;
2663#define I40E_AQC_TUNNEL_TYPE_VXLAN      0x00
2664#define I40E_AQC_TUNNEL_TYPE_NGE        0x01
2665#define I40E_AQC_TUNNEL_TYPE_TEREDO     0x10
2666#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE  0x11
2667        u8      reserved1[10];
2668};
2669
2670I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2671
2672struct i40e_aqc_add_udp_tunnel_completion {
2673        __le16  udp_port;
2674        u8      filter_entry_index;
2675        u8      multiple_pfs;
2676#define I40E_AQC_SINGLE_PF              0x0
2677#define I40E_AQC_MULTIPLE_PFS           0x1
2678        u8      total_filters;
2679        u8      reserved[11];
2680};
2681
2682I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2683
2684/* remove UDP Tunnel command (0x0B01) */
2685struct i40e_aqc_remove_udp_tunnel {
2686        u8      reserved[2];
2687        u8      index; /* 0 to 15 */
2688        u8      reserved2[13];
2689};
2690
2691I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2692
2693struct i40e_aqc_del_udp_tunnel_completion {
2694        __le16  udp_port;
2695        u8      index; /* 0 to 15 */
2696        u8      multiple_pfs;
2697        u8      total_filters_used;
2698        u8      reserved1[11];
2699};
2700
2701I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2702
2703struct i40e_aqc_get_set_rss_key {
2704#define I40E_AQC_SET_RSS_KEY_VSI_VALID          BIT(15)
2705#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT       0
2706#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK        (0x3FF << \
2707                                        I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2708        __le16  vsi_id;
2709        u8      reserved[6];
2710        __le32  addr_high;
2711        __le32  addr_low;
2712};
2713
2714I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2715
2716struct i40e_aqc_get_set_rss_key_data {
2717        u8 standard_rss_key[0x28];
2718        u8 extended_hash_key[0xc];
2719};
2720
2721I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2722
2723struct  i40e_aqc_get_set_rss_lut {
2724#define I40E_AQC_SET_RSS_LUT_VSI_VALID          BIT(15)
2725#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT       0
2726#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK        (0x3FF << \
2727                                        I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2728        __le16  vsi_id;
2729#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT   0
2730#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK    BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2731
2732#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI     0
2733#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF      1
2734        __le16  flags;
2735        u8      reserved[4];
2736        __le32  addr_high;
2737        __le32  addr_low;
2738};
2739
2740I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2741
2742/* tunnel key structure 0x0B10 */
2743
2744struct i40e_aqc_tunnel_key_structure {
2745        u8      key1_off;
2746        u8      key2_off;
2747        u8      key1_len;  /* 0 to 15 */
2748        u8      key2_len;  /* 0 to 15 */
2749        u8      flags;
2750#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE     0x01
2751/* response flags */
2752#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS      0x01
2753#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED     0x02
2754#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN   0x03
2755        u8      network_key_index;
2756#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN                0x0
2757#define I40E_AQC_NETWORK_KEY_INDEX_NGE                  0x1
2758#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP      0x2
2759#define I40E_AQC_NETWORK_KEY_INDEX_GRE                  0x3
2760        u8      reserved[10];
2761};
2762
2763I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2764
2765/* OEM mode commands (direct 0xFE0x) */
2766struct i40e_aqc_oem_param_change {
2767        __le32  param_type;
2768#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL   0
2769#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL   1
2770#define I40E_AQ_OEM_PARAM_MAC           2
2771        __le32  param_value1;
2772        __le16  param_value2;
2773        u8      reserved[6];
2774};
2775
2776I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2777
2778struct i40e_aqc_oem_state_change {
2779        __le32  state;
2780#define I40E_AQ_OEM_STATE_LINK_DOWN     0x0
2781#define I40E_AQ_OEM_STATE_LINK_UP       0x1
2782        u8      reserved[12];
2783};
2784
2785I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2786
2787/* Initialize OCSD (0xFE02, direct) */
2788struct i40e_aqc_opc_oem_ocsd_initialize {
2789        u8 type_status;
2790        u8 reserved1[3];
2791        __le32 ocsd_memory_block_addr_high;
2792        __le32 ocsd_memory_block_addr_low;
2793        __le32 requested_update_interval;
2794};
2795
2796I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2797
2798/* Initialize OCBB  (0xFE03, direct) */
2799struct i40e_aqc_opc_oem_ocbb_initialize {
2800        u8 type_status;
2801        u8 reserved1[3];
2802        __le32 ocbb_memory_block_addr_high;
2803        __le32 ocbb_memory_block_addr_low;
2804        u8 reserved2[4];
2805};
2806
2807I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2808
2809/* debug commands */
2810
2811/* get device id (0xFF00) uses the generic structure */
2812
2813/* set test more (0xFF01, internal) */
2814
2815struct i40e_acq_set_test_mode {
2816        u8      mode;
2817#define I40E_AQ_TEST_PARTIAL    0
2818#define I40E_AQ_TEST_FULL       1
2819#define I40E_AQ_TEST_NVM        2
2820        u8      reserved[3];
2821        u8      command;
2822#define I40E_AQ_TEST_OPEN       0
2823#define I40E_AQ_TEST_CLOSE      1
2824#define I40E_AQ_TEST_INC        2
2825        u8      reserved2[3];
2826        __le32  address_high;
2827        __le32  address_low;
2828};
2829
2830I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2831
2832/* Debug Read Register command (0xFF03)
2833 * Debug Write Register command (0xFF04)
2834 */
2835struct i40e_aqc_debug_reg_read_write {
2836        __le32 reserved;
2837        __le32 address;
2838        __le32 value_high;
2839        __le32 value_low;
2840};
2841
2842I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2843
2844/* Scatter/gather Reg Read  (indirect 0xFF05)
2845 * Scatter/gather Reg Write (indirect 0xFF06)
2846 */
2847
2848/* i40e_aq_desc is used for the command */
2849struct i40e_aqc_debug_reg_sg_element_data {
2850        __le32 address;
2851        __le32 value;
2852};
2853
2854/* Debug Modify register (direct 0xFF07) */
2855struct i40e_aqc_debug_modify_reg {
2856        __le32 address;
2857        __le32 value;
2858        __le32 clear_mask;
2859        __le32 set_mask;
2860};
2861
2862I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2863
2864/* dump internal data (0xFF08, indirect) */
2865
2866#define I40E_AQ_CLUSTER_ID_AUX          0
2867#define I40E_AQ_CLUSTER_ID_SWITCH_FLU   1
2868#define I40E_AQ_CLUSTER_ID_TXSCHED      2
2869#define I40E_AQ_CLUSTER_ID_HMC          3
2870#define I40E_AQ_CLUSTER_ID_MAC0         4
2871#define I40E_AQ_CLUSTER_ID_MAC1         5
2872#define I40E_AQ_CLUSTER_ID_MAC2         6
2873#define I40E_AQ_CLUSTER_ID_MAC3         7
2874#define I40E_AQ_CLUSTER_ID_DCB          8
2875#define I40E_AQ_CLUSTER_ID_EMP_MEM      9
2876#define I40E_AQ_CLUSTER_ID_PKT_BUF      10
2877#define I40E_AQ_CLUSTER_ID_ALTRAM       11
2878
2879struct i40e_aqc_debug_dump_internals {
2880        u8      cluster_id;
2881        u8      table_id;
2882        __le16  data_size;
2883        __le32  idx;
2884        __le32  address_high;
2885        __le32  address_low;
2886};
2887
2888I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2889
2890struct i40e_aqc_debug_modify_internals {
2891        u8      cluster_id;
2892        u8      cluster_specific_params[7];
2893        __le32  address_high;
2894        __le32  address_low;
2895};
2896
2897I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2898
2899#endif /* _I40E_ADMINQ_CMD_H_ */
2900