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6#include "i40e.h"
7#include "i40e_diag.h"
8#include "i40e_txrx_common.h"
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34struct i40e_stats {
35 char stat_string[ETH_GSTRING_LEN];
36 int sizeof_stat;
37 int stat_offset;
38};
39
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43
44#define I40E_STAT(_type, _name, _stat) { \
45 .stat_string = _name, \
46 .sizeof_stat = FIELD_SIZEOF(_type, _stat), \
47 .stat_offset = offsetof(_type, _stat) \
48}
49
50
51
52
53#define I40E_NETDEV_STAT(_net_stat) \
54 I40E_STAT(struct rtnl_link_stats64, #_net_stat, _net_stat)
55
56
57#define I40E_QUEUE_STAT(_name, _stat) \
58 I40E_STAT(struct i40e_ring, _name, _stat)
59
60
61static const struct i40e_stats i40e_gstrings_queue_stats[] = {
62 I40E_QUEUE_STAT("%s-%u.packets", stats.packets),
63 I40E_QUEUE_STAT("%s-%u.bytes", stats.bytes),
64};
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75
76static void
77i40e_add_one_ethtool_stat(u64 *data, void *pointer,
78 const struct i40e_stats *stat)
79{
80 char *p;
81
82 if (!pointer) {
83
84
85
86 *data = 0;
87 return;
88 }
89
90 p = (char *)pointer + stat->stat_offset;
91 switch (stat->sizeof_stat) {
92 case sizeof(u64):
93 *data = *((u64 *)p);
94 break;
95 case sizeof(u32):
96 *data = *((u32 *)p);
97 break;
98 case sizeof(u16):
99 *data = *((u16 *)p);
100 break;
101 case sizeof(u8):
102 *data = *((u8 *)p);
103 break;
104 default:
105 WARN_ONCE(1, "unexpected stat size for %s",
106 stat->stat_string);
107 *data = 0;
108 }
109}
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123
124static void
125__i40e_add_ethtool_stats(u64 **data, void *pointer,
126 const struct i40e_stats stats[],
127 const unsigned int size)
128{
129 unsigned int i;
130
131 for (i = 0; i < size; i++)
132 i40e_add_one_ethtool_stat((*data)++, pointer, &stats[i]);
133}
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148#define i40e_add_ethtool_stats(data, pointer, stats) \
149 __i40e_add_ethtool_stats(data, pointer, stats, ARRAY_SIZE(stats))
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165static void
166i40e_add_queue_stats(u64 **data, struct i40e_ring *ring)
167{
168 const unsigned int size = ARRAY_SIZE(i40e_gstrings_queue_stats);
169 const struct i40e_stats *stats = i40e_gstrings_queue_stats;
170 unsigned int start;
171 unsigned int i;
172
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176
177
178 do {
179 start = !ring ? 0 : u64_stats_fetch_begin_irq(&ring->syncp);
180 for (i = 0; i < size; i++) {
181 i40e_add_one_ethtool_stat(&(*data)[i], ring,
182 &stats[i]);
183 }
184 } while (ring && u64_stats_fetch_retry_irq(&ring->syncp, start));
185
186
187 *data += size;
188}
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199static void __i40e_add_stat_strings(u8 **p, const struct i40e_stats stats[],
200 const unsigned int size, ...)
201{
202 unsigned int i;
203
204 for (i = 0; i < size; i++) {
205 va_list args;
206
207 va_start(args, size);
208 vsnprintf(*p, ETH_GSTRING_LEN, stats[i].stat_string, args);
209 *p += ETH_GSTRING_LEN;
210 va_end(args);
211 }
212}
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226#define i40e_add_stat_strings(p, stats, ...) \
227 __i40e_add_stat_strings(p, stats, ARRAY_SIZE(stats), ## __VA_ARGS__)
228
229#define I40E_PF_STAT(_name, _stat) \
230 I40E_STAT(struct i40e_pf, _name, _stat)
231#define I40E_VSI_STAT(_name, _stat) \
232 I40E_STAT(struct i40e_vsi, _name, _stat)
233#define I40E_VEB_STAT(_name, _stat) \
234 I40E_STAT(struct i40e_veb, _name, _stat)
235#define I40E_PFC_STAT(_name, _stat) \
236 I40E_STAT(struct i40e_pfc_stats, _name, _stat)
237#define I40E_QUEUE_STAT(_name, _stat) \
238 I40E_STAT(struct i40e_ring, _name, _stat)
239
240static const struct i40e_stats i40e_gstrings_net_stats[] = {
241 I40E_NETDEV_STAT(rx_packets),
242 I40E_NETDEV_STAT(tx_packets),
243 I40E_NETDEV_STAT(rx_bytes),
244 I40E_NETDEV_STAT(tx_bytes),
245 I40E_NETDEV_STAT(rx_errors),
246 I40E_NETDEV_STAT(tx_errors),
247 I40E_NETDEV_STAT(rx_dropped),
248 I40E_NETDEV_STAT(tx_dropped),
249 I40E_NETDEV_STAT(collisions),
250 I40E_NETDEV_STAT(rx_length_errors),
251 I40E_NETDEV_STAT(rx_crc_errors),
252};
253
254static const struct i40e_stats i40e_gstrings_veb_stats[] = {
255 I40E_VEB_STAT("veb.rx_bytes", stats.rx_bytes),
256 I40E_VEB_STAT("veb.tx_bytes", stats.tx_bytes),
257 I40E_VEB_STAT("veb.rx_unicast", stats.rx_unicast),
258 I40E_VEB_STAT("veb.tx_unicast", stats.tx_unicast),
259 I40E_VEB_STAT("veb.rx_multicast", stats.rx_multicast),
260 I40E_VEB_STAT("veb.tx_multicast", stats.tx_multicast),
261 I40E_VEB_STAT("veb.rx_broadcast", stats.rx_broadcast),
262 I40E_VEB_STAT("veb.tx_broadcast", stats.tx_broadcast),
263 I40E_VEB_STAT("veb.rx_discards", stats.rx_discards),
264 I40E_VEB_STAT("veb.tx_discards", stats.tx_discards),
265 I40E_VEB_STAT("veb.tx_errors", stats.tx_errors),
266 I40E_VEB_STAT("veb.rx_unknown_protocol", stats.rx_unknown_protocol),
267};
268
269static const struct i40e_stats i40e_gstrings_veb_tc_stats[] = {
270 I40E_VEB_STAT("veb.tc_%u_tx_packets", tc_stats.tc_tx_packets),
271 I40E_VEB_STAT("veb.tc_%u_tx_bytes", tc_stats.tc_tx_bytes),
272 I40E_VEB_STAT("veb.tc_%u_rx_packets", tc_stats.tc_rx_packets),
273 I40E_VEB_STAT("veb.tc_%u_rx_bytes", tc_stats.tc_rx_bytes),
274};
275
276static const struct i40e_stats i40e_gstrings_misc_stats[] = {
277 I40E_VSI_STAT("rx_unicast", eth_stats.rx_unicast),
278 I40E_VSI_STAT("tx_unicast", eth_stats.tx_unicast),
279 I40E_VSI_STAT("rx_multicast", eth_stats.rx_multicast),
280 I40E_VSI_STAT("tx_multicast", eth_stats.tx_multicast),
281 I40E_VSI_STAT("rx_broadcast", eth_stats.rx_broadcast),
282 I40E_VSI_STAT("tx_broadcast", eth_stats.tx_broadcast),
283 I40E_VSI_STAT("rx_unknown_protocol", eth_stats.rx_unknown_protocol),
284 I40E_VSI_STAT("tx_linearize", tx_linearize),
285 I40E_VSI_STAT("tx_force_wb", tx_force_wb),
286 I40E_VSI_STAT("tx_busy", tx_busy),
287 I40E_VSI_STAT("rx_alloc_fail", rx_buf_failed),
288 I40E_VSI_STAT("rx_pg_alloc_fail", rx_page_failed),
289};
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301static const struct i40e_stats i40e_gstrings_stats[] = {
302 I40E_PF_STAT("port.rx_bytes", stats.eth.rx_bytes),
303 I40E_PF_STAT("port.tx_bytes", stats.eth.tx_bytes),
304 I40E_PF_STAT("port.rx_unicast", stats.eth.rx_unicast),
305 I40E_PF_STAT("port.tx_unicast", stats.eth.tx_unicast),
306 I40E_PF_STAT("port.rx_multicast", stats.eth.rx_multicast),
307 I40E_PF_STAT("port.tx_multicast", stats.eth.tx_multicast),
308 I40E_PF_STAT("port.rx_broadcast", stats.eth.rx_broadcast),
309 I40E_PF_STAT("port.tx_broadcast", stats.eth.tx_broadcast),
310 I40E_PF_STAT("port.tx_errors", stats.eth.tx_errors),
311 I40E_PF_STAT("port.rx_dropped", stats.eth.rx_discards),
312 I40E_PF_STAT("port.tx_dropped_link_down", stats.tx_dropped_link_down),
313 I40E_PF_STAT("port.rx_crc_errors", stats.crc_errors),
314 I40E_PF_STAT("port.illegal_bytes", stats.illegal_bytes),
315 I40E_PF_STAT("port.mac_local_faults", stats.mac_local_faults),
316 I40E_PF_STAT("port.mac_remote_faults", stats.mac_remote_faults),
317 I40E_PF_STAT("port.tx_timeout", tx_timeout_count),
318 I40E_PF_STAT("port.rx_csum_bad", hw_csum_rx_error),
319 I40E_PF_STAT("port.rx_length_errors", stats.rx_length_errors),
320 I40E_PF_STAT("port.link_xon_rx", stats.link_xon_rx),
321 I40E_PF_STAT("port.link_xoff_rx", stats.link_xoff_rx),
322 I40E_PF_STAT("port.link_xon_tx", stats.link_xon_tx),
323 I40E_PF_STAT("port.link_xoff_tx", stats.link_xoff_tx),
324 I40E_PF_STAT("port.rx_size_64", stats.rx_size_64),
325 I40E_PF_STAT("port.rx_size_127", stats.rx_size_127),
326 I40E_PF_STAT("port.rx_size_255", stats.rx_size_255),
327 I40E_PF_STAT("port.rx_size_511", stats.rx_size_511),
328 I40E_PF_STAT("port.rx_size_1023", stats.rx_size_1023),
329 I40E_PF_STAT("port.rx_size_1522", stats.rx_size_1522),
330 I40E_PF_STAT("port.rx_size_big", stats.rx_size_big),
331 I40E_PF_STAT("port.tx_size_64", stats.tx_size_64),
332 I40E_PF_STAT("port.tx_size_127", stats.tx_size_127),
333 I40E_PF_STAT("port.tx_size_255", stats.tx_size_255),
334 I40E_PF_STAT("port.tx_size_511", stats.tx_size_511),
335 I40E_PF_STAT("port.tx_size_1023", stats.tx_size_1023),
336 I40E_PF_STAT("port.tx_size_1522", stats.tx_size_1522),
337 I40E_PF_STAT("port.tx_size_big", stats.tx_size_big),
338 I40E_PF_STAT("port.rx_undersize", stats.rx_undersize),
339 I40E_PF_STAT("port.rx_fragments", stats.rx_fragments),
340 I40E_PF_STAT("port.rx_oversize", stats.rx_oversize),
341 I40E_PF_STAT("port.rx_jabber", stats.rx_jabber),
342 I40E_PF_STAT("port.VF_admin_queue_requests", vf_aq_requests),
343 I40E_PF_STAT("port.arq_overflows", arq_overflows),
344 I40E_PF_STAT("port.tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
345 I40E_PF_STAT("port.rx_hwtstamp_cleared", rx_hwtstamp_cleared),
346 I40E_PF_STAT("port.tx_hwtstamp_skipped", tx_hwtstamp_skipped),
347 I40E_PF_STAT("port.fdir_flush_cnt", fd_flush_cnt),
348 I40E_PF_STAT("port.fdir_atr_match", stats.fd_atr_match),
349 I40E_PF_STAT("port.fdir_atr_tunnel_match", stats.fd_atr_tunnel_match),
350 I40E_PF_STAT("port.fdir_atr_status", stats.fd_atr_status),
351 I40E_PF_STAT("port.fdir_sb_match", stats.fd_sb_match),
352 I40E_PF_STAT("port.fdir_sb_status", stats.fd_sb_status),
353
354
355 I40E_PF_STAT("port.tx_lpi_status", stats.tx_lpi_status),
356 I40E_PF_STAT("port.rx_lpi_status", stats.rx_lpi_status),
357 I40E_PF_STAT("port.tx_lpi_count", stats.tx_lpi_count),
358 I40E_PF_STAT("port.rx_lpi_count", stats.rx_lpi_count),
359};
360
361struct i40e_pfc_stats {
362 u64 priority_xon_rx;
363 u64 priority_xoff_rx;
364 u64 priority_xon_tx;
365 u64 priority_xoff_tx;
366 u64 priority_xon_2_xoff;
367};
368
369static const struct i40e_stats i40e_gstrings_pfc_stats[] = {
370 I40E_PFC_STAT("port.tx_priority_%u_xon_tx", priority_xon_tx),
371 I40E_PFC_STAT("port.tx_priority_%u_xoff_tx", priority_xoff_tx),
372 I40E_PFC_STAT("port.rx_priority_%u_xon_rx", priority_xon_rx),
373 I40E_PFC_STAT("port.rx_priority_%u_xoff_rx", priority_xoff_rx),
374 I40E_PFC_STAT("port.rx_priority_%u_xon_2_xoff", priority_xon_2_xoff),
375};
376
377#define I40E_NETDEV_STATS_LEN ARRAY_SIZE(i40e_gstrings_net_stats)
378
379#define I40E_MISC_STATS_LEN ARRAY_SIZE(i40e_gstrings_misc_stats)
380
381#define I40E_VSI_STATS_LEN (I40E_NETDEV_STATS_LEN + I40E_MISC_STATS_LEN)
382
383#define I40E_PFC_STATS_LEN (ARRAY_SIZE(i40e_gstrings_pfc_stats) * \
384 I40E_MAX_USER_PRIORITY)
385
386#define I40E_VEB_STATS_LEN (ARRAY_SIZE(i40e_gstrings_veb_stats) + \
387 (ARRAY_SIZE(i40e_gstrings_veb_tc_stats) * \
388 I40E_MAX_TRAFFIC_CLASS))
389
390#define I40E_GLOBAL_STATS_LEN ARRAY_SIZE(i40e_gstrings_stats)
391
392#define I40E_PF_STATS_LEN (I40E_GLOBAL_STATS_LEN + \
393 I40E_PFC_STATS_LEN + \
394 I40E_VEB_STATS_LEN + \
395 I40E_VSI_STATS_LEN)
396
397
398#define I40E_QUEUE_STATS_LEN ARRAY_SIZE(i40e_gstrings_queue_stats)
399
400enum i40e_ethtool_test_id {
401 I40E_ETH_TEST_REG = 0,
402 I40E_ETH_TEST_EEPROM,
403 I40E_ETH_TEST_INTR,
404 I40E_ETH_TEST_LINK,
405};
406
407static const char i40e_gstrings_test[][ETH_GSTRING_LEN] = {
408 "Register test (offline)",
409 "Eeprom test (offline)",
410 "Interrupt test (offline)",
411 "Link test (on/offline)"
412};
413
414#define I40E_TEST_LEN (sizeof(i40e_gstrings_test) / ETH_GSTRING_LEN)
415
416struct i40e_priv_flags {
417 char flag_string[ETH_GSTRING_LEN];
418 u64 flag;
419 bool read_only;
420};
421
422#define I40E_PRIV_FLAG(_name, _flag, _read_only) { \
423 .flag_string = _name, \
424 .flag = _flag, \
425 .read_only = _read_only, \
426}
427
428static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = {
429
430 I40E_PRIV_FLAG("MFP", I40E_FLAG_MFP_ENABLED, 1),
431 I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENABLED, 0),
432 I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENABLED, 0),
433 I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENABLED, 0),
434 I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_ENABLED, 0),
435 I40E_PRIV_FLAG("link-down-on-close",
436 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED, 0),
437 I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX, 0),
438 I40E_PRIV_FLAG("disable-source-pruning",
439 I40E_FLAG_SOURCE_PRUNING_DISABLED, 0),
440 I40E_PRIV_FLAG("disable-fw-lldp", I40E_FLAG_DISABLE_FW_LLDP, 0),
441 I40E_PRIV_FLAG("rs-fec", I40E_FLAG_RS_FEC, 0),
442 I40E_PRIV_FLAG("base-r-fec", I40E_FLAG_BASE_R_FEC, 0),
443};
444
445#define I40E_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gstrings_priv_flags)
446
447
448static const struct i40e_priv_flags i40e_gl_gstrings_priv_flags[] = {
449 I40E_PRIV_FLAG("vf-true-promisc-support",
450 I40E_FLAG_TRUE_PROMISC_SUPPORT, 0),
451};
452
453#define I40E_GL_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gl_gstrings_priv_flags)
454
455
456
457
458
459static void i40e_partition_setting_complaint(struct i40e_pf *pf)
460{
461 dev_info(&pf->pdev->dev,
462 "The link settings are allowed to be changed only from the first partition of a given port. Please switch to the first partition in order to change the setting.\n");
463}
464
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468
469
470
471static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,
472 struct ethtool_link_ksettings *ks)
473{
474 struct i40e_link_status *hw_link_info = &pf->hw.phy.link_info;
475 u64 phy_types = pf->hw.phy.phy_types;
476
477 ethtool_link_ksettings_zero_link_mode(ks, supported);
478 ethtool_link_ksettings_zero_link_mode(ks, advertising);
479
480 if (phy_types & I40E_CAP_PHY_TYPE_SGMII) {
481 ethtool_link_ksettings_add_link_mode(ks, supported,
482 1000baseT_Full);
483 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
484 ethtool_link_ksettings_add_link_mode(ks, advertising,
485 1000baseT_Full);
486 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
487 ethtool_link_ksettings_add_link_mode(ks, supported,
488 100baseT_Full);
489 ethtool_link_ksettings_add_link_mode(ks, advertising,
490 100baseT_Full);
491 }
492 }
493 if (phy_types & I40E_CAP_PHY_TYPE_XAUI ||
494 phy_types & I40E_CAP_PHY_TYPE_XFI ||
495 phy_types & I40E_CAP_PHY_TYPE_SFI ||
496 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU ||
497 phy_types & I40E_CAP_PHY_TYPE_10GBASE_AOC) {
498 ethtool_link_ksettings_add_link_mode(ks, supported,
499 10000baseT_Full);
500 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
501 ethtool_link_ksettings_add_link_mode(ks, advertising,
502 10000baseT_Full);
503 }
504 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_T) {
505 ethtool_link_ksettings_add_link_mode(ks, supported,
506 10000baseT_Full);
507 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
508 ethtool_link_ksettings_add_link_mode(ks, advertising,
509 10000baseT_Full);
510 }
511 if (phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T) {
512 ethtool_link_ksettings_add_link_mode(ks, supported,
513 2500baseT_Full);
514 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
515 ethtool_link_ksettings_add_link_mode(ks, advertising,
516 2500baseT_Full);
517 }
518 if (phy_types & I40E_CAP_PHY_TYPE_5GBASE_T) {
519 ethtool_link_ksettings_add_link_mode(ks, supported,
520 5000baseT_Full);
521 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
522 ethtool_link_ksettings_add_link_mode(ks, advertising,
523 5000baseT_Full);
524 }
525 if (phy_types & I40E_CAP_PHY_TYPE_XLAUI ||
526 phy_types & I40E_CAP_PHY_TYPE_XLPPI ||
527 phy_types & I40E_CAP_PHY_TYPE_40GBASE_AOC)
528 ethtool_link_ksettings_add_link_mode(ks, supported,
529 40000baseCR4_Full);
530 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
531 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4) {
532 ethtool_link_ksettings_add_link_mode(ks, supported,
533 40000baseCR4_Full);
534 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_40GB)
535 ethtool_link_ksettings_add_link_mode(ks, advertising,
536 40000baseCR4_Full);
537 }
538 if (phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
539 ethtool_link_ksettings_add_link_mode(ks, supported,
540 100baseT_Full);
541 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
542 ethtool_link_ksettings_add_link_mode(ks, advertising,
543 100baseT_Full);
544 }
545 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_T) {
546 ethtool_link_ksettings_add_link_mode(ks, supported,
547 1000baseT_Full);
548 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
549 ethtool_link_ksettings_add_link_mode(ks, advertising,
550 1000baseT_Full);
551 }
552 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_SR4) {
553 ethtool_link_ksettings_add_link_mode(ks, supported,
554 40000baseSR4_Full);
555 ethtool_link_ksettings_add_link_mode(ks, advertising,
556 40000baseSR4_Full);
557 }
558 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_LR4) {
559 ethtool_link_ksettings_add_link_mode(ks, supported,
560 40000baseLR4_Full);
561 ethtool_link_ksettings_add_link_mode(ks, advertising,
562 40000baseLR4_Full);
563 }
564 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4) {
565 ethtool_link_ksettings_add_link_mode(ks, supported,
566 40000baseKR4_Full);
567 ethtool_link_ksettings_add_link_mode(ks, advertising,
568 40000baseKR4_Full);
569 }
570 if (phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2) {
571 ethtool_link_ksettings_add_link_mode(ks, supported,
572 20000baseKR2_Full);
573 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_20GB)
574 ethtool_link_ksettings_add_link_mode(ks, advertising,
575 20000baseKR2_Full);
576 }
577 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4) {
578 ethtool_link_ksettings_add_link_mode(ks, supported,
579 10000baseKX4_Full);
580 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
581 ethtool_link_ksettings_add_link_mode(ks, advertising,
582 10000baseKX4_Full);
583 }
584 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR &&
585 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
586 ethtool_link_ksettings_add_link_mode(ks, supported,
587 10000baseKR_Full);
588 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
589 ethtool_link_ksettings_add_link_mode(ks, advertising,
590 10000baseKR_Full);
591 }
592 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX &&
593 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
594 ethtool_link_ksettings_add_link_mode(ks, supported,
595 1000baseKX_Full);
596 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
597 ethtool_link_ksettings_add_link_mode(ks, advertising,
598 1000baseKX_Full);
599 }
600
601 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR) {
602 ethtool_link_ksettings_add_link_mode(ks, supported,
603 25000baseKR_Full);
604 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
605 ethtool_link_ksettings_add_link_mode(ks, advertising,
606 25000baseKR_Full);
607 }
608 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR) {
609 ethtool_link_ksettings_add_link_mode(ks, supported,
610 25000baseCR_Full);
611 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
612 ethtool_link_ksettings_add_link_mode(ks, advertising,
613 25000baseCR_Full);
614 }
615 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
616 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR) {
617 ethtool_link_ksettings_add_link_mode(ks, supported,
618 25000baseSR_Full);
619 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
620 ethtool_link_ksettings_add_link_mode(ks, advertising,
621 25000baseSR_Full);
622 }
623 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
624 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
625 ethtool_link_ksettings_add_link_mode(ks, supported,
626 25000baseCR_Full);
627 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
628 ethtool_link_ksettings_add_link_mode(ks, advertising,
629 25000baseCR_Full);
630 }
631 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
632 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
633 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
634 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
635 phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
636 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
637 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
638 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
639 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
640 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB) {
641 ethtool_link_ksettings_add_link_mode(ks, advertising,
642 FEC_NONE);
643 ethtool_link_ksettings_add_link_mode(ks, advertising,
644 FEC_RS);
645 ethtool_link_ksettings_add_link_mode(ks, advertising,
646 FEC_BASER);
647 }
648 }
649
650 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
651 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU) {
652 ethtool_link_ksettings_add_link_mode(ks, supported,
653 10000baseCR_Full);
654 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
655 ethtool_link_ksettings_add_link_mode(ks, advertising,
656 10000baseCR_Full);
657 }
658 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR) {
659 ethtool_link_ksettings_add_link_mode(ks, supported,
660 10000baseSR_Full);
661 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
662 ethtool_link_ksettings_add_link_mode(ks, advertising,
663 10000baseSR_Full);
664 }
665 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR) {
666 ethtool_link_ksettings_add_link_mode(ks, supported,
667 10000baseLR_Full);
668 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
669 ethtool_link_ksettings_add_link_mode(ks, advertising,
670 10000baseLR_Full);
671 }
672 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
673 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
674 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL) {
675 ethtool_link_ksettings_add_link_mode(ks, supported,
676 1000baseX_Full);
677 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
678 ethtool_link_ksettings_add_link_mode(ks, advertising,
679 1000baseX_Full);
680 }
681
682 if (phy_types & I40E_CAP_PHY_TYPE_SGMII ||
683 phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4 ||
684 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
685 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4 ||
686 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
687 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
688 phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
689 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
690 phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2 ||
691 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR ||
692 phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR ||
693 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4 ||
694 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR ||
695 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU ||
696 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
697 phy_types & I40E_CAP_PHY_TYPE_10GBASE_T ||
698 phy_types & I40E_CAP_PHY_TYPE_5GBASE_T ||
699 phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T ||
700 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL ||
701 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T ||
702 phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
703 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
704 phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX ||
705 phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
706 ethtool_link_ksettings_add_link_mode(ks, supported,
707 Autoneg);
708 ethtool_link_ksettings_add_link_mode(ks, advertising,
709 Autoneg);
710 }
711}
712
713
714
715
716
717
718
719
720static void i40e_get_settings_link_up(struct i40e_hw *hw,
721 struct ethtool_link_ksettings *ks,
722 struct net_device *netdev,
723 struct i40e_pf *pf)
724{
725 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
726 struct ethtool_link_ksettings cap_ksettings;
727 u32 link_speed = hw_link_info->link_speed;
728
729
730 switch (hw_link_info->phy_type) {
731 case I40E_PHY_TYPE_40GBASE_CR4:
732 case I40E_PHY_TYPE_40GBASE_CR4_CU:
733 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
734 ethtool_link_ksettings_add_link_mode(ks, supported,
735 40000baseCR4_Full);
736 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
737 ethtool_link_ksettings_add_link_mode(ks, advertising,
738 40000baseCR4_Full);
739 break;
740 case I40E_PHY_TYPE_XLAUI:
741 case I40E_PHY_TYPE_XLPPI:
742 case I40E_PHY_TYPE_40GBASE_AOC:
743 ethtool_link_ksettings_add_link_mode(ks, supported,
744 40000baseCR4_Full);
745 ethtool_link_ksettings_add_link_mode(ks, advertising,
746 40000baseCR4_Full);
747 break;
748 case I40E_PHY_TYPE_40GBASE_SR4:
749 ethtool_link_ksettings_add_link_mode(ks, supported,
750 40000baseSR4_Full);
751 ethtool_link_ksettings_add_link_mode(ks, advertising,
752 40000baseSR4_Full);
753 break;
754 case I40E_PHY_TYPE_40GBASE_LR4:
755 ethtool_link_ksettings_add_link_mode(ks, supported,
756 40000baseLR4_Full);
757 ethtool_link_ksettings_add_link_mode(ks, advertising,
758 40000baseLR4_Full);
759 break;
760 case I40E_PHY_TYPE_25GBASE_SR:
761 case I40E_PHY_TYPE_25GBASE_LR:
762 case I40E_PHY_TYPE_10GBASE_SR:
763 case I40E_PHY_TYPE_10GBASE_LR:
764 case I40E_PHY_TYPE_1000BASE_SX:
765 case I40E_PHY_TYPE_1000BASE_LX:
766 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
767 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
768 ethtool_link_ksettings_add_link_mode(ks, supported,
769 25000baseSR_Full);
770 ethtool_link_ksettings_add_link_mode(ks, advertising,
771 25000baseSR_Full);
772 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
773 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
774 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
775 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_NONE);
776 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
777 ethtool_link_ksettings_add_link_mode(ks, advertising,
778 FEC_BASER);
779 ethtool_link_ksettings_add_link_mode(ks, supported,
780 10000baseSR_Full);
781 ethtool_link_ksettings_add_link_mode(ks, advertising,
782 10000baseSR_Full);
783 ethtool_link_ksettings_add_link_mode(ks, supported,
784 10000baseLR_Full);
785 ethtool_link_ksettings_add_link_mode(ks, advertising,
786 10000baseLR_Full);
787 ethtool_link_ksettings_add_link_mode(ks, supported,
788 1000baseX_Full);
789 ethtool_link_ksettings_add_link_mode(ks, advertising,
790 1000baseX_Full);
791 ethtool_link_ksettings_add_link_mode(ks, supported,
792 10000baseT_Full);
793 if (hw_link_info->module_type[2] &
794 I40E_MODULE_TYPE_1000BASE_SX ||
795 hw_link_info->module_type[2] &
796 I40E_MODULE_TYPE_1000BASE_LX) {
797 ethtool_link_ksettings_add_link_mode(ks, supported,
798 1000baseT_Full);
799 if (hw_link_info->requested_speeds &
800 I40E_LINK_SPEED_1GB)
801 ethtool_link_ksettings_add_link_mode(
802 ks, advertising, 1000baseT_Full);
803 }
804 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
805 ethtool_link_ksettings_add_link_mode(ks, advertising,
806 10000baseT_Full);
807 break;
808 case I40E_PHY_TYPE_10GBASE_T:
809 case I40E_PHY_TYPE_5GBASE_T:
810 case I40E_PHY_TYPE_2_5GBASE_T:
811 case I40E_PHY_TYPE_1000BASE_T:
812 case I40E_PHY_TYPE_100BASE_TX:
813 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
814 ethtool_link_ksettings_add_link_mode(ks, supported,
815 10000baseT_Full);
816 ethtool_link_ksettings_add_link_mode(ks, supported,
817 5000baseT_Full);
818 ethtool_link_ksettings_add_link_mode(ks, supported,
819 2500baseT_Full);
820 ethtool_link_ksettings_add_link_mode(ks, supported,
821 1000baseT_Full);
822 ethtool_link_ksettings_add_link_mode(ks, supported,
823 100baseT_Full);
824 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
825 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
826 ethtool_link_ksettings_add_link_mode(ks, advertising,
827 10000baseT_Full);
828 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
829 ethtool_link_ksettings_add_link_mode(ks, advertising,
830 5000baseT_Full);
831 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
832 ethtool_link_ksettings_add_link_mode(ks, advertising,
833 2500baseT_Full);
834 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
835 ethtool_link_ksettings_add_link_mode(ks, advertising,
836 1000baseT_Full);
837 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
838 ethtool_link_ksettings_add_link_mode(ks, advertising,
839 100baseT_Full);
840 break;
841 case I40E_PHY_TYPE_1000BASE_T_OPTICAL:
842 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
843 ethtool_link_ksettings_add_link_mode(ks, supported,
844 1000baseT_Full);
845 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
846 ethtool_link_ksettings_add_link_mode(ks, advertising,
847 1000baseT_Full);
848 break;
849 case I40E_PHY_TYPE_10GBASE_CR1_CU:
850 case I40E_PHY_TYPE_10GBASE_CR1:
851 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
852 ethtool_link_ksettings_add_link_mode(ks, supported,
853 10000baseT_Full);
854 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
855 ethtool_link_ksettings_add_link_mode(ks, advertising,
856 10000baseT_Full);
857 break;
858 case I40E_PHY_TYPE_XAUI:
859 case I40E_PHY_TYPE_XFI:
860 case I40E_PHY_TYPE_SFI:
861 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
862 case I40E_PHY_TYPE_10GBASE_AOC:
863 ethtool_link_ksettings_add_link_mode(ks, supported,
864 10000baseT_Full);
865 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
866 ethtool_link_ksettings_add_link_mode(ks, advertising,
867 10000baseT_Full);
868 break;
869 case I40E_PHY_TYPE_SGMII:
870 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
871 ethtool_link_ksettings_add_link_mode(ks, supported,
872 1000baseT_Full);
873 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
874 ethtool_link_ksettings_add_link_mode(ks, advertising,
875 1000baseT_Full);
876 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
877 ethtool_link_ksettings_add_link_mode(ks, supported,
878 100baseT_Full);
879 if (hw_link_info->requested_speeds &
880 I40E_LINK_SPEED_100MB)
881 ethtool_link_ksettings_add_link_mode(
882 ks, advertising, 100baseT_Full);
883 }
884 break;
885 case I40E_PHY_TYPE_40GBASE_KR4:
886 case I40E_PHY_TYPE_25GBASE_KR:
887 case I40E_PHY_TYPE_20GBASE_KR2:
888 case I40E_PHY_TYPE_10GBASE_KR:
889 case I40E_PHY_TYPE_10GBASE_KX4:
890 case I40E_PHY_TYPE_1000BASE_KX:
891 ethtool_link_ksettings_add_link_mode(ks, supported,
892 40000baseKR4_Full);
893 ethtool_link_ksettings_add_link_mode(ks, supported,
894 25000baseKR_Full);
895 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
896 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
897 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
898 ethtool_link_ksettings_add_link_mode(ks, supported,
899 20000baseKR2_Full);
900 ethtool_link_ksettings_add_link_mode(ks, supported,
901 10000baseKR_Full);
902 ethtool_link_ksettings_add_link_mode(ks, supported,
903 10000baseKX4_Full);
904 ethtool_link_ksettings_add_link_mode(ks, supported,
905 1000baseKX_Full);
906 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
907 ethtool_link_ksettings_add_link_mode(ks, advertising,
908 40000baseKR4_Full);
909 ethtool_link_ksettings_add_link_mode(ks, advertising,
910 25000baseKR_Full);
911 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_NONE);
912 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
913 ethtool_link_ksettings_add_link_mode(ks, advertising,
914 FEC_BASER);
915 ethtool_link_ksettings_add_link_mode(ks, advertising,
916 20000baseKR2_Full);
917 ethtool_link_ksettings_add_link_mode(ks, advertising,
918 10000baseKR_Full);
919 ethtool_link_ksettings_add_link_mode(ks, advertising,
920 10000baseKX4_Full);
921 ethtool_link_ksettings_add_link_mode(ks, advertising,
922 1000baseKX_Full);
923 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
924 break;
925 case I40E_PHY_TYPE_25GBASE_CR:
926 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
927 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
928 ethtool_link_ksettings_add_link_mode(ks, supported,
929 25000baseCR_Full);
930 ethtool_link_ksettings_add_link_mode(ks, advertising,
931 25000baseCR_Full);
932 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
933 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
934 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
935 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_NONE);
936 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
937 ethtool_link_ksettings_add_link_mode(ks, advertising,
938 FEC_BASER);
939 break;
940 case I40E_PHY_TYPE_25GBASE_AOC:
941 case I40E_PHY_TYPE_25GBASE_ACC:
942 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
943 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
944 ethtool_link_ksettings_add_link_mode(ks, supported,
945 25000baseCR_Full);
946 ethtool_link_ksettings_add_link_mode(ks, advertising,
947 25000baseCR_Full);
948 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
949 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
950 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
951 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_NONE);
952 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
953 ethtool_link_ksettings_add_link_mode(ks, advertising,
954 FEC_BASER);
955 ethtool_link_ksettings_add_link_mode(ks, supported,
956 10000baseCR_Full);
957 ethtool_link_ksettings_add_link_mode(ks, advertising,
958 10000baseCR_Full);
959 break;
960 default:
961
962 netdev_info(netdev,
963 "WARNING: Link is up but PHY type 0x%x is not recognized.\n",
964 hw_link_info->phy_type);
965 }
966
967
968
969
970
971 memset(&cap_ksettings, 0, sizeof(struct ethtool_link_ksettings));
972 i40e_phy_type_to_ethtool(pf, &cap_ksettings);
973 ethtool_intersect_link_masks(ks, &cap_ksettings);
974
975
976 switch (link_speed) {
977 case I40E_LINK_SPEED_40GB:
978 ks->base.speed = SPEED_40000;
979 break;
980 case I40E_LINK_SPEED_25GB:
981 ks->base.speed = SPEED_25000;
982 break;
983 case I40E_LINK_SPEED_20GB:
984 ks->base.speed = SPEED_20000;
985 break;
986 case I40E_LINK_SPEED_10GB:
987 ks->base.speed = SPEED_10000;
988 break;
989 case I40E_LINK_SPEED_5GB:
990 ks->base.speed = SPEED_5000;
991 break;
992 case I40E_LINK_SPEED_2_5GB:
993 ks->base.speed = SPEED_2500;
994 break;
995 case I40E_LINK_SPEED_1GB:
996 ks->base.speed = SPEED_1000;
997 break;
998 case I40E_LINK_SPEED_100MB:
999 ks->base.speed = SPEED_100;
1000 break;
1001 default:
1002 ks->base.speed = SPEED_UNKNOWN;
1003 break;
1004 }
1005 ks->base.duplex = DUPLEX_FULL;
1006}
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016static void i40e_get_settings_link_down(struct i40e_hw *hw,
1017 struct ethtool_link_ksettings *ks,
1018 struct i40e_pf *pf)
1019{
1020
1021
1022
1023 i40e_phy_type_to_ethtool(pf, ks);
1024
1025
1026 ks->base.speed = SPEED_UNKNOWN;
1027 ks->base.duplex = DUPLEX_UNKNOWN;
1028}
1029
1030
1031
1032
1033
1034
1035
1036
1037static int i40e_get_link_ksettings(struct net_device *netdev,
1038 struct ethtool_link_ksettings *ks)
1039{
1040 struct i40e_netdev_priv *np = netdev_priv(netdev);
1041 struct i40e_pf *pf = np->vsi->back;
1042 struct i40e_hw *hw = &pf->hw;
1043 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1044 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1045
1046 ethtool_link_ksettings_zero_link_mode(ks, supported);
1047 ethtool_link_ksettings_zero_link_mode(ks, advertising);
1048
1049 if (link_up)
1050 i40e_get_settings_link_up(hw, ks, netdev, pf);
1051 else
1052 i40e_get_settings_link_down(hw, ks, pf);
1053
1054
1055
1056 ks->base.autoneg = ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1057 AUTONEG_ENABLE : AUTONEG_DISABLE);
1058
1059
1060 switch (hw->phy.media_type) {
1061 case I40E_MEDIA_TYPE_BACKPLANE:
1062 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
1063 ethtool_link_ksettings_add_link_mode(ks, supported, Backplane);
1064 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
1065 ethtool_link_ksettings_add_link_mode(ks, advertising,
1066 Backplane);
1067 ks->base.port = PORT_NONE;
1068 break;
1069 case I40E_MEDIA_TYPE_BASET:
1070 ethtool_link_ksettings_add_link_mode(ks, supported, TP);
1071 ethtool_link_ksettings_add_link_mode(ks, advertising, TP);
1072 ks->base.port = PORT_TP;
1073 break;
1074 case I40E_MEDIA_TYPE_DA:
1075 case I40E_MEDIA_TYPE_CX4:
1076 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1077 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1078 ks->base.port = PORT_DA;
1079 break;
1080 case I40E_MEDIA_TYPE_FIBER:
1081 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1082 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1083 ks->base.port = PORT_FIBRE;
1084 break;
1085 case I40E_MEDIA_TYPE_UNKNOWN:
1086 default:
1087 ks->base.port = PORT_OTHER;
1088 break;
1089 }
1090
1091
1092 ethtool_link_ksettings_add_link_mode(ks, supported, Pause);
1093
1094 switch (hw->fc.requested_mode) {
1095 case I40E_FC_FULL:
1096 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1097 break;
1098 case I40E_FC_TX_PAUSE:
1099 ethtool_link_ksettings_add_link_mode(ks, advertising,
1100 Asym_Pause);
1101 break;
1102 case I40E_FC_RX_PAUSE:
1103 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1104 ethtool_link_ksettings_add_link_mode(ks, advertising,
1105 Asym_Pause);
1106 break;
1107 default:
1108 ethtool_link_ksettings_del_link_mode(ks, advertising, Pause);
1109 ethtool_link_ksettings_del_link_mode(ks, advertising,
1110 Asym_Pause);
1111 break;
1112 }
1113
1114 return 0;
1115}
1116
1117
1118
1119
1120
1121
1122
1123
1124static int i40e_set_link_ksettings(struct net_device *netdev,
1125 const struct ethtool_link_ksettings *ks)
1126{
1127 struct i40e_netdev_priv *np = netdev_priv(netdev);
1128 struct i40e_aq_get_phy_abilities_resp abilities;
1129 struct ethtool_link_ksettings safe_ks;
1130 struct ethtool_link_ksettings copy_ks;
1131 struct i40e_aq_set_phy_config config;
1132 struct i40e_pf *pf = np->vsi->back;
1133 struct i40e_vsi *vsi = np->vsi;
1134 struct i40e_hw *hw = &pf->hw;
1135 bool autoneg_changed = false;
1136 i40e_status status = 0;
1137 int timeout = 50;
1138 int err = 0;
1139 u8 autoneg;
1140
1141
1142
1143
1144 if (hw->partition_id != 1) {
1145 i40e_partition_setting_complaint(pf);
1146 return -EOPNOTSUPP;
1147 }
1148 if (vsi != pf->vsi[pf->lan_vsi])
1149 return -EOPNOTSUPP;
1150 if (hw->phy.media_type != I40E_MEDIA_TYPE_BASET &&
1151 hw->phy.media_type != I40E_MEDIA_TYPE_FIBER &&
1152 hw->phy.media_type != I40E_MEDIA_TYPE_BACKPLANE &&
1153 hw->phy.media_type != I40E_MEDIA_TYPE_DA &&
1154 hw->phy.link_info.link_info & I40E_AQ_LINK_UP)
1155 return -EOPNOTSUPP;
1156 if (hw->device_id == I40E_DEV_ID_KX_B ||
1157 hw->device_id == I40E_DEV_ID_KX_C ||
1158 hw->device_id == I40E_DEV_ID_20G_KR2 ||
1159 hw->device_id == I40E_DEV_ID_20G_KR2_A ||
1160 hw->device_id == I40E_DEV_ID_25G_B ||
1161 hw->device_id == I40E_DEV_ID_KX_X722) {
1162 netdev_info(netdev, "Changing settings is not supported on backplane.\n");
1163 return -EOPNOTSUPP;
1164 }
1165
1166
1167 memcpy(©_ks, ks, sizeof(struct ethtool_link_ksettings));
1168
1169
1170 autoneg = copy_ks.base.autoneg;
1171
1172
1173 memset(&safe_ks, 0, sizeof(struct ethtool_link_ksettings));
1174 safe_ks.base.cmd = copy_ks.base.cmd;
1175 safe_ks.base.link_mode_masks_nwords =
1176 copy_ks.base.link_mode_masks_nwords;
1177 i40e_get_link_ksettings(netdev, &safe_ks);
1178
1179
1180
1181
1182 if (!bitmap_subset(copy_ks.link_modes.advertising,
1183 safe_ks.link_modes.supported,
1184 __ETHTOOL_LINK_MODE_MASK_NBITS))
1185 return -EINVAL;
1186
1187
1188 copy_ks.base.autoneg = safe_ks.base.autoneg;
1189
1190
1191
1192
1193 if (memcmp(©_ks.base, &safe_ks.base,
1194 sizeof(struct ethtool_link_settings)))
1195 return -EOPNOTSUPP;
1196
1197 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
1198 timeout--;
1199 if (!timeout)
1200 return -EBUSY;
1201 usleep_range(1000, 2000);
1202 }
1203
1204
1205 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1206 NULL);
1207 if (status) {
1208 err = -EAGAIN;
1209 goto done;
1210 }
1211
1212
1213
1214
1215 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1216 config.abilities = abilities.abilities;
1217
1218
1219 if (autoneg == AUTONEG_ENABLE) {
1220
1221 if (!(hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED)) {
1222
1223 if (!ethtool_link_ksettings_test_link_mode(&safe_ks,
1224 supported,
1225 Autoneg)) {
1226 netdev_info(netdev, "Autoneg not supported on this phy\n");
1227 err = -EINVAL;
1228 goto done;
1229 }
1230
1231 config.abilities = abilities.abilities |
1232 I40E_AQ_PHY_ENABLE_AN;
1233 autoneg_changed = true;
1234 }
1235 } else {
1236
1237 if (hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED) {
1238
1239
1240
1241 if (ethtool_link_ksettings_test_link_mode(&safe_ks,
1242 supported,
1243 Autoneg) &&
1244 hw->phy.link_info.phy_type !=
1245 I40E_PHY_TYPE_10GBASE_T) {
1246 netdev_info(netdev, "Autoneg cannot be disabled on this phy\n");
1247 err = -EINVAL;
1248 goto done;
1249 }
1250
1251 config.abilities = abilities.abilities &
1252 ~I40E_AQ_PHY_ENABLE_AN;
1253 autoneg_changed = true;
1254 }
1255 }
1256
1257 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1258 100baseT_Full))
1259 config.link_speed |= I40E_LINK_SPEED_100MB;
1260 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1261 1000baseT_Full) ||
1262 ethtool_link_ksettings_test_link_mode(ks, advertising,
1263 1000baseX_Full) ||
1264 ethtool_link_ksettings_test_link_mode(ks, advertising,
1265 1000baseKX_Full))
1266 config.link_speed |= I40E_LINK_SPEED_1GB;
1267 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1268 10000baseT_Full) ||
1269 ethtool_link_ksettings_test_link_mode(ks, advertising,
1270 10000baseKX4_Full) ||
1271 ethtool_link_ksettings_test_link_mode(ks, advertising,
1272 10000baseKR_Full) ||
1273 ethtool_link_ksettings_test_link_mode(ks, advertising,
1274 10000baseCR_Full) ||
1275 ethtool_link_ksettings_test_link_mode(ks, advertising,
1276 10000baseSR_Full) ||
1277 ethtool_link_ksettings_test_link_mode(ks, advertising,
1278 10000baseLR_Full))
1279 config.link_speed |= I40E_LINK_SPEED_10GB;
1280 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1281 2500baseT_Full))
1282 config.link_speed |= I40E_LINK_SPEED_2_5GB;
1283 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1284 5000baseT_Full))
1285 config.link_speed |= I40E_LINK_SPEED_5GB;
1286 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1287 20000baseKR2_Full))
1288 config.link_speed |= I40E_LINK_SPEED_20GB;
1289 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1290 25000baseCR_Full) ||
1291 ethtool_link_ksettings_test_link_mode(ks, advertising,
1292 25000baseKR_Full) ||
1293 ethtool_link_ksettings_test_link_mode(ks, advertising,
1294 25000baseSR_Full))
1295 config.link_speed |= I40E_LINK_SPEED_25GB;
1296 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1297 40000baseKR4_Full) ||
1298 ethtool_link_ksettings_test_link_mode(ks, advertising,
1299 40000baseCR4_Full) ||
1300 ethtool_link_ksettings_test_link_mode(ks, advertising,
1301 40000baseSR4_Full) ||
1302 ethtool_link_ksettings_test_link_mode(ks, advertising,
1303 40000baseLR4_Full))
1304 config.link_speed |= I40E_LINK_SPEED_40GB;
1305
1306
1307
1308
1309
1310 if (!config.link_speed)
1311 config.link_speed = abilities.link_speed;
1312 if (autoneg_changed || abilities.link_speed != config.link_speed) {
1313
1314 config.phy_type = abilities.phy_type;
1315 config.phy_type_ext = abilities.phy_type_ext;
1316 config.eee_capability = abilities.eee_capability;
1317 config.eeer = abilities.eeer_val;
1318 config.low_power_ctrl = abilities.d3_lpan;
1319 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1320 I40E_AQ_PHY_FEC_CONFIG_MASK;
1321
1322
1323 hw->phy.link_info.requested_speeds = config.link_speed;
1324
1325 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1326
1327 if (hw->phy.link_info.link_info & I40E_AQ_LINK_UP) {
1328
1329
1330
1331 i40e_print_link_message(vsi, false);
1332 netif_carrier_off(netdev);
1333 netif_tx_stop_all_queues(netdev);
1334 }
1335
1336
1337 status = i40e_aq_set_phy_config(hw, &config, NULL);
1338 if (status) {
1339 netdev_info(netdev,
1340 "Set phy config failed, err %s aq_err %s\n",
1341 i40e_stat_str(hw, status),
1342 i40e_aq_str(hw, hw->aq.asq_last_status));
1343 err = -EAGAIN;
1344 goto done;
1345 }
1346
1347 status = i40e_update_link_info(hw);
1348 if (status)
1349 netdev_dbg(netdev,
1350 "Updating link info failed with err %s aq_err %s\n",
1351 i40e_stat_str(hw, status),
1352 i40e_aq_str(hw, hw->aq.asq_last_status));
1353
1354 } else {
1355 netdev_info(netdev, "Nothing changed, exiting without setting anything.\n");
1356 }
1357
1358done:
1359 clear_bit(__I40E_CONFIG_BUSY, pf->state);
1360
1361 return err;
1362}
1363
1364static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
1365{
1366 struct i40e_netdev_priv *np = netdev_priv(netdev);
1367 struct i40e_aq_get_phy_abilities_resp abilities;
1368 struct i40e_pf *pf = np->vsi->back;
1369 struct i40e_hw *hw = &pf->hw;
1370 i40e_status status = 0;
1371 u32 flags = 0;
1372 int err = 0;
1373
1374 flags = READ_ONCE(pf->flags);
1375 i40e_set_fec_in_flags(fec_cfg, &flags);
1376
1377
1378 memset(&abilities, 0, sizeof(abilities));
1379 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1380 NULL);
1381 if (status) {
1382 err = -EAGAIN;
1383 goto done;
1384 }
1385
1386 if (abilities.fec_cfg_curr_mod_ext_info != fec_cfg) {
1387 struct i40e_aq_set_phy_config config;
1388
1389 memset(&config, 0, sizeof(config));
1390 config.phy_type = abilities.phy_type;
1391 config.abilities = abilities.abilities;
1392 config.phy_type_ext = abilities.phy_type_ext;
1393 config.link_speed = abilities.link_speed;
1394 config.eee_capability = abilities.eee_capability;
1395 config.eeer = abilities.eeer_val;
1396 config.low_power_ctrl = abilities.d3_lpan;
1397 config.fec_config = fec_cfg & I40E_AQ_PHY_FEC_CONFIG_MASK;
1398 status = i40e_aq_set_phy_config(hw, &config, NULL);
1399 if (status) {
1400 netdev_info(netdev,
1401 "Set phy config failed, err %s aq_err %s\n",
1402 i40e_stat_str(hw, status),
1403 i40e_aq_str(hw, hw->aq.asq_last_status));
1404 err = -EAGAIN;
1405 goto done;
1406 }
1407 pf->flags = flags;
1408 status = i40e_update_link_info(hw);
1409 if (status)
1410
1411
1412
1413
1414 netdev_dbg(netdev,
1415 "Updating link info failed with err %s aq_err %s\n",
1416 i40e_stat_str(hw, status),
1417 i40e_aq_str(hw, hw->aq.asq_last_status));
1418 }
1419
1420done:
1421 return err;
1422}
1423
1424static int i40e_get_fec_param(struct net_device *netdev,
1425 struct ethtool_fecparam *fecparam)
1426{
1427 struct i40e_netdev_priv *np = netdev_priv(netdev);
1428 struct i40e_aq_get_phy_abilities_resp abilities;
1429 struct i40e_pf *pf = np->vsi->back;
1430 struct i40e_hw *hw = &pf->hw;
1431 i40e_status status = 0;
1432 int err = 0;
1433
1434
1435 memset(&abilities, 0, sizeof(abilities));
1436 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1437 NULL);
1438 if (status) {
1439 err = -EAGAIN;
1440 goto done;
1441 }
1442
1443 fecparam->fec = 0;
1444 if (abilities.fec_cfg_curr_mod_ext_info & I40E_AQ_SET_FEC_AUTO)
1445 fecparam->fec |= ETHTOOL_FEC_AUTO;
1446 if ((abilities.fec_cfg_curr_mod_ext_info &
1447 I40E_AQ_SET_FEC_REQUEST_RS) ||
1448 (abilities.fec_cfg_curr_mod_ext_info &
1449 I40E_AQ_SET_FEC_ABILITY_RS))
1450 fecparam->fec |= ETHTOOL_FEC_RS;
1451 if ((abilities.fec_cfg_curr_mod_ext_info &
1452 I40E_AQ_SET_FEC_REQUEST_KR) ||
1453 (abilities.fec_cfg_curr_mod_ext_info & I40E_AQ_SET_FEC_ABILITY_KR))
1454 fecparam->fec |= ETHTOOL_FEC_BASER;
1455 if (abilities.fec_cfg_curr_mod_ext_info == 0)
1456 fecparam->fec |= ETHTOOL_FEC_OFF;
1457
1458 if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_KR_ENA)
1459 fecparam->active_fec = ETHTOOL_FEC_BASER;
1460 else if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_RS_ENA)
1461 fecparam->active_fec = ETHTOOL_FEC_RS;
1462 else
1463 fecparam->active_fec = ETHTOOL_FEC_OFF;
1464done:
1465 return err;
1466}
1467
1468static int i40e_set_fec_param(struct net_device *netdev,
1469 struct ethtool_fecparam *fecparam)
1470{
1471 struct i40e_netdev_priv *np = netdev_priv(netdev);
1472 struct i40e_pf *pf = np->vsi->back;
1473 struct i40e_hw *hw = &pf->hw;
1474 u8 fec_cfg = 0;
1475 int err = 0;
1476
1477 if (hw->device_id != I40E_DEV_ID_25G_SFP28 &&
1478 hw->device_id != I40E_DEV_ID_25G_B) {
1479 err = -EPERM;
1480 goto done;
1481 }
1482
1483 switch (fecparam->fec) {
1484 case ETHTOOL_FEC_AUTO:
1485 fec_cfg = I40E_AQ_SET_FEC_AUTO;
1486 break;
1487 case ETHTOOL_FEC_RS:
1488 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
1489 I40E_AQ_SET_FEC_ABILITY_RS);
1490 break;
1491 case ETHTOOL_FEC_BASER:
1492 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
1493 I40E_AQ_SET_FEC_ABILITY_KR);
1494 break;
1495 case ETHTOOL_FEC_OFF:
1496 case ETHTOOL_FEC_NONE:
1497 fec_cfg = 0;
1498 break;
1499 default:
1500 dev_warn(&pf->pdev->dev, "Unsupported FEC mode: %d",
1501 fecparam->fec);
1502 err = -EINVAL;
1503 goto done;
1504 }
1505
1506 err = i40e_set_fec_cfg(netdev, fec_cfg);
1507
1508done:
1509 return err;
1510}
1511
1512static int i40e_nway_reset(struct net_device *netdev)
1513{
1514
1515 struct i40e_netdev_priv *np = netdev_priv(netdev);
1516 struct i40e_pf *pf = np->vsi->back;
1517 struct i40e_hw *hw = &pf->hw;
1518 bool link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1519 i40e_status ret = 0;
1520
1521 ret = i40e_aq_set_link_restart_an(hw, link_up, NULL);
1522 if (ret) {
1523 netdev_info(netdev, "link restart failed, err %s aq_err %s\n",
1524 i40e_stat_str(hw, ret),
1525 i40e_aq_str(hw, hw->aq.asq_last_status));
1526 return -EIO;
1527 }
1528
1529 return 0;
1530}
1531
1532
1533
1534
1535
1536
1537
1538
1539static void i40e_get_pauseparam(struct net_device *netdev,
1540 struct ethtool_pauseparam *pause)
1541{
1542 struct i40e_netdev_priv *np = netdev_priv(netdev);
1543 struct i40e_pf *pf = np->vsi->back;
1544 struct i40e_hw *hw = &pf->hw;
1545 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1546 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1547
1548 pause->autoneg =
1549 ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1550 AUTONEG_ENABLE : AUTONEG_DISABLE);
1551
1552
1553 if (dcbx_cfg->pfc.pfcenable) {
1554 pause->rx_pause = 0;
1555 pause->tx_pause = 0;
1556 return;
1557 }
1558
1559 if (hw->fc.current_mode == I40E_FC_RX_PAUSE) {
1560 pause->rx_pause = 1;
1561 } else if (hw->fc.current_mode == I40E_FC_TX_PAUSE) {
1562 pause->tx_pause = 1;
1563 } else if (hw->fc.current_mode == I40E_FC_FULL) {
1564 pause->rx_pause = 1;
1565 pause->tx_pause = 1;
1566 }
1567}
1568
1569
1570
1571
1572
1573
1574static int i40e_set_pauseparam(struct net_device *netdev,
1575 struct ethtool_pauseparam *pause)
1576{
1577 struct i40e_netdev_priv *np = netdev_priv(netdev);
1578 struct i40e_pf *pf = np->vsi->back;
1579 struct i40e_vsi *vsi = np->vsi;
1580 struct i40e_hw *hw = &pf->hw;
1581 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1582 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1583 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1584 i40e_status status;
1585 u8 aq_failures;
1586 int err = 0;
1587 u32 is_an;
1588
1589
1590
1591
1592 if (hw->partition_id != 1) {
1593 i40e_partition_setting_complaint(pf);
1594 return -EOPNOTSUPP;
1595 }
1596
1597 if (vsi != pf->vsi[pf->lan_vsi])
1598 return -EOPNOTSUPP;
1599
1600 is_an = hw_link_info->an_info & I40E_AQ_AN_COMPLETED;
1601 if (pause->autoneg != is_an) {
1602 netdev_info(netdev, "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
1603 return -EOPNOTSUPP;
1604 }
1605
1606
1607 if (!test_bit(__I40E_DOWN, pf->state) && !is_an) {
1608
1609 netdev_info(netdev, "Autoneg did not complete so changing settings may not result in an actual change.\n");
1610 }
1611
1612 if (dcbx_cfg->pfc.pfcenable) {
1613 netdev_info(netdev,
1614 "Priority flow control enabled. Cannot set link flow control.\n");
1615 return -EOPNOTSUPP;
1616 }
1617
1618 if (pause->rx_pause && pause->tx_pause)
1619 hw->fc.requested_mode = I40E_FC_FULL;
1620 else if (pause->rx_pause && !pause->tx_pause)
1621 hw->fc.requested_mode = I40E_FC_RX_PAUSE;
1622 else if (!pause->rx_pause && pause->tx_pause)
1623 hw->fc.requested_mode = I40E_FC_TX_PAUSE;
1624 else if (!pause->rx_pause && !pause->tx_pause)
1625 hw->fc.requested_mode = I40E_FC_NONE;
1626 else
1627 return -EINVAL;
1628
1629
1630
1631
1632 i40e_print_link_message(vsi, false);
1633 netif_carrier_off(netdev);
1634 netif_tx_stop_all_queues(netdev);
1635
1636
1637 status = i40e_set_fc(hw, &aq_failures, link_up);
1638
1639 if (aq_failures & I40E_SET_FC_AQ_FAIL_GET) {
1640 netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %s aq_err %s\n",
1641 i40e_stat_str(hw, status),
1642 i40e_aq_str(hw, hw->aq.asq_last_status));
1643 err = -EAGAIN;
1644 }
1645 if (aq_failures & I40E_SET_FC_AQ_FAIL_SET) {
1646 netdev_info(netdev, "Set fc failed on the set_phy_config call with err %s aq_err %s\n",
1647 i40e_stat_str(hw, status),
1648 i40e_aq_str(hw, hw->aq.asq_last_status));
1649 err = -EAGAIN;
1650 }
1651 if (aq_failures & I40E_SET_FC_AQ_FAIL_UPDATE) {
1652 netdev_info(netdev, "Set fc failed on the get_link_info call with err %s aq_err %s\n",
1653 i40e_stat_str(hw, status),
1654 i40e_aq_str(hw, hw->aq.asq_last_status));
1655 err = -EAGAIN;
1656 }
1657
1658 if (!test_bit(__I40E_DOWN, pf->state) && is_an) {
1659
1660 msleep(75);
1661 if (!test_bit(__I40E_DOWN, pf->state))
1662 return i40e_nway_reset(netdev);
1663 }
1664
1665 return err;
1666}
1667
1668static u32 i40e_get_msglevel(struct net_device *netdev)
1669{
1670 struct i40e_netdev_priv *np = netdev_priv(netdev);
1671 struct i40e_pf *pf = np->vsi->back;
1672 u32 debug_mask = pf->hw.debug_mask;
1673
1674 if (debug_mask)
1675 netdev_info(netdev, "i40e debug_mask: 0x%08X\n", debug_mask);
1676
1677 return pf->msg_enable;
1678}
1679
1680static void i40e_set_msglevel(struct net_device *netdev, u32 data)
1681{
1682 struct i40e_netdev_priv *np = netdev_priv(netdev);
1683 struct i40e_pf *pf = np->vsi->back;
1684
1685 if (I40E_DEBUG_USER & data)
1686 pf->hw.debug_mask = data;
1687 else
1688 pf->msg_enable = data;
1689}
1690
1691static int i40e_get_regs_len(struct net_device *netdev)
1692{
1693 int reg_count = 0;
1694 int i;
1695
1696 for (i = 0; i40e_reg_list[i].offset != 0; i++)
1697 reg_count += i40e_reg_list[i].elements;
1698
1699 return reg_count * sizeof(u32);
1700}
1701
1702static void i40e_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
1703 void *p)
1704{
1705 struct i40e_netdev_priv *np = netdev_priv(netdev);
1706 struct i40e_pf *pf = np->vsi->back;
1707 struct i40e_hw *hw = &pf->hw;
1708 u32 *reg_buf = p;
1709 unsigned int i, j, ri;
1710 u32 reg;
1711
1712
1713
1714
1715
1716
1717
1718
1719 regs->version = 1;
1720
1721
1722 ri = 0;
1723 for (i = 0; i40e_reg_list[i].offset != 0; i++) {
1724 for (j = 0; j < i40e_reg_list[i].elements; j++) {
1725 reg = i40e_reg_list[i].offset
1726 + (j * i40e_reg_list[i].stride);
1727 reg_buf[ri++] = rd32(hw, reg);
1728 }
1729 }
1730
1731}
1732
1733static int i40e_get_eeprom(struct net_device *netdev,
1734 struct ethtool_eeprom *eeprom, u8 *bytes)
1735{
1736 struct i40e_netdev_priv *np = netdev_priv(netdev);
1737 struct i40e_hw *hw = &np->vsi->back->hw;
1738 struct i40e_pf *pf = np->vsi->back;
1739 int ret_val = 0, len, offset;
1740 u8 *eeprom_buff;
1741 u16 i, sectors;
1742 bool last;
1743 u32 magic;
1744
1745#define I40E_NVM_SECTOR_SIZE 4096
1746 if (eeprom->len == 0)
1747 return -EINVAL;
1748
1749
1750 magic = hw->vendor_id | (hw->device_id << 16);
1751 if (eeprom->magic && eeprom->magic != magic) {
1752 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1753 int errno = 0;
1754
1755
1756 if ((eeprom->magic >> 16) != hw->device_id)
1757 errno = -EINVAL;
1758 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1759 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1760 errno = -EBUSY;
1761 else
1762 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1763
1764 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1765 dev_info(&pf->pdev->dev,
1766 "NVMUpdate read failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1767 ret_val, hw->aq.asq_last_status, errno,
1768 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1769 cmd->offset, cmd->data_size);
1770
1771 return errno;
1772 }
1773
1774
1775 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1776
1777 eeprom_buff = kzalloc(eeprom->len, GFP_KERNEL);
1778 if (!eeprom_buff)
1779 return -ENOMEM;
1780
1781 ret_val = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
1782 if (ret_val) {
1783 dev_info(&pf->pdev->dev,
1784 "Failed Acquiring NVM resource for read err=%d status=0x%x\n",
1785 ret_val, hw->aq.asq_last_status);
1786 goto free_buff;
1787 }
1788
1789 sectors = eeprom->len / I40E_NVM_SECTOR_SIZE;
1790 sectors += (eeprom->len % I40E_NVM_SECTOR_SIZE) ? 1 : 0;
1791 len = I40E_NVM_SECTOR_SIZE;
1792 last = false;
1793 for (i = 0; i < sectors; i++) {
1794 if (i == (sectors - 1)) {
1795 len = eeprom->len - (I40E_NVM_SECTOR_SIZE * i);
1796 last = true;
1797 }
1798 offset = eeprom->offset + (I40E_NVM_SECTOR_SIZE * i),
1799 ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len,
1800 (u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i),
1801 last, NULL);
1802 if (ret_val && hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
1803 dev_info(&pf->pdev->dev,
1804 "read NVM failed, invalid offset 0x%x\n",
1805 offset);
1806 break;
1807 } else if (ret_val &&
1808 hw->aq.asq_last_status == I40E_AQ_RC_EACCES) {
1809 dev_info(&pf->pdev->dev,
1810 "read NVM failed, access, offset 0x%x\n",
1811 offset);
1812 break;
1813 } else if (ret_val) {
1814 dev_info(&pf->pdev->dev,
1815 "read NVM failed offset %d err=%d status=0x%x\n",
1816 offset, ret_val, hw->aq.asq_last_status);
1817 break;
1818 }
1819 }
1820
1821 i40e_release_nvm(hw);
1822 memcpy(bytes, (u8 *)eeprom_buff, eeprom->len);
1823free_buff:
1824 kfree(eeprom_buff);
1825 return ret_val;
1826}
1827
1828static int i40e_get_eeprom_len(struct net_device *netdev)
1829{
1830 struct i40e_netdev_priv *np = netdev_priv(netdev);
1831 struct i40e_hw *hw = &np->vsi->back->hw;
1832 u32 val;
1833
1834#define X722_EEPROM_SCOPE_LIMIT 0x5B9FFF
1835 if (hw->mac.type == I40E_MAC_X722) {
1836 val = X722_EEPROM_SCOPE_LIMIT + 1;
1837 return val;
1838 }
1839 val = (rd32(hw, I40E_GLPCI_LBARCTRL)
1840 & I40E_GLPCI_LBARCTRL_FL_SIZE_MASK)
1841 >> I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT;
1842
1843 val = (64 * 1024) * BIT(val);
1844 return val;
1845}
1846
1847static int i40e_set_eeprom(struct net_device *netdev,
1848 struct ethtool_eeprom *eeprom, u8 *bytes)
1849{
1850 struct i40e_netdev_priv *np = netdev_priv(netdev);
1851 struct i40e_hw *hw = &np->vsi->back->hw;
1852 struct i40e_pf *pf = np->vsi->back;
1853 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1854 int ret_val = 0;
1855 int errno = 0;
1856 u32 magic;
1857
1858
1859 magic = hw->vendor_id | (hw->device_id << 16);
1860 if (eeprom->magic == magic)
1861 errno = -EOPNOTSUPP;
1862
1863 else if (!eeprom->magic || (eeprom->magic >> 16) != hw->device_id)
1864 errno = -EINVAL;
1865 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1866 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1867 errno = -EBUSY;
1868 else
1869 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1870
1871 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1872 dev_info(&pf->pdev->dev,
1873 "NVMUpdate write failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1874 ret_val, hw->aq.asq_last_status, errno,
1875 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1876 cmd->offset, cmd->data_size);
1877
1878 return errno;
1879}
1880
1881static void i40e_get_drvinfo(struct net_device *netdev,
1882 struct ethtool_drvinfo *drvinfo)
1883{
1884 struct i40e_netdev_priv *np = netdev_priv(netdev);
1885 struct i40e_vsi *vsi = np->vsi;
1886 struct i40e_pf *pf = vsi->back;
1887
1888 strlcpy(drvinfo->driver, i40e_driver_name, sizeof(drvinfo->driver));
1889 strlcpy(drvinfo->version, i40e_driver_version_str,
1890 sizeof(drvinfo->version));
1891 strlcpy(drvinfo->fw_version, i40e_nvm_version_str(&pf->hw),
1892 sizeof(drvinfo->fw_version));
1893 strlcpy(drvinfo->bus_info, pci_name(pf->pdev),
1894 sizeof(drvinfo->bus_info));
1895 drvinfo->n_priv_flags = I40E_PRIV_FLAGS_STR_LEN;
1896 if (pf->hw.pf_id == 0)
1897 drvinfo->n_priv_flags += I40E_GL_PRIV_FLAGS_STR_LEN;
1898}
1899
1900static void i40e_get_ringparam(struct net_device *netdev,
1901 struct ethtool_ringparam *ring)
1902{
1903 struct i40e_netdev_priv *np = netdev_priv(netdev);
1904 struct i40e_pf *pf = np->vsi->back;
1905 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
1906
1907 ring->rx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
1908 ring->tx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
1909 ring->rx_mini_max_pending = 0;
1910 ring->rx_jumbo_max_pending = 0;
1911 ring->rx_pending = vsi->rx_rings[0]->count;
1912 ring->tx_pending = vsi->tx_rings[0]->count;
1913 ring->rx_mini_pending = 0;
1914 ring->rx_jumbo_pending = 0;
1915}
1916
1917static bool i40e_active_tx_ring_index(struct i40e_vsi *vsi, u16 index)
1918{
1919 if (i40e_enabled_xdp_vsi(vsi)) {
1920 return index < vsi->num_queue_pairs ||
1921 (index >= vsi->alloc_queue_pairs &&
1922 index < vsi->alloc_queue_pairs + vsi->num_queue_pairs);
1923 }
1924
1925 return index < vsi->num_queue_pairs;
1926}
1927
1928static int i40e_set_ringparam(struct net_device *netdev,
1929 struct ethtool_ringparam *ring)
1930{
1931 struct i40e_ring *tx_rings = NULL, *rx_rings = NULL;
1932 struct i40e_netdev_priv *np = netdev_priv(netdev);
1933 struct i40e_hw *hw = &np->vsi->back->hw;
1934 struct i40e_vsi *vsi = np->vsi;
1935 struct i40e_pf *pf = vsi->back;
1936 u32 new_rx_count, new_tx_count;
1937 u16 tx_alloc_queue_pairs;
1938 int timeout = 50;
1939 int i, err = 0;
1940
1941 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1942 return -EINVAL;
1943
1944 if (ring->tx_pending > I40E_MAX_NUM_DESCRIPTORS ||
1945 ring->tx_pending < I40E_MIN_NUM_DESCRIPTORS ||
1946 ring->rx_pending > I40E_MAX_NUM_DESCRIPTORS ||
1947 ring->rx_pending < I40E_MIN_NUM_DESCRIPTORS) {
1948 netdev_info(netdev,
1949 "Descriptors requested (Tx: %d / Rx: %d) out of range [%d-%d]\n",
1950 ring->tx_pending, ring->rx_pending,
1951 I40E_MIN_NUM_DESCRIPTORS, I40E_MAX_NUM_DESCRIPTORS);
1952 return -EINVAL;
1953 }
1954
1955 new_tx_count = ALIGN(ring->tx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
1956 new_rx_count = ALIGN(ring->rx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
1957
1958
1959 if ((new_tx_count == vsi->tx_rings[0]->count) &&
1960 (new_rx_count == vsi->rx_rings[0]->count))
1961 return 0;
1962
1963
1964
1965
1966
1967 if (i40e_xsk_any_rx_ring_enabled(vsi))
1968 return -EBUSY;
1969
1970 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
1971 timeout--;
1972 if (!timeout)
1973 return -EBUSY;
1974 usleep_range(1000, 2000);
1975 }
1976
1977 if (!netif_running(vsi->netdev)) {
1978
1979 for (i = 0; i < vsi->num_queue_pairs; i++) {
1980 vsi->tx_rings[i]->count = new_tx_count;
1981 vsi->rx_rings[i]->count = new_rx_count;
1982 if (i40e_enabled_xdp_vsi(vsi))
1983 vsi->xdp_rings[i]->count = new_tx_count;
1984 }
1985 vsi->num_tx_desc = new_tx_count;
1986 vsi->num_rx_desc = new_rx_count;
1987 goto done;
1988 }
1989
1990
1991
1992
1993
1994
1995
1996 tx_alloc_queue_pairs = vsi->alloc_queue_pairs *
1997 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
1998 if (new_tx_count != vsi->tx_rings[0]->count) {
1999 netdev_info(netdev,
2000 "Changing Tx descriptor count from %d to %d.\n",
2001 vsi->tx_rings[0]->count, new_tx_count);
2002 tx_rings = kcalloc(tx_alloc_queue_pairs,
2003 sizeof(struct i40e_ring), GFP_KERNEL);
2004 if (!tx_rings) {
2005 err = -ENOMEM;
2006 goto done;
2007 }
2008
2009 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2010 if (!i40e_active_tx_ring_index(vsi, i))
2011 continue;
2012
2013 tx_rings[i] = *vsi->tx_rings[i];
2014 tx_rings[i].count = new_tx_count;
2015
2016
2017
2018 tx_rings[i].desc = NULL;
2019 tx_rings[i].rx_bi = NULL;
2020 err = i40e_setup_tx_descriptors(&tx_rings[i]);
2021 if (err) {
2022 while (i) {
2023 i--;
2024 if (!i40e_active_tx_ring_index(vsi, i))
2025 continue;
2026 i40e_free_tx_resources(&tx_rings[i]);
2027 }
2028 kfree(tx_rings);
2029 tx_rings = NULL;
2030
2031 goto done;
2032 }
2033 }
2034 }
2035
2036
2037 if (new_rx_count != vsi->rx_rings[0]->count) {
2038 netdev_info(netdev,
2039 "Changing Rx descriptor count from %d to %d\n",
2040 vsi->rx_rings[0]->count, new_rx_count);
2041 rx_rings = kcalloc(vsi->alloc_queue_pairs,
2042 sizeof(struct i40e_ring), GFP_KERNEL);
2043 if (!rx_rings) {
2044 err = -ENOMEM;
2045 goto free_tx;
2046 }
2047
2048 for (i = 0; i < vsi->num_queue_pairs; i++) {
2049 u16 unused;
2050
2051
2052 rx_rings[i] = *vsi->rx_rings[i];
2053 rx_rings[i].count = new_rx_count;
2054
2055
2056
2057 rx_rings[i].desc = NULL;
2058 rx_rings[i].rx_bi = NULL;
2059
2060 memset(&rx_rings[i].xdp_rxq, 0, sizeof(rx_rings[i].xdp_rxq));
2061
2062
2063
2064 rx_rings[i].tail = hw->hw_addr + I40E_PRTGEN_STATUS;
2065 err = i40e_setup_rx_descriptors(&rx_rings[i]);
2066 if (err)
2067 goto rx_unwind;
2068
2069
2070
2071
2072 unused = I40E_DESC_UNUSED(&rx_rings[i]);
2073 err = i40e_alloc_rx_buffers(&rx_rings[i], unused);
2074rx_unwind:
2075 if (err) {
2076 do {
2077 i40e_free_rx_resources(&rx_rings[i]);
2078 } while (i--);
2079 kfree(rx_rings);
2080 rx_rings = NULL;
2081
2082 goto free_tx;
2083 }
2084 }
2085 }
2086
2087
2088
2089
2090 i40e_down(vsi);
2091
2092 if (tx_rings) {
2093 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2094 if (i40e_active_tx_ring_index(vsi, i)) {
2095 i40e_free_tx_resources(vsi->tx_rings[i]);
2096 *vsi->tx_rings[i] = tx_rings[i];
2097 }
2098 }
2099 kfree(tx_rings);
2100 tx_rings = NULL;
2101 }
2102
2103 if (rx_rings) {
2104 for (i = 0; i < vsi->num_queue_pairs; i++) {
2105 i40e_free_rx_resources(vsi->rx_rings[i]);
2106
2107 rx_rings[i].tail = vsi->rx_rings[i]->tail;
2108
2109
2110
2111
2112
2113 rx_rings[i].next_to_use = 0;
2114 rx_rings[i].next_to_clean = 0;
2115 rx_rings[i].next_to_alloc = 0;
2116
2117 *vsi->rx_rings[i] = rx_rings[i];
2118 }
2119 kfree(rx_rings);
2120 rx_rings = NULL;
2121 }
2122
2123 vsi->num_tx_desc = new_tx_count;
2124 vsi->num_rx_desc = new_rx_count;
2125 i40e_up(vsi);
2126
2127free_tx:
2128
2129 if (tx_rings) {
2130 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2131 if (i40e_active_tx_ring_index(vsi, i))
2132 i40e_free_tx_resources(vsi->tx_rings[i]);
2133 }
2134 kfree(tx_rings);
2135 tx_rings = NULL;
2136 }
2137
2138done:
2139 clear_bit(__I40E_CONFIG_BUSY, pf->state);
2140
2141 return err;
2142}
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158static int i40e_get_stats_count(struct net_device *netdev)
2159{
2160 struct i40e_netdev_priv *np = netdev_priv(netdev);
2161 struct i40e_vsi *vsi = np->vsi;
2162 struct i40e_pf *pf = vsi->back;
2163 int stats_len;
2164
2165 if (vsi == pf->vsi[pf->lan_vsi] && pf->hw.partition_id == 1)
2166 stats_len = I40E_PF_STATS_LEN;
2167 else
2168 stats_len = I40E_VSI_STATS_LEN;
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184 stats_len += I40E_QUEUE_STATS_LEN * 2 * netdev->num_tx_queues;
2185
2186 return stats_len;
2187}
2188
2189static int i40e_get_sset_count(struct net_device *netdev, int sset)
2190{
2191 struct i40e_netdev_priv *np = netdev_priv(netdev);
2192 struct i40e_vsi *vsi = np->vsi;
2193 struct i40e_pf *pf = vsi->back;
2194
2195 switch (sset) {
2196 case ETH_SS_TEST:
2197 return I40E_TEST_LEN;
2198 case ETH_SS_STATS:
2199 return i40e_get_stats_count(netdev);
2200 case ETH_SS_PRIV_FLAGS:
2201 return I40E_PRIV_FLAGS_STR_LEN +
2202 (pf->hw.pf_id == 0 ? I40E_GL_PRIV_FLAGS_STR_LEN : 0);
2203 default:
2204 return -EOPNOTSUPP;
2205 }
2206}
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217static inline struct i40e_pfc_stats
2218i40e_get_pfc_stats(struct i40e_pf *pf, unsigned int i)
2219{
2220#define I40E_GET_PFC_STAT(stat, priority) \
2221 .stat = pf->stats.stat[priority]
2222
2223 struct i40e_pfc_stats pfc = {
2224 I40E_GET_PFC_STAT(priority_xon_rx, i),
2225 I40E_GET_PFC_STAT(priority_xoff_rx, i),
2226 I40E_GET_PFC_STAT(priority_xon_tx, i),
2227 I40E_GET_PFC_STAT(priority_xoff_tx, i),
2228 I40E_GET_PFC_STAT(priority_xon_2_xoff, i),
2229 };
2230 return pfc;
2231}
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247static void i40e_get_ethtool_stats(struct net_device *netdev,
2248 struct ethtool_stats *stats, u64 *data)
2249{
2250 struct i40e_netdev_priv *np = netdev_priv(netdev);
2251 struct i40e_vsi *vsi = np->vsi;
2252 struct i40e_pf *pf = vsi->back;
2253 struct i40e_veb *veb = pf->veb[pf->lan_veb];
2254 unsigned int i;
2255 bool veb_stats;
2256 u64 *p = data;
2257
2258 i40e_update_stats(vsi);
2259
2260 i40e_add_ethtool_stats(&data, i40e_get_vsi_stats_struct(vsi),
2261 i40e_gstrings_net_stats);
2262
2263 i40e_add_ethtool_stats(&data, vsi, i40e_gstrings_misc_stats);
2264
2265 rcu_read_lock();
2266 for (i = 0; i < netdev->num_tx_queues; i++) {
2267 i40e_add_queue_stats(&data, READ_ONCE(vsi->tx_rings[i]));
2268 i40e_add_queue_stats(&data, READ_ONCE(vsi->rx_rings[i]));
2269 }
2270 rcu_read_unlock();
2271
2272 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2273 goto check_data_pointer;
2274
2275 veb_stats = ((pf->lan_veb != I40E_NO_VEB) &&
2276 (pf->flags & I40E_FLAG_VEB_STATS_ENABLED));
2277
2278
2279
2280
2281
2282 i40e_add_ethtool_stats(&data, veb_stats ? veb : NULL,
2283 i40e_gstrings_veb_stats);
2284
2285 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2286 i40e_add_ethtool_stats(&data, veb_stats ? veb : NULL,
2287 i40e_gstrings_veb_tc_stats);
2288
2289 i40e_add_ethtool_stats(&data, pf, i40e_gstrings_stats);
2290
2291 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
2292 struct i40e_pfc_stats pfc = i40e_get_pfc_stats(pf, i);
2293
2294 i40e_add_ethtool_stats(&data, &pfc, i40e_gstrings_pfc_stats);
2295 }
2296
2297check_data_pointer:
2298 WARN_ONCE(data - p != i40e_get_stats_count(netdev),
2299 "ethtool stats count mismatch!");
2300}
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312static void i40e_get_stat_strings(struct net_device *netdev, u8 *data)
2313{
2314 struct i40e_netdev_priv *np = netdev_priv(netdev);
2315 struct i40e_vsi *vsi = np->vsi;
2316 struct i40e_pf *pf = vsi->back;
2317 unsigned int i;
2318 u8 *p = data;
2319
2320 i40e_add_stat_strings(&data, i40e_gstrings_net_stats);
2321
2322 i40e_add_stat_strings(&data, i40e_gstrings_misc_stats);
2323
2324 for (i = 0; i < netdev->num_tx_queues; i++) {
2325 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2326 "tx", i);
2327 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2328 "rx", i);
2329 }
2330
2331 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2332 return;
2333
2334 i40e_add_stat_strings(&data, i40e_gstrings_veb_stats);
2335
2336 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2337 i40e_add_stat_strings(&data, i40e_gstrings_veb_tc_stats, i);
2338
2339 i40e_add_stat_strings(&data, i40e_gstrings_stats);
2340
2341 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
2342 i40e_add_stat_strings(&data, i40e_gstrings_pfc_stats, i);
2343
2344 WARN_ONCE(data - p != i40e_get_stats_count(netdev) * ETH_GSTRING_LEN,
2345 "stat strings count mismatch!");
2346}
2347
2348static void i40e_get_priv_flag_strings(struct net_device *netdev, u8 *data)
2349{
2350 struct i40e_netdev_priv *np = netdev_priv(netdev);
2351 struct i40e_vsi *vsi = np->vsi;
2352 struct i40e_pf *pf = vsi->back;
2353 char *p = (char *)data;
2354 unsigned int i;
2355
2356 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
2357 snprintf(p, ETH_GSTRING_LEN, "%s",
2358 i40e_gstrings_priv_flags[i].flag_string);
2359 p += ETH_GSTRING_LEN;
2360 }
2361 if (pf->hw.pf_id != 0)
2362 return;
2363 for (i = 0; i < I40E_GL_PRIV_FLAGS_STR_LEN; i++) {
2364 snprintf(p, ETH_GSTRING_LEN, "%s",
2365 i40e_gl_gstrings_priv_flags[i].flag_string);
2366 p += ETH_GSTRING_LEN;
2367 }
2368}
2369
2370static void i40e_get_strings(struct net_device *netdev, u32 stringset,
2371 u8 *data)
2372{
2373 switch (stringset) {
2374 case ETH_SS_TEST:
2375 memcpy(data, i40e_gstrings_test,
2376 I40E_TEST_LEN * ETH_GSTRING_LEN);
2377 break;
2378 case ETH_SS_STATS:
2379 i40e_get_stat_strings(netdev, data);
2380 break;
2381 case ETH_SS_PRIV_FLAGS:
2382 i40e_get_priv_flag_strings(netdev, data);
2383 break;
2384 default:
2385 break;
2386 }
2387}
2388
2389static int i40e_get_ts_info(struct net_device *dev,
2390 struct ethtool_ts_info *info)
2391{
2392 struct i40e_pf *pf = i40e_netdev_to_pf(dev);
2393
2394
2395 if (!(pf->flags & I40E_FLAG_PTP))
2396 return ethtool_op_get_ts_info(dev, info);
2397
2398 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2399 SOF_TIMESTAMPING_RX_SOFTWARE |
2400 SOF_TIMESTAMPING_SOFTWARE |
2401 SOF_TIMESTAMPING_TX_HARDWARE |
2402 SOF_TIMESTAMPING_RX_HARDWARE |
2403 SOF_TIMESTAMPING_RAW_HARDWARE;
2404
2405 if (pf->ptp_clock)
2406 info->phc_index = ptp_clock_index(pf->ptp_clock);
2407 else
2408 info->phc_index = -1;
2409
2410 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
2411
2412 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
2413 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2414 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2415 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
2416
2417 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE)
2418 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2419 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2420 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
2421 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2422 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
2423 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2424 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2425 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
2426
2427 return 0;
2428}
2429
2430static u64 i40e_link_test(struct net_device *netdev, u64 *data)
2431{
2432 struct i40e_netdev_priv *np = netdev_priv(netdev);
2433 struct i40e_pf *pf = np->vsi->back;
2434 i40e_status status;
2435 bool link_up = false;
2436
2437 netif_info(pf, hw, netdev, "link test\n");
2438 status = i40e_get_link_status(&pf->hw, &link_up);
2439 if (status) {
2440 netif_err(pf, drv, netdev, "link query timed out, please retry test\n");
2441 *data = 1;
2442 return *data;
2443 }
2444
2445 if (link_up)
2446 *data = 0;
2447 else
2448 *data = 1;
2449
2450 return *data;
2451}
2452
2453static u64 i40e_reg_test(struct net_device *netdev, u64 *data)
2454{
2455 struct i40e_netdev_priv *np = netdev_priv(netdev);
2456 struct i40e_pf *pf = np->vsi->back;
2457
2458 netif_info(pf, hw, netdev, "register test\n");
2459 *data = i40e_diag_reg_test(&pf->hw);
2460
2461 return *data;
2462}
2463
2464static u64 i40e_eeprom_test(struct net_device *netdev, u64 *data)
2465{
2466 struct i40e_netdev_priv *np = netdev_priv(netdev);
2467 struct i40e_pf *pf = np->vsi->back;
2468
2469 netif_info(pf, hw, netdev, "eeprom test\n");
2470 *data = i40e_diag_eeprom_test(&pf->hw);
2471
2472
2473 pf->hw.nvmupd_state = I40E_NVMUPD_STATE_INIT;
2474
2475 return *data;
2476}
2477
2478static u64 i40e_intr_test(struct net_device *netdev, u64 *data)
2479{
2480 struct i40e_netdev_priv *np = netdev_priv(netdev);
2481 struct i40e_pf *pf = np->vsi->back;
2482 u16 swc_old = pf->sw_int_count;
2483
2484 netif_info(pf, hw, netdev, "interrupt test\n");
2485 wr32(&pf->hw, I40E_PFINT_DYN_CTL0,
2486 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
2487 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
2488 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
2489 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
2490 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
2491 usleep_range(1000, 2000);
2492 *data = (swc_old == pf->sw_int_count);
2493
2494 return *data;
2495}
2496
2497static inline bool i40e_active_vfs(struct i40e_pf *pf)
2498{
2499 struct i40e_vf *vfs = pf->vf;
2500 int i;
2501
2502 for (i = 0; i < pf->num_alloc_vfs; i++)
2503 if (test_bit(I40E_VF_STATE_ACTIVE, &vfs[i].vf_states))
2504 return true;
2505 return false;
2506}
2507
2508static inline bool i40e_active_vmdqs(struct i40e_pf *pf)
2509{
2510 return !!i40e_find_vsi_by_type(pf, I40E_VSI_VMDQ2);
2511}
2512
2513static void i40e_diag_test(struct net_device *netdev,
2514 struct ethtool_test *eth_test, u64 *data)
2515{
2516 struct i40e_netdev_priv *np = netdev_priv(netdev);
2517 bool if_running = netif_running(netdev);
2518 struct i40e_pf *pf = np->vsi->back;
2519
2520 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2521
2522 netif_info(pf, drv, netdev, "offline testing starting\n");
2523
2524 set_bit(__I40E_TESTING, pf->state);
2525
2526 if (i40e_active_vfs(pf) || i40e_active_vmdqs(pf)) {
2527 dev_warn(&pf->pdev->dev,
2528 "Please take active VFs and Netqueues offline and restart the adapter before running NIC diagnostics\n");
2529 data[I40E_ETH_TEST_REG] = 1;
2530 data[I40E_ETH_TEST_EEPROM] = 1;
2531 data[I40E_ETH_TEST_INTR] = 1;
2532 data[I40E_ETH_TEST_LINK] = 1;
2533 eth_test->flags |= ETH_TEST_FL_FAILED;
2534 clear_bit(__I40E_TESTING, pf->state);
2535 goto skip_ol_tests;
2536 }
2537
2538
2539 if (if_running)
2540
2541 i40e_close(netdev);
2542 else
2543
2544
2545
2546
2547
2548 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2549
2550 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2551 eth_test->flags |= ETH_TEST_FL_FAILED;
2552
2553 if (i40e_eeprom_test(netdev, &data[I40E_ETH_TEST_EEPROM]))
2554 eth_test->flags |= ETH_TEST_FL_FAILED;
2555
2556 if (i40e_intr_test(netdev, &data[I40E_ETH_TEST_INTR]))
2557 eth_test->flags |= ETH_TEST_FL_FAILED;
2558
2559
2560 if (i40e_reg_test(netdev, &data[I40E_ETH_TEST_REG]))
2561 eth_test->flags |= ETH_TEST_FL_FAILED;
2562
2563 clear_bit(__I40E_TESTING, pf->state);
2564 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2565
2566 if (if_running)
2567 i40e_open(netdev);
2568 } else {
2569
2570 netif_info(pf, drv, netdev, "online testing starting\n");
2571
2572 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2573 eth_test->flags |= ETH_TEST_FL_FAILED;
2574
2575
2576 data[I40E_ETH_TEST_REG] = 0;
2577 data[I40E_ETH_TEST_EEPROM] = 0;
2578 data[I40E_ETH_TEST_INTR] = 0;
2579 }
2580
2581skip_ol_tests:
2582
2583 netif_info(pf, drv, netdev, "testing finished\n");
2584}
2585
2586static void i40e_get_wol(struct net_device *netdev,
2587 struct ethtool_wolinfo *wol)
2588{
2589 struct i40e_netdev_priv *np = netdev_priv(netdev);
2590 struct i40e_pf *pf = np->vsi->back;
2591 struct i40e_hw *hw = &pf->hw;
2592 u16 wol_nvm_bits;
2593
2594
2595 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2596 if ((BIT(hw->port) & wol_nvm_bits) || (hw->partition_id != 1)) {
2597 wol->supported = 0;
2598 wol->wolopts = 0;
2599 } else {
2600 wol->supported = WAKE_MAGIC;
2601 wol->wolopts = (pf->wol_en ? WAKE_MAGIC : 0);
2602 }
2603}
2604
2605
2606
2607
2608
2609
2610static int i40e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2611{
2612 struct i40e_netdev_priv *np = netdev_priv(netdev);
2613 struct i40e_pf *pf = np->vsi->back;
2614 struct i40e_vsi *vsi = np->vsi;
2615 struct i40e_hw *hw = &pf->hw;
2616 u16 wol_nvm_bits;
2617
2618
2619 if (hw->partition_id != 1) {
2620 i40e_partition_setting_complaint(pf);
2621 return -EOPNOTSUPP;
2622 }
2623
2624 if (vsi != pf->vsi[pf->lan_vsi])
2625 return -EOPNOTSUPP;
2626
2627
2628 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2629 if (BIT(hw->port) & wol_nvm_bits)
2630 return -EOPNOTSUPP;
2631
2632
2633 if (wol->wolopts & ~WAKE_MAGIC)
2634 return -EOPNOTSUPP;
2635
2636
2637 if (pf->wol_en != !!wol->wolopts) {
2638 pf->wol_en = !!wol->wolopts;
2639 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
2640 }
2641
2642 return 0;
2643}
2644
2645static int i40e_set_phys_id(struct net_device *netdev,
2646 enum ethtool_phys_id_state state)
2647{
2648 struct i40e_netdev_priv *np = netdev_priv(netdev);
2649 i40e_status ret = 0;
2650 struct i40e_pf *pf = np->vsi->back;
2651 struct i40e_hw *hw = &pf->hw;
2652 int blink_freq = 2;
2653 u16 temp_status;
2654
2655 switch (state) {
2656 case ETHTOOL_ID_ACTIVE:
2657 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2658 pf->led_status = i40e_led_get(hw);
2659 } else {
2660 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2661 i40e_aq_set_phy_debug(hw, I40E_PHY_DEBUG_ALL,
2662 NULL);
2663 ret = i40e_led_get_phy(hw, &temp_status,
2664 &pf->phy_led_val);
2665 pf->led_status = temp_status;
2666 }
2667 return blink_freq;
2668 case ETHTOOL_ID_ON:
2669 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2670 i40e_led_set(hw, 0xf, false);
2671 else
2672 ret = i40e_led_set_phy(hw, true, pf->led_status, 0);
2673 break;
2674 case ETHTOOL_ID_OFF:
2675 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2676 i40e_led_set(hw, 0x0, false);
2677 else
2678 ret = i40e_led_set_phy(hw, false, pf->led_status, 0);
2679 break;
2680 case ETHTOOL_ID_INACTIVE:
2681 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2682 i40e_led_set(hw, pf->led_status, false);
2683 } else {
2684 ret = i40e_led_set_phy(hw, false, pf->led_status,
2685 (pf->phy_led_val |
2686 I40E_PHY_LED_MODE_ORIG));
2687 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2688 i40e_aq_set_phy_debug(hw, 0, NULL);
2689 }
2690 break;
2691 default:
2692 break;
2693 }
2694 if (ret)
2695 return -ENOENT;
2696 else
2697 return 0;
2698}
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715static int __i40e_get_coalesce(struct net_device *netdev,
2716 struct ethtool_coalesce *ec,
2717 int queue)
2718{
2719 struct i40e_netdev_priv *np = netdev_priv(netdev);
2720 struct i40e_ring *rx_ring, *tx_ring;
2721 struct i40e_vsi *vsi = np->vsi;
2722
2723 ec->tx_max_coalesced_frames_irq = vsi->work_limit;
2724 ec->rx_max_coalesced_frames_irq = vsi->work_limit;
2725
2726
2727
2728
2729 if (queue < 0)
2730 queue = 0;
2731 else if (queue >= vsi->num_queue_pairs)
2732 return -EINVAL;
2733
2734 rx_ring = vsi->rx_rings[queue];
2735 tx_ring = vsi->tx_rings[queue];
2736
2737 if (ITR_IS_DYNAMIC(rx_ring->itr_setting))
2738 ec->use_adaptive_rx_coalesce = 1;
2739
2740 if (ITR_IS_DYNAMIC(tx_ring->itr_setting))
2741 ec->use_adaptive_tx_coalesce = 1;
2742
2743 ec->rx_coalesce_usecs = rx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2744 ec->tx_coalesce_usecs = tx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2745
2746
2747
2748
2749
2750
2751
2752 ec->rx_coalesce_usecs_high = vsi->int_rate_limit;
2753 ec->tx_coalesce_usecs_high = vsi->int_rate_limit;
2754
2755 return 0;
2756}
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767static int i40e_get_coalesce(struct net_device *netdev,
2768 struct ethtool_coalesce *ec)
2769{
2770 return __i40e_get_coalesce(netdev, ec, -1);
2771}
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781static int i40e_get_per_queue_coalesce(struct net_device *netdev, u32 queue,
2782 struct ethtool_coalesce *ec)
2783{
2784 return __i40e_get_coalesce(netdev, ec, queue);
2785}
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795static void i40e_set_itr_per_queue(struct i40e_vsi *vsi,
2796 struct ethtool_coalesce *ec,
2797 int queue)
2798{
2799 struct i40e_ring *rx_ring = vsi->rx_rings[queue];
2800 struct i40e_ring *tx_ring = vsi->tx_rings[queue];
2801 struct i40e_pf *pf = vsi->back;
2802 struct i40e_hw *hw = &pf->hw;
2803 struct i40e_q_vector *q_vector;
2804 u16 intrl;
2805
2806 intrl = i40e_intrl_usec_to_reg(vsi->int_rate_limit);
2807
2808 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);
2809 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);
2810
2811 if (ec->use_adaptive_rx_coalesce)
2812 rx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2813 else
2814 rx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2815
2816 if (ec->use_adaptive_tx_coalesce)
2817 tx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2818 else
2819 tx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2820
2821 q_vector = rx_ring->q_vector;
2822 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting);
2823
2824 q_vector = tx_ring->q_vector;
2825 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting);
2826
2827
2828
2829
2830
2831
2832 wr32(hw, I40E_PFINT_RATEN(q_vector->reg_idx), intrl);
2833 i40e_flush(hw);
2834}
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844static int __i40e_set_coalesce(struct net_device *netdev,
2845 struct ethtool_coalesce *ec,
2846 int queue)
2847{
2848 struct i40e_netdev_priv *np = netdev_priv(netdev);
2849 u16 intrl_reg, cur_rx_itr, cur_tx_itr;
2850 struct i40e_vsi *vsi = np->vsi;
2851 struct i40e_pf *pf = vsi->back;
2852 int i;
2853
2854 if (ec->tx_max_coalesced_frames_irq || ec->rx_max_coalesced_frames_irq)
2855 vsi->work_limit = ec->tx_max_coalesced_frames_irq;
2856
2857 if (queue < 0) {
2858 cur_rx_itr = vsi->rx_rings[0]->itr_setting;
2859 cur_tx_itr = vsi->tx_rings[0]->itr_setting;
2860 } else if (queue < vsi->num_queue_pairs) {
2861 cur_rx_itr = vsi->rx_rings[queue]->itr_setting;
2862 cur_tx_itr = vsi->tx_rings[queue]->itr_setting;
2863 } else {
2864 netif_info(pf, drv, netdev, "Invalid queue value, queue range is 0 - %d\n",
2865 vsi->num_queue_pairs - 1);
2866 return -EINVAL;
2867 }
2868
2869 cur_tx_itr &= ~I40E_ITR_DYNAMIC;
2870 cur_rx_itr &= ~I40E_ITR_DYNAMIC;
2871
2872
2873 if (ec->tx_coalesce_usecs_high != vsi->int_rate_limit) {
2874 netif_info(pf, drv, netdev, "tx-usecs-high is not used, please program rx-usecs-high\n");
2875 return -EINVAL;
2876 }
2877
2878 if (ec->rx_coalesce_usecs_high > INTRL_REG_TO_USEC(I40E_MAX_INTRL)) {
2879 netif_info(pf, drv, netdev, "Invalid value, rx-usecs-high range is 0-%lu\n",
2880 INTRL_REG_TO_USEC(I40E_MAX_INTRL));
2881 return -EINVAL;
2882 }
2883
2884 if (ec->rx_coalesce_usecs != cur_rx_itr &&
2885 ec->use_adaptive_rx_coalesce) {
2886 netif_info(pf, drv, netdev, "RX interrupt moderation cannot be changed if adaptive-rx is enabled.\n");
2887 return -EINVAL;
2888 }
2889
2890 if (ec->rx_coalesce_usecs > I40E_MAX_ITR) {
2891 netif_info(pf, drv, netdev, "Invalid value, rx-usecs range is 0-8160\n");
2892 return -EINVAL;
2893 }
2894
2895 if (ec->tx_coalesce_usecs != cur_tx_itr &&
2896 ec->use_adaptive_tx_coalesce) {
2897 netif_info(pf, drv, netdev, "TX interrupt moderation cannot be changed if adaptive-tx is enabled.\n");
2898 return -EINVAL;
2899 }
2900
2901 if (ec->tx_coalesce_usecs > I40E_MAX_ITR) {
2902 netif_info(pf, drv, netdev, "Invalid value, tx-usecs range is 0-8160\n");
2903 return -EINVAL;
2904 }
2905
2906 if (ec->use_adaptive_rx_coalesce && !cur_rx_itr)
2907 ec->rx_coalesce_usecs = I40E_MIN_ITR;
2908
2909 if (ec->use_adaptive_tx_coalesce && !cur_tx_itr)
2910 ec->tx_coalesce_usecs = I40E_MIN_ITR;
2911
2912 intrl_reg = i40e_intrl_usec_to_reg(ec->rx_coalesce_usecs_high);
2913 vsi->int_rate_limit = INTRL_REG_TO_USEC(intrl_reg);
2914 if (vsi->int_rate_limit != ec->rx_coalesce_usecs_high) {
2915 netif_info(pf, drv, netdev, "Interrupt rate limit rounded down to %d\n",
2916 vsi->int_rate_limit);
2917 }
2918
2919
2920
2921
2922 if (queue < 0) {
2923 for (i = 0; i < vsi->num_queue_pairs; i++)
2924 i40e_set_itr_per_queue(vsi, ec, i);
2925 } else {
2926 i40e_set_itr_per_queue(vsi, ec, queue);
2927 }
2928
2929 return 0;
2930}
2931
2932
2933
2934
2935
2936
2937
2938
2939static int i40e_set_coalesce(struct net_device *netdev,
2940 struct ethtool_coalesce *ec)
2941{
2942 return __i40e_set_coalesce(netdev, ec, -1);
2943}
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953static int i40e_set_per_queue_coalesce(struct net_device *netdev, u32 queue,
2954 struct ethtool_coalesce *ec)
2955{
2956 return __i40e_set_coalesce(netdev, ec, queue);
2957}
2958
2959
2960
2961
2962
2963
2964
2965
2966static int i40e_get_rss_hash_opts(struct i40e_pf *pf, struct ethtool_rxnfc *cmd)
2967{
2968 struct i40e_hw *hw = &pf->hw;
2969 u8 flow_pctype = 0;
2970 u64 i_set = 0;
2971
2972 cmd->data = 0;
2973
2974 switch (cmd->flow_type) {
2975 case TCP_V4_FLOW:
2976 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2977 break;
2978 case UDP_V4_FLOW:
2979 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2980 break;
2981 case TCP_V6_FLOW:
2982 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2983 break;
2984 case UDP_V6_FLOW:
2985 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2986 break;
2987 case SCTP_V4_FLOW:
2988 case AH_ESP_V4_FLOW:
2989 case AH_V4_FLOW:
2990 case ESP_V4_FLOW:
2991 case IPV4_FLOW:
2992 case SCTP_V6_FLOW:
2993 case AH_ESP_V6_FLOW:
2994 case AH_V6_FLOW:
2995 case ESP_V6_FLOW:
2996 case IPV6_FLOW:
2997
2998 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2999 break;
3000 default:
3001 return -EINVAL;
3002 }
3003
3004
3005 if (flow_pctype) {
3006 i_set = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3007 flow_pctype)) |
3008 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3009 flow_pctype)) << 32);
3010 }
3011
3012
3013 if (i_set) {
3014 if (i_set & I40E_L4_SRC_MASK)
3015 cmd->data |= RXH_L4_B_0_1;
3016 if (i_set & I40E_L4_DST_MASK)
3017 cmd->data |= RXH_L4_B_2_3;
3018
3019 if (cmd->flow_type == TCP_V4_FLOW ||
3020 cmd->flow_type == UDP_V4_FLOW) {
3021 if (i_set & I40E_L3_SRC_MASK)
3022 cmd->data |= RXH_IP_SRC;
3023 if (i_set & I40E_L3_DST_MASK)
3024 cmd->data |= RXH_IP_DST;
3025 } else if (cmd->flow_type == TCP_V6_FLOW ||
3026 cmd->flow_type == UDP_V6_FLOW) {
3027 if (i_set & I40E_L3_V6_SRC_MASK)
3028 cmd->data |= RXH_IP_SRC;
3029 if (i_set & I40E_L3_V6_DST_MASK)
3030 cmd->data |= RXH_IP_DST;
3031 }
3032 }
3033
3034 return 0;
3035}
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045static int i40e_check_mask(u64 mask, u64 field)
3046{
3047 u64 value = mask & field;
3048
3049 if (value == field)
3050 return 1;
3051 else if (!value)
3052 return 0;
3053 else
3054 return -1;
3055}
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076static int i40e_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3077 struct i40e_rx_flow_userdef *data)
3078{
3079 u64 value, mask;
3080 int valid;
3081
3082
3083 memset(data, 0, sizeof(*data));
3084
3085 if (!(fsp->flow_type & FLOW_EXT))
3086 return 0;
3087
3088 value = be64_to_cpu(*((__be64 *)fsp->h_ext.data));
3089 mask = be64_to_cpu(*((__be64 *)fsp->m_ext.data));
3090
3091#define I40E_USERDEF_FLEX_WORD GENMASK_ULL(15, 0)
3092#define I40E_USERDEF_FLEX_OFFSET GENMASK_ULL(31, 16)
3093#define I40E_USERDEF_FLEX_FILTER GENMASK_ULL(31, 0)
3094
3095 valid = i40e_check_mask(mask, I40E_USERDEF_FLEX_FILTER);
3096 if (valid < 0) {
3097 return -EINVAL;
3098 } else if (valid) {
3099 data->flex_word = value & I40E_USERDEF_FLEX_WORD;
3100 data->flex_offset =
3101 (value & I40E_USERDEF_FLEX_OFFSET) >> 16;
3102 data->flex_filter = true;
3103 }
3104
3105 return 0;
3106}
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116static void i40e_fill_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3117 struct i40e_rx_flow_userdef *data)
3118{
3119 u64 value = 0, mask = 0;
3120
3121 if (data->flex_filter) {
3122 value |= data->flex_word;
3123 value |= (u64)data->flex_offset << 16;
3124 mask |= I40E_USERDEF_FLEX_FILTER;
3125 }
3126
3127 if (value || mask)
3128 fsp->flow_type |= FLOW_EXT;
3129
3130 *((__be64 *)fsp->h_ext.data) = cpu_to_be64(value);
3131 *((__be64 *)fsp->m_ext.data) = cpu_to_be64(mask);
3132}
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145static int i40e_get_ethtool_fdir_all(struct i40e_pf *pf,
3146 struct ethtool_rxnfc *cmd,
3147 u32 *rule_locs)
3148{
3149 struct i40e_fdir_filter *rule;
3150 struct hlist_node *node2;
3151 int cnt = 0;
3152
3153
3154 cmd->data = i40e_get_fd_cnt_all(pf);
3155
3156 hlist_for_each_entry_safe(rule, node2,
3157 &pf->fdir_filter_list, fdir_node) {
3158 if (cnt == cmd->rule_cnt)
3159 return -EMSGSIZE;
3160
3161 rule_locs[cnt] = rule->fd_id;
3162 cnt++;
3163 }
3164
3165 cmd->rule_cnt = cnt;
3166
3167 return 0;
3168}
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180static int i40e_get_ethtool_fdir_entry(struct i40e_pf *pf,
3181 struct ethtool_rxnfc *cmd)
3182{
3183 struct ethtool_rx_flow_spec *fsp =
3184 (struct ethtool_rx_flow_spec *)&cmd->fs;
3185 struct i40e_rx_flow_userdef userdef = {0};
3186 struct i40e_fdir_filter *rule = NULL;
3187 struct hlist_node *node2;
3188 u64 input_set;
3189 u16 index;
3190
3191 hlist_for_each_entry_safe(rule, node2,
3192 &pf->fdir_filter_list, fdir_node) {
3193 if (fsp->location <= rule->fd_id)
3194 break;
3195 }
3196
3197 if (!rule || fsp->location != rule->fd_id)
3198 return -EINVAL;
3199
3200 fsp->flow_type = rule->flow_type;
3201 if (fsp->flow_type == IP_USER_FLOW) {
3202 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
3203 fsp->h_u.usr_ip4_spec.proto = 0;
3204 fsp->m_u.usr_ip4_spec.proto = 0;
3205 }
3206
3207
3208
3209
3210 fsp->h_u.tcp_ip4_spec.psrc = rule->dst_port;
3211 fsp->h_u.tcp_ip4_spec.pdst = rule->src_port;
3212 fsp->h_u.tcp_ip4_spec.ip4src = rule->dst_ip;
3213 fsp->h_u.tcp_ip4_spec.ip4dst = rule->src_ip;
3214
3215 switch (rule->flow_type) {
3216 case SCTP_V4_FLOW:
3217 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3218 break;
3219 case TCP_V4_FLOW:
3220 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3221 break;
3222 case UDP_V4_FLOW:
3223 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3224 break;
3225 case IP_USER_FLOW:
3226 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3227 break;
3228 default:
3229
3230
3231
3232
3233
3234 WARN(1, "Missing input set index for flow_type %d\n",
3235 rule->flow_type);
3236 input_set = 0xFFFFFFFFFFFFFFFFULL;
3237 goto no_input_set;
3238 }
3239
3240 input_set = i40e_read_fd_input_set(pf, index);
3241
3242no_input_set:
3243 if (input_set & I40E_L3_SRC_MASK)
3244 fsp->m_u.tcp_ip4_spec.ip4src = htonl(0xFFFFFFFF);
3245
3246 if (input_set & I40E_L3_DST_MASK)
3247 fsp->m_u.tcp_ip4_spec.ip4dst = htonl(0xFFFFFFFF);
3248
3249 if (input_set & I40E_L4_SRC_MASK)
3250 fsp->m_u.tcp_ip4_spec.psrc = htons(0xFFFF);
3251
3252 if (input_set & I40E_L4_DST_MASK)
3253 fsp->m_u.tcp_ip4_spec.pdst = htons(0xFFFF);
3254
3255 if (rule->dest_ctl == I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET)
3256 fsp->ring_cookie = RX_CLS_FLOW_DISC;
3257 else
3258 fsp->ring_cookie = rule->q_index;
3259
3260 if (rule->dest_vsi != pf->vsi[pf->lan_vsi]->id) {
3261 struct i40e_vsi *vsi;
3262
3263 vsi = i40e_find_vsi_from_id(pf, rule->dest_vsi);
3264 if (vsi && vsi->type == I40E_VSI_SRIOV) {
3265
3266
3267
3268 u64 ring_vf = vsi->vf_id + 1;
3269
3270 ring_vf <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
3271 fsp->ring_cookie |= ring_vf;
3272 }
3273 }
3274
3275 if (rule->flex_filter) {
3276 userdef.flex_filter = true;
3277 userdef.flex_word = be16_to_cpu(rule->flex_word);
3278 userdef.flex_offset = rule->flex_offset;
3279 }
3280
3281 i40e_fill_rx_flow_user_data(fsp, &userdef);
3282
3283 return 0;
3284}
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3295 u32 *rule_locs)
3296{
3297 struct i40e_netdev_priv *np = netdev_priv(netdev);
3298 struct i40e_vsi *vsi = np->vsi;
3299 struct i40e_pf *pf = vsi->back;
3300 int ret = -EOPNOTSUPP;
3301
3302 switch (cmd->cmd) {
3303 case ETHTOOL_GRXRINGS:
3304 cmd->data = vsi->rss_size;
3305 ret = 0;
3306 break;
3307 case ETHTOOL_GRXFH:
3308 ret = i40e_get_rss_hash_opts(pf, cmd);
3309 break;
3310 case ETHTOOL_GRXCLSRLCNT:
3311 cmd->rule_cnt = pf->fdir_pf_active_filters;
3312
3313 cmd->data = i40e_get_fd_cnt_all(pf);
3314 ret = 0;
3315 break;
3316 case ETHTOOL_GRXCLSRULE:
3317 ret = i40e_get_ethtool_fdir_entry(pf, cmd);
3318 break;
3319 case ETHTOOL_GRXCLSRLALL:
3320 ret = i40e_get_ethtool_fdir_all(pf, cmd, rule_locs);
3321 break;
3322 default:
3323 break;
3324 }
3325
3326 return ret;
3327}
3328
3329
3330
3331
3332
3333
3334
3335
3336static u64 i40e_get_rss_hash_bits(struct ethtool_rxnfc *nfc, u64 i_setc)
3337{
3338 u64 i_set = i_setc;
3339 u64 src_l3 = 0, dst_l3 = 0;
3340
3341 if (nfc->data & RXH_L4_B_0_1)
3342 i_set |= I40E_L4_SRC_MASK;
3343 else
3344 i_set &= ~I40E_L4_SRC_MASK;
3345 if (nfc->data & RXH_L4_B_2_3)
3346 i_set |= I40E_L4_DST_MASK;
3347 else
3348 i_set &= ~I40E_L4_DST_MASK;
3349
3350 if (nfc->flow_type == TCP_V6_FLOW || nfc->flow_type == UDP_V6_FLOW) {
3351 src_l3 = I40E_L3_V6_SRC_MASK;
3352 dst_l3 = I40E_L3_V6_DST_MASK;
3353 } else if (nfc->flow_type == TCP_V4_FLOW ||
3354 nfc->flow_type == UDP_V4_FLOW) {
3355 src_l3 = I40E_L3_SRC_MASK;
3356 dst_l3 = I40E_L3_DST_MASK;
3357 } else {
3358
3359 return i_set;
3360 }
3361
3362 if (nfc->data & RXH_IP_SRC)
3363 i_set |= src_l3;
3364 else
3365 i_set &= ~src_l3;
3366 if (nfc->data & RXH_IP_DST)
3367 i_set |= dst_l3;
3368 else
3369 i_set &= ~dst_l3;
3370
3371 return i_set;
3372}
3373
3374
3375
3376
3377
3378
3379
3380
3381static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
3382{
3383 struct i40e_hw *hw = &pf->hw;
3384 u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
3385 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
3386 u8 flow_pctype = 0;
3387 u64 i_set, i_setc;
3388
3389 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3390 dev_err(&pf->pdev->dev,
3391 "Change of RSS hash input set is not supported when MFP mode is enabled\n");
3392 return -EOPNOTSUPP;
3393 }
3394
3395
3396
3397
3398 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3399 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3400 return -EINVAL;
3401
3402 switch (nfc->flow_type) {
3403 case TCP_V4_FLOW:
3404 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3405 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3406 hena |=
3407 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3408 break;
3409 case TCP_V6_FLOW:
3410 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3411 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3412 hena |=
3413 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3414 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3415 hena |=
3416 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3417 break;
3418 case UDP_V4_FLOW:
3419 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3420 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3421 hena |=
3422 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
3423 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3424
3425 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3426 break;
3427 case UDP_V6_FLOW:
3428 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3429 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3430 hena |=
3431 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
3432 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3433
3434 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3435 break;
3436 case AH_ESP_V4_FLOW:
3437 case AH_V4_FLOW:
3438 case ESP_V4_FLOW:
3439 case SCTP_V4_FLOW:
3440 if ((nfc->data & RXH_L4_B_0_1) ||
3441 (nfc->data & RXH_L4_B_2_3))
3442 return -EINVAL;
3443 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3444 break;
3445 case AH_ESP_V6_FLOW:
3446 case AH_V6_FLOW:
3447 case ESP_V6_FLOW:
3448 case SCTP_V6_FLOW:
3449 if ((nfc->data & RXH_L4_B_0_1) ||
3450 (nfc->data & RXH_L4_B_2_3))
3451 return -EINVAL;
3452 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3453 break;
3454 case IPV4_FLOW:
3455 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |
3456 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3457 break;
3458 case IPV6_FLOW:
3459 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
3460 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3461 break;
3462 default:
3463 return -EINVAL;
3464 }
3465
3466 if (flow_pctype) {
3467 i_setc = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3468 flow_pctype)) |
3469 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3470 flow_pctype)) << 32);
3471 i_set = i40e_get_rss_hash_bits(nfc, i_setc);
3472 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, flow_pctype),
3473 (u32)i_set);
3474 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, flow_pctype),
3475 (u32)(i_set >> 32));
3476 hena |= BIT_ULL(flow_pctype);
3477 }
3478
3479 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
3480 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
3481 i40e_flush(hw);
3482
3483 return 0;
3484}
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498static int i40e_update_ethtool_fdir_entry(struct i40e_vsi *vsi,
3499 struct i40e_fdir_filter *input,
3500 u16 sw_idx,
3501 struct ethtool_rxnfc *cmd)
3502{
3503 struct i40e_fdir_filter *rule, *parent;
3504 struct i40e_pf *pf = vsi->back;
3505 struct hlist_node *node2;
3506 int err = -EINVAL;
3507
3508 parent = NULL;
3509 rule = NULL;
3510
3511 hlist_for_each_entry_safe(rule, node2,
3512 &pf->fdir_filter_list, fdir_node) {
3513
3514 if (rule->fd_id >= sw_idx)
3515 break;
3516 parent = rule;
3517 }
3518
3519
3520 if (rule && (rule->fd_id == sw_idx)) {
3521
3522
3523
3524 err = i40e_add_del_fdir(vsi, rule, false);
3525 hlist_del(&rule->fdir_node);
3526 kfree(rule);
3527 pf->fdir_pf_active_filters--;
3528 }
3529
3530
3531
3532
3533 if (!input)
3534 return err;
3535
3536
3537 INIT_HLIST_NODE(&input->fdir_node);
3538
3539
3540 if (parent)
3541 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
3542 else
3543 hlist_add_head(&input->fdir_node,
3544 &pf->fdir_filter_list);
3545
3546
3547 pf->fdir_pf_active_filters++;
3548
3549 return 0;
3550}
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560static void i40e_prune_flex_pit_list(struct i40e_pf *pf)
3561{
3562 struct i40e_flex_pit *entry, *tmp;
3563 struct i40e_fdir_filter *rule;
3564
3565
3566 list_for_each_entry_safe(entry, tmp, &pf->l3_flex_pit_list, list) {
3567 bool found = false;
3568
3569 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3570 if (rule->flow_type != IP_USER_FLOW)
3571 continue;
3572 if (rule->flex_filter &&
3573 rule->flex_offset == entry->src_offset) {
3574 found = true;
3575 break;
3576 }
3577 }
3578
3579
3580
3581
3582 if (!found) {
3583 list_del(&entry->list);
3584 kfree(entry);
3585 }
3586 }
3587
3588
3589 list_for_each_entry_safe(entry, tmp, &pf->l4_flex_pit_list, list) {
3590 bool found = false;
3591
3592 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3593
3594
3595
3596 if (rule->flow_type == IP_USER_FLOW)
3597 continue;
3598 if (rule->flex_filter &&
3599 rule->flex_offset == entry->src_offset) {
3600 found = true;
3601 break;
3602 }
3603 }
3604
3605
3606
3607
3608 if (!found) {
3609 list_del(&entry->list);
3610 kfree(entry);
3611 }
3612 }
3613}
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625static int i40e_del_fdir_entry(struct i40e_vsi *vsi,
3626 struct ethtool_rxnfc *cmd)
3627{
3628 struct ethtool_rx_flow_spec *fsp =
3629 (struct ethtool_rx_flow_spec *)&cmd->fs;
3630 struct i40e_pf *pf = vsi->back;
3631 int ret = 0;
3632
3633 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
3634 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
3635 return -EBUSY;
3636
3637 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
3638 return -EBUSY;
3639
3640 ret = i40e_update_ethtool_fdir_entry(vsi, NULL, fsp->location, cmd);
3641
3642 i40e_prune_flex_pit_list(pf);
3643
3644 i40e_fdir_check_and_reenable(pf);
3645 return ret;
3646}
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657static u8 i40e_unused_pit_index(struct i40e_pf *pf)
3658{
3659 unsigned long available_index = 0xFF;
3660 struct i40e_flex_pit *entry;
3661
3662
3663
3664
3665
3666
3667 list_for_each_entry(entry, &pf->l4_flex_pit_list, list)
3668 clear_bit(entry->pit_index, &available_index);
3669
3670 list_for_each_entry(entry, &pf->l3_flex_pit_list, list)
3671 clear_bit(entry->pit_index, &available_index);
3672
3673 return find_first_bit(&available_index, 8);
3674}
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685static
3686struct i40e_flex_pit *i40e_find_flex_offset(struct list_head *flex_pit_list,
3687 u16 src_offset)
3688{
3689 struct i40e_flex_pit *entry;
3690 int size = 0;
3691
3692
3693
3694
3695 list_for_each_entry(entry, flex_pit_list, list) {
3696 size++;
3697 if (entry->src_offset == src_offset)
3698 return entry;
3699 }
3700
3701
3702
3703
3704
3705
3706 if (size >= I40E_FLEX_PIT_TABLE_SIZE)
3707 return ERR_PTR(-ENOSPC);
3708
3709 return NULL;
3710}
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725static int i40e_add_flex_offset(struct list_head *flex_pit_list,
3726 u16 src_offset,
3727 u8 pit_index)
3728{
3729 struct i40e_flex_pit *new_pit, *entry;
3730
3731 new_pit = kzalloc(sizeof(*entry), GFP_KERNEL);
3732 if (!new_pit)
3733 return -ENOMEM;
3734
3735 new_pit->src_offset = src_offset;
3736 new_pit->pit_index = pit_index;
3737
3738
3739
3740
3741 list_for_each_entry(entry, flex_pit_list, list) {
3742 if (new_pit->src_offset < entry->src_offset) {
3743 list_add_tail(&new_pit->list, &entry->list);
3744 return 0;
3745 }
3746
3747
3748
3749
3750
3751 if (new_pit->src_offset == entry->src_offset) {
3752 int err = 0;
3753
3754
3755
3756
3757 if (new_pit->pit_index != entry->pit_index)
3758 err = -EINVAL;
3759
3760 kfree(new_pit);
3761 return err;
3762 }
3763 }
3764
3765
3766
3767
3768 list_add_tail(&new_pit->list, flex_pit_list);
3769 return 0;
3770}
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793static void __i40e_reprogram_flex_pit(struct i40e_pf *pf,
3794 struct list_head *flex_pit_list,
3795 int flex_pit_start)
3796{
3797 struct i40e_flex_pit *entry = NULL;
3798 u16 last_offset = 0;
3799 int i = 0, j = 0;
3800
3801
3802
3803
3804 list_for_each_entry(entry, flex_pit_list, list) {
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819 for (j = i + 1; j < 3; j++) {
3820 u16 offset = entry->src_offset + j;
3821 int index = flex_pit_start + i;
3822 u32 value = I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
3823 1,
3824 offset - 3);
3825
3826 if (offset > I40E_MAX_FLEX_SRC_OFFSET) {
3827 i40e_write_rx_ctl(&pf->hw,
3828 I40E_PRTQF_FLX_PIT(index),
3829 value);
3830 i++;
3831 }
3832 }
3833
3834
3835 i40e_write_rx_ctl(&pf->hw,
3836 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
3837 I40E_FLEX_PREP_VAL(entry->pit_index + 50,
3838 1,
3839 entry->src_offset));
3840 i++;
3841 }
3842
3843
3844
3845
3846
3847
3848
3849 if (!list_empty(flex_pit_list))
3850 last_offset = list_prev_entry(entry, list)->src_offset + 1;
3851
3852 for (; i < 3; i++, last_offset++) {
3853 i40e_write_rx_ctl(&pf->hw,
3854 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
3855 I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
3856 1,
3857 last_offset));
3858 }
3859}
3860
3861
3862
3863
3864
3865
3866
3867
3868static void i40e_reprogram_flex_pit(struct i40e_pf *pf)
3869{
3870 __i40e_reprogram_flex_pit(pf, &pf->l3_flex_pit_list,
3871 I40E_FLEX_PIT_IDX_START_L3);
3872
3873 __i40e_reprogram_flex_pit(pf, &pf->l4_flex_pit_list,
3874 I40E_FLEX_PIT_IDX_START_L4);
3875
3876
3877 i40e_write_rx_ctl(&pf->hw,
3878 I40E_GLQF_ORT(I40E_L3_GLQF_ORT_IDX),
3879 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L3,
3880 3, 1));
3881
3882 i40e_write_rx_ctl(&pf->hw,
3883 I40E_GLQF_ORT(I40E_L4_GLQF_ORT_IDX),
3884 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L4,
3885 3, 1));
3886}
3887
3888
3889
3890
3891
3892
3893
3894
3895static const char *i40e_flow_str(struct ethtool_rx_flow_spec *fsp)
3896{
3897 switch (fsp->flow_type & ~FLOW_EXT) {
3898 case TCP_V4_FLOW:
3899 return "tcp4";
3900 case UDP_V4_FLOW:
3901 return "udp4";
3902 case SCTP_V4_FLOW:
3903 return "sctp4";
3904 case IP_USER_FLOW:
3905 return "ip4";
3906 default:
3907 return "unknown";
3908 }
3909}
3910
3911
3912
3913
3914
3915
3916
3917
3918static u64 i40e_pit_index_to_mask(int pit_index)
3919{
3920 switch (pit_index) {
3921 case 0:
3922 return I40E_FLEX_50_MASK;
3923 case 1:
3924 return I40E_FLEX_51_MASK;
3925 case 2:
3926 return I40E_FLEX_52_MASK;
3927 case 3:
3928 return I40E_FLEX_53_MASK;
3929 case 4:
3930 return I40E_FLEX_54_MASK;
3931 case 5:
3932 return I40E_FLEX_55_MASK;
3933 case 6:
3934 return I40E_FLEX_56_MASK;
3935 case 7:
3936 return I40E_FLEX_57_MASK;
3937 default:
3938 return 0;
3939 }
3940}
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952static void i40e_print_input_set(struct i40e_vsi *vsi, u64 old, u64 new)
3953{
3954 struct i40e_pf *pf = vsi->back;
3955 bool old_value, new_value;
3956 int i;
3957
3958 old_value = !!(old & I40E_L3_SRC_MASK);
3959 new_value = !!(new & I40E_L3_SRC_MASK);
3960 if (old_value != new_value)
3961 netif_info(pf, drv, vsi->netdev, "L3 source address: %s -> %s\n",
3962 old_value ? "ON" : "OFF",
3963 new_value ? "ON" : "OFF");
3964
3965 old_value = !!(old & I40E_L3_DST_MASK);
3966 new_value = !!(new & I40E_L3_DST_MASK);
3967 if (old_value != new_value)
3968 netif_info(pf, drv, vsi->netdev, "L3 destination address: %s -> %s\n",
3969 old_value ? "ON" : "OFF",
3970 new_value ? "ON" : "OFF");
3971
3972 old_value = !!(old & I40E_L4_SRC_MASK);
3973 new_value = !!(new & I40E_L4_SRC_MASK);
3974 if (old_value != new_value)
3975 netif_info(pf, drv, vsi->netdev, "L4 source port: %s -> %s\n",
3976 old_value ? "ON" : "OFF",
3977 new_value ? "ON" : "OFF");
3978
3979 old_value = !!(old & I40E_L4_DST_MASK);
3980 new_value = !!(new & I40E_L4_DST_MASK);
3981 if (old_value != new_value)
3982 netif_info(pf, drv, vsi->netdev, "L4 destination port: %s -> %s\n",
3983 old_value ? "ON" : "OFF",
3984 new_value ? "ON" : "OFF");
3985
3986 old_value = !!(old & I40E_VERIFY_TAG_MASK);
3987 new_value = !!(new & I40E_VERIFY_TAG_MASK);
3988 if (old_value != new_value)
3989 netif_info(pf, drv, vsi->netdev, "SCTP verification tag: %s -> %s\n",
3990 old_value ? "ON" : "OFF",
3991 new_value ? "ON" : "OFF");
3992
3993
3994 for (i = 0; i < I40E_FLEX_INDEX_ENTRIES; i++) {
3995 u64 flex_mask = i40e_pit_index_to_mask(i);
3996
3997 old_value = !!(old & flex_mask);
3998 new_value = !!(new & flex_mask);
3999 if (old_value != new_value)
4000 netif_info(pf, drv, vsi->netdev, "FLEX index %d: %s -> %s\n",
4001 i,
4002 old_value ? "ON" : "OFF",
4003 new_value ? "ON" : "OFF");
4004 }
4005
4006 netif_info(pf, drv, vsi->netdev, " Current input set: %0llx\n",
4007 old);
4008 netif_info(pf, drv, vsi->netdev, "Requested input set: %0llx\n",
4009 new);
4010}
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037static int i40e_check_fdir_input_set(struct i40e_vsi *vsi,
4038 struct ethtool_rx_flow_spec *fsp,
4039 struct i40e_rx_flow_userdef *userdef)
4040{
4041 struct i40e_pf *pf = vsi->back;
4042 struct ethtool_tcpip4_spec *tcp_ip4_spec;
4043 struct ethtool_usrip4_spec *usr_ip4_spec;
4044 u64 current_mask, new_mask;
4045 bool new_flex_offset = false;
4046 bool flex_l3 = false;
4047 u16 *fdir_filter_count;
4048 u16 index, src_offset = 0;
4049 u8 pit_index = 0;
4050 int err;
4051
4052 switch (fsp->flow_type & ~FLOW_EXT) {
4053 case SCTP_V4_FLOW:
4054 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4055 fdir_filter_count = &pf->fd_sctp4_filter_cnt;
4056 break;
4057 case TCP_V4_FLOW:
4058 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4059 fdir_filter_count = &pf->fd_tcp4_filter_cnt;
4060 break;
4061 case UDP_V4_FLOW:
4062 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4063 fdir_filter_count = &pf->fd_udp4_filter_cnt;
4064 break;
4065 case IP_USER_FLOW:
4066 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4067 fdir_filter_count = &pf->fd_ip4_filter_cnt;
4068 flex_l3 = true;
4069 break;
4070 default:
4071 return -EOPNOTSUPP;
4072 }
4073
4074
4075 current_mask = i40e_read_fd_input_set(pf, index);
4076 new_mask = current_mask;
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087 switch (fsp->flow_type & ~FLOW_EXT) {
4088 case SCTP_V4_FLOW:
4089 new_mask &= ~I40E_VERIFY_TAG_MASK;
4090
4091 case TCP_V4_FLOW:
4092 case UDP_V4_FLOW:
4093 tcp_ip4_spec = &fsp->m_u.tcp_ip4_spec;
4094
4095
4096 if (tcp_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4097 new_mask |= I40E_L3_SRC_MASK;
4098 else if (!tcp_ip4_spec->ip4src)
4099 new_mask &= ~I40E_L3_SRC_MASK;
4100 else
4101 return -EOPNOTSUPP;
4102
4103
4104 if (tcp_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4105 new_mask |= I40E_L3_DST_MASK;
4106 else if (!tcp_ip4_spec->ip4dst)
4107 new_mask &= ~I40E_L3_DST_MASK;
4108 else
4109 return -EOPNOTSUPP;
4110
4111
4112 if (tcp_ip4_spec->psrc == htons(0xFFFF))
4113 new_mask |= I40E_L4_SRC_MASK;
4114 else if (!tcp_ip4_spec->psrc)
4115 new_mask &= ~I40E_L4_SRC_MASK;
4116 else
4117 return -EOPNOTSUPP;
4118
4119
4120 if (tcp_ip4_spec->pdst == htons(0xFFFF))
4121 new_mask |= I40E_L4_DST_MASK;
4122 else if (!tcp_ip4_spec->pdst)
4123 new_mask &= ~I40E_L4_DST_MASK;
4124 else
4125 return -EOPNOTSUPP;
4126
4127
4128 if (tcp_ip4_spec->tos)
4129 return -EOPNOTSUPP;
4130
4131 break;
4132 case IP_USER_FLOW:
4133 usr_ip4_spec = &fsp->m_u.usr_ip4_spec;
4134
4135
4136 if (usr_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4137 new_mask |= I40E_L3_SRC_MASK;
4138 else if (!usr_ip4_spec->ip4src)
4139 new_mask &= ~I40E_L3_SRC_MASK;
4140 else
4141 return -EOPNOTSUPP;
4142
4143
4144 if (usr_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4145 new_mask |= I40E_L3_DST_MASK;
4146 else if (!usr_ip4_spec->ip4dst)
4147 new_mask &= ~I40E_L3_DST_MASK;
4148 else
4149 return -EOPNOTSUPP;
4150
4151
4152 if (usr_ip4_spec->l4_4_bytes == htonl(0xFFFFFFFF))
4153 new_mask |= I40E_L4_SRC_MASK | I40E_L4_DST_MASK;
4154 else if (!usr_ip4_spec->l4_4_bytes)
4155 new_mask &= ~(I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
4156 else
4157 return -EOPNOTSUPP;
4158
4159
4160 if (usr_ip4_spec->tos)
4161 return -EOPNOTSUPP;
4162
4163
4164 if (usr_ip4_spec->ip_ver)
4165 return -EINVAL;
4166
4167
4168 if (usr_ip4_spec->proto)
4169 return -EINVAL;
4170
4171 break;
4172 default:
4173 return -EOPNOTSUPP;
4174 }
4175
4176
4177 new_mask &= ~I40E_FLEX_INPUT_MASK;
4178
4179
4180
4181
4182
4183
4184 if (userdef->flex_filter) {
4185 struct i40e_flex_pit *l3_flex_pit = NULL, *flex_pit = NULL;
4186
4187
4188
4189
4190 if (userdef->flex_offset & 0x1) {
4191 dev_warn(&pf->pdev->dev,
4192 "Flexible data offset must be 2-byte aligned\n");
4193 return -EINVAL;
4194 }
4195
4196 src_offset = userdef->flex_offset >> 1;
4197
4198
4199 if (src_offset > I40E_MAX_FLEX_SRC_OFFSET) {
4200 dev_warn(&pf->pdev->dev,
4201 "Flexible data must reside within first 64 bytes of the packet payload\n");
4202 return -EINVAL;
4203 }
4204
4205
4206
4207
4208
4209
4210 flex_pit = i40e_find_flex_offset(&pf->l4_flex_pit_list,
4211 src_offset);
4212 if (IS_ERR(flex_pit))
4213 return PTR_ERR(flex_pit);
4214
4215
4216
4217
4218
4219
4220
4221
4222 if (flex_l3) {
4223 l3_flex_pit =
4224 i40e_find_flex_offset(&pf->l3_flex_pit_list,
4225 src_offset);
4226 if (IS_ERR(l3_flex_pit))
4227 return PTR_ERR(l3_flex_pit);
4228
4229 if (flex_pit) {
4230
4231
4232
4233
4234 if (l3_flex_pit) {
4235 if (l3_flex_pit->pit_index !=
4236 flex_pit->pit_index) {
4237 return -EINVAL;
4238 }
4239 } else {
4240 new_flex_offset = true;
4241 }
4242 } else {
4243 flex_pit = l3_flex_pit;
4244 }
4245 }
4246
4247
4248
4249
4250
4251
4252 if (!flex_pit) {
4253 new_flex_offset = true;
4254 pit_index = i40e_unused_pit_index(pf);
4255 } else {
4256 pit_index = flex_pit->pit_index;
4257 }
4258
4259
4260 new_mask |= i40e_pit_index_to_mask(pit_index);
4261 }
4262
4263
4264
4265
4266
4267 if (new_mask == current_mask && !new_flex_offset)
4268 return 0;
4269
4270 netif_info(pf, drv, vsi->netdev, "Input set change requested for %s flows:\n",
4271 i40e_flow_str(fsp));
4272 i40e_print_input_set(vsi, current_mask, new_mask);
4273 if (new_flex_offset) {
4274 netif_info(pf, drv, vsi->netdev, "FLEX index %d: Offset -> %d",
4275 pit_index, src_offset);
4276 }
4277
4278
4279
4280
4281
4282 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4283 netif_err(pf, drv, vsi->netdev, "Cannot change Flow Director input sets while MFP is enabled\n");
4284 return -EOPNOTSUPP;
4285 }
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296 if (*fdir_filter_count) {
4297 netif_err(pf, drv, vsi->netdev, "Cannot change input set for %s flows until %d preexisting filters are removed\n",
4298 i40e_flow_str(fsp),
4299 *fdir_filter_count);
4300 return -EOPNOTSUPP;
4301 }
4302
4303 i40e_write_fd_input_set(pf, index, new_mask);
4304
4305
4306
4307
4308
4309
4310
4311 if (index == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER)
4312 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4,
4313 new_mask);
4314
4315
4316 if (new_flex_offset) {
4317 err = i40e_add_flex_offset(&pf->l4_flex_pit_list, src_offset,
4318 pit_index);
4319 if (err)
4320 return err;
4321
4322 if (flex_l3) {
4323 err = i40e_add_flex_offset(&pf->l3_flex_pit_list,
4324 src_offset,
4325 pit_index);
4326 if (err)
4327 return err;
4328 }
4329
4330 i40e_reprogram_flex_pit(pf);
4331 }
4332
4333 return 0;
4334}
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346static bool i40e_match_fdir_filter(struct i40e_fdir_filter *a,
4347 struct i40e_fdir_filter *b)
4348{
4349
4350 if (a->dst_ip != b->dst_ip ||
4351 a->src_ip != b->src_ip ||
4352 a->dst_port != b->dst_port ||
4353 a->src_port != b->src_port ||
4354 a->flow_type != b->flow_type ||
4355 a->ip4_proto != b->ip4_proto)
4356 return false;
4357
4358 return true;
4359}
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386static int i40e_disallow_matching_filters(struct i40e_vsi *vsi,
4387 struct i40e_fdir_filter *input)
4388{
4389 struct i40e_pf *pf = vsi->back;
4390 struct i40e_fdir_filter *rule;
4391 struct hlist_node *node2;
4392
4393
4394 hlist_for_each_entry_safe(rule, node2,
4395 &pf->fdir_filter_list, fdir_node) {
4396
4397
4398
4399
4400 if (rule->fd_id == input->fd_id)
4401 continue;
4402
4403
4404
4405
4406 if (i40e_match_fdir_filter(rule, input)) {
4407 dev_warn(&pf->pdev->dev,
4408 "Existing user defined filter %d already matches this flow.\n",
4409 rule->fd_id);
4410 return -EINVAL;
4411 }
4412 }
4413
4414 return 0;
4415}
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi,
4426 struct ethtool_rxnfc *cmd)
4427{
4428 struct i40e_rx_flow_userdef userdef;
4429 struct ethtool_rx_flow_spec *fsp;
4430 struct i40e_fdir_filter *input;
4431 u16 dest_vsi = 0, q_index = 0;
4432 struct i40e_pf *pf;
4433 int ret = -EINVAL;
4434 u8 dest_ctl;
4435
4436 if (!vsi)
4437 return -EINVAL;
4438 pf = vsi->back;
4439
4440 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
4441 return -EOPNOTSUPP;
4442
4443 if (test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
4444 return -ENOSPC;
4445
4446 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
4447 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
4448 return -EBUSY;
4449
4450 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
4451 return -EBUSY;
4452
4453 fsp = (struct ethtool_rx_flow_spec *)&cmd->fs;
4454
4455
4456 if (i40e_parse_rx_flow_user_data(fsp, &userdef))
4457 return -EINVAL;
4458
4459
4460 if (fsp->flow_type & FLOW_MAC_EXT)
4461 return -EINVAL;
4462
4463 ret = i40e_check_fdir_input_set(vsi, fsp, &userdef);
4464 if (ret)
4465 return ret;
4466
4467 if (fsp->location >= (pf->hw.func_caps.fd_filters_best_effort +
4468 pf->hw.func_caps.fd_filters_guaranteed)) {
4469 return -EINVAL;
4470 }
4471
4472
4473
4474
4475 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
4476 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
4477 } else {
4478 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
4479 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
4480
4481 if (!vf) {
4482 if (ring >= vsi->num_queue_pairs)
4483 return -EINVAL;
4484 dest_vsi = vsi->id;
4485 } else {
4486
4487 vf--;
4488
4489 if (vf >= pf->num_alloc_vfs)
4490 return -EINVAL;
4491 if (ring >= pf->vf[vf].num_queue_pairs)
4492 return -EINVAL;
4493 dest_vsi = pf->vf[vf].lan_vsi_id;
4494 }
4495 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
4496 q_index = ring;
4497 }
4498
4499 input = kzalloc(sizeof(*input), GFP_KERNEL);
4500
4501 if (!input)
4502 return -ENOMEM;
4503
4504 input->fd_id = fsp->location;
4505 input->q_index = q_index;
4506 input->dest_vsi = dest_vsi;
4507 input->dest_ctl = dest_ctl;
4508 input->fd_status = I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID;
4509 input->cnt_index = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
4510 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4511 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4512 input->flow_type = fsp->flow_type & ~FLOW_EXT;
4513 input->ip4_proto = fsp->h_u.usr_ip4_spec.proto;
4514
4515
4516
4517
4518 input->dst_port = fsp->h_u.tcp_ip4_spec.psrc;
4519 input->src_port = fsp->h_u.tcp_ip4_spec.pdst;
4520 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4521 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4522
4523 if (userdef.flex_filter) {
4524 input->flex_filter = true;
4525 input->flex_word = cpu_to_be16(userdef.flex_word);
4526 input->flex_offset = userdef.flex_offset;
4527 }
4528
4529
4530 ret = i40e_disallow_matching_filters(vsi, input);
4531 if (ret)
4532 goto free_filter_memory;
4533
4534
4535
4536
4537
4538 i40e_update_ethtool_fdir_entry(vsi, input, fsp->location, NULL);
4539 ret = i40e_add_del_fdir(vsi, input, true);
4540 if (ret)
4541 goto remove_sw_rule;
4542 return 0;
4543
4544remove_sw_rule:
4545 hlist_del(&input->fdir_node);
4546 pf->fdir_pf_active_filters--;
4547free_filter_memory:
4548 kfree(input);
4549 return ret;
4550}
4551
4552
4553
4554
4555
4556
4557
4558
4559static int i40e_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
4560{
4561 struct i40e_netdev_priv *np = netdev_priv(netdev);
4562 struct i40e_vsi *vsi = np->vsi;
4563 struct i40e_pf *pf = vsi->back;
4564 int ret = -EOPNOTSUPP;
4565
4566 switch (cmd->cmd) {
4567 case ETHTOOL_SRXFH:
4568 ret = i40e_set_rss_hash_opt(pf, cmd);
4569 break;
4570 case ETHTOOL_SRXCLSRLINS:
4571 ret = i40e_add_fdir_ethtool(vsi, cmd);
4572 break;
4573 case ETHTOOL_SRXCLSRLDEL:
4574 ret = i40e_del_fdir_entry(vsi, cmd);
4575 break;
4576 default:
4577 break;
4578 }
4579
4580 return ret;
4581}
4582
4583
4584
4585
4586
4587static unsigned int i40e_max_channels(struct i40e_vsi *vsi)
4588{
4589
4590 return vsi->alloc_queue_pairs;
4591}
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603static void i40e_get_channels(struct net_device *dev,
4604 struct ethtool_channels *ch)
4605{
4606 struct i40e_netdev_priv *np = netdev_priv(dev);
4607 struct i40e_vsi *vsi = np->vsi;
4608 struct i40e_pf *pf = vsi->back;
4609
4610
4611 ch->max_combined = i40e_max_channels(vsi);
4612
4613
4614 ch->other_count = (pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0;
4615 ch->max_other = ch->other_count;
4616
4617
4618 ch->combined_count = vsi->num_queue_pairs;
4619}
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629static int i40e_set_channels(struct net_device *dev,
4630 struct ethtool_channels *ch)
4631{
4632 const u8 drop = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
4633 struct i40e_netdev_priv *np = netdev_priv(dev);
4634 unsigned int count = ch->combined_count;
4635 struct i40e_vsi *vsi = np->vsi;
4636 struct i40e_pf *pf = vsi->back;
4637 struct i40e_fdir_filter *rule;
4638 struct hlist_node *node2;
4639 int new_count;
4640 int err = 0;
4641
4642
4643 if (vsi->type != I40E_VSI_MAIN)
4644 return -EINVAL;
4645
4646
4647
4648
4649 if (pf->flags & I40E_FLAG_TC_MQPRIO)
4650 return -EINVAL;
4651
4652
4653 if (!count || ch->rx_count || ch->tx_count)
4654 return -EINVAL;
4655
4656
4657 if (ch->other_count != ((pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0))
4658 return -EINVAL;
4659
4660
4661 if (count > i40e_max_channels(vsi))
4662 return -EINVAL;
4663
4664
4665
4666
4667 hlist_for_each_entry_safe(rule, node2,
4668 &pf->fdir_filter_list, fdir_node) {
4669 if (rule->dest_ctl != drop && count <= rule->q_index) {
4670 dev_warn(&pf->pdev->dev,
4671 "Existing user defined filter %d assigns flow to queue %d\n",
4672 rule->fd_id, rule->q_index);
4673 err = -EINVAL;
4674 }
4675 }
4676
4677 if (err) {
4678 dev_err(&pf->pdev->dev,
4679 "Existing filter rules must be deleted to reduce combined channel count to %d\n",
4680 count);
4681 return err;
4682 }
4683
4684
4685
4686
4687
4688
4689
4690 new_count = i40e_reconfig_rss_queues(pf, count);
4691 if (new_count > 0)
4692 return 0;
4693 else
4694 return -EINVAL;
4695}
4696
4697
4698
4699
4700
4701
4702
4703static u32 i40e_get_rxfh_key_size(struct net_device *netdev)
4704{
4705 return I40E_HKEY_ARRAY_SIZE;
4706}
4707
4708
4709
4710
4711
4712
4713
4714static u32 i40e_get_rxfh_indir_size(struct net_device *netdev)
4715{
4716 return I40E_HLUT_ARRAY_SIZE;
4717}
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729static int i40e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
4730 u8 *hfunc)
4731{
4732 struct i40e_netdev_priv *np = netdev_priv(netdev);
4733 struct i40e_vsi *vsi = np->vsi;
4734 u8 *lut, *seed = NULL;
4735 int ret;
4736 u16 i;
4737
4738 if (hfunc)
4739 *hfunc = ETH_RSS_HASH_TOP;
4740
4741 if (!indir)
4742 return 0;
4743
4744 seed = key;
4745 lut = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
4746 if (!lut)
4747 return -ENOMEM;
4748 ret = i40e_get_rss(vsi, seed, lut, I40E_HLUT_ARRAY_SIZE);
4749 if (ret)
4750 goto out;
4751 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
4752 indir[i] = (u32)(lut[i]);
4753
4754out:
4755 kfree(lut);
4756
4757 return ret;
4758}
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770static int i40e_set_rxfh(struct net_device *netdev, const u32 *indir,
4771 const u8 *key, const u8 hfunc)
4772{
4773 struct i40e_netdev_priv *np = netdev_priv(netdev);
4774 struct i40e_vsi *vsi = np->vsi;
4775 struct i40e_pf *pf = vsi->back;
4776 u8 *seed = NULL;
4777 u16 i;
4778
4779 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
4780 return -EOPNOTSUPP;
4781
4782 if (key) {
4783 if (!vsi->rss_hkey_user) {
4784 vsi->rss_hkey_user = kzalloc(I40E_HKEY_ARRAY_SIZE,
4785 GFP_KERNEL);
4786 if (!vsi->rss_hkey_user)
4787 return -ENOMEM;
4788 }
4789 memcpy(vsi->rss_hkey_user, key, I40E_HKEY_ARRAY_SIZE);
4790 seed = vsi->rss_hkey_user;
4791 }
4792 if (!vsi->rss_lut_user) {
4793 vsi->rss_lut_user = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
4794 if (!vsi->rss_lut_user)
4795 return -ENOMEM;
4796 }
4797
4798
4799 if (indir)
4800 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
4801 vsi->rss_lut_user[i] = (u8)(indir[i]);
4802 else
4803 i40e_fill_rss_lut(pf, vsi->rss_lut_user, I40E_HLUT_ARRAY_SIZE,
4804 vsi->rss_size);
4805
4806 return i40e_config_rss(vsi, seed, vsi->rss_lut_user,
4807 I40E_HLUT_ARRAY_SIZE);
4808}
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820static u32 i40e_get_priv_flags(struct net_device *dev)
4821{
4822 struct i40e_netdev_priv *np = netdev_priv(dev);
4823 struct i40e_vsi *vsi = np->vsi;
4824 struct i40e_pf *pf = vsi->back;
4825 u32 i, j, ret_flags = 0;
4826
4827 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
4828 const struct i40e_priv_flags *priv_flags;
4829
4830 priv_flags = &i40e_gstrings_priv_flags[i];
4831
4832 if (priv_flags->flag & pf->flags)
4833 ret_flags |= BIT(i);
4834 }
4835
4836 if (pf->hw.pf_id != 0)
4837 return ret_flags;
4838
4839 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
4840 const struct i40e_priv_flags *priv_flags;
4841
4842 priv_flags = &i40e_gl_gstrings_priv_flags[j];
4843
4844 if (priv_flags->flag & pf->flags)
4845 ret_flags |= BIT(i + j);
4846 }
4847
4848 return ret_flags;
4849}
4850
4851
4852
4853
4854
4855
4856static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
4857{
4858 struct i40e_netdev_priv *np = netdev_priv(dev);
4859 u64 orig_flags, new_flags, changed_flags;
4860 enum i40e_admin_queue_err adq_err;
4861 struct i40e_vsi *vsi = np->vsi;
4862 struct i40e_pf *pf = vsi->back;
4863 bool is_reset_needed;
4864 i40e_status status;
4865 u32 i, j;
4866
4867 orig_flags = READ_ONCE(pf->flags);
4868 new_flags = orig_flags;
4869
4870 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
4871 const struct i40e_priv_flags *priv_flags;
4872
4873 priv_flags = &i40e_gstrings_priv_flags[i];
4874
4875 if (flags & BIT(i))
4876 new_flags |= priv_flags->flag;
4877 else
4878 new_flags &= ~(priv_flags->flag);
4879
4880
4881 if (priv_flags->read_only &&
4882 ((orig_flags ^ new_flags) & ~BIT(i)))
4883 return -EOPNOTSUPP;
4884 }
4885
4886 if (pf->hw.pf_id != 0)
4887 goto flags_complete;
4888
4889 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
4890 const struct i40e_priv_flags *priv_flags;
4891
4892 priv_flags = &i40e_gl_gstrings_priv_flags[j];
4893
4894 if (flags & BIT(i + j))
4895 new_flags |= priv_flags->flag;
4896 else
4897 new_flags &= ~(priv_flags->flag);
4898
4899
4900 if (priv_flags->read_only &&
4901 ((orig_flags ^ new_flags) & ~BIT(i)))
4902 return -EOPNOTSUPP;
4903 }
4904
4905flags_complete:
4906 changed_flags = orig_flags ^ new_flags;
4907
4908 is_reset_needed = !!(changed_flags & (I40E_FLAG_VEB_STATS_ENABLED |
4909 I40E_FLAG_LEGACY_RX | I40E_FLAG_SOURCE_PRUNING_DISABLED |
4910 I40E_FLAG_DISABLE_FW_LLDP));
4911
4912
4913
4914
4915
4916
4917 if ((new_flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) &&
4918 !(pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE))
4919 return -EOPNOTSUPP;
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
4930 if (!(pf->hw.flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) {
4931 dev_warn(&pf->pdev->dev,
4932 "Device does not support changing FW LLDP\n");
4933 return -EOPNOTSUPP;
4934 }
4935 }
4936
4937 if (((changed_flags & I40E_FLAG_RS_FEC) ||
4938 (changed_flags & I40E_FLAG_BASE_R_FEC)) &&
4939 pf->hw.device_id != I40E_DEV_ID_25G_SFP28 &&
4940 pf->hw.device_id != I40E_DEV_ID_25G_B) {
4941 dev_warn(&pf->pdev->dev,
4942 "Device does not support changing FEC configuration\n");
4943 return -EOPNOTSUPP;
4944 }
4945
4946
4947
4948
4949
4950
4951
4952 if ((changed_flags & I40E_FLAG_FD_ATR_ENABLED) &&
4953 !(new_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4954 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
4955 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
4956 }
4957
4958 if (changed_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT) {
4959 u16 sw_flags = 0, valid_flags = 0;
4960 int ret;
4961
4962 if (!(new_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
4963 sw_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
4964 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
4965 ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags,
4966 0, NULL);
4967 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
4968 dev_info(&pf->pdev->dev,
4969 "couldn't set switch config bits, err %s aq_err %s\n",
4970 i40e_stat_str(&pf->hw, ret),
4971 i40e_aq_str(&pf->hw,
4972 pf->hw.aq.asq_last_status));
4973
4974 }
4975 }
4976
4977 if ((changed_flags & I40E_FLAG_RS_FEC) ||
4978 (changed_flags & I40E_FLAG_BASE_R_FEC)) {
4979 u8 fec_cfg = 0;
4980
4981 if (new_flags & I40E_FLAG_RS_FEC &&
4982 new_flags & I40E_FLAG_BASE_R_FEC) {
4983 fec_cfg = I40E_AQ_SET_FEC_AUTO;
4984 } else if (new_flags & I40E_FLAG_RS_FEC) {
4985 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
4986 I40E_AQ_SET_FEC_ABILITY_RS);
4987 } else if (new_flags & I40E_FLAG_BASE_R_FEC) {
4988 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
4989 I40E_AQ_SET_FEC_ABILITY_KR);
4990 }
4991 if (i40e_set_fec_cfg(dev, fec_cfg))
4992 dev_warn(&pf->pdev->dev, "Cannot change FEC config\n");
4993 }
4994
4995 if ((changed_flags & new_flags &
4996 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &&
4997 (new_flags & I40E_FLAG_MFP_ENABLED))
4998 dev_warn(&pf->pdev->dev,
4999 "Turning on link-down-on-close flag may affect other partitions\n");
5000
5001 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5002 if (new_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5003 struct i40e_dcbx_config *dcbcfg;
5004
5005 i40e_aq_stop_lldp(&pf->hw, true, false, NULL);
5006 i40e_aq_set_dcb_parameters(&pf->hw, true, NULL);
5007
5008 dcbcfg = &pf->hw.local_dcbx_config;
5009 dcbcfg->etscfg.willing = 1;
5010 dcbcfg->etscfg.maxtcs = 0;
5011 dcbcfg->etscfg.tcbwtable[0] = 100;
5012 for (i = 1; i < I40E_MAX_TRAFFIC_CLASS; i++)
5013 dcbcfg->etscfg.tcbwtable[i] = 0;
5014 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
5015 dcbcfg->etscfg.prioritytable[i] = 0;
5016 dcbcfg->etscfg.tsatable[0] = I40E_IEEE_TSA_ETS;
5017 dcbcfg->pfc.willing = 1;
5018 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
5019 } else {
5020 status = i40e_aq_start_lldp(&pf->hw, false, NULL);
5021 if (status) {
5022 adq_err = pf->hw.aq.asq_last_status;
5023 switch (adq_err) {
5024 case I40E_AQ_RC_EEXIST:
5025 dev_warn(&pf->pdev->dev,
5026 "FW LLDP agent is already running\n");
5027 is_reset_needed = false;
5028 break;
5029 case I40E_AQ_RC_EPERM:
5030 dev_warn(&pf->pdev->dev,
5031 "Device configuration forbids SW from starting the LLDP agent.\n");
5032 return -EINVAL;
5033 default:
5034 dev_warn(&pf->pdev->dev,
5035 "Starting FW LLDP agent failed: error: %s, %s\n",
5036 i40e_stat_str(&pf->hw,
5037 status),
5038 i40e_aq_str(&pf->hw,
5039 adq_err));
5040 return -EINVAL;
5041 }
5042 }
5043 }
5044 }
5045
5046
5047
5048
5049
5050
5051 pf->flags = new_flags;
5052
5053
5054
5055
5056 if (is_reset_needed)
5057 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
5058
5059 return 0;
5060}
5061
5062
5063
5064
5065
5066
5067static int i40e_get_module_info(struct net_device *netdev,
5068 struct ethtool_modinfo *modinfo)
5069{
5070 struct i40e_netdev_priv *np = netdev_priv(netdev);
5071 struct i40e_vsi *vsi = np->vsi;
5072 struct i40e_pf *pf = vsi->back;
5073 struct i40e_hw *hw = &pf->hw;
5074 u32 sff8472_comp = 0;
5075 u32 sff8472_swap = 0;
5076 u32 sff8636_rev = 0;
5077 i40e_status status;
5078 u32 type = 0;
5079
5080
5081 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
5082 netdev_err(vsi->netdev, "Module EEPROM memory read not supported. Please update the NVM image.\n");
5083 return -EINVAL;
5084 }
5085
5086 status = i40e_update_link_info(hw);
5087 if (status)
5088 return -EIO;
5089
5090 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
5091 netdev_err(vsi->netdev, "Cannot read module EEPROM memory. No module connected.\n");
5092 return -EINVAL;
5093 }
5094
5095 type = hw->phy.link_info.module_type[0];
5096
5097 switch (type) {
5098 case I40E_MODULE_TYPE_SFP:
5099 status = i40e_aq_get_phy_register(hw,
5100 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5101 I40E_I2C_EEPROM_DEV_ADDR,
5102 I40E_MODULE_SFF_8472_COMP,
5103 &sff8472_comp, NULL);
5104 if (status)
5105 return -EIO;
5106
5107 status = i40e_aq_get_phy_register(hw,
5108 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5109 I40E_I2C_EEPROM_DEV_ADDR,
5110 I40E_MODULE_SFF_8472_SWAP,
5111 &sff8472_swap, NULL);
5112 if (status)
5113 return -EIO;
5114
5115
5116
5117
5118 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
5119 netdev_warn(vsi->netdev, "Module address swap to access page 0xA2 is not supported.\n");
5120 modinfo->type = ETH_MODULE_SFF_8079;
5121 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5122 } else if (sff8472_comp == 0x00) {
5123
5124 modinfo->type = ETH_MODULE_SFF_8079;
5125 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5126 } else {
5127 modinfo->type = ETH_MODULE_SFF_8472;
5128 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
5129 }
5130 break;
5131 case I40E_MODULE_TYPE_QSFP_PLUS:
5132
5133 status = i40e_aq_get_phy_register(hw,
5134 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5135 0,
5136 I40E_MODULE_REVISION_ADDR,
5137 &sff8636_rev, NULL);
5138 if (status)
5139 return -EIO;
5140
5141 if (sff8636_rev > 0x02) {
5142
5143 modinfo->type = ETH_MODULE_SFF_8636;
5144 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5145 } else {
5146 modinfo->type = ETH_MODULE_SFF_8436;
5147 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5148 }
5149 break;
5150 case I40E_MODULE_TYPE_QSFP28:
5151 modinfo->type = ETH_MODULE_SFF_8636;
5152 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5153 break;
5154 default:
5155 netdev_err(vsi->netdev, "Module type unrecognized\n");
5156 return -EINVAL;
5157 }
5158 return 0;
5159}
5160
5161
5162
5163
5164
5165
5166
5167static int i40e_get_module_eeprom(struct net_device *netdev,
5168 struct ethtool_eeprom *ee,
5169 u8 *data)
5170{
5171 struct i40e_netdev_priv *np = netdev_priv(netdev);
5172 struct i40e_vsi *vsi = np->vsi;
5173 struct i40e_pf *pf = vsi->back;
5174 struct i40e_hw *hw = &pf->hw;
5175 bool is_sfp = false;
5176 i40e_status status;
5177 u32 value = 0;
5178 int i;
5179
5180 if (!ee || !ee->len || !data)
5181 return -EINVAL;
5182
5183 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
5184 is_sfp = true;
5185
5186 for (i = 0; i < ee->len; i++) {
5187 u32 offset = i + ee->offset;
5188 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
5189
5190
5191 if (is_sfp) {
5192 if (offset >= ETH_MODULE_SFF_8079_LEN) {
5193 offset -= ETH_MODULE_SFF_8079_LEN;
5194 addr = I40E_I2C_EEPROM_DEV_ADDR2;
5195 }
5196 } else {
5197 while (offset >= ETH_MODULE_SFF_8436_LEN) {
5198
5199 offset -= ETH_MODULE_SFF_8436_LEN / 2;
5200 addr++;
5201 }
5202 }
5203
5204 status = i40e_aq_get_phy_register(hw,
5205 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5206 addr, offset, &value, NULL);
5207 if (status)
5208 return -EIO;
5209 data[i] = value;
5210 }
5211 return 0;
5212}
5213
5214static int i40e_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
5215{
5216 return -EOPNOTSUPP;
5217}
5218
5219static int i40e_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
5220{
5221 return -EOPNOTSUPP;
5222}
5223
5224static const struct ethtool_ops i40e_ethtool_recovery_mode_ops = {
5225 .set_eeprom = i40e_set_eeprom,
5226 .get_eeprom_len = i40e_get_eeprom_len,
5227 .get_eeprom = i40e_get_eeprom,
5228};
5229
5230static const struct ethtool_ops i40e_ethtool_ops = {
5231 .get_drvinfo = i40e_get_drvinfo,
5232 .get_regs_len = i40e_get_regs_len,
5233 .get_regs = i40e_get_regs,
5234 .nway_reset = i40e_nway_reset,
5235 .get_link = ethtool_op_get_link,
5236 .get_wol = i40e_get_wol,
5237 .set_wol = i40e_set_wol,
5238 .set_eeprom = i40e_set_eeprom,
5239 .get_eeprom_len = i40e_get_eeprom_len,
5240 .get_eeprom = i40e_get_eeprom,
5241 .get_ringparam = i40e_get_ringparam,
5242 .set_ringparam = i40e_set_ringparam,
5243 .get_pauseparam = i40e_get_pauseparam,
5244 .set_pauseparam = i40e_set_pauseparam,
5245 .get_msglevel = i40e_get_msglevel,
5246 .set_msglevel = i40e_set_msglevel,
5247 .get_rxnfc = i40e_get_rxnfc,
5248 .set_rxnfc = i40e_set_rxnfc,
5249 .self_test = i40e_diag_test,
5250 .get_strings = i40e_get_strings,
5251 .get_eee = i40e_get_eee,
5252 .set_eee = i40e_set_eee,
5253 .set_phys_id = i40e_set_phys_id,
5254 .get_sset_count = i40e_get_sset_count,
5255 .get_ethtool_stats = i40e_get_ethtool_stats,
5256 .get_coalesce = i40e_get_coalesce,
5257 .set_coalesce = i40e_set_coalesce,
5258 .get_rxfh_key_size = i40e_get_rxfh_key_size,
5259 .get_rxfh_indir_size = i40e_get_rxfh_indir_size,
5260 .get_rxfh = i40e_get_rxfh,
5261 .set_rxfh = i40e_set_rxfh,
5262 .get_channels = i40e_get_channels,
5263 .set_channels = i40e_set_channels,
5264 .get_module_info = i40e_get_module_info,
5265 .get_module_eeprom = i40e_get_module_eeprom,
5266 .get_ts_info = i40e_get_ts_info,
5267 .get_priv_flags = i40e_get_priv_flags,
5268 .set_priv_flags = i40e_set_priv_flags,
5269 .get_per_queue_coalesce = i40e_get_per_queue_coalesce,
5270 .set_per_queue_coalesce = i40e_set_per_queue_coalesce,
5271 .get_link_ksettings = i40e_get_link_ksettings,
5272 .set_link_ksettings = i40e_set_link_ksettings,
5273 .get_fecparam = i40e_get_fec_param,
5274 .set_fecparam = i40e_set_fec_param,
5275 .flash_device = i40e_ddp_flash,
5276};
5277
5278void i40e_set_ethtool_ops(struct net_device *netdev)
5279{
5280 struct i40e_netdev_priv *np = netdev_priv(netdev);
5281 struct i40e_pf *pf = np->vsi->back;
5282
5283 if (!test_bit(__I40E_RECOVERY_MODE, pf->state))
5284 netdev->ethtool_ops = &i40e_ethtool_ops;
5285 else
5286 netdev->ethtool_ops = &i40e_ethtool_recovery_mode_ops;
5287}
5288