1
2
3
4#include "ice.h"
5#include "ice_lib.h"
6#include "ice_dcb_lib.h"
7
8
9
10
11
12
13
14static int ice_setup_rx_ctx(struct ice_ring *ring)
15{
16 struct ice_vsi *vsi = ring->vsi;
17 struct ice_hw *hw = &vsi->back->hw;
18 u32 rxdid = ICE_RXDID_FLEX_NIC;
19 struct ice_rlan_ctx rlan_ctx;
20 u32 regval;
21 u16 pf_q;
22 int err;
23
24
25 pf_q = vsi->rxq_map[ring->q_index];
26
27
28 memset(&rlan_ctx, 0, sizeof(rlan_ctx));
29
30 rlan_ctx.base = ring->dma >> 7;
31
32 rlan_ctx.qlen = ring->count;
33
34
35
36
37 rlan_ctx.dbuf = vsi->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
38
39
40 rlan_ctx.dsize = 1;
41
42
43
44
45 rlan_ctx.crcstrip = 1;
46
47
48 rlan_ctx.l2tsel = 1;
49
50 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;
51 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;
52 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;
53
54
55
56
57
58 rlan_ctx.showiv = 0;
59
60
61
62
63 rlan_ctx.rxmax = min_t(u16, vsi->max_frame,
64 ICE_MAX_CHAINED_RX_BUFS * vsi->rx_buf_len);
65
66
67 rlan_ctx.lrxqthresh = 1;
68
69
70
71
72 if (vsi->type != ICE_VSI_VF) {
73 regval = rd32(hw, QRXFLXP_CNTXT(pf_q));
74 regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
75 QRXFLXP_CNTXT_RXDID_IDX_M;
76
77
78
79
80
81 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
82 QRXFLXP_CNTXT_RXDID_PRIO_M;
83
84 wr32(hw, QRXFLXP_CNTXT(pf_q), regval);
85 }
86
87
88 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);
89 if (err) {
90 dev_err(&vsi->back->pdev->dev,
91 "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",
92 pf_q, err);
93 return -EIO;
94 }
95
96 if (vsi->type == ICE_VSI_VF)
97 return 0;
98
99
100 ring->tail = hw->hw_addr + QRX_TAIL(pf_q);
101 writel(0, ring->tail);
102 ice_alloc_rx_bufs(ring, ICE_DESC_UNUSED(ring));
103
104 return 0;
105}
106
107
108
109
110
111
112
113
114
115static void
116ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
117{
118 struct ice_vsi *vsi = ring->vsi;
119 struct ice_hw *hw = &vsi->back->hw;
120
121 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;
122
123 tlan_ctx->port_num = vsi->port_info->lport;
124
125
126 tlan_ctx->qlen = ring->count;
127
128 ice_set_cgd_num(tlan_ctx, ring);
129
130
131 tlan_ctx->pf_num = hw->pf_id;
132
133
134
135
136
137
138
139 switch (vsi->type) {
140 case ICE_VSI_LB:
141
142 case ICE_VSI_PF:
143 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
144 break;
145 case ICE_VSI_VF:
146
147 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id;
148 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;
149 break;
150 default:
151 return;
152 }
153
154
155 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
156
157 tlan_ctx->tso_ena = ICE_TX_LEGACY;
158 tlan_ctx->tso_qnum = pf_q;
159
160
161
162
163
164 tlan_ctx->legacy_int = ICE_TX_LEGACY;
165}
166
167
168
169
170
171
172
173
174
175
176
177
178static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)
179{
180 int i;
181
182 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {
183 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &
184 QRX_CTRL_QENA_STAT_M))
185 return 0;
186
187 usleep_range(20, 40);
188 }
189
190 return -ETIMEDOUT;
191}
192
193
194
195
196
197
198static int ice_vsi_ctrl_rx_rings(struct ice_vsi *vsi, bool ena)
199{
200 struct ice_pf *pf = vsi->back;
201 struct ice_hw *hw = &pf->hw;
202 int i, ret = 0;
203
204 for (i = 0; i < vsi->num_rxq; i++) {
205 int pf_q = vsi->rxq_map[i];
206 u32 rx_reg;
207
208 rx_reg = rd32(hw, QRX_CTRL(pf_q));
209
210
211 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))
212 continue;
213
214
215 if (ena)
216 rx_reg |= QRX_CTRL_QENA_REQ_M;
217 else
218 rx_reg &= ~QRX_CTRL_QENA_REQ_M;
219 wr32(hw, QRX_CTRL(pf_q), rx_reg);
220
221
222 ret = ice_pf_rxq_wait(pf, pf_q, ena);
223 if (ret) {
224 dev_err(&pf->pdev->dev,
225 "VSI idx %d Rx ring %d %sable timeout\n",
226 vsi->idx, pf_q, (ena ? "en" : "dis"));
227 break;
228 }
229 }
230
231 return ret;
232}
233
234
235
236
237
238
239
240
241static int ice_vsi_alloc_arrays(struct ice_vsi *vsi)
242{
243 struct ice_pf *pf = vsi->back;
244
245
246 vsi->tx_rings = devm_kcalloc(&pf->pdev->dev, vsi->alloc_txq,
247 sizeof(*vsi->tx_rings), GFP_KERNEL);
248 if (!vsi->tx_rings)
249 goto err_txrings;
250
251 vsi->rx_rings = devm_kcalloc(&pf->pdev->dev, vsi->alloc_rxq,
252 sizeof(*vsi->rx_rings), GFP_KERNEL);
253 if (!vsi->rx_rings)
254 goto err_rxrings;
255
256
257 if (vsi->type == ICE_VSI_LB)
258 return 0;
259
260
261 vsi->q_vectors = devm_kcalloc(&pf->pdev->dev, vsi->num_q_vectors,
262 sizeof(*vsi->q_vectors), GFP_KERNEL);
263 if (!vsi->q_vectors)
264 goto err_vectors;
265
266 return 0;
267
268err_vectors:
269 devm_kfree(&pf->pdev->dev, vsi->rx_rings);
270err_rxrings:
271 devm_kfree(&pf->pdev->dev, vsi->tx_rings);
272err_txrings:
273 return -ENOMEM;
274}
275
276
277
278
279
280static void ice_vsi_set_num_desc(struct ice_vsi *vsi)
281{
282 switch (vsi->type) {
283 case ICE_VSI_PF:
284
285 case ICE_VSI_LB:
286 vsi->num_rx_desc = ICE_DFLT_NUM_RX_DESC;
287 vsi->num_tx_desc = ICE_DFLT_NUM_TX_DESC;
288 break;
289 default:
290 dev_dbg(&vsi->back->pdev->dev,
291 "Not setting number of Tx/Rx descriptors for VSI type %d\n",
292 vsi->type);
293 break;
294 }
295}
296
297
298
299
300
301
302
303
304static void ice_vsi_set_num_qs(struct ice_vsi *vsi, u16 vf_id)
305{
306 struct ice_pf *pf = vsi->back;
307 struct ice_vf *vf = NULL;
308
309 if (vsi->type == ICE_VSI_VF)
310 vsi->vf_id = vf_id;
311
312 switch (vsi->type) {
313 case ICE_VSI_PF:
314 vsi->alloc_txq = pf->num_lan_tx;
315 vsi->alloc_rxq = pf->num_lan_rx;
316 vsi->num_q_vectors = max_t(int, pf->num_lan_rx, pf->num_lan_tx);
317 break;
318 case ICE_VSI_VF:
319 vf = &pf->vf[vsi->vf_id];
320 vsi->alloc_txq = vf->num_vf_qs;
321 vsi->alloc_rxq = vf->num_vf_qs;
322
323
324
325
326
327 vsi->num_q_vectors = pf->num_vf_msix - ICE_NONQ_VECS_VF;
328 break;
329 case ICE_VSI_LB:
330 vsi->alloc_txq = 1;
331 vsi->alloc_rxq = 1;
332 break;
333 default:
334 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n", vsi->type);
335 break;
336 }
337
338 ice_vsi_set_num_desc(vsi);
339}
340
341
342
343
344
345
346
347
348
349
350static int ice_get_free_slot(void *array, int size, int curr)
351{
352 int **tmp_array = (int **)array;
353 int next;
354
355 if (curr < (size - 1) && !tmp_array[curr + 1]) {
356 next = curr + 1;
357 } else {
358 int i = 0;
359
360 while ((i < size) && (tmp_array[i]))
361 i++;
362 if (i == size)
363 next = ICE_NO_VSI;
364 else
365 next = i;
366 }
367 return next;
368}
369
370
371
372
373
374void ice_vsi_delete(struct ice_vsi *vsi)
375{
376 struct ice_pf *pf = vsi->back;
377 struct ice_vsi_ctx *ctxt;
378 enum ice_status status;
379
380 ctxt = devm_kzalloc(&pf->pdev->dev, sizeof(*ctxt), GFP_KERNEL);
381 if (!ctxt)
382 return;
383
384 if (vsi->type == ICE_VSI_VF)
385 ctxt->vf_num = vsi->vf_id;
386 ctxt->vsi_num = vsi->vsi_num;
387
388 memcpy(&ctxt->info, &vsi->info, sizeof(ctxt->info));
389
390 status = ice_free_vsi(&pf->hw, vsi->idx, ctxt, false, NULL);
391 if (status)
392 dev_err(&pf->pdev->dev, "Failed to delete VSI %i in FW\n",
393 vsi->vsi_num);
394
395 devm_kfree(&pf->pdev->dev, ctxt);
396}
397
398
399
400
401
402static void ice_vsi_free_arrays(struct ice_vsi *vsi)
403{
404 struct ice_pf *pf = vsi->back;
405
406
407 if (vsi->q_vectors) {
408 devm_kfree(&pf->pdev->dev, vsi->q_vectors);
409 vsi->q_vectors = NULL;
410 }
411 if (vsi->tx_rings) {
412 devm_kfree(&pf->pdev->dev, vsi->tx_rings);
413 vsi->tx_rings = NULL;
414 }
415 if (vsi->rx_rings) {
416 devm_kfree(&pf->pdev->dev, vsi->rx_rings);
417 vsi->rx_rings = NULL;
418 }
419}
420
421
422
423
424
425
426
427
428
429
430int ice_vsi_clear(struct ice_vsi *vsi)
431{
432 struct ice_pf *pf = NULL;
433
434 if (!vsi)
435 return 0;
436
437 if (!vsi->back)
438 return -EINVAL;
439
440 pf = vsi->back;
441
442 if (!pf->vsi[vsi->idx] || pf->vsi[vsi->idx] != vsi) {
443 dev_dbg(&pf->pdev->dev, "vsi does not exist at pf->vsi[%d]\n",
444 vsi->idx);
445 return -EINVAL;
446 }
447
448 mutex_lock(&pf->sw_mutex);
449
450
451 pf->vsi[vsi->idx] = NULL;
452 if (vsi->idx < pf->next_vsi)
453 pf->next_vsi = vsi->idx;
454
455 ice_vsi_free_arrays(vsi);
456 mutex_unlock(&pf->sw_mutex);
457 devm_kfree(&pf->pdev->dev, vsi);
458
459 return 0;
460}
461
462
463
464
465
466
467static irqreturn_t ice_msix_clean_rings(int __always_unused irq, void *data)
468{
469 struct ice_q_vector *q_vector = (struct ice_q_vector *)data;
470
471 if (!q_vector->tx.ring && !q_vector->rx.ring)
472 return IRQ_HANDLED;
473
474 napi_schedule(&q_vector->napi);
475
476 return IRQ_HANDLED;
477}
478
479
480
481
482
483
484
485
486
487static struct ice_vsi *
488ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type type, u16 vf_id)
489{
490 struct ice_vsi *vsi = NULL;
491
492
493 mutex_lock(&pf->sw_mutex);
494
495
496
497
498
499 if (pf->next_vsi == ICE_NO_VSI) {
500 dev_dbg(&pf->pdev->dev, "out of VSI slots!\n");
501 goto unlock_pf;
502 }
503
504 vsi = devm_kzalloc(&pf->pdev->dev, sizeof(*vsi), GFP_KERNEL);
505 if (!vsi)
506 goto unlock_pf;
507
508 vsi->type = type;
509 vsi->back = pf;
510 set_bit(__ICE_DOWN, vsi->state);
511 vsi->idx = pf->next_vsi;
512 vsi->work_lmt = ICE_DFLT_IRQ_WORK;
513
514 if (type == ICE_VSI_VF)
515 ice_vsi_set_num_qs(vsi, vf_id);
516 else
517 ice_vsi_set_num_qs(vsi, ICE_INVAL_VFID);
518
519 switch (vsi->type) {
520 case ICE_VSI_PF:
521 if (ice_vsi_alloc_arrays(vsi))
522 goto err_rings;
523
524
525 vsi->irq_handler = ice_msix_clean_rings;
526 break;
527 case ICE_VSI_VF:
528 if (ice_vsi_alloc_arrays(vsi))
529 goto err_rings;
530 break;
531 case ICE_VSI_LB:
532 if (ice_vsi_alloc_arrays(vsi))
533 goto err_rings;
534 break;
535 default:
536 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n", vsi->type);
537 goto unlock_pf;
538 }
539
540
541 pf->vsi[pf->next_vsi] = vsi;
542
543
544 pf->next_vsi = ice_get_free_slot(pf->vsi, pf->num_alloc_vsi,
545 pf->next_vsi);
546 goto unlock_pf;
547
548err_rings:
549 devm_kfree(&pf->pdev->dev, vsi);
550 vsi = NULL;
551unlock_pf:
552 mutex_unlock(&pf->sw_mutex);
553 return vsi;
554}
555
556
557
558
559
560
561
562static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)
563{
564 int offset, i;
565
566 mutex_lock(qs_cfg->qs_mutex);
567 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,
568 0, qs_cfg->q_count, 0);
569 if (offset >= qs_cfg->pf_map_size) {
570 mutex_unlock(qs_cfg->qs_mutex);
571 return -ENOMEM;
572 }
573
574 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);
575 for (i = 0; i < qs_cfg->q_count; i++)
576 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = i + offset;
577 mutex_unlock(qs_cfg->qs_mutex);
578
579 return 0;
580}
581
582
583
584
585
586
587
588static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)
589{
590 int i, index = 0;
591
592 mutex_lock(qs_cfg->qs_mutex);
593 for (i = 0; i < qs_cfg->q_count; i++) {
594 index = find_next_zero_bit(qs_cfg->pf_map,
595 qs_cfg->pf_map_size, index);
596 if (index >= qs_cfg->pf_map_size)
597 goto err_scatter;
598 set_bit(index, qs_cfg->pf_map);
599 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = index;
600 }
601 mutex_unlock(qs_cfg->qs_mutex);
602
603 return 0;
604err_scatter:
605 for (index = 0; index < i; index++) {
606 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);
607 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;
608 }
609 mutex_unlock(qs_cfg->qs_mutex);
610
611 return -ENOMEM;
612}
613
614
615
616
617
618
619
620
621
622
623static int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)
624{
625 int ret = 0;
626
627 ret = __ice_vsi_get_qs_contig(qs_cfg);
628 if (ret) {
629
630 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;
631 qs_cfg->q_count = min_t(u16, qs_cfg->q_count,
632 qs_cfg->scatter_count);
633 ret = __ice_vsi_get_qs_sc(qs_cfg);
634 }
635 return ret;
636}
637
638
639
640
641
642
643
644static int ice_vsi_get_qs(struct ice_vsi *vsi)
645{
646 struct ice_pf *pf = vsi->back;
647 struct ice_qs_cfg tx_qs_cfg = {
648 .qs_mutex = &pf->avail_q_mutex,
649 .pf_map = pf->avail_txqs,
650 .pf_map_size = ICE_MAX_TXQS,
651 .q_count = vsi->alloc_txq,
652 .scatter_count = ICE_MAX_SCATTER_TXQS,
653 .vsi_map = vsi->txq_map,
654 .vsi_map_offset = 0,
655 .mapping_mode = vsi->tx_mapping_mode
656 };
657 struct ice_qs_cfg rx_qs_cfg = {
658 .qs_mutex = &pf->avail_q_mutex,
659 .pf_map = pf->avail_rxqs,
660 .pf_map_size = ICE_MAX_RXQS,
661 .q_count = vsi->alloc_rxq,
662 .scatter_count = ICE_MAX_SCATTER_RXQS,
663 .vsi_map = vsi->rxq_map,
664 .vsi_map_offset = 0,
665 .mapping_mode = vsi->rx_mapping_mode
666 };
667 int ret = 0;
668
669 vsi->tx_mapping_mode = ICE_VSI_MAP_CONTIG;
670 vsi->rx_mapping_mode = ICE_VSI_MAP_CONTIG;
671
672 ret = __ice_vsi_get_qs(&tx_qs_cfg);
673 if (!ret)
674 ret = __ice_vsi_get_qs(&rx_qs_cfg);
675
676 return ret;
677}
678
679
680
681
682
683void ice_vsi_put_qs(struct ice_vsi *vsi)
684{
685 struct ice_pf *pf = vsi->back;
686 int i;
687
688 mutex_lock(&pf->avail_q_mutex);
689
690 for (i = 0; i < vsi->alloc_txq; i++) {
691 clear_bit(vsi->txq_map[i], pf->avail_txqs);
692 vsi->txq_map[i] = ICE_INVAL_Q_INDEX;
693 }
694
695 for (i = 0; i < vsi->alloc_rxq; i++) {
696 clear_bit(vsi->rxq_map[i], pf->avail_rxqs);
697 vsi->rxq_map[i] = ICE_INVAL_Q_INDEX;
698 }
699
700 mutex_unlock(&pf->avail_q_mutex);
701}
702
703
704
705
706
707static void ice_rss_clean(struct ice_vsi *vsi)
708{
709 struct ice_pf *pf;
710
711 pf = vsi->back;
712
713 if (vsi->rss_hkey_user)
714 devm_kfree(&pf->pdev->dev, vsi->rss_hkey_user);
715 if (vsi->rss_lut_user)
716 devm_kfree(&pf->pdev->dev, vsi->rss_lut_user);
717}
718
719
720
721
722
723static void ice_vsi_set_rss_params(struct ice_vsi *vsi)
724{
725 struct ice_hw_common_caps *cap;
726 struct ice_pf *pf = vsi->back;
727
728 if (!test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
729 vsi->rss_size = 1;
730 return;
731 }
732
733 cap = &pf->hw.func_caps.common_cap;
734 switch (vsi->type) {
735 case ICE_VSI_PF:
736
737 vsi->rss_table_size = cap->rss_table_size;
738 vsi->rss_size = min_t(int, num_online_cpus(),
739 BIT(cap->rss_table_entry_width));
740 vsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
741 break;
742 case ICE_VSI_VF:
743
744
745
746 vsi->rss_table_size = ICE_VSIQF_HLUT_ARRAY_SIZE;
747 vsi->rss_size = min_t(int, num_online_cpus(),
748 BIT(cap->rss_table_entry_width));
749 vsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI;
750 break;
751 case ICE_VSI_LB:
752 break;
753 default:
754 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n",
755 vsi->type);
756 break;
757 }
758}
759
760
761
762
763
764
765
766static void ice_set_dflt_vsi_ctx(struct ice_vsi_ctx *ctxt)
767{
768 u32 table = 0;
769
770 memset(&ctxt->info, 0, sizeof(ctxt->info));
771
772 ctxt->alloc_from_pool = true;
773
774 ctxt->info.sw_flags = ICE_AQ_VSI_SW_FLAG_SRC_PRUNE;
775
776 ctxt->info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
777
778
779
780
781 ctxt->info.vlan_flags = ((ICE_AQ_VSI_VLAN_MODE_ALL &
782 ICE_AQ_VSI_VLAN_MODE_M) >>
783 ICE_AQ_VSI_VLAN_MODE_S);
784
785 table |= ICE_UP_TABLE_TRANSLATE(0, 0);
786 table |= ICE_UP_TABLE_TRANSLATE(1, 1);
787 table |= ICE_UP_TABLE_TRANSLATE(2, 2);
788 table |= ICE_UP_TABLE_TRANSLATE(3, 3);
789 table |= ICE_UP_TABLE_TRANSLATE(4, 4);
790 table |= ICE_UP_TABLE_TRANSLATE(5, 5);
791 table |= ICE_UP_TABLE_TRANSLATE(6, 6);
792 table |= ICE_UP_TABLE_TRANSLATE(7, 7);
793 ctxt->info.ingress_table = cpu_to_le32(table);
794 ctxt->info.egress_table = cpu_to_le32(table);
795
796 ctxt->info.outer_up_table = cpu_to_le32(table);
797
798}
799
800
801
802
803
804
805static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
806{
807 u16 offset = 0, qmap = 0, tx_count = 0;
808 u16 qcount_tx = vsi->alloc_txq;
809 u16 qcount_rx = vsi->alloc_rxq;
810 u16 tx_numq_tc, rx_numq_tc;
811 u16 pow = 0, max_rss = 0;
812 bool ena_tc0 = false;
813 u8 netdev_tc = 0;
814 int i;
815
816
817 if (vsi->tc_cfg.numtc) {
818 if (!(vsi->tc_cfg.ena_tc & BIT(0)))
819 ena_tc0 = true;
820 } else {
821 ena_tc0 = true;
822 }
823
824 if (ena_tc0) {
825 vsi->tc_cfg.numtc++;
826 vsi->tc_cfg.ena_tc |= 1;
827 }
828
829 rx_numq_tc = qcount_rx / vsi->tc_cfg.numtc;
830 if (!rx_numq_tc)
831 rx_numq_tc = 1;
832 tx_numq_tc = qcount_tx / vsi->tc_cfg.numtc;
833 if (!tx_numq_tc)
834 tx_numq_tc = 1;
835
836
837
838
839
840
841
842
843
844
845
846
847
848 qcount_rx = rx_numq_tc;
849
850
851 if (test_bit(ICE_FLAG_RSS_ENA, vsi->back->flags)) {
852 if (vsi->type == ICE_VSI_PF || vsi->type == ICE_VSI_VF) {
853 if (vsi->type == ICE_VSI_PF)
854 max_rss = ICE_MAX_LG_RSS_QS;
855 else
856 max_rss = ICE_MAX_SMALL_RSS_QS;
857 qcount_rx = min_t(int, rx_numq_tc, max_rss);
858 qcount_rx = min_t(int, qcount_rx, vsi->rss_size);
859 }
860 }
861
862
863 pow = order_base_2(qcount_rx);
864
865 ice_for_each_traffic_class(i) {
866 if (!(vsi->tc_cfg.ena_tc & BIT(i))) {
867
868 vsi->tc_cfg.tc_info[i].qoffset = 0;
869 vsi->tc_cfg.tc_info[i].qcount_rx = 1;
870 vsi->tc_cfg.tc_info[i].qcount_tx = 1;
871 vsi->tc_cfg.tc_info[i].netdev_tc = 0;
872 ctxt->info.tc_mapping[i] = 0;
873 continue;
874 }
875
876
877 vsi->tc_cfg.tc_info[i].qoffset = offset;
878 vsi->tc_cfg.tc_info[i].qcount_rx = qcount_rx;
879 vsi->tc_cfg.tc_info[i].qcount_tx = tx_numq_tc;
880 vsi->tc_cfg.tc_info[i].netdev_tc = netdev_tc++;
881
882 qmap = ((offset << ICE_AQ_VSI_TC_Q_OFFSET_S) &
883 ICE_AQ_VSI_TC_Q_OFFSET_M) |
884 ((pow << ICE_AQ_VSI_TC_Q_NUM_S) &
885 ICE_AQ_VSI_TC_Q_NUM_M);
886 offset += qcount_rx;
887 tx_count += tx_numq_tc;
888 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
889 }
890
891
892
893
894
895
896
897 if (offset)
898 vsi->num_rxq = offset;
899 else
900 vsi->num_rxq = qcount_rx;
901
902 vsi->num_txq = tx_count;
903
904 if (vsi->type == ICE_VSI_VF && vsi->num_txq != vsi->num_rxq) {
905 dev_dbg(&vsi->back->pdev->dev, "VF VSI should have same number of Tx and Rx queues. Hence making them equal\n");
906
907
908
909 vsi->num_txq = vsi->num_rxq;
910 }
911
912
913 ctxt->info.mapping_flags |= cpu_to_le16(ICE_AQ_VSI_Q_MAP_CONTIG);
914
915
916
917
918 ctxt->info.q_mapping[0] = cpu_to_le16(vsi->rxq_map[0]);
919 ctxt->info.q_mapping[1] = cpu_to_le16(vsi->num_rxq);
920}
921
922
923
924
925
926
927static void ice_set_rss_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)
928{
929 u8 lut_type, hash_type;
930 struct ice_pf *pf;
931
932 pf = vsi->back;
933
934 switch (vsi->type) {
935 case ICE_VSI_PF:
936
937 lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF;
938 hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
939 break;
940 case ICE_VSI_VF:
941
942 lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI;
943 hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
944 break;
945 case ICE_VSI_LB:
946 dev_dbg(&pf->pdev->dev, "Unsupported VSI type %d\n", vsi->type);
947 return;
948 default:
949 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n", vsi->type);
950 return;
951 }
952
953 ctxt->info.q_opt_rss = ((lut_type << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) &
954 ICE_AQ_VSI_Q_OPT_RSS_LUT_M) |
955 ((hash_type << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) &
956 ICE_AQ_VSI_Q_OPT_RSS_HASH_M);
957}
958
959
960
961
962
963
964
965
966static int ice_vsi_init(struct ice_vsi *vsi)
967{
968 struct ice_pf *pf = vsi->back;
969 struct ice_hw *hw = &pf->hw;
970 struct ice_vsi_ctx *ctxt;
971 int ret = 0;
972
973 ctxt = devm_kzalloc(&pf->pdev->dev, sizeof(*ctxt), GFP_KERNEL);
974 if (!ctxt)
975 return -ENOMEM;
976
977 ctxt->info = vsi->info;
978 switch (vsi->type) {
979 case ICE_VSI_LB:
980
981 case ICE_VSI_PF:
982 ctxt->flags = ICE_AQ_VSI_TYPE_PF;
983 break;
984 case ICE_VSI_VF:
985 ctxt->flags = ICE_AQ_VSI_TYPE_VF;
986
987 ctxt->vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
988 break;
989 default:
990 return -ENODEV;
991 }
992
993 ice_set_dflt_vsi_ctx(ctxt);
994
995 if (vsi->vsw->bridge_mode == BRIDGE_MODE_VEB)
996 ctxt->info.sw_flags |= ICE_AQ_VSI_SW_FLAG_ALLOW_LB;
997
998
999 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
1000 ice_set_rss_vsi_ctx(ctxt, vsi);
1001
1002 ctxt->info.sw_id = vsi->port_info->sw_id;
1003 ice_vsi_setup_q_map(vsi, ctxt);
1004
1005
1006 if (vsi->type == ICE_VSI_VF && pf->vf[vsi->vf_id].spoofchk) {
1007 ctxt->info.valid_sections |=
1008 cpu_to_le16(ICE_AQ_VSI_PROP_SECURITY_VALID);
1009 ctxt->info.sec_flags |=
1010 ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF;
1011 }
1012
1013 ret = ice_add_vsi(hw, vsi->idx, ctxt, NULL);
1014 if (ret) {
1015 dev_err(&pf->pdev->dev,
1016 "Add VSI failed, err %d\n", ret);
1017 return -EIO;
1018 }
1019
1020
1021 vsi->info = ctxt->info;
1022
1023
1024 vsi->vsi_num = ctxt->vsi_num;
1025
1026 devm_kfree(&pf->pdev->dev, ctxt);
1027 return ret;
1028}
1029
1030
1031
1032
1033
1034
1035static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)
1036{
1037 struct ice_q_vector *q_vector;
1038 struct ice_pf *pf = vsi->back;
1039 struct ice_ring *ring;
1040
1041 if (!vsi->q_vectors[v_idx]) {
1042 dev_dbg(&pf->pdev->dev, "Queue vector at index %d not found\n",
1043 v_idx);
1044 return;
1045 }
1046 q_vector = vsi->q_vectors[v_idx];
1047
1048 ice_for_each_ring(ring, q_vector->tx)
1049 ring->q_vector = NULL;
1050 ice_for_each_ring(ring, q_vector->rx)
1051 ring->q_vector = NULL;
1052
1053
1054 if (vsi->netdev)
1055 netif_napi_del(&q_vector->napi);
1056
1057 devm_kfree(&pf->pdev->dev, q_vector);
1058 vsi->q_vectors[v_idx] = NULL;
1059}
1060
1061
1062
1063
1064
1065void ice_vsi_free_q_vectors(struct ice_vsi *vsi)
1066{
1067 int v_idx;
1068
1069 ice_for_each_q_vector(vsi, v_idx)
1070 ice_free_q_vector(vsi, v_idx);
1071}
1072
1073
1074
1075
1076
1077
1078
1079
1080static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx)
1081{
1082 struct ice_pf *pf = vsi->back;
1083 struct ice_q_vector *q_vector;
1084
1085
1086 q_vector = devm_kzalloc(&pf->pdev->dev, sizeof(*q_vector), GFP_KERNEL);
1087 if (!q_vector)
1088 return -ENOMEM;
1089
1090 q_vector->vsi = vsi;
1091 q_vector->v_idx = v_idx;
1092 if (vsi->type == ICE_VSI_VF)
1093 goto out;
1094
1095 if (cpu_online(v_idx))
1096 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
1097
1098
1099
1100
1101
1102 if (vsi->netdev)
1103 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll,
1104 NAPI_POLL_WEIGHT);
1105
1106out:
1107
1108 vsi->q_vectors[v_idx] = q_vector;
1109
1110 return 0;
1111}
1112
1113
1114
1115
1116
1117
1118
1119
1120static int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)
1121{
1122 struct ice_pf *pf = vsi->back;
1123 int v_idx = 0, num_q_vectors;
1124 int err;
1125
1126 if (vsi->q_vectors[0]) {
1127 dev_dbg(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
1128 vsi->vsi_num);
1129 return -EEXIST;
1130 }
1131
1132 if (test_bit(ICE_FLAG_MSIX_ENA, pf->flags)) {
1133 num_q_vectors = vsi->num_q_vectors;
1134 } else {
1135 err = -EINVAL;
1136 goto err_out;
1137 }
1138
1139 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1140 err = ice_vsi_alloc_q_vector(vsi, v_idx);
1141 if (err)
1142 goto err_out;
1143 }
1144
1145 return 0;
1146
1147err_out:
1148 while (v_idx--)
1149 ice_free_q_vector(vsi, v_idx);
1150
1151 dev_err(&pf->pdev->dev,
1152 "Failed to allocate %d q_vector for VSI %d, ret=%d\n",
1153 vsi->num_q_vectors, vsi->vsi_num, err);
1154 vsi->num_q_vectors = 0;
1155 return err;
1156}
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168static int ice_vsi_setup_vector_base(struct ice_vsi *vsi)
1169{
1170 struct ice_pf *pf = vsi->back;
1171 u16 num_q_vectors;
1172
1173
1174 if (vsi->type == ICE_VSI_VF)
1175 return 0;
1176
1177 if (vsi->base_vector) {
1178 dev_dbg(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
1179 vsi->vsi_num, vsi->base_vector);
1180 return -EEXIST;
1181 }
1182
1183 if (!test_bit(ICE_FLAG_MSIX_ENA, pf->flags))
1184 return -ENOENT;
1185
1186 num_q_vectors = vsi->num_q_vectors;
1187
1188 vsi->base_vector = ice_get_res(pf, pf->irq_tracker, num_q_vectors,
1189 vsi->idx);
1190 if (vsi->base_vector < 0) {
1191 dev_err(&pf->pdev->dev,
1192 "Failed to get tracking for %d vectors for VSI %d, err=%d\n",
1193 num_q_vectors, vsi->vsi_num, vsi->base_vector);
1194 return -ENOENT;
1195 }
1196 pf->num_avail_sw_msix -= num_q_vectors;
1197
1198 return 0;
1199}
1200
1201
1202
1203
1204
1205static void ice_vsi_clear_rings(struct ice_vsi *vsi)
1206{
1207 int i;
1208
1209 if (vsi->tx_rings) {
1210 for (i = 0; i < vsi->alloc_txq; i++) {
1211 if (vsi->tx_rings[i]) {
1212 kfree_rcu(vsi->tx_rings[i], rcu);
1213 vsi->tx_rings[i] = NULL;
1214 }
1215 }
1216 }
1217 if (vsi->rx_rings) {
1218 for (i = 0; i < vsi->alloc_rxq; i++) {
1219 if (vsi->rx_rings[i]) {
1220 kfree_rcu(vsi->rx_rings[i], rcu);
1221 vsi->rx_rings[i] = NULL;
1222 }
1223 }
1224 }
1225}
1226
1227
1228
1229
1230
1231static int ice_vsi_alloc_rings(struct ice_vsi *vsi)
1232{
1233 struct ice_pf *pf = vsi->back;
1234 int i;
1235
1236
1237 for (i = 0; i < vsi->alloc_txq; i++) {
1238 struct ice_ring *ring;
1239
1240
1241 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1242
1243 if (!ring)
1244 goto err_out;
1245
1246 ring->q_index = i;
1247 ring->reg_idx = vsi->txq_map[i];
1248 ring->ring_active = false;
1249 ring->vsi = vsi;
1250 ring->dev = &pf->pdev->dev;
1251 ring->count = vsi->num_tx_desc;
1252 vsi->tx_rings[i] = ring;
1253 }
1254
1255
1256 for (i = 0; i < vsi->alloc_rxq; i++) {
1257 struct ice_ring *ring;
1258
1259
1260 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1261 if (!ring)
1262 goto err_out;
1263
1264 ring->q_index = i;
1265 ring->reg_idx = vsi->rxq_map[i];
1266 ring->ring_active = false;
1267 ring->vsi = vsi;
1268 ring->netdev = vsi->netdev;
1269 ring->dev = &pf->pdev->dev;
1270 ring->count = vsi->num_rx_desc;
1271 vsi->rx_rings[i] = ring;
1272 }
1273
1274 return 0;
1275
1276err_out:
1277 ice_vsi_clear_rings(vsi);
1278 return -ENOMEM;
1279}
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289#ifdef CONFIG_DCB
1290void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
1291#else
1292static void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
1293#endif
1294{
1295 int q_vectors = vsi->num_q_vectors;
1296 int tx_rings_rem, rx_rings_rem;
1297 int v_id;
1298
1299
1300 tx_rings_rem = vsi->num_txq;
1301 rx_rings_rem = vsi->num_rxq;
1302
1303 for (v_id = 0; v_id < q_vectors; v_id++) {
1304 struct ice_q_vector *q_vector = vsi->q_vectors[v_id];
1305 int tx_rings_per_v, rx_rings_per_v, q_id, q_base;
1306
1307
1308 tx_rings_per_v = DIV_ROUND_UP(tx_rings_rem, q_vectors - v_id);
1309 q_vector->num_ring_tx = tx_rings_per_v;
1310 q_vector->tx.ring = NULL;
1311 q_vector->tx.itr_idx = ICE_TX_ITR;
1312 q_base = vsi->num_txq - tx_rings_rem;
1313
1314 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {
1315 struct ice_ring *tx_ring = vsi->tx_rings[q_id];
1316
1317 tx_ring->q_vector = q_vector;
1318 tx_ring->next = q_vector->tx.ring;
1319 q_vector->tx.ring = tx_ring;
1320 }
1321 tx_rings_rem -= tx_rings_per_v;
1322
1323
1324 rx_rings_per_v = DIV_ROUND_UP(rx_rings_rem, q_vectors - v_id);
1325 q_vector->num_ring_rx = rx_rings_per_v;
1326 q_vector->rx.ring = NULL;
1327 q_vector->rx.itr_idx = ICE_RX_ITR;
1328 q_base = vsi->num_rxq - rx_rings_rem;
1329
1330 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {
1331 struct ice_ring *rx_ring = vsi->rx_rings[q_id];
1332
1333 rx_ring->q_vector = q_vector;
1334 rx_ring->next = q_vector->rx.ring;
1335 q_vector->rx.ring = rx_ring;
1336 }
1337 rx_rings_rem -= rx_rings_per_v;
1338 }
1339}
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350int ice_vsi_manage_rss_lut(struct ice_vsi *vsi, bool ena)
1351{
1352 int err = 0;
1353 u8 *lut;
1354
1355 lut = devm_kzalloc(&vsi->back->pdev->dev, vsi->rss_table_size,
1356 GFP_KERNEL);
1357 if (!lut)
1358 return -ENOMEM;
1359
1360 if (ena) {
1361 if (vsi->rss_lut_user)
1362 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1363 else
1364 ice_fill_rss_lut(lut, vsi->rss_table_size,
1365 vsi->rss_size);
1366 }
1367
1368 err = ice_set_rss(vsi, NULL, lut, vsi->rss_table_size);
1369 devm_kfree(&vsi->back->pdev->dev, lut);
1370 return err;
1371}
1372
1373
1374
1375
1376
1377static int ice_vsi_cfg_rss_lut_key(struct ice_vsi *vsi)
1378{
1379 struct ice_aqc_get_set_rss_keys *key;
1380 struct ice_pf *pf = vsi->back;
1381 enum ice_status status;
1382 int err = 0;
1383 u8 *lut;
1384
1385 vsi->rss_size = min_t(int, vsi->rss_size, vsi->num_rxq);
1386
1387 lut = devm_kzalloc(&pf->pdev->dev, vsi->rss_table_size, GFP_KERNEL);
1388 if (!lut)
1389 return -ENOMEM;
1390
1391 if (vsi->rss_lut_user)
1392 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1393 else
1394 ice_fill_rss_lut(lut, vsi->rss_table_size, vsi->rss_size);
1395
1396 status = ice_aq_set_rss_lut(&pf->hw, vsi->idx, vsi->rss_lut_type, lut,
1397 vsi->rss_table_size);
1398
1399 if (status) {
1400 dev_err(&pf->pdev->dev,
1401 "set_rss_lut failed, error %d\n", status);
1402 err = -EIO;
1403 goto ice_vsi_cfg_rss_exit;
1404 }
1405
1406 key = devm_kzalloc(&pf->pdev->dev, sizeof(*key), GFP_KERNEL);
1407 if (!key) {
1408 err = -ENOMEM;
1409 goto ice_vsi_cfg_rss_exit;
1410 }
1411
1412 if (vsi->rss_hkey_user)
1413 memcpy(key,
1414 (struct ice_aqc_get_set_rss_keys *)vsi->rss_hkey_user,
1415 ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE);
1416 else
1417 netdev_rss_key_fill((void *)key,
1418 ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE);
1419
1420 status = ice_aq_set_rss_key(&pf->hw, vsi->idx, key);
1421
1422 if (status) {
1423 dev_err(&pf->pdev->dev, "set_rss_key failed, error %d\n",
1424 status);
1425 err = -EIO;
1426 }
1427
1428 devm_kfree(&pf->pdev->dev, key);
1429ice_vsi_cfg_rss_exit:
1430 devm_kfree(&pf->pdev->dev, lut);
1431 return err;
1432}
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444int ice_add_mac_to_list(struct ice_vsi *vsi, struct list_head *add_list,
1445 const u8 *macaddr)
1446{
1447 struct ice_fltr_list_entry *tmp;
1448 struct ice_pf *pf = vsi->back;
1449
1450 tmp = devm_kzalloc(&pf->pdev->dev, sizeof(*tmp), GFP_ATOMIC);
1451 if (!tmp)
1452 return -ENOMEM;
1453
1454 tmp->fltr_info.flag = ICE_FLTR_TX;
1455 tmp->fltr_info.src_id = ICE_SRC_ID_VSI;
1456 tmp->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
1457 tmp->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1458 tmp->fltr_info.vsi_handle = vsi->idx;
1459 ether_addr_copy(tmp->fltr_info.l_data.mac.mac_addr, macaddr);
1460
1461 INIT_LIST_HEAD(&tmp->list_entry);
1462 list_add(&tmp->list_entry, add_list);
1463
1464 return 0;
1465}
1466
1467
1468
1469
1470
1471void ice_update_eth_stats(struct ice_vsi *vsi)
1472{
1473 struct ice_eth_stats *prev_es, *cur_es;
1474 struct ice_hw *hw = &vsi->back->hw;
1475 u16 vsi_num = vsi->vsi_num;
1476
1477 prev_es = &vsi->eth_stats_prev;
1478 cur_es = &vsi->eth_stats;
1479
1480 ice_stat_update40(hw, GLV_GORCH(vsi_num), GLV_GORCL(vsi_num),
1481 vsi->stat_offsets_loaded, &prev_es->rx_bytes,
1482 &cur_es->rx_bytes);
1483
1484 ice_stat_update40(hw, GLV_UPRCH(vsi_num), GLV_UPRCL(vsi_num),
1485 vsi->stat_offsets_loaded, &prev_es->rx_unicast,
1486 &cur_es->rx_unicast);
1487
1488 ice_stat_update40(hw, GLV_MPRCH(vsi_num), GLV_MPRCL(vsi_num),
1489 vsi->stat_offsets_loaded, &prev_es->rx_multicast,
1490 &cur_es->rx_multicast);
1491
1492 ice_stat_update40(hw, GLV_BPRCH(vsi_num), GLV_BPRCL(vsi_num),
1493 vsi->stat_offsets_loaded, &prev_es->rx_broadcast,
1494 &cur_es->rx_broadcast);
1495
1496 ice_stat_update32(hw, GLV_RDPC(vsi_num), vsi->stat_offsets_loaded,
1497 &prev_es->rx_discards, &cur_es->rx_discards);
1498
1499 ice_stat_update40(hw, GLV_GOTCH(vsi_num), GLV_GOTCL(vsi_num),
1500 vsi->stat_offsets_loaded, &prev_es->tx_bytes,
1501 &cur_es->tx_bytes);
1502
1503 ice_stat_update40(hw, GLV_UPTCH(vsi_num), GLV_UPTCL(vsi_num),
1504 vsi->stat_offsets_loaded, &prev_es->tx_unicast,
1505 &cur_es->tx_unicast);
1506
1507 ice_stat_update40(hw, GLV_MPTCH(vsi_num), GLV_MPTCL(vsi_num),
1508 vsi->stat_offsets_loaded, &prev_es->tx_multicast,
1509 &cur_es->tx_multicast);
1510
1511 ice_stat_update40(hw, GLV_BPTCH(vsi_num), GLV_BPTCL(vsi_num),
1512 vsi->stat_offsets_loaded, &prev_es->tx_broadcast,
1513 &cur_es->tx_broadcast);
1514
1515 ice_stat_update32(hw, GLV_TEPC(vsi_num), vsi->stat_offsets_loaded,
1516 &prev_es->tx_errors, &cur_es->tx_errors);
1517
1518 vsi->stat_offsets_loaded = true;
1519}
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529void ice_free_fltr_list(struct device *dev, struct list_head *h)
1530{
1531 struct ice_fltr_list_entry *e, *tmp;
1532
1533 list_for_each_entry_safe(e, tmp, h, list_entry) {
1534 list_del(&e->list_entry);
1535 devm_kfree(dev, e);
1536 }
1537}
1538
1539
1540
1541
1542
1543
1544int ice_vsi_add_vlan(struct ice_vsi *vsi, u16 vid)
1545{
1546 struct ice_fltr_list_entry *tmp;
1547 struct ice_pf *pf = vsi->back;
1548 LIST_HEAD(tmp_add_list);
1549 enum ice_status status;
1550 int err = 0;
1551
1552 tmp = devm_kzalloc(&pf->pdev->dev, sizeof(*tmp), GFP_KERNEL);
1553 if (!tmp)
1554 return -ENOMEM;
1555
1556 tmp->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1557 tmp->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1558 tmp->fltr_info.flag = ICE_FLTR_TX;
1559 tmp->fltr_info.src_id = ICE_SRC_ID_VSI;
1560 tmp->fltr_info.vsi_handle = vsi->idx;
1561 tmp->fltr_info.l_data.vlan.vlan_id = vid;
1562
1563 INIT_LIST_HEAD(&tmp->list_entry);
1564 list_add(&tmp->list_entry, &tmp_add_list);
1565
1566 status = ice_add_vlan(&pf->hw, &tmp_add_list);
1567 if (status) {
1568 err = -ENODEV;
1569 dev_err(&pf->pdev->dev, "Failure Adding VLAN %d on VSI %i\n",
1570 vid, vsi->vsi_num);
1571 }
1572
1573 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
1574 return err;
1575}
1576
1577
1578
1579
1580
1581
1582
1583
1584int ice_vsi_kill_vlan(struct ice_vsi *vsi, u16 vid)
1585{
1586 struct ice_fltr_list_entry *list;
1587 struct ice_pf *pf = vsi->back;
1588 LIST_HEAD(tmp_add_list);
1589 enum ice_status status;
1590 int err = 0;
1591
1592 list = devm_kzalloc(&pf->pdev->dev, sizeof(*list), GFP_KERNEL);
1593 if (!list)
1594 return -ENOMEM;
1595
1596 list->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1597 list->fltr_info.vsi_handle = vsi->idx;
1598 list->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1599 list->fltr_info.l_data.vlan.vlan_id = vid;
1600 list->fltr_info.flag = ICE_FLTR_TX;
1601 list->fltr_info.src_id = ICE_SRC_ID_VSI;
1602
1603 INIT_LIST_HEAD(&list->list_entry);
1604 list_add(&list->list_entry, &tmp_add_list);
1605
1606 status = ice_remove_vlan(&pf->hw, &tmp_add_list);
1607 if (status == ICE_ERR_DOES_NOT_EXIST) {
1608 dev_dbg(&pf->pdev->dev,
1609 "Failed to remove VLAN %d on VSI %i, it does not exist, status: %d\n",
1610 vid, vsi->vsi_num, status);
1611 } else if (status) {
1612 dev_err(&pf->pdev->dev,
1613 "Error removing VLAN %d on vsi %i error: %d\n",
1614 vid, vsi->vsi_num, status);
1615 err = -EIO;
1616 }
1617
1618 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
1619 return err;
1620}
1621
1622
1623
1624
1625
1626
1627
1628
1629int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)
1630{
1631 u16 i;
1632
1633 if (vsi->type == ICE_VSI_VF)
1634 goto setup_rings;
1635
1636 if (vsi->netdev && vsi->netdev->mtu > ETH_DATA_LEN)
1637 vsi->max_frame = vsi->netdev->mtu +
1638 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
1639 else
1640 vsi->max_frame = ICE_RXBUF_2048;
1641
1642 vsi->rx_buf_len = ICE_RXBUF_2048;
1643setup_rings:
1644
1645 for (i = 0; i < vsi->num_rxq; i++) {
1646 int err;
1647
1648 err = ice_setup_rx_ctx(vsi->rx_rings[i]);
1649 if (err) {
1650 dev_err(&vsi->back->pdev->dev,
1651 "ice_setup_rx_ctx failed for RxQ %d, err %d\n",
1652 i, err);
1653 return err;
1654 }
1655 }
1656
1657 return 0;
1658}
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669static int
1670ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_ring **rings, int offset)
1671{
1672 struct ice_aqc_add_tx_qgrp *qg_buf;
1673 struct ice_aqc_add_txqs_perq *txq;
1674 struct ice_pf *pf = vsi->back;
1675 u8 num_q_grps, q_idx = 0;
1676 enum ice_status status;
1677 u16 buf_len, i, pf_q;
1678 int err = 0, tc;
1679
1680 buf_len = sizeof(*qg_buf);
1681 qg_buf = devm_kzalloc(&pf->pdev->dev, buf_len, GFP_KERNEL);
1682 if (!qg_buf)
1683 return -ENOMEM;
1684
1685 qg_buf->num_txqs = 1;
1686 num_q_grps = 1;
1687
1688
1689 ice_for_each_traffic_class(tc) {
1690 if (!(vsi->tc_cfg.ena_tc & BIT(tc)))
1691 break;
1692
1693 for (i = 0; i < vsi->tc_cfg.tc_info[tc].qcount_tx; i++) {
1694 struct ice_tlan_ctx tlan_ctx = { 0 };
1695
1696 pf_q = vsi->txq_map[q_idx + offset];
1697 ice_setup_tx_ctx(rings[q_idx], &tlan_ctx, pf_q);
1698
1699 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
1700 ice_set_ctx((u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
1701 ice_tlan_ctx_info);
1702
1703
1704
1705
1706 rings[q_idx]->tail =
1707 pf->hw.hw_addr + QTX_COMM_DBELL(pf_q);
1708 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc,
1709 i, num_q_grps, qg_buf,
1710 buf_len, NULL);
1711 if (status) {
1712 dev_err(&pf->pdev->dev,
1713 "Failed to set LAN Tx queue context, error: %d\n",
1714 status);
1715 err = -ENODEV;
1716 goto err_cfg_txqs;
1717 }
1718
1719
1720
1721
1722
1723 txq = &qg_buf->txqs[0];
1724 if (pf_q == le16_to_cpu(txq->txq_id))
1725 rings[q_idx]->txq_teid =
1726 le32_to_cpu(txq->q_teid);
1727
1728 q_idx++;
1729 }
1730 }
1731err_cfg_txqs:
1732 devm_kfree(&pf->pdev->dev, qg_buf);
1733 return err;
1734}
1735
1736
1737
1738
1739
1740
1741
1742
1743int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi)
1744{
1745 return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, 0);
1746}
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran)
1757{
1758 u32 val = intrl / gran;
1759
1760 if (val)
1761 return val | GLINT_RATE_INTRL_ENA_M;
1762 return 0;
1763}
1764
1765
1766
1767
1768
1769static void ice_cfg_itr_gran(struct ice_hw *hw)
1770{
1771 u32 regval = rd32(hw, GLINT_CTL);
1772
1773
1774 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&
1775 (((regval & GLINT_CTL_ITR_GRAN_200_M) >>
1776 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) &&
1777 (((regval & GLINT_CTL_ITR_GRAN_100_M) >>
1778 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) &&
1779 (((regval & GLINT_CTL_ITR_GRAN_50_M) >>
1780 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) &&
1781 (((regval & GLINT_CTL_ITR_GRAN_25_M) >>
1782 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))
1783 return;
1784
1785 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) &
1786 GLINT_CTL_ITR_GRAN_200_M) |
1787 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) &
1788 GLINT_CTL_ITR_GRAN_100_M) |
1789 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) &
1790 GLINT_CTL_ITR_GRAN_50_M) |
1791 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) &
1792 GLINT_CTL_ITR_GRAN_25_M);
1793 wr32(hw, GLINT_CTL, regval);
1794}
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804static void
1805ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)
1806{
1807 ice_cfg_itr_gran(hw);
1808
1809 if (q_vector->num_ring_rx) {
1810 struct ice_ring_container *rc = &q_vector->rx;
1811
1812
1813 if (!rc->itr_setting)
1814 rc->itr_setting = ICE_DFLT_RX_ITR;
1815
1816 rc->target_itr = ITR_TO_REG(rc->itr_setting);
1817 rc->next_update = jiffies + 1;
1818 rc->current_itr = rc->target_itr;
1819 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
1820 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
1821 }
1822
1823 if (q_vector->num_ring_tx) {
1824 struct ice_ring_container *rc = &q_vector->tx;
1825
1826
1827 if (!rc->itr_setting)
1828 rc->itr_setting = ICE_DFLT_TX_ITR;
1829
1830 rc->target_itr = ITR_TO_REG(rc->itr_setting);
1831 rc->next_update = jiffies + 1;
1832 rc->current_itr = rc->target_itr;
1833 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
1834 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
1835 }
1836}
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848#ifdef CONFIG_PCI_IOV
1849void
1850ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
1851#else
1852static void
1853ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
1854#endif
1855{
1856 struct ice_pf *pf = vsi->back;
1857 struct ice_hw *hw = &pf->hw;
1858 u32 val;
1859
1860 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M;
1861
1862 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
1863 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M);
1864
1865 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
1866}
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878#ifdef CONFIG_PCI_IOV
1879void
1880ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
1881#else
1882static void
1883ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
1884#endif
1885{
1886 struct ice_pf *pf = vsi->back;
1887 struct ice_hw *hw = &pf->hw;
1888 u32 val;
1889
1890 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M;
1891
1892 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
1893 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M);
1894
1895 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
1896
1897 ice_flush(hw);
1898}
1899
1900
1901
1902
1903
1904
1905
1906
1907void ice_vsi_cfg_msix(struct ice_vsi *vsi)
1908{
1909 struct ice_pf *pf = vsi->back;
1910 struct ice_hw *hw = &pf->hw;
1911 u32 txq = 0, rxq = 0;
1912 int i, q;
1913
1914 for (i = 0; i < vsi->num_q_vectors; i++) {
1915 struct ice_q_vector *q_vector = vsi->q_vectors[i];
1916 u16 reg_idx = q_vector->reg_idx;
1917
1918 ice_cfg_itr(hw, q_vector);
1919
1920 wr32(hw, GLINT_RATE(reg_idx),
1921 ice_intrl_usec_to_reg(q_vector->intrl, hw->intrl_gran));
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934 for (q = 0; q < q_vector->num_ring_tx; q++) {
1935 ice_cfg_txq_interrupt(vsi, txq, reg_idx,
1936 q_vector->tx.itr_idx);
1937 txq++;
1938 }
1939
1940 for (q = 0; q < q_vector->num_ring_rx; q++) {
1941 ice_cfg_rxq_interrupt(vsi, rxq, reg_idx,
1942 q_vector->rx.itr_idx);
1943 rxq++;
1944 }
1945 }
1946}
1947
1948
1949
1950
1951
1952int ice_vsi_manage_vlan_insertion(struct ice_vsi *vsi)
1953{
1954 struct device *dev = &vsi->back->pdev->dev;
1955 struct ice_hw *hw = &vsi->back->hw;
1956 struct ice_vsi_ctx *ctxt;
1957 enum ice_status status;
1958 int ret = 0;
1959
1960 ctxt = devm_kzalloc(dev, sizeof(*ctxt), GFP_KERNEL);
1961 if (!ctxt)
1962 return -ENOMEM;
1963
1964
1965
1966
1967
1968 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1969
1970
1971 ctxt->info.vlan_flags |= (vsi->info.vlan_flags &
1972 ICE_AQ_VSI_VLAN_EMOD_M);
1973
1974 ctxt->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);
1975
1976 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
1977 if (status) {
1978 dev_err(dev, "update VSI for VLAN insert failed, err %d aq_err %d\n",
1979 status, hw->adminq.sq_last_status);
1980 ret = -EIO;
1981 goto out;
1982 }
1983
1984 vsi->info.vlan_flags = ctxt->info.vlan_flags;
1985out:
1986 devm_kfree(dev, ctxt);
1987 return ret;
1988}
1989
1990
1991
1992
1993
1994
1995int ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
1996{
1997 struct device *dev = &vsi->back->pdev->dev;
1998 struct ice_hw *hw = &vsi->back->hw;
1999 struct ice_vsi_ctx *ctxt;
2000 enum ice_status status;
2001 int ret = 0;
2002
2003 ctxt = devm_kzalloc(dev, sizeof(*ctxt), GFP_KERNEL);
2004 if (!ctxt)
2005 return -ENOMEM;
2006
2007
2008
2009
2010
2011 if (ena)
2012
2013 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2014 else
2015
2016 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2017
2018
2019 ctxt->info.vlan_flags |= ICE_AQ_VSI_VLAN_MODE_ALL;
2020
2021 ctxt->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);
2022
2023 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
2024 if (status) {
2025 dev_err(dev, "update VSI for VLAN strip failed, ena = %d err %d aq_err %d\n",
2026 ena, status, hw->adminq.sq_last_status);
2027 ret = -EIO;
2028 goto out;
2029 }
2030
2031 vsi->info.vlan_flags = ctxt->info.vlan_flags;
2032out:
2033 devm_kfree(dev, ctxt);
2034 return ret;
2035}
2036
2037
2038
2039
2040
2041
2042
2043int ice_vsi_start_rx_rings(struct ice_vsi *vsi)
2044{
2045 return ice_vsi_ctrl_rx_rings(vsi, true);
2046}
2047
2048
2049
2050
2051
2052
2053
2054int ice_vsi_stop_rx_rings(struct ice_vsi *vsi)
2055{
2056 return ice_vsi_ctrl_rx_rings(vsi, false);
2057}
2058
2059
2060
2061
2062
2063
2064void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector)
2065{
2066 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),
2067 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |
2068 GLINT_DYN_CTL_SWINT_TRIG_M |
2069 GLINT_DYN_CTL_INTENA_M);
2070}
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080static int
2081ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
2082 u16 rel_vmvf_num, struct ice_ring **rings, int offset)
2083{
2084 struct ice_pf *pf = vsi->back;
2085 struct ice_hw *hw = &pf->hw;
2086 int tc, q_idx = 0, err = 0;
2087 u16 *q_ids, *q_handles, i;
2088 enum ice_status status;
2089 u32 *q_teids, val;
2090
2091 if (vsi->num_txq > ICE_LAN_TXQ_MAX_QDIS)
2092 return -EINVAL;
2093
2094 q_teids = devm_kcalloc(&pf->pdev->dev, vsi->num_txq, sizeof(*q_teids),
2095 GFP_KERNEL);
2096 if (!q_teids)
2097 return -ENOMEM;
2098
2099 q_ids = devm_kcalloc(&pf->pdev->dev, vsi->num_txq, sizeof(*q_ids),
2100 GFP_KERNEL);
2101 if (!q_ids) {
2102 err = -ENOMEM;
2103 goto err_alloc_q_ids;
2104 }
2105
2106 q_handles = devm_kcalloc(&pf->pdev->dev, vsi->num_txq,
2107 sizeof(*q_handles), GFP_KERNEL);
2108 if (!q_handles) {
2109 err = -ENOMEM;
2110 goto err_alloc_q_handles;
2111 }
2112
2113
2114 ice_for_each_traffic_class(tc) {
2115 if (!(vsi->tc_cfg.ena_tc & BIT(tc)))
2116 break;
2117
2118 for (i = 0; i < vsi->tc_cfg.tc_info[tc].qcount_tx; i++) {
2119 struct ice_q_vector *q_vector;
2120
2121 if (!rings || !rings[q_idx]) {
2122 err = -EINVAL;
2123 goto err_out;
2124 }
2125
2126 q_ids[i] = vsi->txq_map[q_idx + offset];
2127 q_teids[i] = rings[q_idx]->txq_teid;
2128 q_handles[i] = i;
2129
2130
2131 val = rd32(hw, QINT_TQCTL(rings[i]->reg_idx));
2132 val &= ~QINT_TQCTL_CAUSE_ENA_M;
2133 wr32(hw, QINT_TQCTL(rings[i]->reg_idx), val);
2134
2135
2136 ndelay(100);
2137
2138
2139
2140
2141 q_vector = rings[i]->q_vector;
2142 if (q_vector)
2143 ice_trigger_sw_intr(hw, q_vector);
2144
2145 q_idx++;
2146 }
2147 status = ice_dis_vsi_txq(vsi->port_info, vsi->idx, tc,
2148 vsi->num_txq, q_handles, q_ids,
2149 q_teids, rst_src, rel_vmvf_num, NULL);
2150
2151
2152
2153
2154
2155
2156 if (status == ICE_ERR_RESET_ONGOING) {
2157 dev_dbg(&pf->pdev->dev,
2158 "Reset in progress. LAN Tx queues already disabled\n");
2159 } else if (status) {
2160 dev_err(&pf->pdev->dev,
2161 "Failed to disable LAN Tx queues, error: %d\n",
2162 status);
2163 err = -ENODEV;
2164 }
2165 }
2166
2167err_out:
2168 devm_kfree(&pf->pdev->dev, q_handles);
2169
2170err_alloc_q_handles:
2171 devm_kfree(&pf->pdev->dev, q_ids);
2172
2173err_alloc_q_ids:
2174 devm_kfree(&pf->pdev->dev, q_teids);
2175
2176 return err;
2177}
2178
2179
2180
2181
2182
2183
2184
2185int
2186ice_vsi_stop_lan_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
2187 u16 rel_vmvf_num)
2188{
2189 return ice_vsi_stop_tx_rings(vsi, rst_src, rel_vmvf_num, vsi->tx_rings,
2190 0);
2191}
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201int ice_cfg_vlan_pruning(struct ice_vsi *vsi, bool ena, bool vlan_promisc)
2202{
2203 struct ice_vsi_ctx *ctxt;
2204 struct device *dev;
2205 struct ice_pf *pf;
2206 int status;
2207
2208 if (!vsi)
2209 return -EINVAL;
2210
2211 pf = vsi->back;
2212 dev = &pf->pdev->dev;
2213 ctxt = devm_kzalloc(dev, sizeof(*ctxt), GFP_KERNEL);
2214 if (!ctxt)
2215 return -ENOMEM;
2216
2217 ctxt->info = vsi->info;
2218
2219 if (ena) {
2220 ctxt->info.sec_flags |=
2221 ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2222 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2223 ctxt->info.sw_flags2 |= ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2224 } else {
2225 ctxt->info.sec_flags &=
2226 ~(ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2227 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S);
2228 ctxt->info.sw_flags2 &= ~ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2229 }
2230
2231 if (!vlan_promisc)
2232 ctxt->info.valid_sections =
2233 cpu_to_le16(ICE_AQ_VSI_PROP_SECURITY_VALID |
2234 ICE_AQ_VSI_PROP_SW_VALID);
2235
2236 status = ice_update_vsi(&pf->hw, vsi->idx, ctxt, NULL);
2237 if (status) {
2238 netdev_err(vsi->netdev, "%sabling VLAN pruning on VSI handle: %d, VSI HW ID: %d failed, err = %d, aq_err = %d\n",
2239 ena ? "En" : "Dis", vsi->idx, vsi->vsi_num, status,
2240 pf->hw.adminq.sq_last_status);
2241 goto err_out;
2242 }
2243
2244 vsi->info.sec_flags = ctxt->info.sec_flags;
2245 vsi->info.sw_flags2 = ctxt->info.sw_flags2;
2246
2247 devm_kfree(dev, ctxt);
2248 return 0;
2249
2250err_out:
2251 devm_kfree(dev, ctxt);
2252 return -EIO;
2253}
2254
2255static void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)
2256{
2257 struct ice_dcbx_cfg *cfg = &vsi->port_info->local_dcbx_cfg;
2258
2259 vsi->tc_cfg.ena_tc = ice_dcb_get_ena_tc(cfg);
2260 vsi->tc_cfg.numtc = ice_dcb_get_num_tc(cfg);
2261}
2262
2263
2264
2265
2266
2267static int
2268ice_vsi_set_q_vectors_reg_idx(struct ice_vsi *vsi)
2269{
2270 u16 i;
2271
2272 if (!vsi || !vsi->q_vectors)
2273 return -EINVAL;
2274
2275 ice_for_each_q_vector(vsi, i) {
2276 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2277
2278 if (!q_vector) {
2279 dev_err(&vsi->back->pdev->dev,
2280 "Failed to set reg_idx on q_vector %d VSI %d\n",
2281 i, vsi->vsi_num);
2282 goto clear_reg_idx;
2283 }
2284
2285 if (vsi->type == ICE_VSI_VF) {
2286 struct ice_vf *vf = &vsi->back->vf[vsi->vf_id];
2287
2288 q_vector->reg_idx = ice_calc_vf_reg_idx(vf, q_vector);
2289 } else {
2290 q_vector->reg_idx =
2291 q_vector->v_idx + vsi->base_vector;
2292 }
2293 }
2294
2295 return 0;
2296
2297clear_reg_idx:
2298 ice_for_each_q_vector(vsi, i) {
2299 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2300
2301 if (q_vector)
2302 q_vector->reg_idx = 0;
2303 }
2304
2305 return -EINVAL;
2306}
2307
2308
2309
2310
2311
2312
2313static void
2314ice_vsi_add_rem_eth_mac(struct ice_vsi *vsi, bool add_rule)
2315{
2316 struct ice_fltr_list_entry *list;
2317 struct ice_pf *pf = vsi->back;
2318 LIST_HEAD(tmp_add_list);
2319 enum ice_status status;
2320
2321 list = devm_kzalloc(&pf->pdev->dev, sizeof(*list), GFP_KERNEL);
2322 if (!list)
2323 return;
2324
2325 list->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2326 list->fltr_info.fltr_act = ICE_DROP_PACKET;
2327 list->fltr_info.flag = ICE_FLTR_TX;
2328 list->fltr_info.src_id = ICE_SRC_ID_VSI;
2329 list->fltr_info.vsi_handle = vsi->idx;
2330 list->fltr_info.l_data.ethertype_mac.ethertype = vsi->ethtype;
2331
2332 INIT_LIST_HEAD(&list->list_entry);
2333 list_add(&list->list_entry, &tmp_add_list);
2334
2335 if (add_rule)
2336 status = ice_add_eth_mac(&pf->hw, &tmp_add_list);
2337 else
2338 status = ice_remove_eth_mac(&pf->hw, &tmp_add_list);
2339
2340 if (status)
2341 dev_err(&pf->pdev->dev,
2342 "Failure Adding or Removing Ethertype on VSI %i error: %d\n",
2343 vsi->vsi_num, status);
2344
2345 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
2346}
2347
2348
2349
2350
2351
2352
2353
2354void ice_cfg_sw_lldp(struct ice_vsi *vsi, bool tx, bool create)
2355{
2356 struct ice_fltr_list_entry *list;
2357 struct ice_pf *pf = vsi->back;
2358 LIST_HEAD(tmp_add_list);
2359 enum ice_status status;
2360
2361 list = devm_kzalloc(&pf->pdev->dev, sizeof(*list), GFP_KERNEL);
2362 if (!list)
2363 return;
2364
2365 list->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2366 list->fltr_info.vsi_handle = vsi->idx;
2367 list->fltr_info.l_data.ethertype_mac.ethertype = ETH_P_LLDP;
2368
2369 if (tx) {
2370 list->fltr_info.fltr_act = ICE_DROP_PACKET;
2371 list->fltr_info.flag = ICE_FLTR_TX;
2372 list->fltr_info.src_id = ICE_SRC_ID_VSI;
2373 } else {
2374 list->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2375 list->fltr_info.flag = ICE_FLTR_RX;
2376 list->fltr_info.src_id = ICE_SRC_ID_LPORT;
2377 }
2378
2379 INIT_LIST_HEAD(&list->list_entry);
2380 list_add(&list->list_entry, &tmp_add_list);
2381
2382 if (create)
2383 status = ice_add_eth_mac(&pf->hw, &tmp_add_list);
2384 else
2385 status = ice_remove_eth_mac(&pf->hw, &tmp_add_list);
2386
2387 if (status)
2388 dev_err(&pf->pdev->dev,
2389 "Fail %s %s LLDP rule on VSI %i error: %d\n",
2390 create ? "adding" : "removing", tx ? "TX" : "RX",
2391 vsi->vsi_num, status);
2392
2393 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
2394}
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410struct ice_vsi *
2411ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
2412 enum ice_vsi_type type, u16 vf_id)
2413{
2414 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
2415 struct device *dev = &pf->pdev->dev;
2416 enum ice_status status;
2417 struct ice_vsi *vsi;
2418 int ret, i;
2419
2420 if (type == ICE_VSI_VF)
2421 vsi = ice_vsi_alloc(pf, type, vf_id);
2422 else
2423 vsi = ice_vsi_alloc(pf, type, ICE_INVAL_VFID);
2424
2425 if (!vsi) {
2426 dev_err(dev, "could not allocate VSI\n");
2427 return NULL;
2428 }
2429
2430 vsi->port_info = pi;
2431 vsi->vsw = pf->first_sw;
2432 if (vsi->type == ICE_VSI_PF)
2433 vsi->ethtype = ETH_P_PAUSE;
2434
2435 if (vsi->type == ICE_VSI_VF)
2436 vsi->vf_id = vf_id;
2437
2438 if (ice_vsi_get_qs(vsi)) {
2439 dev_err(dev, "Failed to allocate queues. vsi->idx = %d\n",
2440 vsi->idx);
2441 goto unroll_get_qs;
2442 }
2443
2444
2445 ice_vsi_set_rss_params(vsi);
2446
2447
2448 ice_vsi_set_tc_cfg(vsi);
2449
2450
2451 ret = ice_vsi_init(vsi);
2452 if (ret)
2453 goto unroll_get_qs;
2454
2455 switch (vsi->type) {
2456 case ICE_VSI_PF:
2457 ret = ice_vsi_alloc_q_vectors(vsi);
2458 if (ret)
2459 goto unroll_vsi_init;
2460
2461 ret = ice_vsi_setup_vector_base(vsi);
2462 if (ret)
2463 goto unroll_alloc_q_vector;
2464
2465 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
2466 if (ret)
2467 goto unroll_vector_base;
2468
2469 ret = ice_vsi_alloc_rings(vsi);
2470 if (ret)
2471 goto unroll_vector_base;
2472
2473 ice_vsi_map_rings_to_vectors(vsi);
2474
2475
2476
2477
2478
2479 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
2480 ice_vsi_cfg_rss_lut_key(vsi);
2481 break;
2482 case ICE_VSI_VF:
2483
2484
2485
2486
2487
2488 ret = ice_vsi_alloc_q_vectors(vsi);
2489 if (ret)
2490 goto unroll_vsi_init;
2491
2492 ret = ice_vsi_alloc_rings(vsi);
2493 if (ret)
2494 goto unroll_alloc_q_vector;
2495
2496 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
2497 if (ret)
2498 goto unroll_vector_base;
2499
2500 pf->q_left_tx -= vsi->alloc_txq;
2501 pf->q_left_rx -= vsi->alloc_rxq;
2502
2503
2504
2505
2506
2507 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
2508 ice_vsi_cfg_rss_lut_key(vsi);
2509 break;
2510 case ICE_VSI_LB:
2511 ret = ice_vsi_alloc_rings(vsi);
2512 if (ret)
2513 goto unroll_vsi_init;
2514 break;
2515 default:
2516
2517 goto unroll_vsi_init;
2518 }
2519
2520
2521 for (i = 0; i < vsi->tc_cfg.numtc; i++)
2522 max_txqs[i] = pf->num_lan_tx;
2523
2524 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
2525 max_txqs);
2526 if (status) {
2527 dev_err(&pf->pdev->dev,
2528 "VSI %d failed lan queue config, error %d\n",
2529 vsi->vsi_num, status);
2530 goto unroll_vector_base;
2531 }
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543 if (vsi->type == ICE_VSI_PF) {
2544 ice_vsi_add_rem_eth_mac(vsi, true);
2545
2546
2547 ice_cfg_sw_lldp(vsi, true, true);
2548
2549
2550 if (!test_bit(ICE_FLAG_ENABLE_FW_LLDP, pf->flags))
2551 ice_cfg_sw_lldp(vsi, false, true);
2552 }
2553
2554 return vsi;
2555
2556unroll_vector_base:
2557
2558 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
2559 pf->num_avail_sw_msix += vsi->num_q_vectors;
2560unroll_alloc_q_vector:
2561 ice_vsi_free_q_vectors(vsi);
2562unroll_vsi_init:
2563 ice_vsi_delete(vsi);
2564unroll_get_qs:
2565 ice_vsi_put_qs(vsi);
2566 pf->q_left_tx += vsi->alloc_txq;
2567 pf->q_left_rx += vsi->alloc_rxq;
2568 ice_vsi_clear(vsi);
2569
2570 return NULL;
2571}
2572
2573
2574
2575
2576
2577static void ice_vsi_release_msix(struct ice_vsi *vsi)
2578{
2579 struct ice_pf *pf = vsi->back;
2580 struct ice_hw *hw = &pf->hw;
2581 u32 txq = 0;
2582 u32 rxq = 0;
2583 int i, q;
2584
2585 for (i = 0; i < vsi->num_q_vectors; i++) {
2586 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2587 u16 reg_idx = q_vector->reg_idx;
2588
2589 wr32(hw, GLINT_ITR(ICE_IDX_ITR0, reg_idx), 0);
2590 wr32(hw, GLINT_ITR(ICE_IDX_ITR1, reg_idx), 0);
2591 for (q = 0; q < q_vector->num_ring_tx; q++) {
2592 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), 0);
2593 txq++;
2594 }
2595
2596 for (q = 0; q < q_vector->num_ring_rx; q++) {
2597 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), 0);
2598 rxq++;
2599 }
2600 }
2601
2602 ice_flush(hw);
2603}
2604
2605
2606
2607
2608
2609void ice_vsi_free_irq(struct ice_vsi *vsi)
2610{
2611 struct ice_pf *pf = vsi->back;
2612 int base = vsi->base_vector;
2613
2614 if (test_bit(ICE_FLAG_MSIX_ENA, pf->flags)) {
2615 int i;
2616
2617 if (!vsi->q_vectors || !vsi->irqs_ready)
2618 return;
2619
2620 ice_vsi_release_msix(vsi);
2621 if (vsi->type == ICE_VSI_VF)
2622 return;
2623
2624 vsi->irqs_ready = false;
2625 ice_for_each_q_vector(vsi, i) {
2626 u16 vector = i + base;
2627 int irq_num;
2628
2629 irq_num = pf->msix_entries[vector].vector;
2630
2631
2632 if (!vsi->q_vectors[i] ||
2633 !(vsi->q_vectors[i]->num_ring_tx ||
2634 vsi->q_vectors[i]->num_ring_rx))
2635 continue;
2636
2637
2638 irq_set_affinity_notifier(irq_num, NULL);
2639
2640
2641 irq_set_affinity_hint(irq_num, NULL);
2642 synchronize_irq(irq_num);
2643 devm_free_irq(&pf->pdev->dev, irq_num,
2644 vsi->q_vectors[i]);
2645 }
2646 }
2647}
2648
2649
2650
2651
2652
2653void ice_vsi_free_tx_rings(struct ice_vsi *vsi)
2654{
2655 int i;
2656
2657 if (!vsi->tx_rings)
2658 return;
2659
2660 ice_for_each_txq(vsi, i)
2661 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
2662 ice_free_tx_ring(vsi->tx_rings[i]);
2663}
2664
2665
2666
2667
2668
2669void ice_vsi_free_rx_rings(struct ice_vsi *vsi)
2670{
2671 int i;
2672
2673 if (!vsi->rx_rings)
2674 return;
2675
2676 ice_for_each_rxq(vsi, i)
2677 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
2678 ice_free_rx_ring(vsi->rx_rings[i]);
2679}
2680
2681
2682
2683
2684
2685void ice_vsi_close(struct ice_vsi *vsi)
2686{
2687 if (!test_and_set_bit(__ICE_DOWN, vsi->state))
2688 ice_down(vsi);
2689
2690 ice_vsi_free_irq(vsi);
2691 ice_vsi_free_tx_rings(vsi);
2692 ice_vsi_free_rx_rings(vsi);
2693}
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703int ice_free_res(struct ice_res_tracker *res, u16 index, u16 id)
2704{
2705 int count = 0;
2706 int i;
2707
2708 if (!res || index >= res->end)
2709 return -EINVAL;
2710
2711 id |= ICE_RES_VALID_BIT;
2712 for (i = index; i < res->end && res->list[i] == id; i++) {
2713 res->list[i] = 0;
2714 count++;
2715 }
2716
2717 return count;
2718}
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728static int ice_search_res(struct ice_res_tracker *res, u16 needed, u16 id)
2729{
2730 int start = 0, end = 0;
2731
2732 if (needed > res->end)
2733 return -ENOMEM;
2734
2735 id |= ICE_RES_VALID_BIT;
2736
2737 do {
2738
2739 if (res->list[end++] & ICE_RES_VALID_BIT) {
2740 start = end;
2741 if ((start + needed) > res->end)
2742 break;
2743 }
2744
2745 if (end == (start + needed)) {
2746 int i = start;
2747
2748
2749 while (i != end)
2750 res->list[i++] = id;
2751
2752 return start;
2753 }
2754 } while (end < res->end);
2755
2756 return -ENOMEM;
2757}
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768int
2769ice_get_res(struct ice_pf *pf, struct ice_res_tracker *res, u16 needed, u16 id)
2770{
2771 if (!res || !pf)
2772 return -EINVAL;
2773
2774 if (!needed || needed > res->num_entries || id >= ICE_RES_VALID_BIT) {
2775 dev_err(&pf->pdev->dev,
2776 "param err: needed=%d, num_entries = %d id=0x%04x\n",
2777 needed, res->num_entries, id);
2778 return -EINVAL;
2779 }
2780
2781 return ice_search_res(res, needed, id);
2782}
2783
2784
2785
2786
2787
2788void ice_vsi_dis_irq(struct ice_vsi *vsi)
2789{
2790 int base = vsi->base_vector;
2791 struct ice_pf *pf = vsi->back;
2792 struct ice_hw *hw = &pf->hw;
2793 u32 val;
2794 int i;
2795
2796
2797 if (vsi->tx_rings) {
2798 ice_for_each_txq(vsi, i) {
2799 if (vsi->tx_rings[i]) {
2800 u16 reg;
2801
2802 reg = vsi->tx_rings[i]->reg_idx;
2803 val = rd32(hw, QINT_TQCTL(reg));
2804 val &= ~QINT_TQCTL_CAUSE_ENA_M;
2805 wr32(hw, QINT_TQCTL(reg), val);
2806 }
2807 }
2808 }
2809
2810 if (vsi->rx_rings) {
2811 ice_for_each_rxq(vsi, i) {
2812 if (vsi->rx_rings[i]) {
2813 u16 reg;
2814
2815 reg = vsi->rx_rings[i]->reg_idx;
2816 val = rd32(hw, QINT_RQCTL(reg));
2817 val &= ~QINT_RQCTL_CAUSE_ENA_M;
2818 wr32(hw, QINT_RQCTL(reg), val);
2819 }
2820 }
2821 }
2822
2823
2824 if (test_bit(ICE_FLAG_MSIX_ENA, pf->flags)) {
2825 ice_for_each_q_vector(vsi, i)
2826 wr32(hw, GLINT_DYN_CTL(vsi->q_vectors[i]->reg_idx), 0);
2827
2828 ice_flush(hw);
2829
2830 ice_for_each_q_vector(vsi, i)
2831 synchronize_irq(pf->msix_entries[i + base].vector);
2832 }
2833}
2834
2835
2836
2837
2838
2839void ice_napi_del(struct ice_vsi *vsi)
2840{
2841 int v_idx;
2842
2843 if (!vsi->netdev)
2844 return;
2845
2846 ice_for_each_q_vector(vsi, v_idx)
2847 netif_napi_del(&vsi->q_vectors[v_idx]->napi);
2848}
2849
2850
2851
2852
2853
2854
2855
2856int ice_vsi_release(struct ice_vsi *vsi)
2857{
2858 struct ice_pf *pf;
2859
2860 if (!vsi->back)
2861 return -ENODEV;
2862 pf = vsi->back;
2863
2864
2865
2866
2867
2868
2869
2870 if (vsi->netdev && !ice_is_reset_in_progress(pf->state))
2871 unregister_netdev(vsi->netdev);
2872
2873 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
2874 ice_rss_clean(vsi);
2875
2876
2877 if (vsi->type != ICE_VSI_LB)
2878 ice_vsi_dis_irq(vsi);
2879 ice_vsi_close(vsi);
2880
2881
2882
2883
2884
2885
2886 if (vsi->type != ICE_VSI_VF) {
2887
2888 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
2889 pf->num_avail_sw_msix += vsi->num_q_vectors;
2890 }
2891
2892 if (vsi->type == ICE_VSI_PF) {
2893 ice_vsi_add_rem_eth_mac(vsi, false);
2894 ice_cfg_sw_lldp(vsi, true, false);
2895
2896
2897
2898 if (!test_bit(ICE_FLAG_ENABLE_FW_LLDP, pf->flags))
2899 ice_cfg_sw_lldp(vsi, false, false);
2900 }
2901
2902 ice_remove_vsi_fltr(&pf->hw, vsi->idx);
2903 ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
2904 ice_vsi_delete(vsi);
2905 ice_vsi_free_q_vectors(vsi);
2906
2907
2908 if (vsi->netdev && test_bit(__ICE_DOWN, vsi->state)) {
2909 free_netdev(vsi->netdev);
2910 vsi->netdev = NULL;
2911 }
2912
2913 ice_vsi_clear_rings(vsi);
2914
2915 ice_vsi_put_qs(vsi);
2916 pf->q_left_tx += vsi->alloc_txq;
2917 pf->q_left_rx += vsi->alloc_rxq;
2918
2919
2920
2921
2922
2923 if (!ice_is_reset_in_progress(pf->state))
2924 ice_vsi_clear(vsi);
2925
2926 return 0;
2927}
2928
2929
2930
2931
2932
2933
2934
2935int ice_vsi_rebuild(struct ice_vsi *vsi)
2936{
2937 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
2938 struct ice_vf *vf = NULL;
2939 enum ice_status status;
2940 struct ice_pf *pf;
2941 int ret, i;
2942
2943 if (!vsi)
2944 return -EINVAL;
2945
2946 pf = vsi->back;
2947 if (vsi->type == ICE_VSI_VF)
2948 vf = &pf->vf[vsi->vf_id];
2949
2950 ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
2951 ice_vsi_free_q_vectors(vsi);
2952
2953
2954
2955
2956
2957
2958 if (vsi->type != ICE_VSI_VF) {
2959
2960 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
2961 pf->num_avail_sw_msix += vsi->num_q_vectors;
2962 vsi->base_vector = 0;
2963 }
2964
2965 ice_vsi_clear_rings(vsi);
2966 ice_vsi_free_arrays(vsi);
2967 ice_dev_onetime_setup(&pf->hw);
2968 if (vsi->type == ICE_VSI_VF)
2969 ice_vsi_set_num_qs(vsi, vf->vf_id);
2970 else
2971 ice_vsi_set_num_qs(vsi, ICE_INVAL_VFID);
2972 ice_vsi_set_tc_cfg(vsi);
2973
2974
2975 ret = ice_vsi_init(vsi);
2976 if (ret < 0)
2977 goto err_vsi;
2978
2979 ret = ice_vsi_alloc_arrays(vsi);
2980 if (ret < 0)
2981 goto err_vsi;
2982
2983 switch (vsi->type) {
2984 case ICE_VSI_PF:
2985 ret = ice_vsi_alloc_q_vectors(vsi);
2986 if (ret)
2987 goto err_rings;
2988
2989 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
2990 if (ret)
2991 goto err_vectors;
2992
2993 ret = ice_vsi_alloc_rings(vsi);
2994 if (ret)
2995 goto err_vectors;
2996
2997 ice_vsi_map_rings_to_vectors(vsi);
2998
2999
3000
3001
3002 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
3003 ice_vsi_cfg_rss_lut_key(vsi);
3004 break;
3005 case ICE_VSI_VF:
3006 ret = ice_vsi_alloc_q_vectors(vsi);
3007 if (ret)
3008 goto err_rings;
3009
3010 ret = ice_vsi_setup_vector_base(vsi);
3011 if (ret)
3012 goto err_vectors;
3013
3014 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
3015 if (ret)
3016 goto err_vectors;
3017
3018 ret = ice_vsi_alloc_rings(vsi);
3019 if (ret)
3020 goto err_vectors;
3021
3022 pf->q_left_tx -= vsi->alloc_txq;
3023 pf->q_left_rx -= vsi->alloc_rxq;
3024 break;
3025 default:
3026 break;
3027 }
3028
3029
3030 for (i = 0; i < vsi->tc_cfg.numtc; i++)
3031 max_txqs[i] = pf->num_lan_tx;
3032
3033 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
3034 max_txqs);
3035 if (status) {
3036 dev_err(&pf->pdev->dev,
3037 "VSI %d failed lan queue config, error %d\n",
3038 vsi->vsi_num, status);
3039 goto err_vectors;
3040 }
3041 return 0;
3042
3043err_vectors:
3044 ice_vsi_free_q_vectors(vsi);
3045err_rings:
3046 if (vsi->netdev) {
3047 vsi->current_netdev_flags = 0;
3048 unregister_netdev(vsi->netdev);
3049 free_netdev(vsi->netdev);
3050 vsi->netdev = NULL;
3051 }
3052err_vsi:
3053 ice_vsi_clear(vsi);
3054 set_bit(__ICE_RESET_FAILED, pf->state);
3055 return ret;
3056}
3057
3058
3059
3060
3061
3062bool ice_is_reset_in_progress(unsigned long *state)
3063{
3064 return test_bit(__ICE_RESET_OICR_RECV, state) ||
3065 test_bit(__ICE_PFR_REQ, state) ||
3066 test_bit(__ICE_CORER_REQ, state) ||
3067 test_bit(__ICE_GLOBR_REQ, state);
3068}
3069
3070#ifdef CONFIG_DCB
3071
3072
3073
3074
3075
3076static void ice_vsi_update_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctx)
3077{
3078 vsi->info.mapping_flags = ctx->info.mapping_flags;
3079 memcpy(&vsi->info.q_mapping, &ctx->info.q_mapping,
3080 sizeof(vsi->info.q_mapping));
3081 memcpy(&vsi->info.tc_mapping, ctx->info.tc_mapping,
3082 sizeof(vsi->info.tc_mapping));
3083}
3084
3085
3086
3087
3088
3089
3090static void ice_vsi_cfg_netdev_tc(struct ice_vsi *vsi, u8 ena_tc)
3091{
3092 struct net_device *netdev = vsi->netdev;
3093 struct ice_pf *pf = vsi->back;
3094 struct ice_dcbx_cfg *dcbcfg;
3095 u8 netdev_tc;
3096 int i;
3097
3098 if (!netdev)
3099 return;
3100
3101 if (!ena_tc) {
3102 netdev_reset_tc(netdev);
3103 return;
3104 }
3105
3106 if (netdev_set_num_tc(netdev, vsi->tc_cfg.numtc))
3107 return;
3108
3109 dcbcfg = &pf->hw.port_info->local_dcbx_cfg;
3110
3111 ice_for_each_traffic_class(i)
3112 if (vsi->tc_cfg.ena_tc & BIT(i))
3113 netdev_set_tc_queue(netdev,
3114 vsi->tc_cfg.tc_info[i].netdev_tc,
3115 vsi->tc_cfg.tc_info[i].qcount_tx,
3116 vsi->tc_cfg.tc_info[i].qoffset);
3117
3118 for (i = 0; i < ICE_MAX_USER_PRIORITY; i++) {
3119 u8 ets_tc = dcbcfg->etscfg.prio_table[i];
3120
3121
3122 netdev_tc = vsi->tc_cfg.tc_info[ets_tc].netdev_tc;
3123 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3124 }
3125}
3126
3127
3128
3129
3130
3131
3132
3133
3134int ice_vsi_cfg_tc(struct ice_vsi *vsi, u8 ena_tc)
3135{
3136 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
3137 struct ice_vsi_ctx *ctx;
3138 struct ice_pf *pf = vsi->back;
3139 enum ice_status status;
3140 int i, ret = 0;
3141 u8 num_tc = 0;
3142
3143 ice_for_each_traffic_class(i) {
3144
3145 if (ena_tc & BIT(i))
3146 num_tc++;
3147
3148 max_txqs[i] = pf->num_lan_tx;
3149 }
3150
3151 vsi->tc_cfg.ena_tc = ena_tc;
3152 vsi->tc_cfg.numtc = num_tc;
3153
3154 ctx = devm_kzalloc(&pf->pdev->dev, sizeof(*ctx), GFP_KERNEL);
3155 if (!ctx)
3156 return -ENOMEM;
3157
3158 ctx->vf_num = 0;
3159 ctx->info = vsi->info;
3160
3161 ice_vsi_setup_q_map(vsi, ctx);
3162
3163
3164 ctx->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
3165 status = ice_update_vsi(&pf->hw, vsi->idx, ctx, NULL);
3166 if (status) {
3167 dev_info(&pf->pdev->dev, "Failed VSI Update\n");
3168 ret = -EIO;
3169 goto out;
3170 }
3171
3172 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
3173 max_txqs);
3174
3175 if (status) {
3176 dev_err(&pf->pdev->dev,
3177 "VSI %d failed TC config, error %d\n",
3178 vsi->vsi_num, status);
3179 ret = -EIO;
3180 goto out;
3181 }
3182 ice_vsi_update_q_map(vsi, ctx);
3183 vsi->info.valid_sections = 0;
3184
3185 ice_vsi_cfg_netdev_tc(vsi, ena_tc);
3186out:
3187 devm_kfree(&pf->pdev->dev, ctx);
3188 return ret;
3189}
3190#endif
3191