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9#ifndef MTK_ETH_H
10#define MTK_ETH_H
11
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/of_net.h>
15#include <linux/u64_stats_sync.h>
16#include <linux/refcount.h>
17
18#define MTK_QDMA_PAGE_SIZE 2048
19#define MTK_MAX_RX_LENGTH 1536
20#define MTK_TX_DMA_BUF_LEN 0x3fff
21#define MTK_DMA_SIZE 256
22#define MTK_NAPI_WEIGHT 64
23#define MTK_MAC_COUNT 2
24#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
25#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
26#define MTK_DMA_DUMMY_DESC 0xffffffff
27#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
28 NETIF_MSG_PROBE | \
29 NETIF_MSG_LINK | \
30 NETIF_MSG_TIMER | \
31 NETIF_MSG_IFDOWN | \
32 NETIF_MSG_IFUP | \
33 NETIF_MSG_RX_ERR | \
34 NETIF_MSG_TX_ERR)
35#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
36 NETIF_F_RXCSUM | \
37 NETIF_F_HW_VLAN_CTAG_TX | \
38 NETIF_F_HW_VLAN_CTAG_RX | \
39 NETIF_F_SG | NETIF_F_TSO | \
40 NETIF_F_TSO6 | \
41 NETIF_F_IPV6_CSUM)
42#define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
43
44#define MTK_MAX_RX_RING_NUM 4
45#define MTK_HW_LRO_DMA_SIZE 8
46
47#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
48#define MTK_MAX_LRO_IP_CNT 2
49#define MTK_HW_LRO_TIMER_UNIT 1
50#define MTK_HW_LRO_REFRESH_TIME 50000
51#define MTK_HW_LRO_AGG_TIME 10
52#define MTK_HW_LRO_AGE_TIME 50
53#define MTK_HW_LRO_MAX_AGG_CNT 64
54#define MTK_HW_LRO_BW_THRE 3000
55#define MTK_HW_LRO_REPLACE_DELTA 1000
56#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
57
58
59#define MTK_RST_GL 0x04
60#define RST_GL_PSE BIT(0)
61
62
63#define MTK_INT_STATUS2 0x08
64#define MTK_GDM1_AF BIT(28)
65#define MTK_GDM2_AF BIT(29)
66
67
68#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
69
70
71#define MTK_FE_INT_GRP 0x20
72
73
74#define MTK_CDMQ_IG_CTRL 0x1400
75#define MTK_CDMQ_STAG_EN BIT(0)
76
77
78#define MTK_CDMP_EG_CTRL 0x404
79
80
81#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
82#define MTK_GDMA_ICS_EN BIT(22)
83#define MTK_GDMA_TCS_EN BIT(21)
84#define MTK_GDMA_UCS_EN BIT(20)
85
86
87#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
88
89
90#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
91
92
93#define MTK_PRX_BASE_PTR0 0x900
94#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
95
96
97#define MTK_PRX_MAX_CNT0 0x904
98#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
99
100
101#define MTK_PRX_CRX_IDX0 0x908
102#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
103
104
105#define MTK_PDMA_LRO_CTRL_DW0 0x980
106#define MTK_LRO_EN BIT(0)
107#define MTK_L3_CKS_UPD_EN BIT(7)
108#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
109#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
110#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
111
112#define MTK_PDMA_LRO_CTRL_DW1 0x984
113#define MTK_PDMA_LRO_CTRL_DW2 0x988
114#define MTK_PDMA_LRO_CTRL_DW3 0x98c
115#define MTK_ADMA_MODE BIT(15)
116#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
117
118
119#define MTK_PDMA_GLO_CFG 0xa04
120#define MTK_MULTI_EN BIT(10)
121
122
123#define MTK_PDMA_RST_IDX 0xa08
124#define MTK_PST_DRX_IDX0 BIT(16)
125#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
126
127
128#define MTK_PDMA_DELAY_INT 0xa0c
129#define MTK_PDMA_DELAY_RX_EN BIT(15)
130#define MTK_PDMA_DELAY_RX_PINT 4
131#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
132#define MTK_PDMA_DELAY_RX_PTIME 4
133#define MTK_PDMA_DELAY_RX_DELAY \
134 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
135 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
136
137
138#define MTK_PDMA_INT_STATUS 0xa20
139
140
141#define MTK_PDMA_INT_MASK 0xa28
142
143
144#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
145
146
147#define MTK_PDMA_INT_GRP1 0xa50
148#define MTK_PDMA_INT_GRP2 0xa54
149
150
151#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
152#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
153#define MTK_RING_MYIP_VLD BIT(9)
154
155
156#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
157#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
158#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
159#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
160#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
161#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
162#define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
163#define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
164#define MTK_RING_AUTO_LERAN_MODE (3 << 6)
165#define MTK_RING_VLD BIT(8)
166#define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
167#define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
168#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
169
170
171#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
172#define QDMA_RES_THRES 4
173
174
175#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
176
177
178#define MTK_QRX_BASE_PTR0 0x1900
179
180
181#define MTK_QRX_MAX_CNT0 0x1904
182
183
184#define MTK_QRX_CRX_IDX0 0x1908
185
186
187#define MTK_QRX_DRX_IDX0 0x190C
188
189
190#define MTK_QDMA_GLO_CFG 0x1A04
191#define MTK_RX_2B_OFFSET BIT(31)
192#define MTK_RX_BT_32DWORDS (3 << 11)
193#define MTK_NDP_CO_PRO BIT(10)
194#define MTK_TX_WB_DDONE BIT(6)
195#define MTK_DMA_SIZE_16DWORDS (2 << 4)
196#define MTK_RX_DMA_BUSY BIT(3)
197#define MTK_TX_DMA_BUSY BIT(1)
198#define MTK_RX_DMA_EN BIT(2)
199#define MTK_TX_DMA_EN BIT(0)
200#define MTK_DMA_BUSY_TIMEOUT HZ
201
202
203#define MTK_QDMA_RST_IDX 0x1A08
204
205
206#define MTK_QDMA_DELAY_INT 0x1A0C
207
208
209#define MTK_QDMA_FC_THRES 0x1A10
210#define FC_THRES_DROP_MODE BIT(20)
211#define FC_THRES_DROP_EN (7 << 16)
212#define FC_THRES_MIN 0x4444
213
214
215#define MTK_QMTK_INT_STATUS 0x1A18
216#define MTK_RX_DONE_DLY BIT(30)
217#define MTK_RX_DONE_INT3 BIT(19)
218#define MTK_RX_DONE_INT2 BIT(18)
219#define MTK_RX_DONE_INT1 BIT(17)
220#define MTK_RX_DONE_INT0 BIT(16)
221#define MTK_TX_DONE_INT3 BIT(3)
222#define MTK_TX_DONE_INT2 BIT(2)
223#define MTK_TX_DONE_INT1 BIT(1)
224#define MTK_TX_DONE_INT0 BIT(0)
225#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
226#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
227 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
228
229
230#define MTK_QDMA_INT_GRP1 0x1a20
231#define MTK_QDMA_INT_GRP2 0x1a24
232#define MTK_RLS_DONE_INT BIT(0)
233
234
235#define MTK_QDMA_INT_MASK 0x1A1C
236
237
238#define MTK_QDMA_HRED2 0x1A44
239
240
241#define MTK_QTX_CTX_PTR 0x1B00
242
243
244#define MTK_QTX_DTX_PTR 0x1B04
245
246
247#define MTK_QTX_CRX_PTR 0x1B10
248
249
250#define MTK_QTX_DRX_PTR 0x1B14
251
252
253#define MTK_QDMA_FQ_HEAD 0x1B20
254
255
256#define MTK_QDMA_FQ_TAIL 0x1B24
257
258
259#define MTK_QDMA_FQ_CNT 0x1B28
260
261
262#define MTK_QDMA_FQ_BLEN 0x1B2C
263
264
265#define MTK_GDM1_TX_GBCNT 0x2400
266#define MTK_STAT_OFFSET 0x40
267
268
269#define TX_DMA_CHKSUM (0x7 << 29)
270#define TX_DMA_TSO BIT(28)
271#define TX_DMA_FPORT_SHIFT 25
272#define TX_DMA_FPORT_MASK 0x7
273#define TX_DMA_INS_VLAN BIT(16)
274
275
276#define TX_DMA_OWNER_CPU BIT(31)
277#define TX_DMA_LS0 BIT(30)
278#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
279#define TX_DMA_SWC BIT(14)
280#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
281
282
283#define RX_DMA_DONE BIT(31)
284#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
285#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
286
287
288#define RX_DMA_VID(_x) ((_x) & 0xfff)
289
290
291#define RX_DMA_L4_VALID BIT(24)
292#define RX_DMA_FPORT_SHIFT 19
293#define RX_DMA_FPORT_MASK 0x7
294
295
296#define MTK_PHY_IAC 0x10004
297#define PHY_IAC_ACCESS BIT(31)
298#define PHY_IAC_READ BIT(19)
299#define PHY_IAC_WRITE BIT(18)
300#define PHY_IAC_START BIT(16)
301#define PHY_IAC_ADDR_SHIFT 20
302#define PHY_IAC_REG_SHIFT 25
303#define PHY_IAC_TIMEOUT HZ
304
305#define MTK_MAC_MISC 0x1000c
306#define MTK_MUX_TO_ESW BIT(0)
307
308
309#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
310#define MAC_MCR_MAX_RX_1536 BIT(24)
311#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
312#define MAC_MCR_FORCE_MODE BIT(15)
313#define MAC_MCR_TX_EN BIT(14)
314#define MAC_MCR_RX_EN BIT(13)
315#define MAC_MCR_BACKOFF_EN BIT(9)
316#define MAC_MCR_BACKPR_EN BIT(8)
317#define MAC_MCR_FORCE_RX_FC BIT(5)
318#define MAC_MCR_FORCE_TX_FC BIT(4)
319#define MAC_MCR_SPEED_1000 BIT(3)
320#define MAC_MCR_SPEED_100 BIT(2)
321#define MAC_MCR_FORCE_DPX BIT(1)
322#define MAC_MCR_FORCE_LINK BIT(0)
323#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
324 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
325 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
326 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
327 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
328 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
329
330
331#define TRGMII_RCK_CTRL 0x10300
332#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
333#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
334#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
335#define RXC_DQSISEL BIT(30)
336#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
337#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
338
339
340#define TRGMII_TCK_CTRL 0x10340
341#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
342#define TXC_INV BIT(30)
343#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
344#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
345
346
347#define INTF_MODE 0x10390
348#define TRGMII_INTF_DIS BIT(0)
349#define TRGMII_MODE BIT(1)
350#define TRGMII_CENTRAL_ALIGNED BIT(2)
351#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
352#define INTF_MODE_RGMII_10_100 0
353
354
355#define GPIO_OD33_CTRL8 0x4c0
356#define GPIO_BIAS_CTRL 0xed0
357#define GPIO_DRV_SEL10 0xf00
358
359
360#define ETHSYS_CHIPID0_3 0x0
361#define ETHSYS_CHIPID4_7 0x4
362#define MT7623_ETH 7623
363#define MT7622_ETH 7622
364#define MT7621_ETH 7621
365
366
367#define ETHSYS_SYSCFG 0x10
368#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
369
370
371#define ETHSYS_SYSCFG0 0x14
372#define SYSCFG0_GE_MASK 0x3
373#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
374#define SYSCFG0_SGMII_MASK GENMASK(9, 8)
375#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
376#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
377#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
378#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
379
380
381
382#define ETHSYS_CLKCFG0 0x2c
383#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
384#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
385#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
386#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
387
388
389#define ETHSYS_RSTCTRL 0x34
390#define RSTCTRL_FE BIT(6)
391#define RSTCTRL_PPE BIT(31)
392
393
394
395#define SGMSYS_PCS_CONTROL_1 0x0
396#define SGMII_AN_RESTART BIT(9)
397
398
399#define SGMSYS_PCS_LINK_TIMER 0x18
400#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
401
402
403#define SGMSYS_SGMII_MODE 0x20
404#define SGMII_REMOTE_FAULT_DIS BIT(8)
405
406
407#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
408#define SGMII_PHYA_PWD BIT(4)
409
410
411#define INFRA_MISC2 0x70c
412#define CO_QPHY_SEL BIT(0)
413#define GEPHY_MAC_SEL BIT(1)
414
415struct mtk_rx_dma {
416 unsigned int rxd1;
417 unsigned int rxd2;
418 unsigned int rxd3;
419 unsigned int rxd4;
420} __packed __aligned(4);
421
422struct mtk_tx_dma {
423 unsigned int txd1;
424 unsigned int txd2;
425 unsigned int txd3;
426 unsigned int txd4;
427} __packed __aligned(4);
428
429struct mtk_eth;
430struct mtk_mac;
431
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440
441struct mtk_hw_stats {
442 u64 tx_bytes;
443 u64 tx_packets;
444 u64 tx_skip;
445 u64 tx_collisions;
446 u64 rx_bytes;
447 u64 rx_packets;
448 u64 rx_overflow;
449 u64 rx_fcs_errors;
450 u64 rx_short_errors;
451 u64 rx_long_errors;
452 u64 rx_checksum_errors;
453 u64 rx_flow_control_packets;
454
455 spinlock_t stats_lock;
456 u32 reg_offset;
457 struct u64_stats_sync syncp;
458};
459
460enum mtk_tx_flags {
461
462
463
464 MTK_TX_FLAGS_SINGLE0 = 0x01,
465 MTK_TX_FLAGS_PAGE0 = 0x02,
466
467
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469
470 MTK_TX_FLAGS_FPORT0 = 0x04,
471 MTK_TX_FLAGS_FPORT1 = 0x08,
472};
473
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475
476
477enum mtk_clks_map {
478 MTK_CLK_ETHIF,
479 MTK_CLK_SGMIITOP,
480 MTK_CLK_ESW,
481 MTK_CLK_GP0,
482 MTK_CLK_GP1,
483 MTK_CLK_GP2,
484 MTK_CLK_FE,
485 MTK_CLK_TRGPLL,
486 MTK_CLK_SGMII_TX_250M,
487 MTK_CLK_SGMII_RX_250M,
488 MTK_CLK_SGMII_CDR_REF,
489 MTK_CLK_SGMII_CDR_FB,
490 MTK_CLK_SGMII2_TX_250M,
491 MTK_CLK_SGMII2_RX_250M,
492 MTK_CLK_SGMII2_CDR_REF,
493 MTK_CLK_SGMII2_CDR_FB,
494 MTK_CLK_SGMII_CK,
495 MTK_CLK_ETH2PLL,
496 MTK_CLK_MAX
497};
498
499#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
500 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
501 BIT(MTK_CLK_TRGPLL))
502#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
503 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
504 BIT(MTK_CLK_GP2) | \
505 BIT(MTK_CLK_SGMII_TX_250M) | \
506 BIT(MTK_CLK_SGMII_RX_250M) | \
507 BIT(MTK_CLK_SGMII_CDR_REF) | \
508 BIT(MTK_CLK_SGMII_CDR_FB) | \
509 BIT(MTK_CLK_SGMII_CK) | \
510 BIT(MTK_CLK_ETH2PLL))
511#define MT7621_CLKS_BITMAP (0)
512#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
513 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
514 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
515 BIT(MTK_CLK_SGMII_TX_250M) | \
516 BIT(MTK_CLK_SGMII_RX_250M) | \
517 BIT(MTK_CLK_SGMII_CDR_REF) | \
518 BIT(MTK_CLK_SGMII_CDR_FB) | \
519 BIT(MTK_CLK_SGMII2_TX_250M) | \
520 BIT(MTK_CLK_SGMII2_RX_250M) | \
521 BIT(MTK_CLK_SGMII2_CDR_REF) | \
522 BIT(MTK_CLK_SGMII2_CDR_FB) | \
523 BIT(MTK_CLK_SGMII_CK) | \
524 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
525
526enum mtk_dev_state {
527 MTK_HW_INIT,
528 MTK_RESETTING
529};
530
531
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536
537
538
539struct mtk_tx_buf {
540 struct sk_buff *skb;
541 u32 flags;
542 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
543 DEFINE_DMA_UNMAP_LEN(dma_len0);
544 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
545 DEFINE_DMA_UNMAP_LEN(dma_len1);
546};
547
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557
558struct mtk_tx_ring {
559 struct mtk_tx_dma *dma;
560 struct mtk_tx_buf *buf;
561 dma_addr_t phys;
562 struct mtk_tx_dma *next_free;
563 struct mtk_tx_dma *last_free;
564 u16 thresh;
565 atomic_t free_count;
566};
567
568
569enum mtk_rx_flags {
570 MTK_RX_FLAGS_NORMAL = 0,
571 MTK_RX_FLAGS_HWLRO,
572 MTK_RX_FLAGS_QDMA,
573};
574
575
576
577
578
579
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581
582
583struct mtk_rx_ring {
584 struct mtk_rx_dma *dma;
585 u8 **data;
586 dma_addr_t phys;
587 u16 frag_size;
588 u16 buf_size;
589 u16 dma_size;
590 bool calc_idx_update;
591 u16 calc_idx;
592 u32 crx_idx_reg;
593};
594
595enum mkt_eth_capabilities {
596 MTK_RGMII_BIT = 0,
597 MTK_TRGMII_BIT,
598 MTK_SGMII_BIT,
599 MTK_ESW_BIT,
600 MTK_GEPHY_BIT,
601 MTK_MUX_BIT,
602 MTK_INFRA_BIT,
603 MTK_SHARED_SGMII_BIT,
604 MTK_HWLRO_BIT,
605 MTK_SHARED_INT_BIT,
606 MTK_TRGMII_MT7621_CLK_BIT,
607
608
609 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
610 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
611 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
612 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
613 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
614
615
616 MTK_ETH_PATH_GMAC1_RGMII_BIT,
617 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
618 MTK_ETH_PATH_GMAC1_SGMII_BIT,
619 MTK_ETH_PATH_GMAC2_RGMII_BIT,
620 MTK_ETH_PATH_GMAC2_SGMII_BIT,
621 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
622 MTK_ETH_PATH_GDM1_ESW_BIT,
623};
624
625
626#define MTK_RGMII BIT(MTK_RGMII_BIT)
627#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
628#define MTK_SGMII BIT(MTK_SGMII_BIT)
629#define MTK_ESW BIT(MTK_ESW_BIT)
630#define MTK_GEPHY BIT(MTK_GEPHY_BIT)
631#define MTK_MUX BIT(MTK_MUX_BIT)
632#define MTK_INFRA BIT(MTK_INFRA_BIT)
633#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
634#define MTK_HWLRO BIT(MTK_HWLRO_BIT)
635#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
636#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
637
638#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
639 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
640#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
641 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
642#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
643 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
644#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
645 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
646#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
647 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
648
649
650#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
651#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
652#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
653#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
654#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
655#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
656#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
657
658#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
659#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
660#define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
661#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
662#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
663#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
664#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
665
666
667
668#define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
669
670
671#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
672 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
673
674
675#define MTK_MUX_U3_GMAC2_TO_QPHY \
676 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
677
678
679#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
680 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
681 MTK_SHARED_SGMII)
682
683
684#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
685 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
686
687#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
688
689#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
690 MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK)
691
692#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
693 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
694 MTK_MUX_GDM1_TO_GMAC1_ESW | \
695 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII)
696
697#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII)
698
699#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
700 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
701 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
702 MTK_MUX_U3_GMAC2_TO_QPHY | \
703 MTK_MUX_GMAC12_TO_GEPHY_SGMII)
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715struct mtk_soc_data {
716 u32 ana_rgc3;
717 u32 caps;
718 u32 required_clks;
719 bool required_pctl;
720};
721
722
723#define MTK_MAX_DEVS 2
724
725#define MTK_SGMII_PHYSPEED_AN BIT(31)
726#define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
727#define MTK_SGMII_PHYSPEED_1000 BIT(0)
728#define MTK_SGMII_PHYSPEED_2500 BIT(1)
729#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
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738
739struct mtk_sgmii {
740 struct regmap *regmap[MTK_MAX_DEVS];
741 u32 flags[MTK_MAX_DEVS];
742 u32 ana_rgc3;
743};
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780struct mtk_eth {
781 struct device *dev;
782 void __iomem *base;
783 spinlock_t page_lock;
784 spinlock_t tx_irq_lock;
785 spinlock_t rx_irq_lock;
786 struct net_device dummy_dev;
787 struct net_device *netdev[MTK_MAX_DEVS];
788 struct mtk_mac *mac[MTK_MAX_DEVS];
789 int irq[3];
790 u32 msg_enable;
791 unsigned long sysclk;
792 struct regmap *ethsys;
793 struct regmap *infra;
794 struct mtk_sgmii *sgmii;
795 struct regmap *pctl;
796 bool hwlro;
797 refcount_t dma_refcnt;
798 struct mtk_tx_ring tx_ring;
799 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
800 struct mtk_rx_ring rx_ring_qdma;
801 struct napi_struct tx_napi;
802 struct napi_struct rx_napi;
803 struct mtk_tx_dma *scratch_ring;
804 dma_addr_t phy_scratch_ring;
805 void *scratch_head;
806 struct clk *clks[MTK_CLK_MAX];
807
808 struct mii_bus *mii_bus;
809 struct work_struct pending_work;
810 unsigned long state;
811
812 const struct mtk_soc_data *soc;
813};
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825struct mtk_mac {
826 int id;
827 int ge_mode;
828 struct device_node *of_node;
829 struct mtk_eth *hw;
830 struct mtk_hw_stats *hw_stats;
831 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
832 int hwlro_ip_cnt;
833 bool trgmii;
834};
835
836
837extern const struct of_device_id of_mtk_match[];
838
839
840void mtk_stats_update_mac(struct mtk_mac *mac);
841
842void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
843u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
844
845int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
846 u32 ana_rgc3);
847int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
848int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id);
849int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode);
850
851#endif
852