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33#include "en.h"
34#include "en/port.h"
35#include "en/xsk/umem.h"
36#include "lib/clock.h"
37
38void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
40{
41 struct mlx5_core_dev *mdev = priv->mdev;
42
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
44 strlcpy(drvinfo->version, DRIVER_VERSION,
45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
47 "%d.%d.%04d (%.16s)",
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 mdev->board_id);
50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
51 sizeof(drvinfo->bus_info));
52}
53
54static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
56{
57 struct mlx5e_priv *priv = netdev_priv(dev);
58
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
60}
61
62struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
65};
66
67static
68struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
69static
70struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
71
72#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
73 ({ \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
87 } \
88 })
89
90void mlx5e_build_ptys2ethtool_map(void)
91{
92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
170 ext,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
197}
198
199static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
200 struct ptys2ethtool_config **arr,
201 u32 *size)
202{
203 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
204
205 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
206 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
207 ARRAY_SIZE(ptys2legacy_ethtool_table);
208}
209
210typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
211
212struct pflag_desc {
213 char name[ETH_GSTRING_LEN];
214 mlx5e_pflag_handler handler;
215};
216
217static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
218
219int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
220{
221 int i, num_stats = 0;
222
223 switch (sset) {
224 case ETH_SS_STATS:
225 for (i = 0; i < mlx5e_num_stats_grps; i++)
226 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
227 return num_stats;
228 case ETH_SS_PRIV_FLAGS:
229 return MLX5E_NUM_PFLAGS;
230 case ETH_SS_TEST:
231 return mlx5e_self_test_num(priv);
232
233 default:
234 return -EOPNOTSUPP;
235 }
236}
237
238static int mlx5e_get_sset_count(struct net_device *dev, int sset)
239{
240 struct mlx5e_priv *priv = netdev_priv(dev);
241
242 return mlx5e_ethtool_get_sset_count(priv, sset);
243}
244
245static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
246{
247 int i, idx = 0;
248
249 for (i = 0; i < mlx5e_num_stats_grps; i++)
250 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
251}
252
253void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
254{
255 int i;
256
257 switch (stringset) {
258 case ETH_SS_PRIV_FLAGS:
259 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
260 strcpy(data + i * ETH_GSTRING_LEN,
261 mlx5e_priv_flags[i].name);
262 break;
263
264 case ETH_SS_TEST:
265 for (i = 0; i < mlx5e_self_test_num(priv); i++)
266 strcpy(data + i * ETH_GSTRING_LEN,
267 mlx5e_self_tests[i]);
268 break;
269
270 case ETH_SS_STATS:
271 mlx5e_fill_stats_strings(priv, data);
272 break;
273 }
274}
275
276static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
277{
278 struct mlx5e_priv *priv = netdev_priv(dev);
279
280 mlx5e_ethtool_get_strings(priv, stringset, data);
281}
282
283void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
284 struct ethtool_stats *stats, u64 *data)
285{
286 int i, idx = 0;
287
288 mutex_lock(&priv->state_lock);
289 mlx5e_update_stats(priv);
290 mutex_unlock(&priv->state_lock);
291
292 for (i = 0; i < mlx5e_num_stats_grps; i++)
293 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
294}
295
296static void mlx5e_get_ethtool_stats(struct net_device *dev,
297 struct ethtool_stats *stats,
298 u64 *data)
299{
300 struct mlx5e_priv *priv = netdev_priv(dev);
301
302 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
303}
304
305void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
306 struct ethtool_ringparam *param)
307{
308 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
309 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
310 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
311 param->tx_pending = 1 << priv->channels.params.log_sq_size;
312}
313
314static void mlx5e_get_ringparam(struct net_device *dev,
315 struct ethtool_ringparam *param)
316{
317 struct mlx5e_priv *priv = netdev_priv(dev);
318
319 mlx5e_ethtool_get_ringparam(priv, param);
320}
321
322int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
323 struct ethtool_ringparam *param)
324{
325 struct mlx5e_channels new_channels = {};
326 u8 log_rq_size;
327 u8 log_sq_size;
328 int err = 0;
329
330 if (param->rx_jumbo_pending) {
331 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
332 __func__);
333 return -EINVAL;
334 }
335 if (param->rx_mini_pending) {
336 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
337 __func__);
338 return -EINVAL;
339 }
340
341 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
342 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
343 __func__, param->rx_pending,
344 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
345 return -EINVAL;
346 }
347
348 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
349 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
350 __func__, param->tx_pending,
351 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
352 return -EINVAL;
353 }
354
355 log_rq_size = order_base_2(param->rx_pending);
356 log_sq_size = order_base_2(param->tx_pending);
357
358 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
359 log_sq_size == priv->channels.params.log_sq_size)
360 return 0;
361
362 mutex_lock(&priv->state_lock);
363
364 new_channels.params = priv->channels.params;
365 new_channels.params.log_rq_mtu_frames = log_rq_size;
366 new_channels.params.log_sq_size = log_sq_size;
367
368 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
369 priv->channels.params = new_channels.params;
370 goto unlock;
371 }
372
373 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
374
375unlock:
376 mutex_unlock(&priv->state_lock);
377
378 return err;
379}
380
381static int mlx5e_set_ringparam(struct net_device *dev,
382 struct ethtool_ringparam *param)
383{
384 struct mlx5e_priv *priv = netdev_priv(dev);
385
386 return mlx5e_ethtool_set_ringparam(priv, param);
387}
388
389void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
390 struct ethtool_channels *ch)
391{
392 mutex_lock(&priv->state_lock);
393
394 ch->max_combined = priv->max_nch;
395 ch->combined_count = priv->channels.params.num_channels;
396 if (priv->xsk.refcnt) {
397
398 ch->max_combined *= 2;
399 ch->combined_count *= 2;
400 }
401
402 mutex_unlock(&priv->state_lock);
403}
404
405static void mlx5e_get_channels(struct net_device *dev,
406 struct ethtool_channels *ch)
407{
408 struct mlx5e_priv *priv = netdev_priv(dev);
409
410 mlx5e_ethtool_get_channels(priv, ch);
411}
412
413int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
414 struct ethtool_channels *ch)
415{
416 struct mlx5e_params *cur_params = &priv->channels.params;
417 unsigned int count = ch->combined_count;
418 struct mlx5e_channels new_channels = {};
419 bool arfs_enabled;
420 int err = 0;
421
422 if (!count) {
423 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
424 __func__);
425 return -EINVAL;
426 }
427
428 if (cur_params->num_channels == count)
429 return 0;
430
431 mutex_lock(&priv->state_lock);
432
433
434
435
436 if (priv->xsk.refcnt) {
437 err = -EINVAL;
438 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
439 __func__);
440 goto out;
441 }
442
443 new_channels.params = priv->channels.params;
444 new_channels.params.num_channels = count;
445
446 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
447 *cur_params = new_channels.params;
448 if (!netif_is_rxfh_configured(priv->netdev))
449 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
450 MLX5E_INDIR_RQT_SIZE, count);
451 goto out;
452 }
453
454 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
455 if (arfs_enabled)
456 mlx5e_arfs_disable(priv);
457
458 if (!netif_is_rxfh_configured(priv->netdev))
459 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
460 MLX5E_INDIR_RQT_SIZE, count);
461
462
463 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
464
465 if (arfs_enabled) {
466 int err2 = mlx5e_arfs_enable(priv);
467
468 if (err2)
469 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
470 __func__, err2);
471 }
472
473out:
474 mutex_unlock(&priv->state_lock);
475
476 return err;
477}
478
479static int mlx5e_set_channels(struct net_device *dev,
480 struct ethtool_channels *ch)
481{
482 struct mlx5e_priv *priv = netdev_priv(dev);
483
484 return mlx5e_ethtool_set_channels(priv, ch);
485}
486
487int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
488 struct ethtool_coalesce *coal)
489{
490 struct dim_cq_moder *rx_moder, *tx_moder;
491
492 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
493 return -EOPNOTSUPP;
494
495 rx_moder = &priv->channels.params.rx_cq_moderation;
496 coal->rx_coalesce_usecs = rx_moder->usec;
497 coal->rx_max_coalesced_frames = rx_moder->pkts;
498 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
499
500 tx_moder = &priv->channels.params.tx_cq_moderation;
501 coal->tx_coalesce_usecs = tx_moder->usec;
502 coal->tx_max_coalesced_frames = tx_moder->pkts;
503 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
504
505 return 0;
506}
507
508static int mlx5e_get_coalesce(struct net_device *netdev,
509 struct ethtool_coalesce *coal)
510{
511 struct mlx5e_priv *priv = netdev_priv(netdev);
512
513 return mlx5e_ethtool_get_coalesce(priv, coal);
514}
515
516#define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
517#define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
518
519static void
520mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
521{
522 struct mlx5_core_dev *mdev = priv->mdev;
523 int tc;
524 int i;
525
526 for (i = 0; i < priv->channels.num; ++i) {
527 struct mlx5e_channel *c = priv->channels.c[i];
528
529 for (tc = 0; tc < c->num_tc; tc++) {
530 mlx5_core_modify_cq_moderation(mdev,
531 &c->sq[tc].cq.mcq,
532 coal->tx_coalesce_usecs,
533 coal->tx_max_coalesced_frames);
534 }
535
536 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
537 coal->rx_coalesce_usecs,
538 coal->rx_max_coalesced_frames);
539 }
540}
541
542int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
543 struct ethtool_coalesce *coal)
544{
545 struct dim_cq_moder *rx_moder, *tx_moder;
546 struct mlx5_core_dev *mdev = priv->mdev;
547 struct mlx5e_channels new_channels = {};
548 int err = 0;
549 bool reset;
550
551 if (!MLX5_CAP_GEN(mdev, cq_moderation))
552 return -EOPNOTSUPP;
553
554 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
555 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
556 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
557 __func__, MLX5E_MAX_COAL_TIME);
558 return -ERANGE;
559 }
560
561 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
562 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
563 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
564 __func__, MLX5E_MAX_COAL_FRAMES);
565 return -ERANGE;
566 }
567
568 mutex_lock(&priv->state_lock);
569 new_channels.params = priv->channels.params;
570
571 rx_moder = &new_channels.params.rx_cq_moderation;
572 rx_moder->usec = coal->rx_coalesce_usecs;
573 rx_moder->pkts = coal->rx_max_coalesced_frames;
574 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
575
576 tx_moder = &new_channels.params.tx_cq_moderation;
577 tx_moder->usec = coal->tx_coalesce_usecs;
578 tx_moder->pkts = coal->tx_max_coalesced_frames;
579 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
580
581 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
582 priv->channels.params = new_channels.params;
583 goto out;
584 }
585
586
587 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
588 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
589
590 if (!reset) {
591 mlx5e_set_priv_channels_coalesce(priv, coal);
592 priv->channels.params = new_channels.params;
593 goto out;
594 }
595
596 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
597
598out:
599 mutex_unlock(&priv->state_lock);
600 return err;
601}
602
603static int mlx5e_set_coalesce(struct net_device *netdev,
604 struct ethtool_coalesce *coal)
605{
606 struct mlx5e_priv *priv = netdev_priv(netdev);
607
608 return mlx5e_ethtool_set_coalesce(priv, coal);
609}
610
611static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
612 unsigned long *supported_modes,
613 u32 eth_proto_cap)
614{
615 unsigned long proto_cap = eth_proto_cap;
616 struct ptys2ethtool_config *table;
617 u32 max_size;
618 int proto;
619
620 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
621 for_each_set_bit(proto, &proto_cap, max_size)
622 bitmap_or(supported_modes, supported_modes,
623 table[proto].supported,
624 __ETHTOOL_LINK_MODE_MASK_NBITS);
625}
626
627static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
628 u32 eth_proto_cap, bool ext)
629{
630 unsigned long proto_cap = eth_proto_cap;
631 struct ptys2ethtool_config *table;
632 u32 max_size;
633 int proto;
634
635 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
636 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
637 ARRAY_SIZE(ptys2legacy_ethtool_table);
638
639 for_each_set_bit(proto, &proto_cap, max_size)
640 bitmap_or(advertising_modes, advertising_modes,
641 table[proto].advertised,
642 __ETHTOOL_LINK_MODE_MASK_NBITS);
643}
644
645static const u32 pplm_fec_2_ethtool[] = {
646 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
647 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
648 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
649};
650
651static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
652{
653 int mode = 0;
654
655 if (!fec_mode)
656 return ETHTOOL_FEC_AUTO;
657
658 mode = find_first_bit(&fec_mode, size);
659
660 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
661 return pplm_fec_2_ethtool[mode];
662
663 return 0;
664}
665
666
667static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
668{
669 u32 offset;
670
671 offset = find_first_bit(ðtool_fec_code, sizeof(u32));
672 offset -= ETHTOOL_FEC_OFF_BIT;
673 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
674
675 return offset;
676}
677
678static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
679 struct ethtool_link_ksettings *link_ksettings)
680{
681 u_long fec_caps = 0;
682 u32 active_fec = 0;
683 u32 offset;
684 u32 bitn;
685 int err;
686
687 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
688 if (err)
689 return (err == -EOPNOTSUPP) ? 0 : err;
690
691 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
692 if (err)
693 return err;
694
695 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
696 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
697
698 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
699 __set_bit(offset, link_ksettings->link_modes.supported);
700 }
701
702 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
703 offset = ethtool_fec2ethtool_caps(active_fec);
704 __set_bit(offset, link_ksettings->link_modes.advertising);
705
706 return 0;
707}
708
709static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
710 u32 eth_proto_cap,
711 u8 connector_type)
712{
713 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
714 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
715 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
716 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
717 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
718 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
719 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
720 ethtool_link_ksettings_add_link_mode(link_ksettings,
721 supported,
722 FIBRE);
723 ethtool_link_ksettings_add_link_mode(link_ksettings,
724 advertising,
725 FIBRE);
726 }
727
728 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
729 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
730 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
731 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
732 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
733 ethtool_link_ksettings_add_link_mode(link_ksettings,
734 supported,
735 Backplane);
736 ethtool_link_ksettings_add_link_mode(link_ksettings,
737 advertising,
738 Backplane);
739 }
740 return;
741 }
742
743 switch (connector_type) {
744 case MLX5E_PORT_TP:
745 ethtool_link_ksettings_add_link_mode(link_ksettings,
746 supported, TP);
747 ethtool_link_ksettings_add_link_mode(link_ksettings,
748 advertising, TP);
749 break;
750 case MLX5E_PORT_AUI:
751 ethtool_link_ksettings_add_link_mode(link_ksettings,
752 supported, AUI);
753 ethtool_link_ksettings_add_link_mode(link_ksettings,
754 advertising, AUI);
755 break;
756 case MLX5E_PORT_BNC:
757 ethtool_link_ksettings_add_link_mode(link_ksettings,
758 supported, BNC);
759 ethtool_link_ksettings_add_link_mode(link_ksettings,
760 advertising, BNC);
761 break;
762 case MLX5E_PORT_MII:
763 ethtool_link_ksettings_add_link_mode(link_ksettings,
764 supported, MII);
765 ethtool_link_ksettings_add_link_mode(link_ksettings,
766 advertising, MII);
767 break;
768 case MLX5E_PORT_FIBRE:
769 ethtool_link_ksettings_add_link_mode(link_ksettings,
770 supported, FIBRE);
771 ethtool_link_ksettings_add_link_mode(link_ksettings,
772 advertising, FIBRE);
773 break;
774 case MLX5E_PORT_DA:
775 ethtool_link_ksettings_add_link_mode(link_ksettings,
776 supported, Backplane);
777 ethtool_link_ksettings_add_link_mode(link_ksettings,
778 advertising, Backplane);
779 break;
780 case MLX5E_PORT_NONE:
781 case MLX5E_PORT_OTHER:
782 default:
783 break;
784 }
785}
786
787static void get_speed_duplex(struct net_device *netdev,
788 u32 eth_proto_oper, bool force_legacy,
789 struct ethtool_link_ksettings *link_ksettings)
790{
791 struct mlx5e_priv *priv = netdev_priv(netdev);
792 u32 speed = SPEED_UNKNOWN;
793 u8 duplex = DUPLEX_UNKNOWN;
794
795 if (!netif_carrier_ok(netdev))
796 goto out;
797
798 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
799 if (!speed) {
800 speed = SPEED_UNKNOWN;
801 goto out;
802 }
803
804 duplex = DUPLEX_FULL;
805
806out:
807 link_ksettings->base.speed = speed;
808 link_ksettings->base.duplex = duplex;
809}
810
811static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
812 struct ethtool_link_ksettings *link_ksettings)
813{
814 unsigned long *supported = link_ksettings->link_modes.supported;
815 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
816
817 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
818}
819
820static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
821 struct ethtool_link_ksettings *link_ksettings,
822 bool ext)
823{
824 unsigned long *advertising = link_ksettings->link_modes.advertising;
825 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
826
827 if (rx_pause)
828 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
829 if (tx_pause ^ rx_pause)
830 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
831}
832
833static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
834 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
835 [MLX5E_PORT_NONE] = PORT_NONE,
836 [MLX5E_PORT_TP] = PORT_TP,
837 [MLX5E_PORT_AUI] = PORT_AUI,
838 [MLX5E_PORT_BNC] = PORT_BNC,
839 [MLX5E_PORT_MII] = PORT_MII,
840 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
841 [MLX5E_PORT_DA] = PORT_DA,
842 [MLX5E_PORT_OTHER] = PORT_OTHER,
843 };
844
845static u8 get_connector_port(u32 eth_proto, u8 connector_type)
846{
847 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
848 return ptys2connector_type[connector_type];
849
850 if (eth_proto &
851 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
852 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
853 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
854 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
855 return PORT_FIBRE;
856 }
857
858 if (eth_proto &
859 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
860 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
861 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
862 return PORT_DA;
863 }
864
865 if (eth_proto &
866 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
867 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
868 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
869 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
870 return PORT_NONE;
871 }
872
873 return PORT_OTHER;
874}
875
876static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
877 struct ethtool_link_ksettings *link_ksettings)
878{
879 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
880 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
881
882 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
883}
884
885int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
886 struct ethtool_link_ksettings *link_ksettings)
887{
888 struct mlx5_core_dev *mdev = priv->mdev;
889 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
890 u32 rx_pause = 0;
891 u32 tx_pause = 0;
892 u32 eth_proto_cap;
893 u32 eth_proto_admin;
894 u32 eth_proto_lp;
895 u32 eth_proto_oper;
896 u8 an_disable_admin;
897 u8 an_status;
898 u8 connector_type;
899 bool admin_ext;
900 bool ext;
901 int err;
902
903 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
904 if (err) {
905 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
906 __func__, err);
907 goto err_query_regs;
908 }
909 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
910 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
911 eth_proto_capability);
912 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
913 eth_proto_admin);
914
915
916
917
918
919
920 admin_ext = ext;
921 if (ext && !eth_proto_admin) {
922 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
923 eth_proto_admin);
924 admin_ext = false;
925 }
926
927 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
928 eth_proto_oper);
929 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
930 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
931 an_status = MLX5_GET(ptys_reg, out, an_status);
932 connector_type = MLX5_GET(ptys_reg, out, connector_type);
933
934 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
935
936 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
937 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
938
939 get_supported(mdev, eth_proto_cap, link_ksettings);
940 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
941 admin_ext);
942 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
943 link_ksettings);
944
945 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
946
947 link_ksettings->base.port = get_connector_port(eth_proto_oper,
948 connector_type);
949 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
950 connector_type);
951 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
952
953 if (an_status == MLX5_AN_COMPLETE)
954 ethtool_link_ksettings_add_link_mode(link_ksettings,
955 lp_advertising, Autoneg);
956
957 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
958 AUTONEG_ENABLE;
959 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
960 Autoneg);
961
962 err = get_fec_supported_advertised(mdev, link_ksettings);
963 if (err) {
964 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
965 __func__, err);
966 err = 0;
967 }
968
969 if (!an_disable_admin)
970 ethtool_link_ksettings_add_link_mode(link_ksettings,
971 advertising, Autoneg);
972
973err_query_regs:
974 return err;
975}
976
977static int mlx5e_get_link_ksettings(struct net_device *netdev,
978 struct ethtool_link_ksettings *link_ksettings)
979{
980 struct mlx5e_priv *priv = netdev_priv(netdev);
981
982 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
983}
984
985static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
986{
987 u32 i, ptys_modes = 0;
988
989 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
990 if (*ptys2legacy_ethtool_table[i].advertised == 0)
991 continue;
992 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
993 link_modes,
994 __ETHTOOL_LINK_MODE_MASK_NBITS))
995 ptys_modes |= MLX5E_PROT_MASK(i);
996 }
997
998 return ptys_modes;
999}
1000
1001static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1002{
1003 u32 i, ptys_modes = 0;
1004 unsigned long modes[2];
1005
1006 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1007 if (*ptys2ext_ethtool_table[i].advertised == 0)
1008 continue;
1009 memset(modes, 0, sizeof(modes));
1010 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1011 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1012
1013 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1014 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1015 ptys_modes |= MLX5E_PROT_MASK(i);
1016 }
1017 return ptys_modes;
1018}
1019
1020static bool ext_link_mode_requested(const unsigned long *adver)
1021{
1022#define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1023 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1024 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes);
1025
1026 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1027 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1028}
1029
1030static bool ext_speed_requested(u32 speed)
1031{
1032#define MLX5E_MAX_PTYS_LEGACY_SPEED 100000
1033 return !!(speed > MLX5E_MAX_PTYS_LEGACY_SPEED);
1034}
1035
1036static bool ext_requested(u8 autoneg, const unsigned long *adver, u32 speed)
1037{
1038 bool ext_link_mode = ext_link_mode_requested(adver);
1039 bool ext_speed = ext_speed_requested(speed);
1040
1041 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_speed;
1042}
1043
1044int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1045 const struct ethtool_link_ksettings *link_ksettings)
1046{
1047 struct mlx5_core_dev *mdev = priv->mdev;
1048 struct mlx5e_port_eth_proto eproto;
1049 const unsigned long *adver;
1050 bool an_changes = false;
1051 u8 an_disable_admin;
1052 bool ext_supported;
1053 u8 an_disable_cap;
1054 bool an_disable;
1055 u32 link_modes;
1056 u8 an_status;
1057 u8 autoneg;
1058 u32 speed;
1059 bool ext;
1060 int err;
1061
1062 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1063
1064 adver = link_ksettings->link_modes.advertising;
1065 autoneg = link_ksettings->base.autoneg;
1066 speed = link_ksettings->base.speed;
1067
1068 ext = ext_requested(autoneg, adver, speed),
1069 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
1070 if (!ext_supported && ext)
1071 return -EOPNOTSUPP;
1072
1073 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1074 mlx5e_ethtool2ptys_adver_link;
1075 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1076 if (err) {
1077 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1078 __func__, err);
1079 goto out;
1080 }
1081 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1082 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1083
1084 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1085 autoneg != AUTONEG_ENABLE) {
1086 netdev_err(priv->netdev, "%s: 56G link speed requires autoneg enabled\n",
1087 __func__);
1088 err = -EINVAL;
1089 goto out;
1090 }
1091
1092 link_modes = link_modes & eproto.cap;
1093 if (!link_modes) {
1094 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1095 __func__);
1096 err = -EINVAL;
1097 goto out;
1098 }
1099
1100 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1101 &an_disable_admin);
1102
1103 an_disable = autoneg == AUTONEG_DISABLE;
1104 an_changes = ((!an_disable && an_disable_admin) ||
1105 (an_disable && !an_disable_admin));
1106
1107 if (!an_changes && link_modes == eproto.admin)
1108 goto out;
1109
1110 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1111 mlx5_toggle_port_link(mdev);
1112
1113out:
1114 return err;
1115}
1116
1117static int mlx5e_set_link_ksettings(struct net_device *netdev,
1118 const struct ethtool_link_ksettings *link_ksettings)
1119{
1120 struct mlx5e_priv *priv = netdev_priv(netdev);
1121
1122 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1123}
1124
1125u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1126{
1127 return sizeof(priv->rss_params.toeplitz_hash_key);
1128}
1129
1130static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1131{
1132 struct mlx5e_priv *priv = netdev_priv(netdev);
1133
1134 return mlx5e_ethtool_get_rxfh_key_size(priv);
1135}
1136
1137u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1138{
1139 return MLX5E_INDIR_RQT_SIZE;
1140}
1141
1142static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1143{
1144 struct mlx5e_priv *priv = netdev_priv(netdev);
1145
1146 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1147}
1148
1149static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1150 u8 *hfunc)
1151{
1152 struct mlx5e_priv *priv = netdev_priv(netdev);
1153 struct mlx5e_rss_params *rss = &priv->rss_params;
1154
1155 if (indir)
1156 memcpy(indir, rss->indirection_rqt,
1157 sizeof(rss->indirection_rqt));
1158
1159 if (key)
1160 memcpy(key, rss->toeplitz_hash_key,
1161 sizeof(rss->toeplitz_hash_key));
1162
1163 if (hfunc)
1164 *hfunc = rss->hfunc;
1165
1166 return 0;
1167}
1168
1169static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1170 const u8 *key, const u8 hfunc)
1171{
1172 struct mlx5e_priv *priv = netdev_priv(dev);
1173 struct mlx5e_rss_params *rss = &priv->rss_params;
1174 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1175 bool hash_changed = false;
1176 void *in;
1177
1178 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1179 (hfunc != ETH_RSS_HASH_XOR) &&
1180 (hfunc != ETH_RSS_HASH_TOP))
1181 return -EINVAL;
1182
1183 in = kvzalloc(inlen, GFP_KERNEL);
1184 if (!in)
1185 return -ENOMEM;
1186
1187 mutex_lock(&priv->state_lock);
1188
1189 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1190 rss->hfunc = hfunc;
1191 hash_changed = true;
1192 }
1193
1194 if (indir) {
1195 memcpy(rss->indirection_rqt, indir,
1196 sizeof(rss->indirection_rqt));
1197
1198 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1199 u32 rqtn = priv->indir_rqt.rqtn;
1200 struct mlx5e_redirect_rqt_param rrp = {
1201 .is_rss = true,
1202 {
1203 .rss = {
1204 .hfunc = rss->hfunc,
1205 .channels = &priv->channels,
1206 },
1207 },
1208 };
1209
1210 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1211 }
1212 }
1213
1214 if (key) {
1215 memcpy(rss->toeplitz_hash_key, key,
1216 sizeof(rss->toeplitz_hash_key));
1217 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1218 }
1219
1220 if (hash_changed)
1221 mlx5e_modify_tirs_hash(priv, in, inlen);
1222
1223 mutex_unlock(&priv->state_lock);
1224
1225 kvfree(in);
1226
1227 return 0;
1228}
1229
1230#define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1231#define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1232#define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1233#define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1234#define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1235 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1236 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1237
1238static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1239 u16 *pfc_prevention_tout)
1240{
1241 struct mlx5e_priv *priv = netdev_priv(netdev);
1242 struct mlx5_core_dev *mdev = priv->mdev;
1243
1244 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1245 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1246 return -EOPNOTSUPP;
1247
1248 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1249}
1250
1251static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1252 u16 pfc_preven)
1253{
1254 struct mlx5e_priv *priv = netdev_priv(netdev);
1255 struct mlx5_core_dev *mdev = priv->mdev;
1256 u16 critical_tout;
1257 u16 minor;
1258
1259 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1260 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1261 return -EOPNOTSUPP;
1262
1263 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1264 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1265 pfc_preven;
1266
1267 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1268 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1269 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1270 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1271 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1272 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1273 return -EINVAL;
1274 }
1275
1276 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1277 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1278 minor);
1279}
1280
1281static int mlx5e_get_tunable(struct net_device *dev,
1282 const struct ethtool_tunable *tuna,
1283 void *data)
1284{
1285 int err;
1286
1287 switch (tuna->id) {
1288 case ETHTOOL_PFC_PREVENTION_TOUT:
1289 err = mlx5e_get_pfc_prevention_tout(dev, data);
1290 break;
1291 default:
1292 err = -EINVAL;
1293 break;
1294 }
1295
1296 return err;
1297}
1298
1299static int mlx5e_set_tunable(struct net_device *dev,
1300 const struct ethtool_tunable *tuna,
1301 const void *data)
1302{
1303 struct mlx5e_priv *priv = netdev_priv(dev);
1304 int err;
1305
1306 mutex_lock(&priv->state_lock);
1307
1308 switch (tuna->id) {
1309 case ETHTOOL_PFC_PREVENTION_TOUT:
1310 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1311 break;
1312 default:
1313 err = -EINVAL;
1314 break;
1315 }
1316
1317 mutex_unlock(&priv->state_lock);
1318 return err;
1319}
1320
1321void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1322 struct ethtool_pauseparam *pauseparam)
1323{
1324 struct mlx5_core_dev *mdev = priv->mdev;
1325 int err;
1326
1327 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1328 &pauseparam->tx_pause);
1329 if (err) {
1330 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1331 __func__, err);
1332 }
1333}
1334
1335static void mlx5e_get_pauseparam(struct net_device *netdev,
1336 struct ethtool_pauseparam *pauseparam)
1337{
1338 struct mlx5e_priv *priv = netdev_priv(netdev);
1339
1340 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1341}
1342
1343int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1344 struct ethtool_pauseparam *pauseparam)
1345{
1346 struct mlx5_core_dev *mdev = priv->mdev;
1347 int err;
1348
1349 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1350 return -EOPNOTSUPP;
1351
1352 if (pauseparam->autoneg)
1353 return -EINVAL;
1354
1355 err = mlx5_set_port_pause(mdev,
1356 pauseparam->rx_pause ? 1 : 0,
1357 pauseparam->tx_pause ? 1 : 0);
1358 if (err) {
1359 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1360 __func__, err);
1361 }
1362
1363 return err;
1364}
1365
1366static int mlx5e_set_pauseparam(struct net_device *netdev,
1367 struct ethtool_pauseparam *pauseparam)
1368{
1369 struct mlx5e_priv *priv = netdev_priv(netdev);
1370
1371 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1372}
1373
1374int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1375 struct ethtool_ts_info *info)
1376{
1377 struct mlx5_core_dev *mdev = priv->mdev;
1378
1379 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1380
1381 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1382 info->phc_index == -1)
1383 return 0;
1384
1385 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1386 SOF_TIMESTAMPING_RX_HARDWARE |
1387 SOF_TIMESTAMPING_RAW_HARDWARE;
1388
1389 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1390 BIT(HWTSTAMP_TX_ON);
1391
1392 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1393 BIT(HWTSTAMP_FILTER_ALL);
1394
1395 return 0;
1396}
1397
1398static int mlx5e_get_ts_info(struct net_device *dev,
1399 struct ethtool_ts_info *info)
1400{
1401 struct mlx5e_priv *priv = netdev_priv(dev);
1402
1403 return mlx5e_ethtool_get_ts_info(priv, info);
1404}
1405
1406static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1407{
1408 __u32 ret = 0;
1409
1410 if (MLX5_CAP_GEN(mdev, wol_g))
1411 ret |= WAKE_MAGIC;
1412
1413 if (MLX5_CAP_GEN(mdev, wol_s))
1414 ret |= WAKE_MAGICSECURE;
1415
1416 if (MLX5_CAP_GEN(mdev, wol_a))
1417 ret |= WAKE_ARP;
1418
1419 if (MLX5_CAP_GEN(mdev, wol_b))
1420 ret |= WAKE_BCAST;
1421
1422 if (MLX5_CAP_GEN(mdev, wol_m))
1423 ret |= WAKE_MCAST;
1424
1425 if (MLX5_CAP_GEN(mdev, wol_u))
1426 ret |= WAKE_UCAST;
1427
1428 if (MLX5_CAP_GEN(mdev, wol_p))
1429 ret |= WAKE_PHY;
1430
1431 return ret;
1432}
1433
1434static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1435{
1436 __u32 ret = 0;
1437
1438 if (mode & MLX5_WOL_MAGIC)
1439 ret |= WAKE_MAGIC;
1440
1441 if (mode & MLX5_WOL_SECURED_MAGIC)
1442 ret |= WAKE_MAGICSECURE;
1443
1444 if (mode & MLX5_WOL_ARP)
1445 ret |= WAKE_ARP;
1446
1447 if (mode & MLX5_WOL_BROADCAST)
1448 ret |= WAKE_BCAST;
1449
1450 if (mode & MLX5_WOL_MULTICAST)
1451 ret |= WAKE_MCAST;
1452
1453 if (mode & MLX5_WOL_UNICAST)
1454 ret |= WAKE_UCAST;
1455
1456 if (mode & MLX5_WOL_PHY_ACTIVITY)
1457 ret |= WAKE_PHY;
1458
1459 return ret;
1460}
1461
1462static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1463{
1464 u8 ret = 0;
1465
1466 if (mode & WAKE_MAGIC)
1467 ret |= MLX5_WOL_MAGIC;
1468
1469 if (mode & WAKE_MAGICSECURE)
1470 ret |= MLX5_WOL_SECURED_MAGIC;
1471
1472 if (mode & WAKE_ARP)
1473 ret |= MLX5_WOL_ARP;
1474
1475 if (mode & WAKE_BCAST)
1476 ret |= MLX5_WOL_BROADCAST;
1477
1478 if (mode & WAKE_MCAST)
1479 ret |= MLX5_WOL_MULTICAST;
1480
1481 if (mode & WAKE_UCAST)
1482 ret |= MLX5_WOL_UNICAST;
1483
1484 if (mode & WAKE_PHY)
1485 ret |= MLX5_WOL_PHY_ACTIVITY;
1486
1487 return ret;
1488}
1489
1490static void mlx5e_get_wol(struct net_device *netdev,
1491 struct ethtool_wolinfo *wol)
1492{
1493 struct mlx5e_priv *priv = netdev_priv(netdev);
1494 struct mlx5_core_dev *mdev = priv->mdev;
1495 u8 mlx5_wol_mode;
1496 int err;
1497
1498 memset(wol, 0, sizeof(*wol));
1499
1500 wol->supported = mlx5e_get_wol_supported(mdev);
1501 if (!wol->supported)
1502 return;
1503
1504 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1505 if (err)
1506 return;
1507
1508 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1509}
1510
1511static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1512{
1513 struct mlx5e_priv *priv = netdev_priv(netdev);
1514 struct mlx5_core_dev *mdev = priv->mdev;
1515 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1516 u32 mlx5_wol_mode;
1517
1518 if (!wol_supported)
1519 return -EOPNOTSUPP;
1520
1521 if (wol->wolopts & ~wol_supported)
1522 return -EINVAL;
1523
1524 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1525
1526 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1527}
1528
1529static int mlx5e_get_fecparam(struct net_device *netdev,
1530 struct ethtool_fecparam *fecparam)
1531{
1532 struct mlx5e_priv *priv = netdev_priv(netdev);
1533 struct mlx5_core_dev *mdev = priv->mdev;
1534 u8 fec_configured = 0;
1535 u32 fec_active = 0;
1536 int err;
1537
1538 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1539
1540 if (err)
1541 return err;
1542
1543 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1544 sizeof(u32) * BITS_PER_BYTE);
1545
1546 if (!fecparam->active_fec)
1547 return -EOPNOTSUPP;
1548
1549 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1550 sizeof(u8) * BITS_PER_BYTE);
1551
1552 return 0;
1553}
1554
1555static int mlx5e_set_fecparam(struct net_device *netdev,
1556 struct ethtool_fecparam *fecparam)
1557{
1558 struct mlx5e_priv *priv = netdev_priv(netdev);
1559 struct mlx5_core_dev *mdev = priv->mdev;
1560 u8 fec_policy = 0;
1561 int mode;
1562 int err;
1563
1564 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1565 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1566 continue;
1567 fec_policy |= (1 << mode);
1568 break;
1569 }
1570
1571 err = mlx5e_set_fec_mode(mdev, fec_policy);
1572
1573 if (err)
1574 return err;
1575
1576 mlx5_toggle_port_link(mdev);
1577
1578 return 0;
1579}
1580
1581static u32 mlx5e_get_msglevel(struct net_device *dev)
1582{
1583 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1584}
1585
1586static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1587{
1588 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1589}
1590
1591static int mlx5e_set_phys_id(struct net_device *dev,
1592 enum ethtool_phys_id_state state)
1593{
1594 struct mlx5e_priv *priv = netdev_priv(dev);
1595 struct mlx5_core_dev *mdev = priv->mdev;
1596 u16 beacon_duration;
1597
1598 if (!MLX5_CAP_GEN(mdev, beacon_led))
1599 return -EOPNOTSUPP;
1600
1601 switch (state) {
1602 case ETHTOOL_ID_ACTIVE:
1603 beacon_duration = MLX5_BEACON_DURATION_INF;
1604 break;
1605 case ETHTOOL_ID_INACTIVE:
1606 beacon_duration = MLX5_BEACON_DURATION_OFF;
1607 break;
1608 default:
1609 return -EOPNOTSUPP;
1610 }
1611
1612 return mlx5_set_port_beacon(mdev, beacon_duration);
1613}
1614
1615static int mlx5e_get_module_info(struct net_device *netdev,
1616 struct ethtool_modinfo *modinfo)
1617{
1618 struct mlx5e_priv *priv = netdev_priv(netdev);
1619 struct mlx5_core_dev *dev = priv->mdev;
1620 int size_read = 0;
1621 u8 data[4] = {0};
1622
1623 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1624 if (size_read < 2)
1625 return -EIO;
1626
1627
1628 switch (data[0]) {
1629 case MLX5_MODULE_ID_QSFP:
1630 modinfo->type = ETH_MODULE_SFF_8436;
1631 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1632 break;
1633 case MLX5_MODULE_ID_QSFP_PLUS:
1634 case MLX5_MODULE_ID_QSFP28:
1635
1636 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1637 modinfo->type = ETH_MODULE_SFF_8636;
1638 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1639 } else {
1640 modinfo->type = ETH_MODULE_SFF_8436;
1641 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1642 }
1643 break;
1644 case MLX5_MODULE_ID_SFP:
1645 modinfo->type = ETH_MODULE_SFF_8472;
1646 modinfo->eeprom_len = MLX5_EEPROM_PAGE_LENGTH;
1647 break;
1648 default:
1649 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1650 __func__, data[0]);
1651 return -EINVAL;
1652 }
1653
1654 return 0;
1655}
1656
1657static int mlx5e_get_module_eeprom(struct net_device *netdev,
1658 struct ethtool_eeprom *ee,
1659 u8 *data)
1660{
1661 struct mlx5e_priv *priv = netdev_priv(netdev);
1662 struct mlx5_core_dev *mdev = priv->mdev;
1663 int offset = ee->offset;
1664 int size_read;
1665 int i = 0;
1666
1667 if (!ee->len)
1668 return -EINVAL;
1669
1670 memset(data, 0, ee->len);
1671
1672 while (i < ee->len) {
1673 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1674 data + i);
1675
1676 if (!size_read)
1677
1678 return 0;
1679
1680 if (size_read < 0) {
1681 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1682 __func__, size_read);
1683 return 0;
1684 }
1685
1686 i += size_read;
1687 offset += size_read;
1688 }
1689
1690 return 0;
1691}
1692
1693int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1694 struct ethtool_flash *flash)
1695{
1696 struct mlx5_core_dev *mdev = priv->mdev;
1697 struct net_device *dev = priv->netdev;
1698 const struct firmware *fw;
1699 int err;
1700
1701 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1702 return -EOPNOTSUPP;
1703
1704 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1705 if (err)
1706 return err;
1707
1708 dev_hold(dev);
1709 rtnl_unlock();
1710
1711 err = mlx5_firmware_flash(mdev, fw, NULL);
1712 release_firmware(fw);
1713
1714 rtnl_lock();
1715 dev_put(dev);
1716 return err;
1717}
1718
1719static int mlx5e_flash_device(struct net_device *dev,
1720 struct ethtool_flash *flash)
1721{
1722 struct mlx5e_priv *priv = netdev_priv(dev);
1723
1724 return mlx5e_ethtool_flash_device(priv, flash);
1725}
1726
1727static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1728 bool is_rx_cq)
1729{
1730 struct mlx5e_priv *priv = netdev_priv(netdev);
1731 struct mlx5_core_dev *mdev = priv->mdev;
1732 struct mlx5e_channels new_channels = {};
1733 bool mode_changed;
1734 u8 cq_period_mode, current_cq_period_mode;
1735
1736 cq_period_mode = enable ?
1737 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1738 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1739 current_cq_period_mode = is_rx_cq ?
1740 priv->channels.params.rx_cq_moderation.cq_period_mode :
1741 priv->channels.params.tx_cq_moderation.cq_period_mode;
1742 mode_changed = cq_period_mode != current_cq_period_mode;
1743
1744 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1745 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1746 return -EOPNOTSUPP;
1747
1748 if (!mode_changed)
1749 return 0;
1750
1751 new_channels.params = priv->channels.params;
1752 if (is_rx_cq)
1753 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1754 else
1755 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1756
1757 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1758 priv->channels.params = new_channels.params;
1759 return 0;
1760 }
1761
1762 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1763}
1764
1765static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1766{
1767 return set_pflag_cqe_based_moder(netdev, enable, false);
1768}
1769
1770static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1771{
1772 return set_pflag_cqe_based_moder(netdev, enable, true);
1773}
1774
1775int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1776{
1777 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1778 struct mlx5e_channels new_channels = {};
1779 int err = 0;
1780
1781 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1782 return new_val ? -EOPNOTSUPP : 0;
1783
1784 if (curr_val == new_val)
1785 return 0;
1786
1787 new_channels.params = priv->channels.params;
1788 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1789
1790 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1791 priv->channels.params = new_channels.params;
1792 return 0;
1793 }
1794
1795 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1796 if (err)
1797 return err;
1798
1799 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1800 MLX5E_GET_PFLAG(&priv->channels.params,
1801 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1802
1803 return 0;
1804}
1805
1806static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1807 bool enable)
1808{
1809 struct mlx5e_priv *priv = netdev_priv(netdev);
1810 struct mlx5_core_dev *mdev = priv->mdev;
1811
1812 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1813 return -EOPNOTSUPP;
1814
1815 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1816 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1817 return -EINVAL;
1818 }
1819
1820 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1821 priv->channels.params.rx_cqe_compress_def = enable;
1822
1823 return 0;
1824}
1825
1826static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1827{
1828 struct mlx5e_priv *priv = netdev_priv(netdev);
1829 struct mlx5_core_dev *mdev = priv->mdev;
1830 struct mlx5e_channels new_channels = {};
1831
1832 if (enable) {
1833 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1834 return -EOPNOTSUPP;
1835 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1836 return -EINVAL;
1837 } else if (priv->channels.params.lro_en) {
1838 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1839 return -EINVAL;
1840 }
1841
1842 new_channels.params = priv->channels.params;
1843
1844 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1845 mlx5e_set_rq_type(mdev, &new_channels.params);
1846
1847 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1848 priv->channels.params = new_channels.params;
1849 return 0;
1850 }
1851
1852 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1853}
1854
1855static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1856{
1857 struct mlx5e_priv *priv = netdev_priv(netdev);
1858 struct mlx5e_channels *channels = &priv->channels;
1859 struct mlx5e_channel *c;
1860 int i;
1861
1862 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1863 priv->channels.params.xdp_prog)
1864 return 0;
1865
1866 for (i = 0; i < channels->num; i++) {
1867 c = channels->c[i];
1868 if (enable)
1869 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1870 else
1871 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1872 }
1873
1874 return 0;
1875}
1876
1877static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1878{
1879 struct mlx5e_priv *priv = netdev_priv(netdev);
1880 struct mlx5_core_dev *mdev = priv->mdev;
1881 struct mlx5e_channels new_channels = {};
1882 int err;
1883
1884 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1885 return -EOPNOTSUPP;
1886
1887 new_channels.params = priv->channels.params;
1888
1889 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1890
1891 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1892 priv->channels.params = new_channels.params;
1893 return 0;
1894 }
1895
1896 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1897 return err;
1898}
1899
1900static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1901 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1902 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1903 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1904 { "rx_striding_rq", set_pflag_rx_striding_rq },
1905 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1906 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1907};
1908
1909static int mlx5e_handle_pflag(struct net_device *netdev,
1910 u32 wanted_flags,
1911 enum mlx5e_priv_flag flag)
1912{
1913 struct mlx5e_priv *priv = netdev_priv(netdev);
1914 bool enable = !!(wanted_flags & BIT(flag));
1915 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1916 int err;
1917
1918 if (!(changes & BIT(flag)))
1919 return 0;
1920
1921 err = mlx5e_priv_flags[flag].handler(netdev, enable);
1922 if (err) {
1923 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1924 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
1925 return err;
1926 }
1927
1928 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1929 return 0;
1930}
1931
1932static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1933{
1934 struct mlx5e_priv *priv = netdev_priv(netdev);
1935 enum mlx5e_priv_flag pflag;
1936 int err;
1937
1938 mutex_lock(&priv->state_lock);
1939
1940 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1941 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1942 if (err)
1943 break;
1944 }
1945
1946 mutex_unlock(&priv->state_lock);
1947
1948
1949 netdev_update_features(netdev);
1950
1951 return err;
1952}
1953
1954static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1955{
1956 struct mlx5e_priv *priv = netdev_priv(netdev);
1957
1958 return priv->channels.params.pflags;
1959}
1960
1961#ifndef CONFIG_MLX5_EN_RXNFC
1962
1963
1964
1965static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, u32 *rule_locs)
1966{
1967 struct mlx5e_priv *priv = netdev_priv(dev);
1968
1969 if (info->cmd != ETHTOOL_GRXRINGS)
1970 return -EOPNOTSUPP;
1971
1972 info->data = priv->channels.params.num_channels;
1973 return 0;
1974}
1975#endif
1976
1977const struct ethtool_ops mlx5e_ethtool_ops = {
1978 .get_drvinfo = mlx5e_get_drvinfo,
1979 .get_link = ethtool_op_get_link,
1980 .get_strings = mlx5e_get_strings,
1981 .get_sset_count = mlx5e_get_sset_count,
1982 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1983 .get_ringparam = mlx5e_get_ringparam,
1984 .set_ringparam = mlx5e_set_ringparam,
1985 .get_channels = mlx5e_get_channels,
1986 .set_channels = mlx5e_set_channels,
1987 .get_coalesce = mlx5e_get_coalesce,
1988 .set_coalesce = mlx5e_set_coalesce,
1989 .get_link_ksettings = mlx5e_get_link_ksettings,
1990 .set_link_ksettings = mlx5e_set_link_ksettings,
1991 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1992 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1993 .get_rxfh = mlx5e_get_rxfh,
1994 .set_rxfh = mlx5e_set_rxfh,
1995 .get_rxnfc = mlx5e_get_rxnfc,
1996#ifdef CONFIG_MLX5_EN_RXNFC
1997 .set_rxnfc = mlx5e_set_rxnfc,
1998#endif
1999 .get_tunable = mlx5e_get_tunable,
2000 .set_tunable = mlx5e_set_tunable,
2001 .get_pauseparam = mlx5e_get_pauseparam,
2002 .set_pauseparam = mlx5e_set_pauseparam,
2003 .get_ts_info = mlx5e_get_ts_info,
2004 .set_phys_id = mlx5e_set_phys_id,
2005 .get_wol = mlx5e_get_wol,
2006 .set_wol = mlx5e_set_wol,
2007 .get_module_info = mlx5e_get_module_info,
2008 .get_module_eeprom = mlx5e_get_module_eeprom,
2009 .flash_device = mlx5e_flash_device,
2010 .get_priv_flags = mlx5e_get_priv_flags,
2011 .set_priv_flags = mlx5e_set_priv_flags,
2012 .self_test = mlx5e_self_test,
2013 .get_msglevel = mlx5e_get_msglevel,
2014 .set_msglevel = mlx5e_set_msglevel,
2015 .get_fecparam = mlx5e_get_fecparam,
2016 .set_fecparam = mlx5e_set_fecparam,
2017};
2018
