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32#ifndef __MLX5_EN_STATS_H__
33#define __MLX5_EN_STATS_H__
34
35#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
43
44#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
45#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46#define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
47#define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
48#define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
49#define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
50#define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
51#define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
52
53struct counter_desc {
54 char format[ETH_GSTRING_LEN];
55 size_t offset;
56};
57
58struct mlx5e_sw_stats {
59 u64 rx_packets;
60 u64 rx_bytes;
61 u64 tx_packets;
62 u64 tx_bytes;
63 u64 tx_tso_packets;
64 u64 tx_tso_bytes;
65 u64 tx_tso_inner_packets;
66 u64 tx_tso_inner_bytes;
67 u64 tx_added_vlan_packets;
68 u64 tx_nop;
69 u64 rx_lro_packets;
70 u64 rx_lro_bytes;
71 u64 rx_ecn_mark;
72 u64 rx_removed_vlan_packets;
73 u64 rx_csum_unnecessary;
74 u64 rx_csum_none;
75 u64 rx_csum_complete;
76 u64 rx_csum_complete_tail;
77 u64 rx_csum_complete_tail_slow;
78 u64 rx_csum_unnecessary_inner;
79 u64 rx_xdp_drop;
80 u64 rx_xdp_redirect;
81 u64 rx_xdp_tx_xmit;
82 u64 rx_xdp_tx_mpwqe;
83 u64 rx_xdp_tx_inlnw;
84 u64 rx_xdp_tx_full;
85 u64 rx_xdp_tx_err;
86 u64 rx_xdp_tx_cqe;
87 u64 tx_csum_none;
88 u64 tx_csum_partial;
89 u64 tx_csum_partial_inner;
90 u64 tx_queue_stopped;
91 u64 tx_queue_dropped;
92 u64 tx_xmit_more;
93 u64 tx_recover;
94 u64 tx_cqes;
95 u64 tx_queue_wake;
96 u64 tx_cqe_err;
97 u64 tx_xdp_xmit;
98 u64 tx_xdp_mpwqe;
99 u64 tx_xdp_inlnw;
100 u64 tx_xdp_full;
101 u64 tx_xdp_err;
102 u64 tx_xdp_cqes;
103 u64 rx_wqe_err;
104 u64 rx_mpwqe_filler_cqes;
105 u64 rx_mpwqe_filler_strides;
106 u64 rx_oversize_pkts_sw_drop;
107 u64 rx_buff_alloc_err;
108 u64 rx_cqe_compress_blks;
109 u64 rx_cqe_compress_pkts;
110 u64 rx_cache_reuse;
111 u64 rx_cache_full;
112 u64 rx_cache_empty;
113 u64 rx_cache_busy;
114 u64 rx_cache_waive;
115 u64 rx_congst_umr;
116 u64 rx_arfs_err;
117 u64 ch_events;
118 u64 ch_poll;
119 u64 ch_arm;
120 u64 ch_aff_change;
121 u64 ch_force_irq;
122 u64 ch_eq_rearm;
123
124#ifdef CONFIG_MLX5_EN_TLS
125 u64 tx_tls_encrypted_packets;
126 u64 tx_tls_encrypted_bytes;
127 u64 tx_tls_ctx;
128 u64 tx_tls_ooo;
129 u64 tx_tls_resync_bytes;
130 u64 tx_tls_drop_no_sync_data;
131 u64 tx_tls_drop_bypass_req;
132 u64 tx_tls_dump_packets;
133 u64 tx_tls_dump_bytes;
134#endif
135
136 u64 rx_xsk_packets;
137 u64 rx_xsk_bytes;
138 u64 rx_xsk_csum_complete;
139 u64 rx_xsk_csum_unnecessary;
140 u64 rx_xsk_csum_unnecessary_inner;
141 u64 rx_xsk_csum_none;
142 u64 rx_xsk_ecn_mark;
143 u64 rx_xsk_removed_vlan_packets;
144 u64 rx_xsk_xdp_drop;
145 u64 rx_xsk_xdp_redirect;
146 u64 rx_xsk_wqe_err;
147 u64 rx_xsk_mpwqe_filler_cqes;
148 u64 rx_xsk_mpwqe_filler_strides;
149 u64 rx_xsk_oversize_pkts_sw_drop;
150 u64 rx_xsk_buff_alloc_err;
151 u64 rx_xsk_cqe_compress_blks;
152 u64 rx_xsk_cqe_compress_pkts;
153 u64 rx_xsk_congst_umr;
154 u64 rx_xsk_arfs_err;
155 u64 tx_xsk_xmit;
156 u64 tx_xsk_mpwqe;
157 u64 tx_xsk_inlnw;
158 u64 tx_xsk_full;
159 u64 tx_xsk_err;
160 u64 tx_xsk_cqes;
161};
162
163struct mlx5e_qcounter_stats {
164 u32 rx_out_of_buffer;
165 u32 rx_if_down_packets;
166};
167
168struct mlx5e_vnic_env_stats {
169 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
170};
171
172#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
173 vstats->query_vport_out, c)
174
175struct mlx5e_vport_stats {
176 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
177};
178
179#define PPORT_802_3_GET(pstats, c) \
180 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
181 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
182#define PPORT_2863_GET(pstats, c) \
183 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
184 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
185#define PPORT_2819_GET(pstats, c) \
186 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
187 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
188#define PPORT_PHY_STATISTICAL_GET(pstats, c) \
189 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
190 counter_set.phys_layer_statistical_cntrs.c##_high)
191#define PPORT_PER_PRIO_GET(pstats, prio, c) \
192 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
193 counter_set.eth_per_prio_grp_data_layout.c##_high)
194#define NUM_PPORT_PRIO 8
195#define PPORT_ETH_EXT_GET(pstats, c) \
196 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
197 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
198
199struct mlx5e_pport_stats {
200 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
201 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
202 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
203 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
204 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
205 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
206 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
207};
208
209#define PCIE_PERF_GET(pcie_stats, c) \
210 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
211 counter_set.pcie_perf_cntrs_grp_data_layout.c)
212
213#define PCIE_PERF_GET64(pcie_stats, c) \
214 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
215 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
216
217struct mlx5e_pcie_stats {
218 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
219};
220
221struct mlx5e_rq_stats {
222 u64 packets;
223 u64 bytes;
224 u64 csum_complete;
225 u64 csum_complete_tail;
226 u64 csum_complete_tail_slow;
227 u64 csum_unnecessary;
228 u64 csum_unnecessary_inner;
229 u64 csum_none;
230 u64 lro_packets;
231 u64 lro_bytes;
232 u64 ecn_mark;
233 u64 removed_vlan_packets;
234 u64 xdp_drop;
235 u64 xdp_redirect;
236 u64 wqe_err;
237 u64 mpwqe_filler_cqes;
238 u64 mpwqe_filler_strides;
239 u64 oversize_pkts_sw_drop;
240 u64 buff_alloc_err;
241 u64 cqe_compress_blks;
242 u64 cqe_compress_pkts;
243 u64 cache_reuse;
244 u64 cache_full;
245 u64 cache_empty;
246 u64 cache_busy;
247 u64 cache_waive;
248 u64 congst_umr;
249 u64 arfs_err;
250};
251
252struct mlx5e_sq_stats {
253
254 u64 packets;
255 u64 bytes;
256 u64 xmit_more;
257 u64 tso_packets;
258 u64 tso_bytes;
259 u64 tso_inner_packets;
260 u64 tso_inner_bytes;
261 u64 csum_partial;
262 u64 csum_partial_inner;
263 u64 added_vlan_packets;
264 u64 nop;
265#ifdef CONFIG_MLX5_EN_TLS
266 u64 tls_encrypted_packets;
267 u64 tls_encrypted_bytes;
268 u64 tls_ctx;
269 u64 tls_ooo;
270 u64 tls_resync_bytes;
271 u64 tls_drop_no_sync_data;
272 u64 tls_drop_bypass_req;
273 u64 tls_dump_packets;
274 u64 tls_dump_bytes;
275#endif
276
277 u64 csum_none;
278 u64 stopped;
279 u64 dropped;
280 u64 recover;
281
282 u64 cqes ____cacheline_aligned_in_smp;
283 u64 wake;
284 u64 cqe_err;
285};
286
287struct mlx5e_xdpsq_stats {
288 u64 xmit;
289 u64 mpwqe;
290 u64 inlnw;
291 u64 full;
292 u64 err;
293
294 u64 cqes ____cacheline_aligned_in_smp;
295};
296
297struct mlx5e_ch_stats {
298 u64 events;
299 u64 poll;
300 u64 arm;
301 u64 aff_change;
302 u64 force_irq;
303 u64 eq_rearm;
304};
305
306struct mlx5e_stats {
307 struct mlx5e_sw_stats sw;
308 struct mlx5e_qcounter_stats qcnt;
309 struct mlx5e_vnic_env_stats vnic;
310 struct mlx5e_vport_stats vport;
311 struct mlx5e_pport_stats pport;
312 struct rtnl_link_stats64 vf_vport;
313 struct mlx5e_pcie_stats pcie;
314};
315
316enum {
317 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
318};
319
320struct mlx5e_priv;
321struct mlx5e_stats_grp {
322 u16 update_stats_mask;
323 int (*get_num_stats)(struct mlx5e_priv *priv);
324 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
325 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
326 void (*update_stats)(struct mlx5e_priv *priv);
327};
328
329extern const struct mlx5e_stats_grp mlx5e_stats_grps[];
330extern const int mlx5e_num_stats_grps;
331
332void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv);
333
334#endif
335
