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33#include <linux/highmem.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/interrupt.h>
42#include <linux/delay.h>
43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/debugfs.h>
47#include <linux/kmod.h>
48#include <linux/mlx5/mlx5_ifc.h>
49#include <linux/mlx5/vport.h>
50#ifdef CONFIG_RFS_ACCEL
51#include <linux/cpu_rmap.h>
52#endif
53#include <net/devlink.h>
54#include "mlx5_core.h"
55#include "lib/eq.h"
56#include "fs_core.h"
57#include "lib/mpfs.h"
58#include "eswitch.h"
59#include "devlink.h"
60#include "lib/mlx5.h"
61#include "fpga/core.h"
62#include "fpga/ipsec.h"
63#include "accel/ipsec.h"
64#include "accel/tls.h"
65#include "lib/clock.h"
66#include "lib/vxlan.h"
67#include "lib/geneve.h"
68#include "lib/devcom.h"
69#include "lib/pci_vsc.h"
70#include "diag/fw_tracer.h"
71#include "ecpf.h"
72
73MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
74MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(DRIVER_VERSION);
77
78unsigned int mlx5_core_debug_mask;
79module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
80MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
81
82#define MLX5_DEFAULT_PROF 2
83static unsigned int prof_sel = MLX5_DEFAULT_PROF;
84module_param_named(prof_sel, prof_sel, uint, 0444);
85MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
86
87static u32 sw_owner_id[4];
88
89enum {
90 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
91 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
92};
93
94static struct mlx5_profile profile[] = {
95 [0] = {
96 .mask = 0,
97 },
98 [1] = {
99 .mask = MLX5_PROF_MASK_QP_SIZE,
100 .log_max_qp = 12,
101 },
102 [2] = {
103 .mask = MLX5_PROF_MASK_QP_SIZE |
104 MLX5_PROF_MASK_MR_CACHE,
105 .log_max_qp = 18,
106 .mr_cache[0] = {
107 .size = 500,
108 .limit = 250
109 },
110 .mr_cache[1] = {
111 .size = 500,
112 .limit = 250
113 },
114 .mr_cache[2] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[3] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[4] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[5] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[6] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[7] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[8] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[9] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[10] = {
147 .size = 500,
148 .limit = 250
149 },
150 .mr_cache[11] = {
151 .size = 500,
152 .limit = 250
153 },
154 .mr_cache[12] = {
155 .size = 64,
156 .limit = 32
157 },
158 .mr_cache[13] = {
159 .size = 32,
160 .limit = 16
161 },
162 .mr_cache[14] = {
163 .size = 16,
164 .limit = 8
165 },
166 .mr_cache[15] = {
167 .size = 8,
168 .limit = 4
169 },
170 },
171};
172
173#define FW_INIT_TIMEOUT_MILI 2000
174#define FW_INIT_WAIT_MS 2
175#define FW_PRE_INIT_TIMEOUT_MILI 120000
176#define FW_INIT_WARN_MESSAGE_INTERVAL 20000
177
178static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
179 u32 warn_time_mili)
180{
181 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
182 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
183 int err = 0;
184
185 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
186
187 while (fw_initializing(dev)) {
188 if (time_after(jiffies, end)) {
189 err = -EBUSY;
190 break;
191 }
192 if (warn_time_mili && time_after(jiffies, warn)) {
193 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
194 jiffies_to_msecs(end - warn) / 1000);
195 warn = jiffies + msecs_to_jiffies(warn_time_mili);
196 }
197 msleep(FW_INIT_WAIT_MS);
198 }
199
200 return err;
201}
202
203static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
204{
205 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
206 driver_version);
207 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
208 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
209 int remaining_size = driver_ver_sz;
210 char *string;
211
212 if (!MLX5_CAP_GEN(dev, driver_version))
213 return;
214
215 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
216
217 strncpy(string, "Linux", remaining_size);
218
219 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
220 strncat(string, ",", remaining_size);
221
222 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
223 strncat(string, DRIVER_NAME, remaining_size);
224
225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
226 strncat(string, ",", remaining_size);
227
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, DRIVER_VERSION, remaining_size);
230
231
232 MLX5_SET(set_driver_version_in, in, opcode,
233 MLX5_CMD_OP_SET_DRIVER_VERSION);
234
235 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
236}
237
238static int set_dma_caps(struct pci_dev *pdev)
239{
240 int err;
241
242 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
243 if (err) {
244 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
245 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
246 if (err) {
247 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
248 return err;
249 }
250 }
251
252 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
253 if (err) {
254 dev_warn(&pdev->dev,
255 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
256 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
257 if (err) {
258 dev_err(&pdev->dev,
259 "Can't set consistent PCI DMA mask, aborting\n");
260 return err;
261 }
262 }
263
264 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
265 return err;
266}
267
268static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
269{
270 struct pci_dev *pdev = dev->pdev;
271 int err = 0;
272
273 mutex_lock(&dev->pci_status_mutex);
274 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
275 err = pci_enable_device(pdev);
276 if (!err)
277 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
278 }
279 mutex_unlock(&dev->pci_status_mutex);
280
281 return err;
282}
283
284static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
285{
286 struct pci_dev *pdev = dev->pdev;
287
288 mutex_lock(&dev->pci_status_mutex);
289 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
290 pci_disable_device(pdev);
291 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
292 }
293 mutex_unlock(&dev->pci_status_mutex);
294}
295
296static int request_bar(struct pci_dev *pdev)
297{
298 int err = 0;
299
300 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
301 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
302 return -ENODEV;
303 }
304
305 err = pci_request_regions(pdev, DRIVER_NAME);
306 if (err)
307 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
308
309 return err;
310}
311
312static void release_bar(struct pci_dev *pdev)
313{
314 pci_release_regions(pdev);
315}
316
317struct mlx5_reg_host_endianness {
318 u8 he;
319 u8 rsvd[15];
320};
321
322#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
323
324enum {
325 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
326 MLX5_DEV_CAP_FLAG_DCT,
327};
328
329static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
330{
331 switch (size) {
332 case 128:
333 return 0;
334 case 256:
335 return 1;
336 case 512:
337 return 2;
338 case 1024:
339 return 3;
340 case 2048:
341 return 4;
342 case 4096:
343 return 5;
344 default:
345 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
346 return 0;
347 }
348}
349
350static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
351 enum mlx5_cap_type cap_type,
352 enum mlx5_cap_mode cap_mode)
353{
354 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
355 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
356 void *out, *hca_caps;
357 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
358 int err;
359
360 memset(in, 0, sizeof(in));
361 out = kzalloc(out_sz, GFP_KERNEL);
362 if (!out)
363 return -ENOMEM;
364
365 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
366 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
367 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
368 if (err) {
369 mlx5_core_warn(dev,
370 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
371 cap_type, cap_mode, err);
372 goto query_ex;
373 }
374
375 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
376
377 switch (cap_mode) {
378 case HCA_CAP_OPMOD_GET_MAX:
379 memcpy(dev->caps.hca_max[cap_type], hca_caps,
380 MLX5_UN_SZ_BYTES(hca_cap_union));
381 break;
382 case HCA_CAP_OPMOD_GET_CUR:
383 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
384 MLX5_UN_SZ_BYTES(hca_cap_union));
385 break;
386 default:
387 mlx5_core_warn(dev,
388 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
389 cap_type, cap_mode);
390 err = -EINVAL;
391 break;
392 }
393query_ex:
394 kfree(out);
395 return err;
396}
397
398int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
399{
400 int ret;
401
402 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
403 if (ret)
404 return ret;
405 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
406}
407
408static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
409{
410 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
411
412 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
413 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
414 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
415}
416
417static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
418{
419 void *set_ctx;
420 void *set_hca_cap;
421 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
422 int req_endianness;
423 int err;
424
425 if (MLX5_CAP_GEN(dev, atomic)) {
426 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
427 if (err)
428 return err;
429 } else {
430 return 0;
431 }
432
433 req_endianness =
434 MLX5_CAP_ATOMIC(dev,
435 supported_atomic_req_8B_endianness_mode_1);
436
437 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
438 return 0;
439
440 set_ctx = kzalloc(set_sz, GFP_KERNEL);
441 if (!set_ctx)
442 return -ENOMEM;
443
444 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
445
446
447 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
448 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
449
450 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
451
452 kfree(set_ctx);
453 return err;
454}
455
456static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
457{
458 void *set_hca_cap;
459 void *set_ctx;
460 int set_sz;
461 bool do_set = false;
462 int err;
463
464 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
465 !MLX5_CAP_GEN(dev, pg))
466 return 0;
467
468 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
469 if (err)
470 return err;
471
472 set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
473 set_ctx = kzalloc(set_sz, GFP_KERNEL);
474 if (!set_ctx)
475 return -ENOMEM;
476
477 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
478 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
479 MLX5_ST_SZ_BYTES(odp_cap));
480
481#define ODP_CAP_SET_MAX(dev, field) \
482 do { \
483 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
484 if (_res) { \
485 do_set = true; \
486 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
487 } \
488 } while (0)
489
490 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
491 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
492 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
493 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
494 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
495 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
496 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
497 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
498
499 if (do_set)
500 err = set_caps(dev, set_ctx, set_sz,
501 MLX5_SET_HCA_CAP_OP_MOD_ODP);
502
503 kfree(set_ctx);
504
505 return err;
506}
507
508static int handle_hca_cap(struct mlx5_core_dev *dev)
509{
510 void *set_ctx = NULL;
511 struct mlx5_profile *prof = dev->profile;
512 int err = -ENOMEM;
513 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
514 void *set_hca_cap;
515
516 set_ctx = kzalloc(set_sz, GFP_KERNEL);
517 if (!set_ctx)
518 goto query_ex;
519
520 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
521 if (err)
522 goto query_ex;
523
524 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
525 capability);
526 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
527 MLX5_ST_SZ_BYTES(cmd_hca_cap));
528
529 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
530 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
531 128);
532
533 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
534 to_fw_pkey_sz(dev, 128));
535
536
537 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
538 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
539 profile[prof_sel].log_max_qp,
540 MLX5_CAP_GEN_MAX(dev, log_max_qp));
541 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
542 }
543 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
544 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
545 prof->log_max_qp);
546
547
548 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
549
550
551
552
553 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
554 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
555
556 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
557
558 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
559 MLX5_SET(cmd_hca_cap,
560 set_hca_cap,
561 cache_line_128byte,
562 cache_line_size() >= 128 ? 1 : 0);
563
564 if (MLX5_CAP_GEN_MAX(dev, dct))
565 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
566
567 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
568 MLX5_SET(cmd_hca_cap,
569 set_hca_cap,
570 num_vhca_ports,
571 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
572
573 err = set_caps(dev, set_ctx, set_sz,
574 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
575
576query_ex:
577 kfree(set_ctx);
578 return err;
579}
580
581static int set_hca_cap(struct mlx5_core_dev *dev)
582{
583 int err;
584
585 err = handle_hca_cap(dev);
586 if (err) {
587 mlx5_core_err(dev, "handle_hca_cap failed\n");
588 goto out;
589 }
590
591 err = handle_hca_cap_atomic(dev);
592 if (err) {
593 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
594 goto out;
595 }
596
597 err = handle_hca_cap_odp(dev);
598 if (err) {
599 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
600 goto out;
601 }
602
603out:
604 return err;
605}
606
607static int set_hca_ctrl(struct mlx5_core_dev *dev)
608{
609 struct mlx5_reg_host_endianness he_in;
610 struct mlx5_reg_host_endianness he_out;
611 int err;
612
613 if (!mlx5_core_is_pf(dev))
614 return 0;
615
616 memset(&he_in, 0, sizeof(he_in));
617 he_in.he = MLX5_SET_HOST_ENDIANNESS;
618 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
619 &he_out, sizeof(he_out),
620 MLX5_REG_HOST_ENDIANNESS, 0, 1);
621 return err;
622}
623
624static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
625{
626 int ret = 0;
627
628
629 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
630 ret = mlx5_nic_vport_update_local_lb(dev, false);
631
632 return ret;
633}
634
635int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
636{
637 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
638 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
639
640 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
641 MLX5_SET(enable_hca_in, in, function_id, func_id);
642 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
643 dev->caps.embedded_cpu);
644 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
645}
646
647int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
648{
649 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
650 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
651
652 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
653 MLX5_SET(disable_hca_in, in, function_id, func_id);
654 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
655 dev->caps.embedded_cpu);
656 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
657}
658
659u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
660 struct ptp_system_timestamp *sts)
661{
662 u32 timer_h, timer_h1, timer_l;
663
664 timer_h = ioread32be(&dev->iseg->internal_timer_h);
665 ptp_read_system_prets(sts);
666 timer_l = ioread32be(&dev->iseg->internal_timer_l);
667 ptp_read_system_postts(sts);
668 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
669 if (timer_h != timer_h1) {
670
671 ptp_read_system_prets(sts);
672 timer_l = ioread32be(&dev->iseg->internal_timer_l);
673 ptp_read_system_postts(sts);
674 }
675
676 return (u64)timer_l | (u64)timer_h1 << 32;
677}
678
679static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
680{
681 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
682 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
683 u32 sup_issi;
684 int err;
685
686 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
687 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
688 query_out, sizeof(query_out));
689 if (err) {
690 u32 syndrome;
691 u8 status;
692
693 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
694 if (!status || syndrome == MLX5_DRIVER_SYND) {
695 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
696 err, status, syndrome);
697 return err;
698 }
699
700 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
701 dev->issi = 0;
702 return 0;
703 }
704
705 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
706
707 if (sup_issi & (1 << 1)) {
708 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
709 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
710
711 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
712 MLX5_SET(set_issi_in, set_in, current_issi, 1);
713 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
714 set_out, sizeof(set_out));
715 if (err) {
716 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
717 err);
718 return err;
719 }
720
721 dev->issi = 1;
722
723 return 0;
724 } else if (sup_issi & (1 << 0) || !sup_issi) {
725 return 0;
726 }
727
728 return -EOPNOTSUPP;
729}
730
731static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
732 const struct pci_device_id *id)
733{
734 struct mlx5_priv *priv = &dev->priv;
735 int err = 0;
736
737 mutex_init(&dev->pci_status_mutex);
738 pci_set_drvdata(dev->pdev, dev);
739
740 dev->bar_addr = pci_resource_start(pdev, 0);
741 priv->numa_node = dev_to_node(&dev->pdev->dev);
742
743 err = mlx5_pci_enable_device(dev);
744 if (err) {
745 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
746 return err;
747 }
748
749 err = request_bar(pdev);
750 if (err) {
751 mlx5_core_err(dev, "error requesting BARs, aborting\n");
752 goto err_disable;
753 }
754
755 pci_set_master(pdev);
756
757 err = set_dma_caps(pdev);
758 if (err) {
759 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
760 goto err_clr_master;
761 }
762
763 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
764 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
765 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
766 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
767
768 dev->iseg_base = dev->bar_addr;
769 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
770 if (!dev->iseg) {
771 err = -ENOMEM;
772 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
773 goto err_clr_master;
774 }
775
776 mlx5_pci_vsc_init(dev);
777
778 return 0;
779
780err_clr_master:
781 pci_clear_master(dev->pdev);
782 release_bar(dev->pdev);
783err_disable:
784 mlx5_pci_disable_device(dev);
785 return err;
786}
787
788static void mlx5_pci_close(struct mlx5_core_dev *dev)
789{
790 iounmap(dev->iseg);
791 pci_clear_master(dev->pdev);
792 release_bar(dev->pdev);
793 mlx5_pci_disable_device(dev);
794}
795
796static int mlx5_init_once(struct mlx5_core_dev *dev)
797{
798 int err;
799
800 dev->priv.devcom = mlx5_devcom_register_device(dev);
801 if (IS_ERR(dev->priv.devcom))
802 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
803 dev->priv.devcom);
804
805 err = mlx5_query_board_id(dev);
806 if (err) {
807 mlx5_core_err(dev, "query board id failed\n");
808 goto err_devcom;
809 }
810
811 err = mlx5_irq_table_init(dev);
812 if (err) {
813 mlx5_core_err(dev, "failed to initialize irq table\n");
814 goto err_devcom;
815 }
816
817 err = mlx5_eq_table_init(dev);
818 if (err) {
819 mlx5_core_err(dev, "failed to initialize eq\n");
820 goto err_irq_cleanup;
821 }
822
823 err = mlx5_events_init(dev);
824 if (err) {
825 mlx5_core_err(dev, "failed to initialize events\n");
826 goto err_eq_cleanup;
827 }
828
829 err = mlx5_cq_debugfs_init(dev);
830 if (err) {
831 mlx5_core_err(dev, "failed to initialize cq debugfs\n");
832 goto err_events_cleanup;
833 }
834
835 mlx5_init_qp_table(dev);
836
837 mlx5_init_mkey_table(dev);
838
839 mlx5_init_reserved_gids(dev);
840
841 mlx5_init_clock(dev);
842
843 dev->vxlan = mlx5_vxlan_create(dev);
844 dev->geneve = mlx5_geneve_create(dev);
845
846 err = mlx5_init_rl_table(dev);
847 if (err) {
848 mlx5_core_err(dev, "Failed to init rate limiting\n");
849 goto err_tables_cleanup;
850 }
851
852 err = mlx5_mpfs_init(dev);
853 if (err) {
854 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
855 goto err_rl_cleanup;
856 }
857
858 err = mlx5_sriov_init(dev);
859 if (err) {
860 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
861 goto err_mpfs_cleanup;
862 }
863
864 err = mlx5_eswitch_init(dev);
865 if (err) {
866 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
867 goto err_sriov_cleanup;
868 }
869
870 err = mlx5_fpga_init(dev);
871 if (err) {
872 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
873 goto err_eswitch_cleanup;
874 }
875
876 dev->tracer = mlx5_fw_tracer_create(dev);
877
878 return 0;
879
880err_eswitch_cleanup:
881 mlx5_eswitch_cleanup(dev->priv.eswitch);
882err_sriov_cleanup:
883 mlx5_sriov_cleanup(dev);
884err_mpfs_cleanup:
885 mlx5_mpfs_cleanup(dev);
886err_rl_cleanup:
887 mlx5_cleanup_rl_table(dev);
888err_tables_cleanup:
889 mlx5_geneve_destroy(dev->geneve);
890 mlx5_vxlan_destroy(dev->vxlan);
891 mlx5_cleanup_mkey_table(dev);
892 mlx5_cleanup_qp_table(dev);
893 mlx5_cq_debugfs_cleanup(dev);
894err_events_cleanup:
895 mlx5_events_cleanup(dev);
896err_eq_cleanup:
897 mlx5_eq_table_cleanup(dev);
898err_irq_cleanup:
899 mlx5_irq_table_cleanup(dev);
900err_devcom:
901 mlx5_devcom_unregister_device(dev->priv.devcom);
902
903 return err;
904}
905
906static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
907{
908 mlx5_fw_tracer_destroy(dev->tracer);
909 mlx5_fpga_cleanup(dev);
910 mlx5_eswitch_cleanup(dev->priv.eswitch);
911 mlx5_sriov_cleanup(dev);
912 mlx5_mpfs_cleanup(dev);
913 mlx5_cleanup_rl_table(dev);
914 mlx5_geneve_destroy(dev->geneve);
915 mlx5_vxlan_destroy(dev->vxlan);
916 mlx5_cleanup_clock(dev);
917 mlx5_cleanup_reserved_gids(dev);
918 mlx5_cleanup_mkey_table(dev);
919 mlx5_cleanup_qp_table(dev);
920 mlx5_cq_debugfs_cleanup(dev);
921 mlx5_events_cleanup(dev);
922 mlx5_eq_table_cleanup(dev);
923 mlx5_irq_table_cleanup(dev);
924 mlx5_devcom_unregister_device(dev->priv.devcom);
925}
926
927static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
928{
929 int err;
930
931 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
932 fw_rev_min(dev), fw_rev_sub(dev));
933
934
935 if (mlx5_core_is_pf(dev))
936 pcie_print_link_status(dev->pdev);
937
938
939
940 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
941 if (err) {
942 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
943 FW_PRE_INIT_TIMEOUT_MILI);
944 return err;
945 }
946
947 err = mlx5_cmd_init(dev);
948 if (err) {
949 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
950 return err;
951 }
952
953 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
954 if (err) {
955 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
956 FW_INIT_TIMEOUT_MILI);
957 goto err_cmd_cleanup;
958 }
959
960 err = mlx5_core_enable_hca(dev, 0);
961 if (err) {
962 mlx5_core_err(dev, "enable hca failed\n");
963 goto err_cmd_cleanup;
964 }
965
966 err = mlx5_core_set_issi(dev);
967 if (err) {
968 mlx5_core_err(dev, "failed to set issi\n");
969 goto err_disable_hca;
970 }
971
972 err = mlx5_satisfy_startup_pages(dev, 1);
973 if (err) {
974 mlx5_core_err(dev, "failed to allocate boot pages\n");
975 goto err_disable_hca;
976 }
977
978 err = set_hca_ctrl(dev);
979 if (err) {
980 mlx5_core_err(dev, "set_hca_ctrl failed\n");
981 goto reclaim_boot_pages;
982 }
983
984 err = set_hca_cap(dev);
985 if (err) {
986 mlx5_core_err(dev, "set_hca_cap failed\n");
987 goto reclaim_boot_pages;
988 }
989
990 err = mlx5_satisfy_startup_pages(dev, 0);
991 if (err) {
992 mlx5_core_err(dev, "failed to allocate init pages\n");
993 goto reclaim_boot_pages;
994 }
995
996 err = mlx5_cmd_init_hca(dev, sw_owner_id);
997 if (err) {
998 mlx5_core_err(dev, "init hca failed\n");
999 goto reclaim_boot_pages;
1000 }
1001
1002 mlx5_set_driver_version(dev);
1003
1004 mlx5_start_health_poll(dev);
1005
1006 err = mlx5_query_hca_caps(dev);
1007 if (err) {
1008 mlx5_core_err(dev, "query hca failed\n");
1009 goto stop_health;
1010 }
1011
1012 return 0;
1013
1014stop_health:
1015 mlx5_stop_health_poll(dev, boot);
1016reclaim_boot_pages:
1017 mlx5_reclaim_startup_pages(dev);
1018err_disable_hca:
1019 mlx5_core_disable_hca(dev, 0);
1020err_cmd_cleanup:
1021 mlx5_cmd_cleanup(dev);
1022
1023 return err;
1024}
1025
1026static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1027{
1028 int err;
1029
1030 mlx5_stop_health_poll(dev, boot);
1031 err = mlx5_cmd_teardown_hca(dev);
1032 if (err) {
1033 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1034 return err;
1035 }
1036 mlx5_reclaim_startup_pages(dev);
1037 mlx5_core_disable_hca(dev, 0);
1038 mlx5_cmd_cleanup(dev);
1039
1040 return 0;
1041}
1042
1043static int mlx5_load(struct mlx5_core_dev *dev)
1044{
1045 int err;
1046
1047 dev->priv.uar = mlx5_get_uars_page(dev);
1048 if (IS_ERR(dev->priv.uar)) {
1049 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1050 err = PTR_ERR(dev->priv.uar);
1051 return err;
1052 }
1053
1054 mlx5_events_start(dev);
1055 mlx5_pagealloc_start(dev);
1056
1057 err = mlx5_irq_table_create(dev);
1058 if (err) {
1059 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1060 goto err_irq_table;
1061 }
1062
1063 err = mlx5_eq_table_create(dev);
1064 if (err) {
1065 mlx5_core_err(dev, "Failed to create EQs\n");
1066 goto err_eq_table;
1067 }
1068
1069 err = mlx5_fw_tracer_init(dev->tracer);
1070 if (err) {
1071 mlx5_core_err(dev, "Failed to init FW tracer\n");
1072 goto err_fw_tracer;
1073 }
1074
1075 err = mlx5_fpga_device_start(dev);
1076 if (err) {
1077 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1078 goto err_fpga_start;
1079 }
1080
1081 err = mlx5_accel_ipsec_init(dev);
1082 if (err) {
1083 mlx5_core_err(dev, "IPSec device start failed %d\n", err);
1084 goto err_ipsec_start;
1085 }
1086
1087 err = mlx5_accel_tls_init(dev);
1088 if (err) {
1089 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1090 goto err_tls_start;
1091 }
1092
1093 err = mlx5_init_fs(dev);
1094 if (err) {
1095 mlx5_core_err(dev, "Failed to init flow steering\n");
1096 goto err_fs;
1097 }
1098
1099 err = mlx5_core_set_hca_defaults(dev);
1100 if (err) {
1101 mlx5_core_err(dev, "Failed to set hca defaults\n");
1102 goto err_sriov;
1103 }
1104
1105 err = mlx5_sriov_attach(dev);
1106 if (err) {
1107 mlx5_core_err(dev, "sriov init failed %d\n", err);
1108 goto err_sriov;
1109 }
1110
1111 err = mlx5_ec_init(dev);
1112 if (err) {
1113 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1114 goto err_ec;
1115 }
1116
1117 return 0;
1118
1119err_ec:
1120 mlx5_sriov_detach(dev);
1121err_sriov:
1122 mlx5_cleanup_fs(dev);
1123err_fs:
1124 mlx5_accel_tls_cleanup(dev);
1125err_tls_start:
1126 mlx5_accel_ipsec_cleanup(dev);
1127err_ipsec_start:
1128 mlx5_fpga_device_stop(dev);
1129err_fpga_start:
1130 mlx5_fw_tracer_cleanup(dev->tracer);
1131err_fw_tracer:
1132 mlx5_eq_table_destroy(dev);
1133err_eq_table:
1134 mlx5_irq_table_destroy(dev);
1135err_irq_table:
1136 mlx5_pagealloc_stop(dev);
1137 mlx5_events_stop(dev);
1138 mlx5_put_uars_page(dev, dev->priv.uar);
1139 return err;
1140}
1141
1142static void mlx5_unload(struct mlx5_core_dev *dev)
1143{
1144 mlx5_ec_cleanup(dev);
1145 mlx5_sriov_detach(dev);
1146 mlx5_cleanup_fs(dev);
1147 mlx5_accel_ipsec_cleanup(dev);
1148 mlx5_accel_tls_cleanup(dev);
1149 mlx5_fpga_device_stop(dev);
1150 mlx5_fw_tracer_cleanup(dev->tracer);
1151 mlx5_eq_table_destroy(dev);
1152 mlx5_irq_table_destroy(dev);
1153 mlx5_pagealloc_stop(dev);
1154 mlx5_events_stop(dev);
1155 mlx5_put_uars_page(dev, dev->priv.uar);
1156}
1157
1158static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1159{
1160 int err = 0;
1161
1162 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1163 mutex_lock(&dev->intf_state_mutex);
1164 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1165 mlx5_core_warn(dev, "interface is up, NOP\n");
1166 goto out;
1167 }
1168
1169 dev->state = MLX5_DEVICE_STATE_UP;
1170
1171 err = mlx5_function_setup(dev, boot);
1172 if (err)
1173 goto out;
1174
1175 if (boot) {
1176 err = mlx5_init_once(dev);
1177 if (err) {
1178 mlx5_core_err(dev, "sw objs init failed\n");
1179 goto function_teardown;
1180 }
1181 }
1182
1183 err = mlx5_load(dev);
1184 if (err)
1185 goto err_load;
1186
1187 if (mlx5_device_registered(dev)) {
1188 mlx5_attach_device(dev);
1189 } else {
1190 err = mlx5_register_device(dev);
1191 if (err) {
1192 mlx5_core_err(dev, "register device failed %d\n", err);
1193 goto err_reg_dev;
1194 }
1195 }
1196
1197 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1198out:
1199 mutex_unlock(&dev->intf_state_mutex);
1200
1201 return err;
1202
1203err_reg_dev:
1204 mlx5_unload(dev);
1205err_load:
1206 if (boot)
1207 mlx5_cleanup_once(dev);
1208function_teardown:
1209 mlx5_function_teardown(dev, boot);
1210 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1211 mutex_unlock(&dev->intf_state_mutex);
1212
1213 return err;
1214}
1215
1216static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1217{
1218 int err = 0;
1219
1220 if (cleanup)
1221 mlx5_drain_health_wq(dev);
1222
1223 mutex_lock(&dev->intf_state_mutex);
1224 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1225 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1226 __func__);
1227 if (cleanup)
1228 mlx5_cleanup_once(dev);
1229 goto out;
1230 }
1231
1232 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1233
1234 if (mlx5_device_registered(dev))
1235 mlx5_detach_device(dev);
1236
1237 mlx5_unload(dev);
1238
1239 if (cleanup)
1240 mlx5_cleanup_once(dev);
1241
1242 mlx5_function_teardown(dev, cleanup);
1243out:
1244 mutex_unlock(&dev->intf_state_mutex);
1245 return err;
1246}
1247
1248static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1249{
1250 struct mlx5_priv *priv = &dev->priv;
1251 int err;
1252
1253 dev->profile = &profile[profile_idx];
1254
1255 INIT_LIST_HEAD(&priv->ctx_list);
1256 spin_lock_init(&priv->ctx_lock);
1257 mutex_init(&dev->intf_state_mutex);
1258
1259 mutex_init(&priv->bfregs.reg_head.lock);
1260 mutex_init(&priv->bfregs.wc_head.lock);
1261 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1262 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1263
1264 mutex_init(&priv->alloc_mutex);
1265 mutex_init(&priv->pgdir_mutex);
1266 INIT_LIST_HEAD(&priv->pgdir_list);
1267 spin_lock_init(&priv->mkey_lock);
1268
1269 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1270 mlx5_debugfs_root);
1271 if (!priv->dbg_root) {
1272 dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n");
1273 return -ENOMEM;
1274 }
1275
1276 err = mlx5_health_init(dev);
1277 if (err)
1278 goto err_health_init;
1279
1280 err = mlx5_pagealloc_init(dev);
1281 if (err)
1282 goto err_pagealloc_init;
1283
1284 return 0;
1285
1286err_pagealloc_init:
1287 mlx5_health_cleanup(dev);
1288err_health_init:
1289 debugfs_remove(dev->priv.dbg_root);
1290
1291 return err;
1292}
1293
1294static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1295{
1296 mlx5_pagealloc_cleanup(dev);
1297 mlx5_health_cleanup(dev);
1298 debugfs_remove_recursive(dev->priv.dbg_root);
1299}
1300
1301#define MLX5_IB_MOD "mlx5_ib"
1302static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1303{
1304 struct mlx5_core_dev *dev;
1305 struct devlink *devlink;
1306 int err;
1307
1308 devlink = mlx5_devlink_alloc();
1309 if (!devlink) {
1310 dev_err(&pdev->dev, "devlink alloc failed\n");
1311 return -ENOMEM;
1312 }
1313
1314 dev = devlink_priv(devlink);
1315 dev->device = &pdev->dev;
1316 dev->pdev = pdev;
1317
1318 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1319 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1320
1321 err = mlx5_mdev_init(dev, prof_sel);
1322 if (err)
1323 goto mdev_init_err;
1324
1325 err = mlx5_pci_init(dev, pdev, id);
1326 if (err) {
1327 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1328 err);
1329 goto pci_init_err;
1330 }
1331
1332 err = mlx5_load_one(dev, true);
1333 if (err) {
1334 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1335 err);
1336 goto err_load_one;
1337 }
1338
1339 request_module_nowait(MLX5_IB_MOD);
1340
1341 err = mlx5_devlink_register(devlink, &pdev->dev);
1342 if (err)
1343 goto clean_load;
1344
1345 err = mlx5_crdump_enable(dev);
1346 if (err)
1347 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1348
1349 pci_save_state(pdev);
1350 return 0;
1351
1352clean_load:
1353 mlx5_unload_one(dev, true);
1354
1355err_load_one:
1356 mlx5_pci_close(dev);
1357pci_init_err:
1358 mlx5_mdev_uninit(dev);
1359mdev_init_err:
1360 mlx5_devlink_free(devlink);
1361
1362 return err;
1363}
1364
1365static void remove_one(struct pci_dev *pdev)
1366{
1367 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1368 struct devlink *devlink = priv_to_devlink(dev);
1369
1370 mlx5_crdump_disable(dev);
1371 mlx5_devlink_unregister(devlink);
1372 mlx5_unregister_device(dev);
1373
1374 if (mlx5_unload_one(dev, true)) {
1375 mlx5_core_err(dev, "mlx5_unload_one failed\n");
1376 mlx5_health_flush(dev);
1377 return;
1378 }
1379
1380 mlx5_pci_close(dev);
1381 mlx5_mdev_uninit(dev);
1382 mlx5_devlink_free(devlink);
1383}
1384
1385static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1386 pci_channel_state_t state)
1387{
1388 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1389
1390 mlx5_core_info(dev, "%s was called\n", __func__);
1391
1392 mlx5_enter_error_state(dev, false);
1393 mlx5_error_sw_reset(dev);
1394 mlx5_unload_one(dev, false);
1395 mlx5_drain_health_wq(dev);
1396 mlx5_pci_disable_device(dev);
1397
1398 return state == pci_channel_io_perm_failure ?
1399 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1400}
1401
1402
1403
1404
1405static int wait_vital(struct pci_dev *pdev)
1406{
1407 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1408 struct mlx5_core_health *health = &dev->priv.health;
1409 const int niter = 100;
1410 u32 last_count = 0;
1411 u32 count;
1412 int i;
1413
1414 for (i = 0; i < niter; i++) {
1415 count = ioread32be(health->health_counter);
1416 if (count && count != 0xffffffff) {
1417 if (last_count && last_count != count) {
1418 mlx5_core_info(dev,
1419 "wait vital counter value 0x%x after %d iterations\n",
1420 count, i);
1421 return 0;
1422 }
1423 last_count = count;
1424 }
1425 msleep(50);
1426 }
1427
1428 return -ETIMEDOUT;
1429}
1430
1431static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1432{
1433 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1434 int err;
1435
1436 mlx5_core_info(dev, "%s was called\n", __func__);
1437
1438 err = mlx5_pci_enable_device(dev);
1439 if (err) {
1440 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1441 __func__, err);
1442 return PCI_ERS_RESULT_DISCONNECT;
1443 }
1444
1445 pci_set_master(pdev);
1446 pci_restore_state(pdev);
1447 pci_save_state(pdev);
1448
1449 if (wait_vital(pdev)) {
1450 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1451 return PCI_ERS_RESULT_DISCONNECT;
1452 }
1453
1454 return PCI_ERS_RESULT_RECOVERED;
1455}
1456
1457static void mlx5_pci_resume(struct pci_dev *pdev)
1458{
1459 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1460 int err;
1461
1462 mlx5_core_info(dev, "%s was called\n", __func__);
1463
1464 err = mlx5_load_one(dev, false);
1465 if (err)
1466 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1467 __func__, err);
1468 else
1469 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1470}
1471
1472static const struct pci_error_handlers mlx5_err_handler = {
1473 .error_detected = mlx5_pci_err_detected,
1474 .slot_reset = mlx5_pci_slot_reset,
1475 .resume = mlx5_pci_resume
1476};
1477
1478static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1479{
1480 bool fast_teardown = false, force_teardown = false;
1481 int ret = 1;
1482
1483 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1484 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1485
1486 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1487 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1488
1489 if (!fast_teardown && !force_teardown)
1490 return -EOPNOTSUPP;
1491
1492 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1493 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1494 return -EAGAIN;
1495 }
1496
1497
1498
1499
1500 mlx5_drain_health_wq(dev);
1501 mlx5_stop_health_poll(dev, false);
1502
1503 ret = mlx5_cmd_fast_teardown_hca(dev);
1504 if (!ret)
1505 goto succeed;
1506
1507 ret = mlx5_cmd_force_teardown_hca(dev);
1508 if (!ret)
1509 goto succeed;
1510
1511 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1512 mlx5_start_health_poll(dev);
1513 return ret;
1514
1515succeed:
1516 mlx5_enter_error_state(dev, true);
1517
1518
1519
1520
1521
1522
1523 mlx5_core_eq_free_irqs(dev);
1524
1525 return 0;
1526}
1527
1528static void shutdown(struct pci_dev *pdev)
1529{
1530 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1531 int err;
1532
1533 mlx5_core_info(dev, "Shutdown was called\n");
1534 err = mlx5_try_fast_unload(dev);
1535 if (err)
1536 mlx5_unload_one(dev, false);
1537 mlx5_pci_disable_device(dev);
1538}
1539
1540static const struct pci_device_id mlx5_core_pci_table[] = {
1541 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1542 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF},
1543 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1544 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF},
1545 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1546 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF},
1547 { PCI_VDEVICE(MELLANOX, 0x1017) },
1548 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF},
1549 { PCI_VDEVICE(MELLANOX, 0x1019) },
1550 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF},
1551 { PCI_VDEVICE(MELLANOX, 0x101b) },
1552 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF},
1553 { PCI_VDEVICE(MELLANOX, 0x101d) },
1554 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF},
1555 { PCI_VDEVICE(MELLANOX, 0xa2d2) },
1556 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF},
1557 { 0, }
1558};
1559
1560MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1561
1562void mlx5_disable_device(struct mlx5_core_dev *dev)
1563{
1564 mlx5_error_sw_reset(dev);
1565 mlx5_unload_one(dev, false);
1566}
1567
1568void mlx5_recover_device(struct mlx5_core_dev *dev)
1569{
1570 mlx5_pci_disable_device(dev);
1571 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1572 mlx5_pci_resume(dev->pdev);
1573}
1574
1575static struct pci_driver mlx5_core_driver = {
1576 .name = DRIVER_NAME,
1577 .id_table = mlx5_core_pci_table,
1578 .probe = init_one,
1579 .remove = remove_one,
1580 .shutdown = shutdown,
1581 .err_handler = &mlx5_err_handler,
1582 .sriov_configure = mlx5_core_sriov_configure,
1583};
1584
1585static void mlx5_core_verify_params(void)
1586{
1587 if (prof_sel >= ARRAY_SIZE(profile)) {
1588 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1589 prof_sel,
1590 ARRAY_SIZE(profile) - 1,
1591 MLX5_DEFAULT_PROF);
1592 prof_sel = MLX5_DEFAULT_PROF;
1593 }
1594}
1595
1596static int __init init(void)
1597{
1598 int err;
1599
1600 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1601
1602 mlx5_core_verify_params();
1603 mlx5_accel_ipsec_build_fs_cmds();
1604 mlx5_register_debugfs();
1605
1606 err = pci_register_driver(&mlx5_core_driver);
1607 if (err)
1608 goto err_debug;
1609
1610#ifdef CONFIG_MLX5_CORE_EN
1611 mlx5e_init();
1612#endif
1613
1614 return 0;
1615
1616err_debug:
1617 mlx5_unregister_debugfs();
1618 return err;
1619}
1620
1621static void __exit cleanup(void)
1622{
1623#ifdef CONFIG_MLX5_CORE_EN
1624 mlx5e_cleanup();
1625#endif
1626 pci_unregister_driver(&mlx5_core_driver);
1627 mlx5_unregister_debugfs();
1628}
1629
1630module_init(init);
1631module_exit(cleanup);
1632
