1
2
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>
9#include <linux/bitops.h>
10#include <linux/if_vlan.h>
11
12#include "item.h"
13#include "port.h"
14
15struct mlxsw_reg_info {
16 u16 id;
17 u16 len;
18 const char *name;
19};
20
21#define MLXSW_REG_DEFINE(_name, _id, _len) \
22static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26}
27
28#define MLXSW_REG(type) (&mlxsw_reg_##type)
29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32
33
34
35
36#define MLXSW_REG_SGCR_ID 0x2000
37#define MLXSW_REG_SGCR_LEN 0x10
38
39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41
42
43
44
45
46
47MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48
49static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50{
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
53}
54
55
56
57
58
59#define MLXSW_REG_SPAD_ID 0x2002
60#define MLXSW_REG_SPAD_LEN 0x10
61
62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64
65
66
67
68
69
70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72
73
74
75
76
77
78#define MLXSW_REG_SMID_ID 0x2007
79#define MLXSW_REG_SMID_LEN 0x240
80
81MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
82
83
84
85
86
87MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
88
89
90
91
92
93
94MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
95
96
97
98
99
100MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
101
102
103
104
105
106MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
107
108static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
109 u8 port, bool set)
110{
111 MLXSW_REG_ZERO(smid, payload);
112 mlxsw_reg_smid_swid_set(payload, 0);
113 mlxsw_reg_smid_mid_set(payload, mid);
114 mlxsw_reg_smid_port_set(payload, port, set);
115 mlxsw_reg_smid_port_mask_set(payload, port, 1);
116}
117
118
119
120
121
122#define MLXSW_REG_SSPR_ID 0x2008
123#define MLXSW_REG_SSPR_LEN 0x8
124
125MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
126
127
128
129
130
131
132
133
134
135
136
137MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
138
139
140
141
142
143
144MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
145
146
147
148
149
150
151
152MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
153
154
155
156
157
158
159
160
161
162MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163
164static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
165{
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
171}
172
173
174
175
176
177
178#define MLXSW_REG_SFDAT_ID 0x2009
179#define MLXSW_REG_SFDAT_LEN 0x8
180
181MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
182
183
184
185
186
187MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
188
189
190
191
192
193
194
195
196MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
197
198static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
199{
200 MLXSW_REG_ZERO(sfdat, payload);
201 mlxsw_reg_sfdat_swid_set(payload, 0);
202 mlxsw_reg_sfdat_age_time_set(payload, age_time);
203}
204
205
206
207
208
209
210
211
212#define MLXSW_REG_SFD_ID 0x200A
213#define MLXSW_REG_SFD_BASE_LEN 0x10
214#define MLXSW_REG_SFD_REC_LEN 0x10
215#define MLXSW_REG_SFD_REC_MAX_COUNT 64
216#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
218
219MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
220
221
222
223
224
225MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
226
227enum mlxsw_reg_sfd_op {
228
229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230
231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232
233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234
235
236
237 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238
239
240
241
242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243
244
245
246
247
248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249
250
251
252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
253};
254
255
256
257
258
259MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
260
261
262
263
264
265
266
267
268MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
269
270
271
272
273
274
275
276
277MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
278
279static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
280 u32 record_locator)
281{
282 MLXSW_REG_ZERO(sfd, payload);
283 mlxsw_reg_sfd_op_set(payload, op);
284 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
285}
286
287
288
289
290
291MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 MLXSW_REG_SFD_REC_LEN, 0x00, false);
293
294enum mlxsw_reg_sfd_rec_type {
295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
299};
300
301
302
303
304
305MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 MLXSW_REG_SFD_REC_LEN, 0x00, false);
307
308enum mlxsw_reg_sfd_rec_policy {
309
310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311
312
313
314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315
316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
317};
318
319
320
321
322
323MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 MLXSW_REG_SFD_REC_LEN, 0x00, false);
325
326
327
328
329
330
331
332MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 MLXSW_REG_SFD_REC_LEN, 0x00, false);
334
335
336
337
338
339MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 MLXSW_REG_SFD_REC_LEN, 0x02);
341
342enum mlxsw_reg_sfd_rec_action {
343
344 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345
346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347
348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349
350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
352};
353
354
355
356
357
358
359MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
361
362
363
364
365
366
367
368MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 MLXSW_REG_SFD_REC_LEN, 0x08, false);
370
371
372
373
374
375
376
377
378
379
380
381MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 MLXSW_REG_SFD_REC_LEN, 0x08, false);
383
384
385
386
387
388MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
390
391static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 enum mlxsw_reg_sfd_rec_type rec_type,
393 const char *mac,
394 enum mlxsw_reg_sfd_rec_action action)
395{
396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
397
398 if (rec_index >= num_rec)
399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404}
405
406static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
410 u8 local_port)
411{
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418}
419
420static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 char *mac, u16 *p_fid_vid,
422 u8 *p_local_port)
423{
424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
427}
428
429
430
431
432
433
434MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 MLXSW_REG_SFD_REC_LEN, 0x08, false);
436
437
438
439
440
441
442
443
444
445
446
447MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 MLXSW_REG_SFD_REC_LEN, 0x08, false);
449
450
451
452
453
454MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
456
457
458
459
460
461MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
463
464static inline void
465mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 enum mlxsw_reg_sfd_rec_policy policy,
467 const char *mac, u16 fid_vid,
468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
469 u16 lag_id)
470{
471 mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
473 mac, action);
474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
479}
480
481static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 char *mac, u16 *p_vid,
483 u16 *p_lag_id)
484{
485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
488}
489
490
491
492
493
494
495
496
497MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 MLXSW_REG_SFD_REC_LEN, 0x08, false);
499
500
501
502
503
504
505MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 MLXSW_REG_SFD_REC_LEN, 0x08, false);
507
508
509
510
511
512
513
514MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
516
517static inline void
518mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 const char *mac, u16 fid_vid,
520 enum mlxsw_reg_sfd_rec_action action, u16 mid)
521{
522 mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
527}
528
529
530
531
532
533
534
535MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
537
538
539
540
541
542MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 MLXSW_REG_SFD_REC_LEN, 0x08, false);
544
545enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
548};
549
550
551
552
553
554MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
556
557
558
559
560
561
562
563
564MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
566
567static inline void
568mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 enum mlxsw_reg_sfd_rec_policy policy,
570 const char *mac, u16 fid,
571 enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
573{
574 mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
576 action);
577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
582}
583
584
585
586
587
588
589#define MLXSW_REG_SFN_ID 0x200B
590#define MLXSW_REG_SFN_BASE_LEN 0x10
591#define MLXSW_REG_SFN_REC_LEN 0x10
592#define MLXSW_REG_SFN_REC_MAX_COUNT 64
593#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
595
596MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
597
598
599
600
601
602MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
603
604
605
606
607
608MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
609
610
611
612
613
614
615
616
617
618MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
619
620static inline void mlxsw_reg_sfn_pack(char *payload)
621{
622 MLXSW_REG_ZERO(sfn, payload);
623 mlxsw_reg_sfn_swid_set(payload, 0);
624 mlxsw_reg_sfn_end_set(payload, 1);
625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
626}
627
628
629
630
631
632MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
633 MLXSW_REG_SFN_REC_LEN, 0x00, false);
634
635enum mlxsw_reg_sfn_rec_type {
636
637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
638
639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
640
641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
642
643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
644
645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
646
647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
648};
649
650
651
652
653
654MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
655 MLXSW_REG_SFN_REC_LEN, 0x00, false);
656
657
658
659
660
661MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
662 MLXSW_REG_SFN_REC_LEN, 0x02);
663
664
665
666
667
668
669MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
670 MLXSW_REG_SFN_REC_LEN, 0x08, false);
671
672
673
674
675
676MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
677 MLXSW_REG_SFN_REC_LEN, 0x08, false);
678
679
680
681
682
683MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
684 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
685
686static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
687 char *mac, u16 *p_vid,
688 u8 *p_local_port)
689{
690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
693}
694
695
696
697
698
699MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
700 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
701
702static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
703 char *mac, u16 *p_vid,
704 u16 *p_lag_id)
705{
706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
709}
710
711
712
713
714
715
716
717MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
719
720enum mlxsw_reg_sfn_uc_tunnel_protocol {
721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
723};
724
725
726
727
728
729MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
731
732
733
734
735
736
737
738MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
740
741enum mlxsw_reg_sfn_tunnel_port {
742 MLXSW_REG_SFN_TUNNEL_PORT_NVE,
743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
746};
747
748
749
750
751
752
753MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
754 MLXSW_REG_SFN_REC_LEN, 0x10, false);
755
756static inline void
757mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
758 u16 *p_fid, u32 *p_uip,
759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
760{
761 u32 uip_msb, uip_lsb;
762
763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
767 *p_uip = uip_msb << 24 | uip_lsb;
768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
769}
770
771
772
773
774
775#define MLXSW_REG_SPMS_ID 0x200D
776#define MLXSW_REG_SPMS_LEN 0x404
777
778MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
779
780
781
782
783
784MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
785
786enum mlxsw_reg_spms_state {
787 MLXSW_REG_SPMS_STATE_NO_CHANGE,
788 MLXSW_REG_SPMS_STATE_DISCARDING,
789 MLXSW_REG_SPMS_STATE_LEARNING,
790 MLXSW_REG_SPMS_STATE_FORWARDING,
791};
792
793
794
795
796
797
798
799
800
801MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
802
803static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
804{
805 MLXSW_REG_ZERO(spms, payload);
806 mlxsw_reg_spms_local_port_set(payload, local_port);
807}
808
809static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
810 enum mlxsw_reg_spms_state state)
811{
812 mlxsw_reg_spms_state_set(payload, vid, state);
813}
814
815
816
817
818
819#define MLXSW_REG_SPVID_ID 0x200E
820#define MLXSW_REG_SPVID_LEN 0x08
821
822MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
823
824
825
826
827
828MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
829
830
831
832
833
834
835MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
836
837
838
839
840
841MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
842
843static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
844{
845 MLXSW_REG_ZERO(spvid, payload);
846 mlxsw_reg_spvid_local_port_set(payload, local_port);
847 mlxsw_reg_spvid_pvid_set(payload, pvid);
848}
849
850
851
852
853
854
855
856#define MLXSW_REG_SPVM_ID 0x200F
857#define MLXSW_REG_SPVM_BASE_LEN 0x04
858#define MLXSW_REG_SPVM_REC_LEN 0x04
859#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
860#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
862
863MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
864
865
866
867
868
869
870
871MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
872
873
874
875
876
877
878MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
879
880
881
882
883
884MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
885
886
887
888
889
890
891MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
892
893
894
895
896
897MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
898
899
900
901
902
903MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
904 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
905 MLXSW_REG_SPVM_REC_LEN, 0, false);
906
907
908
909
910
911MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
912 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
913 MLXSW_REG_SPVM_REC_LEN, 0, false);
914
915
916
917
918
919
920MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
921 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
922 MLXSW_REG_SPVM_REC_LEN, 0, false);
923
924
925
926
927
928MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
929 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
930 MLXSW_REG_SPVM_REC_LEN, 0, false);
931
932static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
933 u16 vid_begin, u16 vid_end,
934 bool is_member, bool untagged)
935{
936 int size = vid_end - vid_begin + 1;
937 int i;
938
939 MLXSW_REG_ZERO(spvm, payload);
940 mlxsw_reg_spvm_local_port_set(payload, local_port);
941 mlxsw_reg_spvm_num_rec_set(payload, size);
942
943 for (i = 0; i < size; i++) {
944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
948 }
949}
950
951
952
953
954
955
956#define MLXSW_REG_SPAFT_ID 0x2010
957#define MLXSW_REG_SPAFT_LEN 0x08
958
959MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
960
961
962
963
964
965
966
967MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
968
969
970
971
972
973
974MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
975
976
977
978
979
980MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
981
982
983
984
985
986MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
987
988
989
990
991
992MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
993
994static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
995 bool allow_untagged)
996{
997 MLXSW_REG_ZERO(spaft, payload);
998 mlxsw_reg_spaft_local_port_set(payload, local_port);
999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1001 mlxsw_reg_spaft_allow_tagged_set(payload, true);
1002}
1003
1004
1005
1006
1007
1008
1009#define MLXSW_REG_SFGC_ID 0x2011
1010#define MLXSW_REG_SFGC_LEN 0x10
1011
1012MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1013
1014enum mlxsw_reg_sfgc_type {
1015 MLXSW_REG_SFGC_TYPE_BROADCAST,
1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019 MLXSW_REG_SFGC_TYPE_RESERVED,
1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023 MLXSW_REG_SFGC_TYPE_MAX,
1024};
1025
1026
1027
1028
1029
1030MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1031
1032enum mlxsw_reg_sfgc_bridge_type {
1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1035};
1036
1037
1038
1039
1040
1041
1042MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1043
1044enum mlxsw_flood_table_type {
1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1050};
1051
1052
1053
1054
1055
1056
1057
1058MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1059
1060
1061
1062
1063
1064
1065MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1066
1067
1068
1069
1070
1071MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1072
1073
1074
1075
1076
1077MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1078
1079
1080
1081
1082
1083MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1084
1085static inline void
1086mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088 enum mlxsw_flood_table_type table_type,
1089 unsigned int flood_table)
1090{
1091 MLXSW_REG_ZERO(sfgc, payload);
1092 mlxsw_reg_sfgc_type_set(payload, type);
1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1097}
1098
1099
1100
1101
1102
1103
1104#define MLXSW_REG_SFTR_ID 0x2012
1105#define MLXSW_REG_SFTR_LEN 0x420
1106
1107MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1108
1109
1110
1111
1112
1113MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1114
1115
1116
1117
1118
1119
1120MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1121
1122
1123
1124
1125
1126
1127MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1128
1129
1130
1131
1132
1133MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1134
1135
1136
1137
1138
1139MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1140
1141
1142
1143
1144
1145MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1146
1147
1148
1149
1150
1151MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1152
1153static inline void mlxsw_reg_sftr_pack(char *payload,
1154 unsigned int flood_table,
1155 unsigned int index,
1156 enum mlxsw_flood_table_type table_type,
1157 unsigned int range, u8 port, bool set)
1158{
1159 MLXSW_REG_ZERO(sftr, payload);
1160 mlxsw_reg_sftr_swid_set(payload, 0);
1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162 mlxsw_reg_sftr_index_set(payload, index);
1163 mlxsw_reg_sftr_table_type_set(payload, table_type);
1164 mlxsw_reg_sftr_range_set(payload, range);
1165 mlxsw_reg_sftr_port_set(payload, port, set);
1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1167}
1168
1169
1170
1171
1172
1173
1174#define MLXSW_REG_SFDF_ID 0x2013
1175#define MLXSW_REG_SFDF_LEN 0x14
1176
1177MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1178
1179
1180
1181
1182
1183MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1184
1185enum mlxsw_reg_sfdf_flush_type {
1186 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187 MLXSW_REG_SFDF_FLUSH_PER_FID,
1188 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1194};
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1211
1212
1213
1214
1215
1216
1217
1218MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1219
1220static inline void mlxsw_reg_sfdf_pack(char *payload,
1221 enum mlxsw_reg_sfdf_flush_type type)
1222{
1223 MLXSW_REG_ZERO(sfdf, payload);
1224 mlxsw_reg_sfdf_flush_type_set(payload, type);
1225 mlxsw_reg_sfdf_flush_static_set(payload, true);
1226}
1227
1228
1229
1230
1231
1232MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1233
1234
1235
1236
1237
1238MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1239
1240
1241
1242
1243
1244MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1245
1246
1247
1248
1249
1250MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1251
1252
1253
1254
1255
1256MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1257
1258
1259
1260
1261
1262
1263
1264#define MLXSW_REG_SLDR_ID 0x2014
1265#define MLXSW_REG_SLDR_LEN 0x0C
1266
1267MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1268
1269enum mlxsw_reg_sldr_op {
1270
1271 MLXSW_REG_SLDR_OP_LAG_CREATE,
1272 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273
1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275
1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1277};
1278
1279
1280
1281
1282
1283MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1284
1285
1286
1287
1288
1289MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1290
1291static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1292{
1293 MLXSW_REG_ZERO(sldr, payload);
1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1296}
1297
1298static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1299{
1300 MLXSW_REG_ZERO(sldr, payload);
1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1303}
1304
1305
1306
1307
1308
1309
1310
1311MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1312
1313
1314
1315
1316
1317MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1318
1319static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1320 u8 local_port)
1321{
1322 MLXSW_REG_ZERO(sldr, payload);
1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325 mlxsw_reg_sldr_num_ports_set(payload, 1);
1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1327}
1328
1329static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1330 u8 local_port)
1331{
1332 MLXSW_REG_ZERO(sldr, payload);
1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335 mlxsw_reg_sldr_num_ports_set(payload, 1);
1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1337}
1338
1339
1340
1341
1342
1343
1344#define MLXSW_REG_SLCR_ID 0x2015
1345#define MLXSW_REG_SLCR_LEN 0x10
1346
1347MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1348
1349enum mlxsw_reg_slcr_pp {
1350
1351 MLXSW_REG_SLCR_PP_GLOBAL,
1352
1353 MLXSW_REG_SLCR_PP_PER_PORT,
1354};
1355
1356
1357
1358
1359
1360
1361MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1362
1363
1364
1365
1366
1367
1368
1369
1370MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1371
1372enum mlxsw_reg_slcr_type {
1373 MLXSW_REG_SLCR_TYPE_CRC,
1374 MLXSW_REG_SLCR_TYPE_XOR,
1375 MLXSW_REG_SLCR_TYPE_RANDOM,
1376};
1377
1378
1379
1380
1381
1382MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1383
1384
1385#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1386
1387#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1388
1389#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1390#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393
1394#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1395
1396#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1397#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400
1401#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1402
1403#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1404#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407
1408#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1409
1410#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1411#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414
1415#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1416
1417#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1418
1419#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1420
1421#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1422
1423#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1424
1425#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1426
1427#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1428
1429#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1430
1431#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1432
1433#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1434
1435
1436
1437
1438
1439
1440
1441
1442MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1443
1444
1445
1446
1447
1448MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1449
1450static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1451{
1452 MLXSW_REG_ZERO(slcr, payload);
1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456 mlxsw_reg_slcr_seed_set(payload, seed);
1457}
1458
1459
1460
1461
1462
1463
1464#define MLXSW_REG_SLCOR_ID 0x2016
1465#define MLXSW_REG_SLCOR_LEN 0x10
1466
1467MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1468
1469enum mlxsw_reg_slcor_col {
1470
1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1475};
1476
1477
1478
1479
1480
1481MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1482
1483
1484
1485
1486
1487
1488MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1489
1490
1491
1492
1493
1494MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1495
1496
1497
1498
1499
1500
1501MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1502
1503static inline void mlxsw_reg_slcor_pack(char *payload,
1504 u8 local_port, u16 lag_id,
1505 enum mlxsw_reg_slcor_col col)
1506{
1507 MLXSW_REG_ZERO(slcor, payload);
1508 mlxsw_reg_slcor_col_set(payload, col);
1509 mlxsw_reg_slcor_local_port_set(payload, local_port);
1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1511}
1512
1513static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514 u8 local_port, u16 lag_id,
1515 u8 port_index)
1516{
1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519 mlxsw_reg_slcor_port_index_set(payload, port_index);
1520}
1521
1522static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523 u8 local_port, u16 lag_id)
1524{
1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1527}
1528
1529static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530 u8 local_port, u16 lag_id)
1531{
1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1534}
1535
1536static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537 u8 local_port, u16 lag_id)
1538{
1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1541}
1542
1543
1544
1545
1546
1547#define MLXSW_REG_SPMLR_ID 0x2018
1548#define MLXSW_REG_SPMLR_LEN 0x8
1549
1550MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1551
1552
1553
1554
1555
1556MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1557
1558
1559
1560
1561
1562
1563MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1564
1565enum mlxsw_reg_spmlr_learn_mode {
1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1569};
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1583
1584static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585 enum mlxsw_reg_spmlr_learn_mode mode)
1586{
1587 MLXSW_REG_ZERO(spmlr, payload);
1588 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1591}
1592
1593
1594
1595
1596
1597
1598#define MLXSW_REG_SVFA_ID 0x201C
1599#define MLXSW_REG_SVFA_LEN 0x10
1600
1601MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1602
1603
1604
1605
1606
1607MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1608
1609
1610
1611
1612
1613
1614
1615MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1616
1617enum mlxsw_reg_svfa_mt {
1618 MLXSW_REG_SVFA_MT_VID_TO_FID,
1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1620};
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1631
1632
1633
1634
1635
1636
1637
1638
1639MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1640
1641
1642
1643
1644
1645MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1646
1647
1648
1649
1650
1651MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1652
1653
1654
1655
1656
1657
1658
1659MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1660
1661
1662
1663
1664
1665
1666
1667MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1668
1669static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670 enum mlxsw_reg_svfa_mt mt, bool valid,
1671 u16 fid, u16 vid)
1672{
1673 MLXSW_REG_ZERO(svfa, payload);
1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675 mlxsw_reg_svfa_swid_set(payload, 0);
1676 mlxsw_reg_svfa_local_port_set(payload, local_port);
1677 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678 mlxsw_reg_svfa_v_set(payload, valid);
1679 mlxsw_reg_svfa_fid_set(payload, fid);
1680 mlxsw_reg_svfa_vid_set(payload, vid);
1681}
1682
1683
1684
1685
1686
1687#define MLXSW_REG_SVPE_ID 0x201E
1688#define MLXSW_REG_SVPE_LEN 0x4
1689
1690MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1691
1692
1693
1694
1695
1696
1697
1698MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1699
1700
1701
1702
1703
1704
1705
1706MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1707
1708static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1709 bool enable)
1710{
1711 MLXSW_REG_ZERO(svpe, payload);
1712 mlxsw_reg_svpe_local_port_set(payload, local_port);
1713 mlxsw_reg_svpe_vp_en_set(payload, enable);
1714}
1715
1716
1717
1718
1719
1720#define MLXSW_REG_SFMR_ID 0x201F
1721#define MLXSW_REG_SFMR_LEN 0x18
1722
1723MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1724
1725enum mlxsw_reg_sfmr_op {
1726 MLXSW_REG_SFMR_OP_CREATE_FID,
1727 MLXSW_REG_SFMR_OP_DESTROY_FID,
1728};
1729
1730
1731
1732
1733
1734
1735
1736MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1737
1738
1739
1740
1741
1742MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1743
1744
1745
1746
1747
1748
1749
1750MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1751
1752
1753
1754
1755
1756
1757
1758
1759MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1760
1761
1762
1763
1764
1765
1766
1767MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1768
1769
1770
1771
1772
1773
1774
1775
1776MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1777
1778
1779
1780
1781
1782
1783
1784MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1785
1786static inline void mlxsw_reg_sfmr_pack(char *payload,
1787 enum mlxsw_reg_sfmr_op op, u16 fid,
1788 u16 fid_offset)
1789{
1790 MLXSW_REG_ZERO(sfmr, payload);
1791 mlxsw_reg_sfmr_op_set(payload, op);
1792 mlxsw_reg_sfmr_fid_set(payload, fid);
1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794 mlxsw_reg_sfmr_vtfp_set(payload, false);
1795 mlxsw_reg_sfmr_vv_set(payload, false);
1796}
1797
1798
1799
1800
1801
1802#define MLXSW_REG_SPVMLR_ID 0x2020
1803#define MLXSW_REG_SPVMLR_BASE_LEN 0x04
1804#define MLXSW_REG_SPVMLR_REC_LEN 0x04
1805#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807 MLXSW_REG_SPVMLR_REC_LEN * \
1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1809
1810MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1811
1812
1813
1814
1815
1816
1817
1818MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1819
1820
1821
1822
1823
1824MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1825
1826
1827
1828
1829
1830
1831MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1833
1834
1835
1836
1837
1838MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1840
1841static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842 u16 vid_begin, u16 vid_end,
1843 bool learn_enable)
1844{
1845 int num_rec = vid_end - vid_begin + 1;
1846 int i;
1847
1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1849
1850 MLXSW_REG_ZERO(spvmlr, payload);
1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1853
1854 for (i = 0; i < num_rec; i++) {
1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1857 }
1858}
1859
1860
1861
1862
1863
1864#define MLXSW_REG_CWTP_ID 0x2802
1865#define MLXSW_REG_CWTP_BASE_LEN 0x28
1866#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867#define MLXSW_REG_CWTP_LEN 0x40
1868
1869MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1870
1871
1872
1873
1874
1875
1876MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1877
1878
1879
1880
1881
1882MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1883
1884
1885
1886
1887
1888MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1890
1891
1892
1893
1894
1895
1896MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1898
1899
1900
1901
1902
1903MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1905
1906#define MLXSW_REG_CWTP_MIN_VALUE 64
1907#define MLXSW_REG_CWTP_MAX_PROFILE 2
1908#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1909
1910static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1911 u8 traffic_class)
1912{
1913 int i;
1914
1915 MLXSW_REG_ZERO(cwtp, payload);
1916 mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1918
1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920 mlxsw_reg_cwtp_profile_min_set(payload, i,
1921 MLXSW_REG_CWTP_MIN_VALUE);
1922 mlxsw_reg_cwtp_profile_max_set(payload, i,
1923 MLXSW_REG_CWTP_MIN_VALUE);
1924 }
1925}
1926
1927#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1928
1929static inline void
1930mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1931 u32 probability)
1932{
1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1934
1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1938}
1939
1940
1941
1942
1943
1944#define MLXSW_REG_CWTPM_ID 0x2803
1945#define MLXSW_REG_CWTPM_LEN 0x44
1946
1947MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1948
1949
1950
1951
1952
1953
1954MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1955
1956
1957
1958
1959
1960MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1961
1962
1963
1964
1965
1966
1967
1968MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1969
1970
1971
1972
1973
1974
1975
1976MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1977
1978
1979
1980
1981
1982
1983
1984MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1985
1986
1987
1988
1989
1990
1991
1992MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1993
1994
1995
1996
1997
1998
1999
2000MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2001
2002
2003
2004
2005
2006
2007
2008MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2009
2010
2011
2012
2013
2014
2015
2016MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2017
2018
2019
2020
2021
2022
2023
2024MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2025
2026#define MLXSW_REG_CWTPM_RESET_PROFILE 0
2027
2028static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029 u8 traffic_class, u8 profile,
2030 bool wred, bool ecn)
2031{
2032 MLXSW_REG_ZERO(cwtpm, payload);
2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035 mlxsw_reg_cwtpm_ew_set(payload, wred);
2036 mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2043}
2044
2045
2046
2047
2048
2049#define MLXSW_REG_PGCR_ID 0x3001
2050#define MLXSW_REG_PGCR_LEN 0x20
2051
2052MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2053
2054
2055
2056
2057
2058
2059MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2060
2061static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2062{
2063 MLXSW_REG_ZERO(pgcr, payload);
2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2065}
2066
2067
2068
2069
2070
2071#define MLXSW_REG_PPBT_ID 0x3002
2072#define MLXSW_REG_PPBT_LEN 0x14
2073
2074MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2075
2076enum mlxsw_reg_pxbt_e {
2077 MLXSW_REG_PXBT_E_IACL,
2078 MLXSW_REG_PXBT_E_EACL,
2079};
2080
2081
2082
2083
2084MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2085
2086enum mlxsw_reg_pxbt_op {
2087 MLXSW_REG_PXBT_OP_BIND,
2088 MLXSW_REG_PXBT_OP_UNBIND,
2089};
2090
2091
2092
2093
2094MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2095
2096
2097
2098
2099
2100MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2101
2102
2103
2104
2105
2106
2107
2108MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2109
2110
2111
2112
2113
2114
2115MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2116
2117static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118 enum mlxsw_reg_pxbt_op op,
2119 u8 local_port, u16 acl_info)
2120{
2121 MLXSW_REG_ZERO(ppbt, payload);
2122 mlxsw_reg_ppbt_e_set(payload, e);
2123 mlxsw_reg_ppbt_op_set(payload, op);
2124 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125 mlxsw_reg_ppbt_g_set(payload, true);
2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2127}
2128
2129
2130
2131
2132
2133#define MLXSW_REG_PACL_ID 0x3004
2134#define MLXSW_REG_PACL_LEN 0x70
2135
2136MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2137
2138
2139
2140
2141
2142
2143MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2144
2145
2146
2147
2148
2149
2150MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2151
2152#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2153
2154
2155
2156
2157
2158
2159MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2161
2162static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163 bool valid, const char *tcam_region_info)
2164{
2165 MLXSW_REG_ZERO(pacl, payload);
2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167 mlxsw_reg_pacl_v_set(payload, valid);
2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2169}
2170
2171
2172
2173
2174
2175#define MLXSW_REG_PAGT_ID 0x3005
2176#define MLXSW_REG_PAGT_BASE_LEN 0x30
2177#define MLXSW_REG_PAGT_ACL_LEN 4
2178#define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2181
2182MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2194
2195
2196
2197
2198
2199
2200MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2201
2202
2203
2204
2205
2206
2207
2208MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2209
2210
2211
2212
2213
2214MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2215
2216static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2217{
2218 MLXSW_REG_ZERO(pagt, payload);
2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2220}
2221
2222static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223 u16 acl_id, bool multi)
2224{
2225 u8 size = mlxsw_reg_pagt_size_get(payload);
2226
2227 if (index >= size)
2228 mlxsw_reg_pagt_size_set(payload, index + 1);
2229 mlxsw_reg_pagt_multi_set(payload, index, multi);
2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2231}
2232
2233
2234
2235
2236
2237
2238#define MLXSW_REG_PTAR_ID 0x3006
2239#define MLXSW_REG_PTAR_BASE_LEN 0x20
2240#define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2244
2245MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2246
2247enum mlxsw_reg_ptar_op {
2248
2249 MLXSW_REG_PTAR_OP_ALLOC,
2250
2251 MLXSW_REG_PTAR_OP_RESIZE,
2252
2253 MLXSW_REG_PTAR_OP_FREE,
2254
2255 MLXSW_REG_PTAR_OP_TEST,
2256};
2257
2258
2259
2260
2261MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2262
2263
2264
2265
2266
2267
2268MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2269
2270enum mlxsw_reg_ptar_key_type {
2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50,
2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51,
2273};
2274
2275
2276
2277
2278
2279MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2290
2291
2292
2293
2294
2295
2296MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2297
2298
2299
2300
2301
2302
2303
2304MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2317
2318static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319 enum mlxsw_reg_ptar_key_type key_type,
2320 u16 region_size, u16 region_id,
2321 const char *tcam_region_info)
2322{
2323 MLXSW_REG_ZERO(ptar, payload);
2324 mlxsw_reg_ptar_op_set(payload, op);
2325 mlxsw_reg_ptar_action_set_type_set(payload, 2);
2326 mlxsw_reg_ptar_key_type_set(payload, key_type);
2327 mlxsw_reg_ptar_region_size_set(payload, region_size);
2328 mlxsw_reg_ptar_region_id_set(payload, region_id);
2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2330}
2331
2332static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2333 u16 key_id)
2334{
2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2336}
2337
2338static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2339{
2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2341}
2342
2343
2344
2345
2346
2347#define MLXSW_REG_PPBS_ID 0x300C
2348#define MLXSW_REG_PPBS_LEN 0x14
2349
2350MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2351
2352
2353
2354
2355
2356
2357MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2358
2359
2360
2361
2362
2363MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2364
2365static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2366 u16 system_port)
2367{
2368 MLXSW_REG_ZERO(ppbs, payload);
2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2371}
2372
2373
2374
2375
2376
2377#define MLXSW_REG_PRCR_ID 0x300D
2378#define MLXSW_REG_PRCR_LEN 0x40
2379
2380MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2381
2382enum mlxsw_reg_prcr_op {
2383
2384
2385
2386
2387 MLXSW_REG_PRCR_OP_MOVE,
2388
2389
2390
2391
2392 MLXSW_REG_PRCR_OP_COPY,
2393};
2394
2395
2396
2397
2398MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2399
2400
2401
2402
2403
2404MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2405
2406
2407
2408
2409
2410MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2411
2412
2413
2414
2415
2416MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2418
2419
2420
2421
2422
2423MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2424
2425
2426
2427
2428
2429MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2431
2432static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433 const char *src_tcam_region_info,
2434 u16 src_offset,
2435 const char *dest_tcam_region_info,
2436 u16 dest_offset, u16 size)
2437{
2438 MLXSW_REG_ZERO(prcr, payload);
2439 mlxsw_reg_prcr_op_set(payload, op);
2440 mlxsw_reg_prcr_offset_set(payload, src_offset);
2441 mlxsw_reg_prcr_size_set(payload, size);
2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443 src_tcam_region_info);
2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446 dest_tcam_region_info);
2447}
2448
2449
2450
2451
2452
2453
2454#define MLXSW_REG_PEFA_ID 0x300F
2455#define MLXSW_REG_PEFA_LEN 0xB0
2456
2457MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2458
2459
2460
2461
2462
2463MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2464
2465
2466
2467
2468
2469
2470
2471
2472MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2473
2474
2475
2476
2477
2478
2479
2480MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2481
2482#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2483
2484
2485
2486
2487
2488
2489MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2490
2491static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492 const char *flex_action_set)
2493{
2494 MLXSW_REG_ZERO(pefa, payload);
2495 mlxsw_reg_pefa_index_set(payload, index);
2496 mlxsw_reg_pefa_ca_set(payload, ca);
2497 if (flex_action_set)
2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2499 flex_action_set);
2500}
2501
2502static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2503{
2504 *p_a = mlxsw_reg_pefa_a_get(payload);
2505}
2506
2507
2508
2509
2510
2511
2512
2513#define MLXSW_REG_PEMRBT_ID 0x3014
2514#define MLXSW_REG_PEMRBT_LEN 0x14
2515
2516MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2517
2518enum mlxsw_reg_pemrbt_protocol {
2519 MLXSW_REG_PEMRBT_PROTO_IPV4,
2520 MLXSW_REG_PEMRBT_PROTO_IPV6,
2521};
2522
2523
2524
2525
2526MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2527
2528
2529
2530
2531
2532
2533MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2534
2535static inline void
2536mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2537 u16 group_id)
2538{
2539 MLXSW_REG_ZERO(pemrbt, payload);
2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2542}
2543
2544
2545
2546
2547
2548
2549
2550
2551#define MLXSW_REG_PTCE2_ID 0x3017
2552#define MLXSW_REG_PTCE2_LEN 0x1D8
2553
2554MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2555
2556
2557
2558
2559
2560MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2561
2562
2563
2564
2565
2566
2567MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2568
2569enum mlxsw_reg_ptce2_op {
2570
2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572
2573
2574
2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576
2577
2578
2579
2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581
2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583
2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2585};
2586
2587
2588
2589
2590MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2591
2592
2593
2594
2595MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2596
2597
2598
2599
2600
2601
2602
2603
2604MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2605
2606
2607
2608
2609
2610MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2612
2613#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2614
2615
2616
2617
2618
2619MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2621
2622
2623
2624
2625
2626
2627
2628MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2630
2631
2632
2633
2634
2635MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636 MLXSW_REG_FLEX_ACTION_SET_LEN);
2637
2638static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639 enum mlxsw_reg_ptce2_op op,
2640 const char *tcam_region_info,
2641 u16 offset, u32 priority)
2642{
2643 MLXSW_REG_ZERO(ptce2, payload);
2644 mlxsw_reg_ptce2_v_set(payload, valid);
2645 mlxsw_reg_ptce2_op_set(payload, op);
2646 mlxsw_reg_ptce2_offset_set(payload, offset);
2647 mlxsw_reg_ptce2_priority_set(payload, priority);
2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2649}
2650
2651
2652
2653
2654
2655#define MLXSW_REG_PERPT_ID 0x3021
2656#define MLXSW_REG_PERPT_LEN 0x80
2657
2658MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2659
2660
2661
2662
2663
2664
2665MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2666
2667
2668
2669
2670
2671
2672MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2673
2674enum mlxsw_reg_perpt_key_size {
2675 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2679};
2680
2681
2682
2683
2684MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2685
2686
2687
2688
2689
2690
2691
2692
2693MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2694
2695
2696
2697
2698
2699MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2700
2701
2702
2703
2704
2705
2706MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2707
2708
2709
2710
2711
2712
2713MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2714
2715
2716
2717
2718
2719MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2720
2721
2722
2723
2724
2725MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2726
2727
2728
2729
2730
2731
2732
2733MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2734
2735static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736 unsigned long *erp_vector,
2737 unsigned long size)
2738{
2739 unsigned long bit;
2740
2741 for_each_set_bit(bit, erp_vector, size)
2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2743}
2744
2745static inline void
2746mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2749 char *mask)
2750{
2751 MLXSW_REG_ZERO(perpt, payload);
2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754 mlxsw_reg_perpt_key_size_set(payload, key_size);
2755 mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2761}
2762
2763
2764
2765
2766
2767
2768#define MLXSW_REG_PERAR_ID 0x3026
2769#define MLXSW_REG_PERAR_LEN 0x08
2770
2771MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2772
2773
2774
2775
2776
2777
2778MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2779
2780static inline unsigned int
2781mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2782{
2783 return DIV_ROUND_UP(block_num, 4);
2784}
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2795
2796static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2797 u16 hw_region)
2798{
2799 MLXSW_REG_ZERO(perar, payload);
2800 mlxsw_reg_perar_region_id_set(payload, region_id);
2801 mlxsw_reg_perar_hw_region_set(payload, hw_region);
2802}
2803
2804
2805
2806
2807
2808
2809#define MLXSW_REG_PTCE3_ID 0x3027
2810#define MLXSW_REG_PTCE3_LEN 0xF0
2811
2812MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2813
2814
2815
2816
2817
2818MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2819
2820enum mlxsw_reg_ptce3_op {
2821
2822
2823
2824
2825
2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827
2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829
2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2831};
2832
2833
2834
2835
2836MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2837
2838
2839
2840
2841
2842
2843
2844MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2845
2846
2847
2848
2849
2850MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2852
2853
2854
2855
2856
2857
2858MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2860
2861
2862
2863
2864
2865MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2866
2867
2868
2869
2870
2871
2872MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2884
2885
2886
2887
2888
2889
2890MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2903
2904
2905
2906
2907
2908
2909
2910MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2934
2935
2936
2937
2938
2939
2940MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2941
2942static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943 enum mlxsw_reg_ptce3_op op,
2944 u32 priority,
2945 const char *tcam_region_info,
2946 const char *key, u8 erp_id,
2947 u16 delta_start, u8 delta_mask,
2948 u8 delta_value, bool large_exists,
2949 u32 lkey_id, u32 action_pointer)
2950{
2951 MLXSW_REG_ZERO(ptce3, payload);
2952 mlxsw_reg_ptce3_v_set(payload, valid);
2953 mlxsw_reg_ptce3_op_set(payload, op);
2954 mlxsw_reg_ptce3_priority_set(payload, priority);
2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2964}
2965
2966
2967
2968
2969
2970
2971#define MLXSW_REG_PERCR_ID 0x302A
2972#define MLXSW_REG_PERCR_LEN 0x80
2973
2974MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2975
2976
2977
2978
2979
2980
2981MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2982
2983
2984
2985
2986
2987MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2988
2989
2990
2991
2992
2993MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2994
2995
2996
2997
2998
2999
3000
3001
3002MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3003
3004
3005
3006
3007
3008
3009
3010MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3011
3012static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3013{
3014 MLXSW_REG_ZERO(percr, payload);
3015 mlxsw_reg_percr_region_id_set(payload, region_id);
3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018 mlxsw_reg_percr_bf_bypass_set(payload, false);
3019}
3020
3021
3022
3023
3024
3025
3026#define MLXSW_REG_PERERP_ID 0x302B
3027#define MLXSW_REG_PERERP_LEN 0x1C
3028
3029MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3030
3031
3032
3033
3034
3035
3036MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3037
3038
3039
3040
3041
3042MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3043
3044
3045
3046
3047
3048MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3049
3050
3051
3052
3053
3054
3055MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3056
3057
3058
3059
3060
3061
3062
3063
3064MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3065
3066
3067
3068
3069
3070
3071
3072
3073MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3074
3075
3076
3077
3078
3079
3080
3081MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3082
3083static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084 unsigned long *erp_vector,
3085 unsigned long size)
3086{
3087 unsigned long bit;
3088
3089 for_each_set_bit(bit, erp_vector, size)
3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3091}
3092
3093static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094 bool ctcam_le, bool erpt_pointer_valid,
3095 u8 erpt_bank_pointer, u8 erpt_pointer,
3096 u8 master_rp_id)
3097{
3098 MLXSW_REG_ZERO(pererp, payload);
3099 mlxsw_reg_pererp_region_id_set(payload, region_id);
3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3105}
3106
3107
3108
3109
3110
3111#define MLXSW_REG_PEABFE_ID 0x3022
3112#define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113#define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116 MLXSW_REG_PEABFE_BF_REC_LEN * \
3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3118
3119MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3120
3121
3122
3123
3124
3125
3126MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3127
3128
3129
3130
3131
3132
3133
3134MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3137
3138
3139
3140
3141
3142
3143MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3146
3147
3148
3149
3150
3151
3152MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3155
3156static inline void mlxsw_reg_peabfe_pack(char *payload)
3157{
3158 MLXSW_REG_ZERO(peabfe, payload);
3159}
3160
3161static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162 u8 state, u8 bank, u32 bf_index)
3163{
3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3165
3166 if (rec_index >= num_rec)
3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3171}
3172
3173
3174
3175
3176
3177
3178
3179#define MLXSW_REG_IEDR_ID 0x3804
3180#define MLXSW_REG_IEDR_BASE_LEN 0x10
3181#define MLXSW_REG_IEDR_REC_LEN 0x8
3182#define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3184 MLXSW_REG_IEDR_REC_LEN * \
3185 MLXSW_REG_IEDR_REC_MAX_COUNT)
3186
3187MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3188
3189
3190
3191
3192
3193MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3194
3195
3196
3197
3198
3199MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3201
3202
3203
3204
3205
3206MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3208
3209
3210
3211
3212
3213MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3215
3216static inline void mlxsw_reg_iedr_pack(char *payload)
3217{
3218 MLXSW_REG_ZERO(iedr, payload);
3219}
3220
3221static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222 u8 rec_type, u16 rec_size,
3223 u32 rec_index_start)
3224{
3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3226
3227 if (rec_index >= num_rec)
3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3232}
3233
3234
3235
3236
3237
3238
3239#define MLXSW_REG_QPTS_ID 0x4002
3240#define MLXSW_REG_QPTS_LEN 0x8
3241
3242MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3243
3244
3245
3246
3247
3248
3249
3250MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3251
3252enum mlxsw_reg_qpts_trust_state {
3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2,
3255};
3256
3257
3258
3259
3260
3261MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3262
3263static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264 enum mlxsw_reg_qpts_trust_state ts)
3265{
3266 MLXSW_REG_ZERO(qpts, payload);
3267
3268 mlxsw_reg_qpts_local_port_set(payload, local_port);
3269 mlxsw_reg_qpts_trust_state_set(payload, ts);
3270}
3271
3272
3273
3274
3275
3276
3277#define MLXSW_REG_QPCR_ID 0x4004
3278#define MLXSW_REG_QPCR_LEN 0x28
3279
3280MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3281
3282enum mlxsw_reg_qpcr_g {
3283 MLXSW_REG_QPCR_G_GLOBAL = 2,
3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3285};
3286
3287
3288
3289
3290
3291MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3292
3293
3294
3295
3296
3297MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3298
3299
3300
3301
3302
3303
3304MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3305
3306
3307
3308
3309
3310
3311
3312MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3313
3314enum mlxsw_reg_qpcr_ir_units {
3315 MLXSW_REG_QPCR_IR_UNITS_M,
3316 MLXSW_REG_QPCR_IR_UNITS_K,
3317};
3318
3319
3320
3321
3322
3323
3324
3325MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3326
3327enum mlxsw_reg_qpcr_rate_type {
3328 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3330};
3331
3332
3333
3334
3335
3336
3337
3338MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3352
3353
3354
3355
3356
3357
3358
3359
3360MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3371
3372#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3373
3374
3375
3376
3377
3378MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3379
3380enum mlxsw_reg_qpcr_action {
3381
3382 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383
3384
3385
3386 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3387};
3388
3389
3390
3391
3392
3393
3394MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3395
3396static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397 enum mlxsw_reg_qpcr_ir_units ir_units,
3398 bool bytes, u32 cir, u16 cbs)
3399{
3400 MLXSW_REG_ZERO(qpcr, payload);
3401 mlxsw_reg_qpcr_pid_set(payload, pid);
3402 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404 mlxsw_reg_qpcr_violate_action_set(payload,
3405 MLXSW_REG_QPCR_ACTION_DISCARD);
3406 mlxsw_reg_qpcr_cir_set(payload, cir);
3407 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3410}
3411
3412
3413
3414
3415
3416
3417#define MLXSW_REG_QTCT_ID 0x400A
3418#define MLXSW_REG_QTCT_LEN 0x08
3419
3420MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3421
3422
3423
3424
3425
3426
3427
3428MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3429
3430
3431
3432
3433
3434
3435MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3436
3437
3438
3439
3440
3441MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3452
3453static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454 u8 switch_prio, u8 tclass)
3455{
3456 MLXSW_REG_ZERO(qtct, payload);
3457 mlxsw_reg_qtct_local_port_set(payload, local_port);
3458 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459 mlxsw_reg_qtct_tclass_set(payload, tclass);
3460}
3461
3462
3463
3464
3465
3466#define MLXSW_REG_QEEC_ID 0x400D
3467#define MLXSW_REG_QEEC_LEN 0x20
3468
3469MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3470
3471
3472
3473
3474
3475
3476
3477MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3478
3479enum mlxsw_reg_qeec_hr {
3480 MLXSW_REG_QEEC_HIERARCY_PORT,
3481 MLXSW_REG_QEEC_HIERARCY_GROUP,
3482 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3483 MLXSW_REG_QEEC_HIERARCY_TC,
3484};
3485
3486
3487
3488
3489
3490
3491
3492
3493MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3494
3495
3496
3497
3498
3499MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3500
3501
3502
3503
3504
3505
3506
3507MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3508
3509
3510
3511
3512
3513
3514
3515
3516MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3529
3530enum {
3531 MLXSW_REG_QEEC_BYTES_MODE,
3532 MLXSW_REG_QEEC_PACKETS_MODE,
3533};
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3545
3546
3547#define MLXSW_REG_QEEC_MIS_MIN 200000
3548
3549
3550
3551
3552
3553
3554
3555MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3556
3557
3558
3559
3560
3561
3562
3563
3564MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3565
3566
3567#define MLXSW_REG_QEEC_MAS_DIS 200000000
3568
3569
3570
3571
3572
3573
3574
3575MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3576
3577
3578
3579
3580
3581
3582
3583
3584MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3585
3586
3587
3588
3589
3590
3591
3592
3593MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3604
3605static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3606 enum mlxsw_reg_qeec_hr hr, u8 index,
3607 u8 next_index)
3608{
3609 MLXSW_REG_ZERO(qeec, payload);
3610 mlxsw_reg_qeec_local_port_set(payload, local_port);
3611 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3612 mlxsw_reg_qeec_element_index_set(payload, index);
3613 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3614}
3615
3616static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3617 bool ptps)
3618{
3619 MLXSW_REG_ZERO(qeec, payload);
3620 mlxsw_reg_qeec_local_port_set(payload, local_port);
3621 mlxsw_reg_qeec_element_hierarchy_set(payload,
3622 MLXSW_REG_QEEC_HIERARCY_PORT);
3623 mlxsw_reg_qeec_ptps_set(payload, ptps);
3624}
3625
3626
3627
3628
3629
3630#define MLXSW_REG_QRWE_ID 0x400F
3631#define MLXSW_REG_QRWE_LEN 0x08
3632
3633MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3634
3635
3636
3637
3638
3639
3640
3641MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3642
3643
3644
3645
3646
3647MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3648
3649
3650
3651
3652
3653MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3654
3655static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3656 bool rewrite_pcp, bool rewrite_dscp)
3657{
3658 MLXSW_REG_ZERO(qrwe, payload);
3659 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3660 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3661 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3662}
3663
3664
3665
3666
3667
3668#define MLXSW_REG_QPDSM_ID 0x4011
3669#define MLXSW_REG_QPDSM_BASE_LEN 0x04
3670#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4
3671#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3672#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3673 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3674 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3675
3676MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3677
3678
3679
3680
3681
3682MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3683
3684
3685
3686
3687
3688MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3689 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3690 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3691
3692
3693
3694
3695
3696
3697MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3698 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3699 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3700
3701
3702
3703
3704
3705MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3706 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3707 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3708
3709
3710
3711
3712
3713
3714MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3715 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3716 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3717
3718
3719
3720
3721
3722MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3723 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3724 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3725
3726
3727
3728
3729
3730
3731MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3732 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3733 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3734
3735static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3736{
3737 MLXSW_REG_ZERO(qpdsm, payload);
3738 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3739}
3740
3741static inline void
3742mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3743{
3744 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3745 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3746 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3747 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3748 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3749 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3750}
3751
3752
3753
3754
3755
3756
3757#define MLXSW_REG_QPDPM_ID 0x4013
3758#define MLXSW_REG_QPDPM_BASE_LEN 0x4
3759#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2
3760#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3761#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
3762 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
3763 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3764
3765MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3766
3767
3768
3769
3770
3771MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3772
3773
3774
3775
3776
3777
3778
3779MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3780 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3781
3782
3783
3784
3785
3786MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3787 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3788 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3789
3790static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3791{
3792 MLXSW_REG_ZERO(qpdpm, payload);
3793 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3794}
3795
3796static inline void
3797mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3798{
3799 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3800 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3801}
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812#define MLXSW_REG_QTCTM_ID 0x401A
3813#define MLXSW_REG_QTCTM_LEN 0x08
3814
3815MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3816
3817
3818
3819
3820
3821
3822MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3823
3824
3825
3826
3827
3828
3829MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3830
3831static inline void
3832mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3833{
3834 MLXSW_REG_ZERO(qtctm, payload);
3835 mlxsw_reg_qtctm_local_port_set(payload, local_port);
3836 mlxsw_reg_qtctm_mc_set(payload, mc);
3837}
3838
3839
3840
3841
3842
3843
3844#define MLXSW_REG_QPSC_ID 0x401B
3845#define MLXSW_REG_QPSC_LEN 0x28
3846
3847MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
3848
3849enum mlxsw_reg_qpsc_port_speed {
3850 MLXSW_REG_QPSC_PORT_SPEED_100M,
3851 MLXSW_REG_QPSC_PORT_SPEED_1G,
3852 MLXSW_REG_QPSC_PORT_SPEED_10G,
3853 MLXSW_REG_QPSC_PORT_SPEED_25G,
3854};
3855
3856
3857
3858
3859
3860MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
3861
3862
3863
3864
3865
3866
3867
3868MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
3869
3870
3871
3872
3873
3874
3875
3876MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
3877
3878
3879
3880
3881
3882
3883MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
3884
3885
3886
3887
3888
3889
3890
3891MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
3892
3893
3894
3895
3896
3897MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
3898
3899
3900
3901
3902
3903
3904
3905MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
3926
3927static inline void
3928mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
3929 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
3930 u8 shaper_bs, u8 port_to_shaper_credits,
3931 int ing_timestamp_inc, int egr_timestamp_inc)
3932{
3933 MLXSW_REG_ZERO(qpsc, payload);
3934 mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
3935 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
3936 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
3937 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
3938 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
3939 mlxsw_reg_qpsc_ptsc_we_set(payload, true);
3940 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
3941 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
3942 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
3943}
3944
3945
3946
3947
3948
3949#define MLXSW_REG_PMLP_ID 0x5002
3950#define MLXSW_REG_PMLP_LEN 0x40
3951
3952MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3953
3954
3955
3956
3957
3958
3959MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3960
3961
3962
3963
3964
3965MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3966
3967
3968
3969
3970
3971
3972
3973
3974MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3975
3976
3977
3978
3979
3980MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3981
3982
3983
3984
3985
3986MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3987
3988
3989
3990
3991
3992
3993MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3994
3995static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3996{
3997 MLXSW_REG_ZERO(pmlp, payload);
3998 mlxsw_reg_pmlp_local_port_set(payload, local_port);
3999}
4000
4001
4002
4003
4004
4005#define MLXSW_REG_PMTU_ID 0x5003
4006#define MLXSW_REG_PMTU_LEN 0x10
4007
4008MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4009
4010
4011
4012
4013
4014MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
4015
4016
4017
4018
4019
4020
4021
4022
4023MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4024
4025
4026
4027
4028
4029
4030
4031MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4032
4033
4034
4035
4036
4037
4038
4039
4040MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4041
4042static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
4043 u16 new_mtu)
4044{
4045 MLXSW_REG_ZERO(pmtu, payload);
4046 mlxsw_reg_pmtu_local_port_set(payload, local_port);
4047 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4048 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4049 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4050}
4051
4052
4053
4054
4055
4056
4057
4058
4059#define MLXSW_REG_PTYS_ID 0x5004
4060#define MLXSW_REG_PTYS_LEN 0x40
4061
4062MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4063
4064
4065
4066
4067
4068
4069
4070MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4071
4072
4073
4074
4075
4076MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
4077
4078#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
4079#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
4080
4081
4082
4083
4084
4085
4086
4087
4088MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4089
4090enum {
4091 MLXSW_REG_PTYS_AN_STATUS_NA,
4092 MLXSW_REG_PTYS_AN_STATUS_OK,
4093 MLXSW_REG_PTYS_AN_STATUS_FAIL,
4094};
4095
4096
4097
4098
4099
4100MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4101
4102#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
4103#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
4104#define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2)
4105#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
4106#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
4107#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
4108#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
4109#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
4110#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
4111#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
4112#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
4113#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
4114
4115
4116
4117
4118
4119MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4120
4121#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
4122#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
4123#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
4124#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
4125#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
4126#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
4127#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
4128#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
4129#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
4130#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
4131#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
4132#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
4133#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
4134#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
4135#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
4136#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
4137#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
4138#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
4139#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
4140#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
4141#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
4142#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
4143#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
4144#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
4145#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
4146#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
4147#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
4148#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
4149
4150
4151
4152
4153
4154MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4155
4156
4157
4158
4159
4160MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4161
4162#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
4163#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
4164#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
4165#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
4166#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
4167#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
4168
4169
4170
4171
4172
4173MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4174
4175
4176
4177
4178
4179MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4180
4181
4182
4183
4184
4185MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4186
4187
4188
4189
4190
4191MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4192
4193
4194
4195
4196
4197MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4198
4199
4200
4201
4202
4203MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4204
4205
4206
4207
4208
4209MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4210
4211
4212
4213
4214
4215MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4216
4217
4218
4219
4220
4221MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4222
4223enum mlxsw_reg_ptys_connector_type {
4224 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4225 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4226 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4227 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4228 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4229 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4230 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4231 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4232 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4233};
4234
4235
4236
4237
4238
4239MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4240
4241static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4242 u32 proto_admin, bool autoneg)
4243{
4244 MLXSW_REG_ZERO(ptys, payload);
4245 mlxsw_reg_ptys_local_port_set(payload, local_port);
4246 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4247 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4248 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4249}
4250
4251static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4252 u32 proto_admin, bool autoneg)
4253{
4254 MLXSW_REG_ZERO(ptys, payload);
4255 mlxsw_reg_ptys_local_port_set(payload, local_port);
4256 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4257 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4258 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4259}
4260
4261static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4262 u32 *p_eth_proto_cap,
4263 u32 *p_eth_proto_admin,
4264 u32 *p_eth_proto_oper)
4265{
4266 if (p_eth_proto_cap)
4267 *p_eth_proto_cap =
4268 mlxsw_reg_ptys_eth_proto_cap_get(payload);
4269 if (p_eth_proto_admin)
4270 *p_eth_proto_admin =
4271 mlxsw_reg_ptys_eth_proto_admin_get(payload);
4272 if (p_eth_proto_oper)
4273 *p_eth_proto_oper =
4274 mlxsw_reg_ptys_eth_proto_oper_get(payload);
4275}
4276
4277static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4278 u32 *p_eth_proto_cap,
4279 u32 *p_eth_proto_admin,
4280 u32 *p_eth_proto_oper)
4281{
4282 if (p_eth_proto_cap)
4283 *p_eth_proto_cap =
4284 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4285 if (p_eth_proto_admin)
4286 *p_eth_proto_admin =
4287 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4288 if (p_eth_proto_oper)
4289 *p_eth_proto_oper =
4290 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4291}
4292
4293static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4294 u16 proto_admin, u16 link_width)
4295{
4296 MLXSW_REG_ZERO(ptys, payload);
4297 mlxsw_reg_ptys_local_port_set(payload, local_port);
4298 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4299 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4300 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4301}
4302
4303static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4304 u16 *p_ib_link_width_cap,
4305 u16 *p_ib_proto_oper,
4306 u16 *p_ib_link_width_oper)
4307{
4308 if (p_ib_proto_cap)
4309 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4310 if (p_ib_link_width_cap)
4311 *p_ib_link_width_cap =
4312 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4313 if (p_ib_proto_oper)
4314 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4315 if (p_ib_link_width_oper)
4316 *p_ib_link_width_oper =
4317 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4318}
4319
4320
4321
4322
4323
4324#define MLXSW_REG_PPAD_ID 0x5005
4325#define MLXSW_REG_PPAD_LEN 0x10
4326
4327MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4328
4329
4330
4331
4332
4333
4334
4335MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4336
4337
4338
4339
4340
4341MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4342
4343
4344
4345
4346
4347
4348MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4349
4350static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4351 u8 local_port)
4352{
4353 MLXSW_REG_ZERO(ppad, payload);
4354 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4355 mlxsw_reg_ppad_local_port_set(payload, local_port);
4356}
4357
4358
4359
4360
4361
4362#define MLXSW_REG_PAOS_ID 0x5006
4363#define MLXSW_REG_PAOS_LEN 0x10
4364
4365MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4366
4367
4368
4369
4370
4371
4372
4373
4374MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4375
4376
4377
4378
4379
4380MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4402
4403
4404
4405
4406
4407MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4408
4409
4410
4411
4412
4413
4414MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4415
4416
4417
4418
4419
4420
4421
4422
4423MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4424
4425static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4426 enum mlxsw_port_admin_status status)
4427{
4428 MLXSW_REG_ZERO(paos, payload);
4429 mlxsw_reg_paos_swid_set(payload, 0);
4430 mlxsw_reg_paos_local_port_set(payload, local_port);
4431 mlxsw_reg_paos_admin_status_set(payload, status);
4432 mlxsw_reg_paos_oper_status_set(payload, 0);
4433 mlxsw_reg_paos_ase_set(payload, 1);
4434 mlxsw_reg_paos_ee_set(payload, 1);
4435 mlxsw_reg_paos_e_set(payload, 1);
4436}
4437
4438
4439
4440
4441
4442#define MLXSW_REG_PFCC_ID 0x5007
4443#define MLXSW_REG_PFCC_LEN 0x20
4444
4445MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4446
4447
4448
4449
4450
4451MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4452
4453
4454
4455
4456
4457
4458
4459MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4460
4461
4462
4463
4464
4465
4466
4467
4468MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4469
4470
4471
4472
4473
4474
4475
4476
4477MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4490
4491
4492
4493
4494
4495
4496MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4497
4498
4499
4500
4501
4502
4503MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4504
4505
4506
4507
4508
4509
4510
4511MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4512
4513
4514
4515
4516
4517
4518
4519MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4532
4533
4534
4535
4536
4537
4538
4539MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4540
4541
4542
4543
4544
4545
4546
4547MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4548
4549
4550
4551
4552
4553
4554
4555
4556MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4557
4558#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4559
4560static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4561{
4562 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4563 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4564 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4565 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4566}
4567
4568static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4569{
4570 MLXSW_REG_ZERO(pfcc, payload);
4571 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4572}
4573
4574
4575
4576
4577
4578#define MLXSW_REG_PPCNT_ID 0x5008
4579#define MLXSW_REG_PPCNT_LEN 0x100
4580#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4581
4582MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4594
4595
4596
4597
4598
4599
4600
4601MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4602
4603
4604
4605
4606
4607
4608
4609MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4610
4611enum mlxsw_reg_ppcnt_grp {
4612 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4613 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4614 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4615 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4616 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4617 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4618 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4619 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4620 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4621};
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4641
4642
4643
4644
4645
4646
4647
4648MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4659
4660
4661
4662
4663
4664
4665MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4666 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4667
4668
4669
4670
4671MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4672 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4673
4674
4675
4676
4677MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4678 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4679
4680
4681
4682
4683MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4684 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4685
4686
4687
4688
4689MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4690 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4691
4692
4693
4694
4695MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4696 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4697
4698
4699
4700
4701MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4702 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4703
4704
4705
4706
4707MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4708 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4709
4710
4711
4712
4713MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4714 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4715
4716
4717
4718
4719MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4720 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4721
4722
4723
4724
4725MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4726 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4727
4728
4729
4730
4731MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4732 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4733
4734
4735
4736
4737MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4738 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4739
4740
4741
4742
4743MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4744 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4745
4746
4747
4748
4749MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4750 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4751
4752
4753
4754
4755MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4756 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4757
4758
4759
4760
4761MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4762 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4763
4764
4765
4766
4767MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4768 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4769
4770
4771
4772
4773MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4774 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4775
4776
4777
4778
4779
4780
4781MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4782 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4783
4784
4785
4786
4787MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4788 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4789
4790
4791
4792
4793MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4794 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4795
4796
4797
4798
4799
4800
4801MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4802 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4803
4804
4805
4806
4807MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4808 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4809
4810
4811
4812
4813MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4814 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4815
4816
4817
4818
4819MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4820 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4821
4822
4823
4824
4825MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4826 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4827
4828
4829
4830
4831MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4832 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4833
4834
4835
4836
4837MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4838 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4839
4840
4841
4842
4843MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4844 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4845
4846
4847
4848
4849MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4850 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4851
4852
4853
4854
4855MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4856 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4857
4858
4859
4860
4861MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4862 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4863
4864
4865
4866
4867MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4868 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4869
4870
4871
4872
4873MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4874 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4875
4876
4877
4878
4879
4880
4881MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4882 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4883
4884
4885
4886
4887MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
4888 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4889
4890
4891
4892
4893MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
4894 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4895
4896
4897
4898
4899MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
4900 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4901
4902
4903
4904
4905
4906
4907MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4908 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4909
4910
4911
4912
4913
4914
4915MLXSW_ITEM64(reg, ppcnt, ingress_general,
4916 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4917
4918
4919
4920
4921MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
4922 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4923
4924
4925
4926
4927MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
4928 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4929
4930
4931
4932
4933MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
4934 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4935
4936
4937
4938
4939MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
4940 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4941
4942
4943
4944
4945MLXSW_ITEM64(reg, ppcnt, loopback_filter,
4946 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4947
4948
4949
4950
4951MLXSW_ITEM64(reg, ppcnt, egress_general,
4952 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4953
4954
4955
4956
4957MLXSW_ITEM64(reg, ppcnt, egress_hoq,
4958 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4959
4960
4961
4962
4963MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
4964 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4965
4966
4967
4968
4969MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
4970 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4971
4972
4973
4974
4975MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
4976 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4977
4978
4979
4980
4981MLXSW_ITEM64(reg, ppcnt, egress_sll,
4982 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4983
4984
4985
4986
4987
4988
4989MLXSW_ITEM64(reg, ppcnt, rx_octets,
4990 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4991
4992
4993
4994
4995MLXSW_ITEM64(reg, ppcnt, rx_frames,
4996 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4997
4998
4999
5000
5001MLXSW_ITEM64(reg, ppcnt, tx_octets,
5002 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5003
5004
5005
5006
5007MLXSW_ITEM64(reg, ppcnt, tx_frames,
5008 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5009
5010
5011
5012
5013MLXSW_ITEM64(reg, ppcnt, rx_pause,
5014 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5015
5016
5017
5018
5019MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5020 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5021
5022
5023
5024
5025MLXSW_ITEM64(reg, ppcnt, tx_pause,
5026 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5027
5028
5029
5030
5031MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5032 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5033
5034
5035
5036
5037MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5038 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5049 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5050
5051
5052
5053
5054
5055
5056MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5057 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5058
5059
5060
5061
5062
5063
5064MLXSW_ITEM64(reg, ppcnt, wred_discard,
5065 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5066
5067static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
5068 enum mlxsw_reg_ppcnt_grp grp,
5069 u8 prio_tc)
5070{
5071 MLXSW_REG_ZERO(ppcnt, payload);
5072 mlxsw_reg_ppcnt_swid_set(payload, 0);
5073 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5074 mlxsw_reg_ppcnt_pnat_set(payload, 0);
5075 mlxsw_reg_ppcnt_grp_set(payload, grp);
5076 mlxsw_reg_ppcnt_clr_set(payload, 0);
5077 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5078}
5079
5080
5081
5082
5083
5084#define MLXSW_REG_PLIB_ID 0x500A
5085#define MLXSW_REG_PLIB_LEN 0x10
5086
5087MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5088
5089
5090
5091
5092
5093MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
5094
5095
5096
5097
5098
5099MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5100
5101
5102
5103
5104
5105#define MLXSW_REG_PPTB_ID 0x500B
5106#define MLXSW_REG_PPTB_LEN 0x10
5107
5108MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5109
5110enum {
5111 MLXSW_REG_PPTB_MM_UM,
5112 MLXSW_REG_PPTB_MM_UNICAST,
5113 MLXSW_REG_PPTB_MM_MULTICAST,
5114};
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5126
5127
5128
5129
5130
5131MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5132
5133
5134
5135
5136
5137MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5138
5139
5140
5141
5142
5143
5144MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5145
5146
5147
5148
5149
5150
5151MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5152
5153
5154
5155
5156
5157
5158MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5159
5160
5161
5162
5163
5164
5165
5166
5167MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5168
5169
5170
5171
5172
5173
5174MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5175
5176#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5177
5178static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5179{
5180 MLXSW_REG_ZERO(pptb, payload);
5181 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5182 mlxsw_reg_pptb_local_port_set(payload, local_port);
5183 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5184 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5185}
5186
5187static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5188 u8 buff)
5189{
5190 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5191 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5192}
5193
5194
5195
5196
5197
5198
5199#define MLXSW_REG_PBMC_ID 0x500C
5200#define MLXSW_REG_PBMC_LEN 0x6C
5201
5202MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5203
5204
5205
5206
5207
5208MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5209
5210
5211
5212
5213
5214
5215MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5216
5217
5218
5219
5220
5221
5222
5223MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5224
5225#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5226
5227
5228
5229
5230
5231
5232
5233MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5234
5235
5236
5237
5238
5239
5240
5241
5242MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5243
5244
5245
5246
5247
5248
5249MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5261 0x08, 0x04, false);
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5273 0x08, 0x04, false);
5274
5275static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5276 u16 xoff_timer_value, u16 xoff_refresh)
5277{
5278 MLXSW_REG_ZERO(pbmc, payload);
5279 mlxsw_reg_pbmc_local_port_set(payload, local_port);
5280 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5281 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5282}
5283
5284static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5285 int buf_index,
5286 u16 size)
5287{
5288 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5289 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5290 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5291}
5292
5293static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5294 int buf_index, u16 size,
5295 u16 threshold)
5296{
5297 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5298 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5299 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5300 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5301 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5302}
5303
5304
5305
5306
5307
5308
5309#define MLXSW_REG_PSPA_ID 0x500D
5310#define MLXSW_REG_PSPA_LEN 0x8
5311
5312MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5313
5314
5315
5316
5317
5318MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5319
5320
5321
5322
5323
5324MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5325
5326
5327
5328
5329
5330
5331MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5332
5333static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5334{
5335 MLXSW_REG_ZERO(pspa, payload);
5336 mlxsw_reg_pspa_swid_set(payload, swid);
5337 mlxsw_reg_pspa_local_port_set(payload, local_port);
5338 mlxsw_reg_pspa_sub_port_set(payload, 0);
5339}
5340
5341
5342
5343
5344
5345#define MLXSW_REG_PPLR_ID 0x5018
5346#define MLXSW_REG_PPLR_LEN 0x8
5347
5348MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5349
5350
5351
5352
5353
5354MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5355
5356
5357
5358
5359#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5360
5361
5362
5363
5364
5365MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5366
5367static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5368 bool phy_local)
5369{
5370 MLXSW_REG_ZERO(pplr, payload);
5371 mlxsw_reg_pplr_local_port_set(payload, local_port);
5372 mlxsw_reg_pplr_lb_en_set(payload,
5373 phy_local ?
5374 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5375}
5376
5377
5378
5379
5380
5381#define MLXSW_REG_HTGT_ID 0x7002
5382#define MLXSW_REG_HTGT_LEN 0x20
5383
5384MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5385
5386
5387
5388
5389
5390MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5391
5392#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0
5393
5394
5395
5396
5397
5398MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5399
5400enum mlxsw_reg_htgt_trap_group {
5401 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5402 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
5403 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
5404 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5405 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5406 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5407 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
5408 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5409 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5410 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5411 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5412 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
5413 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
5414 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5415 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
5416 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5417 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5418 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
5419 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5420 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
5421 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
5422 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5423 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
5424 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
5425};
5426
5427
5428
5429
5430
5431
5432
5433MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5434
5435enum {
5436 MLXSW_REG_HTGT_POLICER_DISABLE,
5437 MLXSW_REG_HTGT_POLICER_ENABLE,
5438};
5439
5440
5441
5442
5443
5444MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
5445
5446#define MLXSW_REG_HTGT_INVALID_POLICER 0xff
5447
5448
5449
5450
5451
5452MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
5453
5454#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
5466
5467
5468
5469
5470
5471MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
5472
5473#define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
5487
5488#define MLXSW_REG_HTGT_DEFAULT_TC 7
5489
5490
5491
5492
5493
5494MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
5495
5496enum mlxsw_reg_htgt_local_path_rdq {
5497 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
5498 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
5499 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
5500 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
5501};
5502
5503
5504
5505
5506MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
5507
5508static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
5509 u8 priority, u8 tc)
5510{
5511 MLXSW_REG_ZERO(htgt, payload);
5512
5513 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
5514 mlxsw_reg_htgt_pide_set(payload,
5515 MLXSW_REG_HTGT_POLICER_DISABLE);
5516 } else {
5517 mlxsw_reg_htgt_pide_set(payload,
5518 MLXSW_REG_HTGT_POLICER_ENABLE);
5519 mlxsw_reg_htgt_pid_set(payload, policer_id);
5520 }
5521
5522 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
5523 mlxsw_reg_htgt_trap_group_set(payload, group);
5524 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
5525 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
5526 mlxsw_reg_htgt_priority_set(payload, priority);
5527 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
5528 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
5529}
5530
5531
5532
5533
5534
5535#define MLXSW_REG_HPKT_ID 0x7003
5536#define MLXSW_REG_HPKT_LEN 0x10
5537
5538MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
5539
5540enum {
5541 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
5542 MLXSW_REG_HPKT_ACK_REQUIRED,
5543};
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
5554
5555enum mlxsw_reg_hpkt_action {
5556 MLXSW_REG_HPKT_ACTION_FORWARD,
5557 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
5558 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
5559 MLXSW_REG_HPKT_ACTION_DISCARD,
5560 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5561 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5562};
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5578
5579
5580
5581
5582
5583MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5584
5585
5586
5587
5588
5589
5590
5591
5592MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5593
5594enum {
5595 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5596 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5597 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5598};
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5609
5610static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5611 enum mlxsw_reg_htgt_trap_group trap_group,
5612 bool is_ctrl)
5613{
5614 MLXSW_REG_ZERO(hpkt, payload);
5615 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5616 mlxsw_reg_hpkt_action_set(payload, action);
5617 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5618 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5619 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5620 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5621 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5622}
5623
5624
5625
5626
5627
5628#define MLXSW_REG_RGCR_ID 0x8001
5629#define MLXSW_REG_RGCR_LEN 0x28
5630
5631MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5632
5633
5634
5635
5636
5637MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5638
5639
5640
5641
5642
5643MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5644
5645
5646
5647
5648
5649
5650MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5688
5689static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5690 bool ipv6_en)
5691{
5692 MLXSW_REG_ZERO(rgcr, payload);
5693 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5694 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5695}
5696
5697
5698
5699
5700
5701#define MLXSW_REG_RITR_ID 0x8002
5702#define MLXSW_REG_RITR_LEN 0x40
5703
5704MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5705
5706
5707
5708
5709
5710MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5711
5712
5713
5714
5715
5716
5717MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5718
5719
5720
5721
5722
5723
5724MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5725
5726
5727
5728
5729
5730MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5731
5732
5733
5734
5735
5736MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5737
5738enum mlxsw_reg_ritr_if_type {
5739
5740 MLXSW_REG_RITR_VLAN_IF,
5741
5742 MLXSW_REG_RITR_FID_IF,
5743
5744 MLXSW_REG_RITR_SP_IF,
5745
5746 MLXSW_REG_RITR_LOOPBACK_IF,
5747};
5748
5749
5750
5751
5752
5753MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5754
5755enum {
5756 MLXSW_REG_RITR_RIF_CREATE,
5757 MLXSW_REG_RITR_RIF_DEL,
5758};
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5770
5771
5772
5773
5774
5775MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5776
5777
5778
5779
5780
5781
5782
5783
5784MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5785
5786
5787
5788
5789
5790
5791
5792
5793MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5794
5795
5796
5797
5798
5799
5800
5801MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5802
5803
5804
5805
5806
5807
5808
5809MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5810
5811
5812
5813
5814
5815
5816
5817
5818MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5819
5820
5821
5822
5823
5824MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5825
5826
5827
5828
5829
5830MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5831
5832
5833
5834
5835
5836MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5837
5838
5839
5840
5841
5842
5843MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5844
5845
5846
5847
5848
5849
5850MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5851
5852
5853
5854
5855
5856
5857MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5858
5859
5860
5861
5862
5863
5864
5865MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5866
5867
5868
5869
5870
5871
5872
5873
5874MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5875
5876static inline void mlxsw_reg_ritr_fid_set(char *payload,
5877 enum mlxsw_reg_ritr_if_type rif_type,
5878 u16 fid)
5879{
5880 if (rif_type == MLXSW_REG_RITR_FID_IF)
5881 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5882 else
5883 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5884}
5885
5886
5887
5888
5889
5890
5891
5892
5893MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5894
5895
5896
5897
5898
5899
5900MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5901
5902
5903
5904
5905
5906MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5907
5908
5909
5910enum mlxsw_reg_ritr_loopback_protocol {
5911
5912 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5913
5914 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5915
5916 MLXSW_REG_RITR_LOOPBACK_GENERIC,
5917};
5918
5919
5920
5921
5922MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5923
5924enum mlxsw_reg_ritr_loopback_ipip_type {
5925
5926 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5927
5928 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5929
5930 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5931};
5932
5933
5934
5935
5936
5937MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5938
5939enum mlxsw_reg_ritr_loopback_ipip_options {
5940
5941 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5942};
5943
5944
5945
5946
5947MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5948
5949
5950
5951
5952
5953
5954
5955MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5956
5957
5958
5959
5960
5961
5962MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
5963
5964
5965
5966
5967
5968MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5969MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5970
5971
5972
5973
5974
5975
5976MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5977
5978
5979enum mlxsw_reg_ritr_counter_set_type {
5980
5981 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5982
5983
5984
5985
5986
5987
5988 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
5989};
5990
5991
5992
5993
5994
5995MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
5996
5997
5998
5999
6000
6001MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6002
6003
6004
6005
6006
6007MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6008
6009
6010
6011
6012
6013MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6014
6015static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6016 bool enable, bool egress)
6017{
6018 enum mlxsw_reg_ritr_counter_set_type set_type;
6019
6020 if (enable)
6021 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6022 else
6023 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6024 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6025
6026 if (egress)
6027 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6028 else
6029 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6030}
6031
6032static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6033{
6034 MLXSW_REG_ZERO(ritr, payload);
6035 mlxsw_reg_ritr_rif_set(payload, rif);
6036}
6037
6038static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6039 u16 system_port, u16 vid)
6040{
6041 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6042 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6043 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6044}
6045
6046static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6047 enum mlxsw_reg_ritr_if_type type,
6048 u16 rif, u16 vr_id, u16 mtu)
6049{
6050 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6051
6052 MLXSW_REG_ZERO(ritr, payload);
6053 mlxsw_reg_ritr_enable_set(payload, enable);
6054 mlxsw_reg_ritr_ipv4_set(payload, 1);
6055 mlxsw_reg_ritr_ipv6_set(payload, 1);
6056 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6057 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6058 mlxsw_reg_ritr_type_set(payload, type);
6059 mlxsw_reg_ritr_op_set(payload, op);
6060 mlxsw_reg_ritr_rif_set(payload, rif);
6061 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6062 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6063 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6064 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6065 mlxsw_reg_ritr_lb_en_set(payload, 1);
6066 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6067 mlxsw_reg_ritr_mtu_set(payload, mtu);
6068}
6069
6070static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6071{
6072 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6073}
6074
6075static inline void
6076mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6077 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6078 enum mlxsw_reg_ritr_loopback_ipip_options options,
6079 u16 uvr_id, u16 underlay_rif, u32 gre_key)
6080{
6081 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6082 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6083 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6084 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6085 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6086}
6087
6088static inline void
6089mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6090 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6091 enum mlxsw_reg_ritr_loopback_ipip_options options,
6092 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6093{
6094 mlxsw_reg_ritr_loopback_protocol_set(payload,
6095 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6096 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6097 uvr_id, underlay_rif, gre_key);
6098 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6099}
6100
6101
6102
6103
6104
6105#define MLXSW_REG_RTAR_ID 0x8004
6106#define MLXSW_REG_RTAR_LEN 0x20
6107
6108MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6109
6110enum mlxsw_reg_rtar_op {
6111 MLXSW_REG_RTAR_OP_ALLOCATE,
6112 MLXSW_REG_RTAR_OP_RESIZE,
6113 MLXSW_REG_RTAR_OP_DEALLOCATE,
6114};
6115
6116
6117
6118
6119MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6120
6121enum mlxsw_reg_rtar_key_type {
6122 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6123 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6124};
6125
6126
6127
6128
6129
6130MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6131
6132
6133
6134
6135
6136
6137
6138
6139MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6140
6141static inline void mlxsw_reg_rtar_pack(char *payload,
6142 enum mlxsw_reg_rtar_op op,
6143 enum mlxsw_reg_rtar_key_type key_type,
6144 u16 region_size)
6145{
6146 MLXSW_REG_ZERO(rtar, payload);
6147 mlxsw_reg_rtar_op_set(payload, op);
6148 mlxsw_reg_rtar_key_type_set(payload, key_type);
6149 mlxsw_reg_rtar_region_size_set(payload, region_size);
6150}
6151
6152
6153
6154
6155
6156
6157#define MLXSW_REG_RATR_ID 0x8008
6158#define MLXSW_REG_RATR_LEN 0x2C
6159
6160MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6161
6162enum mlxsw_reg_ratr_op {
6163
6164 MLXSW_REG_RATR_OP_QUERY_READ = 0,
6165
6166 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6167
6168 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6169
6170
6171
6172
6173
6174
6175 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6176};
6177
6178
6179
6180
6181
6182
6183
6184MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6199
6200
6201
6202
6203
6204
6205MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6206
6207enum mlxsw_reg_ratr_type {
6208
6209 MLXSW_REG_RATR_TYPE_ETHERNET,
6210
6211
6212
6213 MLXSW_REG_RATR_TYPE_IPOIB_UC,
6214
6215
6216
6217
6218 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6219
6220
6221
6222 MLXSW_REG_RATR_TYPE_IPOIB_MC,
6223
6224
6225
6226 MLXSW_REG_RATR_TYPE_MPLS,
6227
6228
6229
6230 MLXSW_REG_RATR_TYPE_IPIP,
6231};
6232
6233
6234
6235
6236
6237MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6238
6239
6240
6241
6242
6243
6244
6245
6246MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6247
6248
6249
6250
6251
6252MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6253
6254enum mlxsw_reg_ratr_trap_action {
6255 MLXSW_REG_RATR_TRAP_ACTION_NOP,
6256 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6257 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6258 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6259 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6260};
6261
6262
6263
6264
6265
6266MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6267
6268
6269
6270
6271
6272MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6273
6274enum mlxsw_reg_ratr_trap_id {
6275 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6276 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6277};
6278
6279
6280
6281
6282
6283
6284
6285MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6286
6287
6288
6289
6290
6291MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6292
6293enum mlxsw_reg_ratr_ipip_type {
6294
6295 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6296
6297 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6298};
6299
6300
6301
6302
6303
6304
6305MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6306
6307
6308
6309
6310
6311
6312MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6313
6314
6315
6316
6317
6318
6319MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6320
6321enum mlxsw_reg_flow_counter_set_type {
6322
6323 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6324
6325 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6326
6327 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6328};
6329
6330
6331
6332
6333
6334MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6335
6336
6337
6338
6339
6340MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6341
6342static inline void
6343mlxsw_reg_ratr_pack(char *payload,
6344 enum mlxsw_reg_ratr_op op, bool valid,
6345 enum mlxsw_reg_ratr_type type,
6346 u32 adjacency_index, u16 egress_rif)
6347{
6348 MLXSW_REG_ZERO(ratr, payload);
6349 mlxsw_reg_ratr_op_set(payload, op);
6350 mlxsw_reg_ratr_v_set(payload, valid);
6351 mlxsw_reg_ratr_type_set(payload, type);
6352 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6353 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6354 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6355}
6356
6357static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6358 const char *dest_mac)
6359{
6360 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6361}
6362
6363static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6364{
6365 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6366 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6367}
6368
6369static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6370 bool counter_enable)
6371{
6372 enum mlxsw_reg_flow_counter_set_type set_type;
6373
6374 if (counter_enable)
6375 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6376 else
6377 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6378
6379 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6380 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6381}
6382
6383
6384
6385
6386
6387#define MLXSW_REG_RDPM_ID 0x8009
6388#define MLXSW_REG_RDPM_BASE_LEN 0x00
6389#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6390#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6391#define MLXSW_REG_RDPM_LEN 0x40
6392#define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6393 MLXSW_REG_RDPM_LEN - \
6394 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6395
6396MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6397
6398
6399
6400
6401
6402MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6403 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6404
6405
6406
6407
6408
6409MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6410 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6411
6412static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6413 u8 prio)
6414{
6415 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6416 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6417}
6418
6419
6420
6421
6422
6423#define MLXSW_REG_RICNT_ID 0x800B
6424#define MLXSW_REG_RICNT_LEN 0x100
6425
6426MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6427
6428
6429
6430
6431
6432MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6433
6434enum mlxsw_reg_ricnt_counter_set_type {
6435
6436 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6437
6438
6439
6440
6441
6442
6443 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
6444};
6445
6446
6447
6448
6449
6450MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
6451
6452enum mlxsw_reg_ricnt_opcode {
6453
6454 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
6455
6456
6457
6458 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
6459};
6460
6461
6462
6463
6464
6465MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
6466
6467
6468
6469
6470
6471MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
6472
6473
6474
6475
6476
6477MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
6478
6479
6480
6481
6482
6483MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
6484
6485
6486
6487
6488
6489
6490MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
6491
6492
6493
6494
6495
6496
6497MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
6498
6499
6500
6501
6502
6503
6504MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
6505
6506
6507
6508
6509
6510MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
6511
6512
6513
6514
6515
6516MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
6517
6518
6519
6520
6521
6522
6523MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
6524
6525
6526
6527
6528
6529
6530MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
6531
6532static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
6533 enum mlxsw_reg_ricnt_opcode op)
6534{
6535 MLXSW_REG_ZERO(ricnt, payload);
6536 mlxsw_reg_ricnt_op_set(payload, op);
6537 mlxsw_reg_ricnt_counter_index_set(payload, index);
6538 mlxsw_reg_ricnt_counter_set_type_set(payload,
6539 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
6540}
6541
6542
6543
6544
6545
6546#define MLXSW_REG_RRCR_ID 0x800F
6547#define MLXSW_REG_RRCR_LEN 0x24
6548
6549MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
6550
6551enum mlxsw_reg_rrcr_op {
6552
6553 MLXSW_REG_RRCR_OP_MOVE,
6554
6555 MLXSW_REG_RRCR_OP_COPY,
6556};
6557
6558
6559
6560
6561MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
6562
6563
6564
6565
6566
6567MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
6568
6569
6570
6571
6572
6573MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6574
6575
6576
6577
6578
6579
6580MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6581
6582
6583
6584
6585
6586MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6587
6588static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6589 u16 offset, u16 size,
6590 enum mlxsw_reg_rtar_key_type table_id,
6591 u16 dest_offset)
6592{
6593 MLXSW_REG_ZERO(rrcr, payload);
6594 mlxsw_reg_rrcr_op_set(payload, op);
6595 mlxsw_reg_rrcr_offset_set(payload, offset);
6596 mlxsw_reg_rrcr_size_set(payload, size);
6597 mlxsw_reg_rrcr_table_id_set(payload, table_id);
6598 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6599}
6600
6601
6602
6603
6604
6605#define MLXSW_REG_RALTA_ID 0x8010
6606#define MLXSW_REG_RALTA_LEN 0x04
6607
6608MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6609
6610
6611
6612
6613
6614
6615
6616MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6617
6618enum mlxsw_reg_ralxx_protocol {
6619 MLXSW_REG_RALXX_PROTOCOL_IPV4,
6620 MLXSW_REG_RALXX_PROTOCOL_IPV6,
6621};
6622
6623
6624
6625
6626
6627
6628MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6629
6630
6631
6632
6633
6634
6635
6636MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6637
6638static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6639 enum mlxsw_reg_ralxx_protocol protocol,
6640 u8 tree_id)
6641{
6642 MLXSW_REG_ZERO(ralta, payload);
6643 mlxsw_reg_ralta_op_set(payload, !alloc);
6644 mlxsw_reg_ralta_protocol_set(payload, protocol);
6645 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6646}
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657#define MLXSW_REG_RALST_ID 0x8011
6658#define MLXSW_REG_RALST_LEN 0x104
6659
6660MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6661
6662
6663
6664
6665
6666
6667
6668MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6669
6670
6671
6672
6673
6674MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6675
6676#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6677#define MLXSW_REG_RALST_BIN_OFFSET 0x04
6678#define MLXSW_REG_RALST_BIN_COUNT 128
6679
6680
6681
6682
6683
6684
6685
6686MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6687
6688
6689
6690
6691
6692
6693
6694MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6695 false);
6696
6697static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6698{
6699 MLXSW_REG_ZERO(ralst, payload);
6700
6701
6702 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6703 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6704
6705 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6706 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6707}
6708
6709static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6710 u8 left_child_bin,
6711 u8 right_child_bin)
6712{
6713 int bin_index = bin_number - 1;
6714
6715 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6716 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6717 right_child_bin);
6718}
6719
6720
6721
6722
6723
6724#define MLXSW_REG_RALTB_ID 0x8012
6725#define MLXSW_REG_RALTB_LEN 0x04
6726
6727MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6728
6729
6730
6731
6732
6733
6734MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6735
6736
6737
6738
6739
6740MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6741
6742
6743
6744
6745
6746
6747
6748MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6749
6750static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6751 enum mlxsw_reg_ralxx_protocol protocol,
6752 u8 tree_id)
6753{
6754 MLXSW_REG_ZERO(raltb, payload);
6755 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6756 mlxsw_reg_raltb_protocol_set(payload, protocol);
6757 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6758}
6759
6760
6761
6762
6763
6764
6765#define MLXSW_REG_RALUE_ID 0x8013
6766#define MLXSW_REG_RALUE_LEN 0x38
6767
6768MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6769
6770
6771
6772
6773
6774MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6775
6776enum mlxsw_reg_ralue_op {
6777
6778 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6779
6780
6781
6782 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6783
6784
6785
6786
6787 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6788
6789
6790
6791
6792 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6793
6794
6795
6796 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6797
6798
6799
6800 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6801};
6802
6803
6804
6805
6806
6807MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6808
6809
6810
6811
6812
6813
6814
6815
6816MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6817
6818
6819
6820
6821
6822
6823MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6824
6825#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
6826#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
6827#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
6828
6829
6830
6831
6832
6833
6834
6835
6836MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6837
6838
6839
6840
6841
6842
6843
6844MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6845
6846
6847
6848
6849
6850
6851
6852
6853
6854MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6855MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6856
6857enum mlxsw_reg_ralue_entry_type {
6858 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6859 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6860 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6861};
6862
6863
6864
6865
6866
6867
6868MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6879
6880enum mlxsw_reg_ralue_action_type {
6881 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6882 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6883 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6884};
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6896
6897enum mlxsw_reg_ralue_trap_action {
6898 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6899 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6900 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6901 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6902 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6903};
6904
6905
6906
6907
6908
6909
6910MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6911
6912
6913
6914
6915
6916
6917
6918MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6919
6920
6921
6922
6923
6924
6925MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6936
6937
6938
6939
6940
6941
6942MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6943
6944
6945
6946
6947
6948
6949
6950
6951
6952
6953
6954MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6955
6956
6957
6958
6959
6960
6961
6962MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6963
6964static inline void mlxsw_reg_ralue_pack(char *payload,
6965 enum mlxsw_reg_ralxx_protocol protocol,
6966 enum mlxsw_reg_ralue_op op,
6967 u16 virtual_router, u8 prefix_len)
6968{
6969 MLXSW_REG_ZERO(ralue, payload);
6970 mlxsw_reg_ralue_protocol_set(payload, protocol);
6971 mlxsw_reg_ralue_op_set(payload, op);
6972 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6973 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6974 mlxsw_reg_ralue_entry_type_set(payload,
6975 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6976 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6977}
6978
6979static inline void mlxsw_reg_ralue_pack4(char *payload,
6980 enum mlxsw_reg_ralxx_protocol protocol,
6981 enum mlxsw_reg_ralue_op op,
6982 u16 virtual_router, u8 prefix_len,
6983 u32 dip)
6984{
6985 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6986 mlxsw_reg_ralue_dip4_set(payload, dip);
6987}
6988
6989static inline void mlxsw_reg_ralue_pack6(char *payload,
6990 enum mlxsw_reg_ralxx_protocol protocol,
6991 enum mlxsw_reg_ralue_op op,
6992 u16 virtual_router, u8 prefix_len,
6993 const void *dip)
6994{
6995 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6996 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
6997}
6998
6999static inline void
7000mlxsw_reg_ralue_act_remote_pack(char *payload,
7001 enum mlxsw_reg_ralue_trap_action trap_action,
7002 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7003{
7004 mlxsw_reg_ralue_action_type_set(payload,
7005 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7006 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7007 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7008 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7009 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7010}
7011
7012static inline void
7013mlxsw_reg_ralue_act_local_pack(char *payload,
7014 enum mlxsw_reg_ralue_trap_action trap_action,
7015 u16 trap_id, u16 local_erif)
7016{
7017 mlxsw_reg_ralue_action_type_set(payload,
7018 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7019 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7020 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7021 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7022}
7023
7024static inline void
7025mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7026{
7027 mlxsw_reg_ralue_action_type_set(payload,
7028 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7029}
7030
7031static inline void
7032mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7033{
7034 mlxsw_reg_ralue_action_type_set(payload,
7035 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7036 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7037 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7038}
7039
7040
7041
7042
7043
7044
7045#define MLXSW_REG_RAUHT_ID 0x8014
7046#define MLXSW_REG_RAUHT_LEN 0x74
7047
7048MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7049
7050enum mlxsw_reg_rauht_type {
7051 MLXSW_REG_RAUHT_TYPE_IPV4,
7052 MLXSW_REG_RAUHT_TYPE_IPV6,
7053};
7054
7055
7056
7057
7058MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7059
7060enum mlxsw_reg_rauht_op {
7061 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7062
7063 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7064
7065
7066
7067 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7068
7069
7070
7071 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7072
7073
7074
7075
7076 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7077
7078 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7079
7080 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7081
7082
7083
7084};
7085
7086
7087
7088
7089MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7090
7091
7092
7093
7094
7095
7096
7097
7098MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7099
7100
7101
7102
7103
7104MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7105
7106
7107
7108
7109
7110MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7111MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7112
7113enum mlxsw_reg_rauht_trap_action {
7114 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7115 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7116 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7117 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7118 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7119};
7120
7121
7122
7123
7124MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7125
7126enum mlxsw_reg_rauht_trap_id {
7127 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7128 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7129};
7130
7131
7132
7133
7134
7135
7136
7137
7138MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7139
7140
7141
7142
7143
7144MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7145
7146
7147
7148
7149
7150MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7151
7152
7153
7154
7155
7156MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7157
7158static inline void mlxsw_reg_rauht_pack(char *payload,
7159 enum mlxsw_reg_rauht_op op, u16 rif,
7160 const char *mac)
7161{
7162 MLXSW_REG_ZERO(rauht, payload);
7163 mlxsw_reg_rauht_op_set(payload, op);
7164 mlxsw_reg_rauht_rif_set(payload, rif);
7165 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7166}
7167
7168static inline void mlxsw_reg_rauht_pack4(char *payload,
7169 enum mlxsw_reg_rauht_op op, u16 rif,
7170 const char *mac, u32 dip)
7171{
7172 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7173 mlxsw_reg_rauht_dip4_set(payload, dip);
7174}
7175
7176static inline void mlxsw_reg_rauht_pack6(char *payload,
7177 enum mlxsw_reg_rauht_op op, u16 rif,
7178 const char *mac, const char *dip)
7179{
7180 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7181 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7182 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7183}
7184
7185static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7186 u64 counter_index)
7187{
7188 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7189 mlxsw_reg_rauht_counter_set_type_set(payload,
7190 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7191}
7192
7193
7194
7195
7196
7197
7198
7199#define MLXSW_REG_RALEU_ID 0x8015
7200#define MLXSW_REG_RALEU_LEN 0x28
7201
7202MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7203
7204
7205
7206
7207
7208MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7209
7210
7211
7212
7213
7214
7215MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7216
7217
7218
7219
7220
7221MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7222
7223
7224
7225
7226
7227MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7228
7229
7230
7231
7232
7233MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7234
7235
7236
7237
7238
7239MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7240
7241static inline void mlxsw_reg_raleu_pack(char *payload,
7242 enum mlxsw_reg_ralxx_protocol protocol,
7243 u16 virtual_router,
7244 u32 adjacency_index, u16 ecmp_size,
7245 u32 new_adjacency_index,
7246 u16 new_ecmp_size)
7247{
7248 MLXSW_REG_ZERO(raleu, payload);
7249 mlxsw_reg_raleu_protocol_set(payload, protocol);
7250 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7251 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7252 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7253 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7254 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7255}
7256
7257
7258
7259
7260
7261
7262
7263
7264
7265
7266#define MLXSW_REG_RAUHTD_ID 0x8018
7267#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7268#define MLXSW_REG_RAUHTD_REC_LEN 0x20
7269#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7270#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7271 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7272#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7273
7274MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7275
7276#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7277#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7278
7279
7280
7281
7282
7283
7284
7285
7286MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7287
7288enum mlxsw_reg_rauhtd_op {
7289 MLXSW_REG_RAUHTD_OP_DUMP,
7290 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7291};
7292
7293
7294
7295
7296MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7307
7308
7309
7310
7311
7312
7313MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7314
7315enum mlxsw_reg_rauhtd_type {
7316 MLXSW_REG_RAUHTD_TYPE_IPV4,
7317 MLXSW_REG_RAUHTD_TYPE_IPV6,
7318};
7319
7320
7321
7322
7323
7324
7325
7326MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7327
7328
7329
7330
7331
7332
7333MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7334
7335static inline void mlxsw_reg_rauhtd_pack(char *payload,
7336 enum mlxsw_reg_rauhtd_type type)
7337{
7338 MLXSW_REG_ZERO(rauhtd, payload);
7339 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7340 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7341 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7342 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7343 mlxsw_reg_rauhtd_type_set(payload, type);
7344}
7345
7346
7347
7348
7349
7350
7351
7352
7353
7354MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7355 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7356 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7357
7358
7359
7360
7361
7362
7363
7364MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7365 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7366
7367#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7368
7369
7370
7371
7372
7373
7374MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7375 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7376
7377
7378
7379
7380
7381MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7382 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7383
7384
7385
7386
7387
7388MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7389 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7390
7391#define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7392
7393
7394
7395
7396
7397
7398MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7399 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7400
7401
7402
7403
7404
7405MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7406 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7407
7408
7409
7410
7411
7412MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7413 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7414
7415static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7416 int ent_index, u16 *p_rif,
7417 u32 *p_dip)
7418{
7419 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7420 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7421}
7422
7423static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7424 int rec_index, u16 *p_rif,
7425 char *p_dip)
7426{
7427 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7428 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7429}
7430
7431
7432
7433
7434
7435
7436#define MLXSW_REG_RTDP_ID 0x8020
7437#define MLXSW_REG_RTDP_LEN 0x44
7438
7439MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
7440
7441enum mlxsw_reg_rtdp_type {
7442 MLXSW_REG_RTDP_TYPE_NVE,
7443 MLXSW_REG_RTDP_TYPE_IPIP,
7444};
7445
7446
7447
7448
7449
7450MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
7451
7452
7453
7454
7455
7456
7457MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
7458
7459
7460
7461
7462
7463
7464MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
7465
7466
7467
7468
7469
7470
7471
7472MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
7473
7474enum mlxsw_reg_rtdp_ipip_sip_check {
7475
7476 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
7477
7478
7479
7480 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
7481
7482
7483
7484 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
7485};
7486
7487
7488
7489
7490
7491
7492MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
7493
7494
7495#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
7496
7497#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
7498
7499#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
7500
7501
7502
7503
7504
7505
7506MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
7507
7508
7509
7510
7511
7512
7513
7514
7515
7516
7517MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
7518
7519
7520
7521
7522
7523
7524MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
7525
7526
7527
7528
7529
7530
7531
7532
7533MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
7534
7535
7536
7537
7538
7539
7540MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
7541
7542static inline void mlxsw_reg_rtdp_pack(char *payload,
7543 enum mlxsw_reg_rtdp_type type,
7544 u32 tunnel_index)
7545{
7546 MLXSW_REG_ZERO(rtdp, payload);
7547 mlxsw_reg_rtdp_type_set(payload, type);
7548 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
7549}
7550
7551static inline void
7552mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
7553 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
7554 unsigned int type_check, bool gre_key_check,
7555 u32 ipv4_usip, u32 expected_gre_key)
7556{
7557 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
7558 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
7559 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
7560 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
7561 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
7562 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
7563}
7564
7565
7566
7567
7568
7569
7570#define MLXSW_REG_RIGR2_ID 0x8023
7571#define MLXSW_REG_RIGR2_LEN 0xB0
7572
7573#define MLXSW_REG_RIGR2_MAX_ERIFS 32
7574
7575MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
7576
7577
7578
7579
7580
7581MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7582
7583
7584
7585
7586
7587MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7588
7589
7590
7591
7592
7593
7594MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7595
7596
7597
7598
7599
7600MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7601
7602
7603
7604
7605
7606
7607
7608
7609MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7620
7621
7622
7623
7624
7625
7626
7627MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7628
7629static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7630 bool vnext, u32 next_rigr_index)
7631{
7632 MLXSW_REG_ZERO(rigr2, payload);
7633 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7634 mlxsw_reg_rigr2_vnext_set(payload, vnext);
7635 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7636 mlxsw_reg_rigr2_vrmid_set(payload, 0);
7637 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7638}
7639
7640static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7641 bool v, u16 erif)
7642{
7643 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7644 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7645}
7646
7647
7648
7649
7650#define MLXSW_REG_RECR2_ID 0x8025
7651#define MLXSW_REG_RECR2_LEN 0x38
7652
7653MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7654
7655
7656
7657
7658
7659MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7660
7661
7662
7663
7664
7665MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7666
7667
7668
7669
7670
7671MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7672
7673enum {
7674
7675 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7676
7677 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
7678
7679 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7680
7681 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
7682
7683 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
7684
7685 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
7686};
7687
7688
7689
7690
7691
7692
7693MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7694
7695enum {
7696
7697 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
7698 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
7699
7700 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
7701 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
7702
7703 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
7704
7705 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
7706 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
7707 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
7708
7709 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
7710 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
7711 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
7712
7713 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
7714
7715 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
7716
7717 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
7718
7719 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
7720};
7721
7722
7723
7724
7725
7726MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7727
7728static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7729{
7730 int i;
7731
7732 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7733 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7734 true);
7735}
7736
7737static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7738{
7739 int i;
7740
7741 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7742 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7743 true);
7744}
7745
7746static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7747{
7748 int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7749
7750 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7751
7752 i = MLXSW_REG_RECR2_IPV6_SIP8;
7753 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7754 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7755 true);
7756}
7757
7758static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7759{
7760 int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7761
7762 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7763
7764 i = MLXSW_REG_RECR2_IPV6_DIP8;
7765 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7766 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7767 true);
7768}
7769
7770static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7771{
7772 MLXSW_REG_ZERO(recr2, payload);
7773 mlxsw_reg_recr2_pp_set(payload, false);
7774 mlxsw_reg_recr2_sh_set(payload, true);
7775 mlxsw_reg_recr2_seed_set(payload, seed);
7776}
7777
7778
7779
7780
7781
7782#define MLXSW_REG_RMFT2_ID 0x8027
7783#define MLXSW_REG_RMFT2_LEN 0x174
7784
7785MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7786
7787
7788
7789
7790
7791MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7792
7793enum mlxsw_reg_rmft2_type {
7794 MLXSW_REG_RMFT2_TYPE_IPV4,
7795 MLXSW_REG_RMFT2_TYPE_IPV6
7796};
7797
7798
7799
7800
7801MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7802
7803enum mlxsw_sp_reg_rmft2_op {
7804
7805
7806
7807
7808
7809
7810
7811 MLXSW_REG_RMFT2_OP_READ_WRITE,
7812};
7813
7814
7815
7816
7817
7818MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7819
7820
7821
7822
7823
7824
7825MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7826
7827
7828
7829
7830
7831MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7832
7833
7834
7835
7836
7837MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7838
7839enum mlxsw_reg_rmft2_irif_mask {
7840 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7841 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7842};
7843
7844
7845
7846
7847
7848MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7849
7850
7851
7852
7853
7854MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7855
7856
7857
7858
7859
7860MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7861MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7862
7863
7864
7865
7866
7867
7868MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7869MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7870
7871
7872
7873
7874
7875MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7876MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7877
7878
7879
7880
7881
7882
7883MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7884MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7885
7886
7887
7888
7889
7890
7891
7892
7893
7894
7895
7896
7897MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7898 MLXSW_REG_FLEX_ACTION_SET_LEN);
7899
7900static inline void
7901mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7902 u16 virtual_router,
7903 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7904 const char *flex_action_set)
7905{
7906 MLXSW_REG_ZERO(rmft2, payload);
7907 mlxsw_reg_rmft2_v_set(payload, v);
7908 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7909 mlxsw_reg_rmft2_offset_set(payload, offset);
7910 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7911 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7912 mlxsw_reg_rmft2_irif_set(payload, irif);
7913 if (flex_action_set)
7914 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7915 flex_action_set);
7916}
7917
7918static inline void
7919mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7920 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7921 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7922 const char *flexible_action_set)
7923{
7924 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7925 irif_mask, irif, flexible_action_set);
7926 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7927 mlxsw_reg_rmft2_dip4_set(payload, dip4);
7928 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7929 mlxsw_reg_rmft2_sip4_set(payload, sip4);
7930 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7931}
7932
7933static inline void
7934mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7935 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7936 struct in6_addr dip6, struct in6_addr dip6_mask,
7937 struct in6_addr sip6, struct in6_addr sip6_mask,
7938 const char *flexible_action_set)
7939{
7940 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7941 irif_mask, irif, flexible_action_set);
7942 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7943 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7944 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7945 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7946 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7947}
7948
7949
7950
7951
7952
7953#define MLXSW_REG_MFCR_ID 0x9001
7954#define MLXSW_REG_MFCR_LEN 0x08
7955
7956MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7957
7958enum mlxsw_reg_mfcr_pwm_frequency {
7959 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7960 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7961 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7962 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7963 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7964 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7965 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7966 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7967};
7968
7969
7970
7971
7972
7973MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7974
7975#define MLXSW_MFCR_TACHOS_MAX 10
7976
7977
7978
7979
7980
7981MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7982
7983#define MLXSW_MFCR_PWMS_MAX 5
7984
7985
7986
7987
7988
7989MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
7990
7991static inline void
7992mlxsw_reg_mfcr_pack(char *payload,
7993 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
7994{
7995 MLXSW_REG_ZERO(mfcr, payload);
7996 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
7997}
7998
7999static inline void
8000mlxsw_reg_mfcr_unpack(char *payload,
8001 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
8002 u16 *p_tacho_active, u8 *p_pwm_active)
8003{
8004 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
8005 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
8006 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
8007}
8008
8009
8010
8011
8012
8013#define MLXSW_REG_MFSC_ID 0x9002
8014#define MLXSW_REG_MFSC_LEN 0x08
8015
8016MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
8017
8018
8019
8020
8021
8022MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
8023
8024
8025
8026
8027
8028
8029MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
8030
8031static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
8032 u8 pwm_duty_cycle)
8033{
8034 MLXSW_REG_ZERO(mfsc, payload);
8035 mlxsw_reg_mfsc_pwm_set(payload, pwm);
8036 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
8037}
8038
8039
8040
8041
8042
8043
8044#define MLXSW_REG_MFSM_ID 0x9003
8045#define MLXSW_REG_MFSM_LEN 0x08
8046
8047MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
8048
8049
8050
8051
8052
8053MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
8054
8055
8056
8057
8058
8059MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
8060
8061static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
8062{
8063 MLXSW_REG_ZERO(mfsm, payload);
8064 mlxsw_reg_mfsm_tacho_set(payload, tacho);
8065}
8066
8067
8068
8069
8070
8071
8072
8073#define MLXSW_REG_MFSL_ID 0x9004
8074#define MLXSW_REG_MFSL_LEN 0x0C
8075
8076MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
8077
8078
8079
8080
8081
8082MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
8083
8084
8085
8086
8087
8088MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
8089
8090
8091
8092
8093
8094MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
8095
8096static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
8097 u16 tach_min, u16 tach_max)
8098{
8099 MLXSW_REG_ZERO(mfsl, payload);
8100 mlxsw_reg_mfsl_tacho_set(payload, tacho);
8101 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
8102 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
8103}
8104
8105static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
8106 u16 *p_tach_min, u16 *p_tach_max)
8107{
8108 if (p_tach_min)
8109 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
8110
8111 if (p_tach_max)
8112 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
8113}
8114
8115
8116
8117
8118
8119
8120#define MLXSW_REG_FORE_ID 0x9007
8121#define MLXSW_REG_FORE_LEN 0x0C
8122
8123MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
8124
8125
8126
8127
8128
8129
8130
8131MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
8132
8133static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
8134 bool *fault)
8135{
8136 u16 limit;
8137
8138 if (fault) {
8139 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
8140 *fault = limit & BIT(tacho);
8141 }
8142}
8143
8144
8145
8146
8147
8148
8149#define MLXSW_REG_MTCAP_ID 0x9009
8150#define MLXSW_REG_MTCAP_LEN 0x08
8151
8152MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
8153
8154
8155
8156
8157
8158
8159MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
8160
8161
8162
8163
8164
8165
8166
8167#define MLXSW_REG_MTMP_ID 0x900A
8168#define MLXSW_REG_MTMP_LEN 0x20
8169
8170MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
8171
8172#define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
8173#define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
8174
8175
8176
8177
8178
8179
8180MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
8181
8182
8183#define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
8184 ((v_) >= 0) ? ((v_) * 125) : \
8185 ((s16)((GENMASK(15, 0) + (v_) + 1) \
8186 * 125)); })
8187
8188
8189
8190
8191
8192
8193MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
8194
8195
8196
8197
8198
8199MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
8200
8201
8202
8203
8204
8205MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
8206
8207
8208
8209
8210
8211
8212MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
8213
8214
8215
8216
8217
8218
8219
8220
8221MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
8222
8223#define MLXSW_REG_MTMP_THRESH_HI 0x348
8224
8225
8226
8227
8228
8229MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
8230
8231
8232
8233
8234
8235MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
8236
8237#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
8238
8239
8240
8241
8242
8243MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
8244
8245static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
8246 bool max_temp_enable,
8247 bool max_temp_reset)
8248{
8249 MLXSW_REG_ZERO(mtmp, payload);
8250 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
8251 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
8252 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
8253 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
8254 MLXSW_REG_MTMP_THRESH_HI);
8255}
8256
8257static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
8258 int *p_max_temp, char *sensor_name)
8259{
8260 s16 temp;
8261
8262 if (p_temp) {
8263 temp = mlxsw_reg_mtmp_temperature_get(payload);
8264 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8265 }
8266 if (p_max_temp) {
8267 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
8268 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8269 }
8270 if (sensor_name)
8271 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
8272}
8273
8274
8275
8276
8277
8278#define MLXSW_REG_MTBR_ID 0x900F
8279#define MLXSW_REG_MTBR_BASE_LEN 0x10
8280#define MLXSW_REG_MTBR_REC_LEN 0x04
8281#define MLXSW_REG_MTBR_REC_MAX_COUNT 47
8282#define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \
8283 MLXSW_REG_MTBR_REC_LEN * \
8284 MLXSW_REG_MTBR_REC_MAX_COUNT)
8285
8286MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
8287
8288
8289
8290
8291
8292
8293MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
8294
8295
8296
8297
8298
8299
8300
8301
8302MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
8303
8304
8305
8306
8307
8308
8309MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
8310 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8311
8312
8313
8314
8315
8316
8317MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
8318 MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8319
8320static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
8321 u8 num_rec)
8322{
8323 MLXSW_REG_ZERO(mtbr, payload);
8324 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
8325 mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
8326}
8327
8328
8329enum mlxsw_reg_mtbr_temp_status {
8330 MLXSW_REG_MTBR_NO_CONN = 0x8000,
8331 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001,
8332 MLXSW_REG_MTBR_INDEX_NA = 0x8002,
8333 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003,
8334};
8335
8336
8337#define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
8338
8339static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
8340 u16 *p_temp, u16 *p_max_temp)
8341{
8342 if (p_temp)
8343 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
8344 if (p_max_temp)
8345 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
8346}
8347
8348
8349
8350
8351
8352
8353#define MLXSW_REG_MCIA_ID 0x9014
8354#define MLXSW_REG_MCIA_LEN 0x40
8355
8356MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
8357
8358
8359
8360
8361
8362
8363
8364MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
8365
8366
8367
8368
8369
8370MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
8371
8372
8373
8374
8375
8376MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
8377
8378
8379
8380
8381
8382MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
8383
8384
8385
8386
8387
8388MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
8389
8390
8391
8392
8393
8394MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
8395
8396
8397
8398
8399
8400MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
8401
8402#define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256
8403#define MLXSW_REG_MCIA_EEPROM_SIZE 48
8404#define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50
8405#define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51
8406#define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0
8407#define MLXSW_REG_MCIA_TH_ITEM_SIZE 2
8408#define MLXSW_REG_MCIA_TH_PAGE_NUM 3
8409#define MLXSW_REG_MCIA_PAGE0_LO 0
8410#define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80
8411
8412enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
8413 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
8414 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
8415 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
8416};
8417
8418enum mlxsw_reg_mcia_eeprom_module_info_id {
8419 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03,
8420 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
8421 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
8422 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
8423 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18,
8424};
8425
8426enum mlxsw_reg_mcia_eeprom_module_info {
8427 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
8428 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
8429 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
8430};
8431
8432
8433
8434
8435
8436MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
8437
8438static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
8439 u8 page_number, u16 device_addr,
8440 u8 size, u8 i2c_device_addr)
8441{
8442 MLXSW_REG_ZERO(mcia, payload);
8443 mlxsw_reg_mcia_module_set(payload, module);
8444 mlxsw_reg_mcia_l_set(payload, lock);
8445 mlxsw_reg_mcia_page_number_set(payload, page_number);
8446 mlxsw_reg_mcia_device_address_set(payload, device_addr);
8447 mlxsw_reg_mcia_size_set(payload, size);
8448 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
8449}
8450
8451
8452
8453
8454
8455
8456#define MLXSW_REG_MPAT_ID 0x901A
8457#define MLXSW_REG_MPAT_LEN 0x78
8458
8459MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
8460
8461
8462
8463
8464
8465MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
8466
8467
8468
8469
8470
8471MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
8472
8473
8474
8475
8476
8477MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
8478
8479
8480
8481
8482
8483
8484
8485
8486
8487
8488MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
8489
8490
8491
8492
8493
8494
8495
8496
8497
8498MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
8499
8500enum mlxsw_reg_mpat_span_type {
8501
8502
8503
8504 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
8505
8506
8507
8508
8509
8510 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
8511
8512
8513
8514
8515 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
8516};
8517
8518
8519
8520
8521
8522MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
8523
8524
8525
8526
8527
8528
8529
8530
8531
8532MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
8533
8534
8535
8536
8537
8538enum mlxsw_reg_mpat_eth_rspan_version {
8539 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
8540};
8541
8542
8543
8544
8545
8546MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
8547
8548
8549
8550
8551
8552MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
8553
8554
8555
8556
8557
8558MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
8559
8560
8561
8562
8563
8564enum mlxsw_reg_mpat_eth_rspan_protocol {
8565 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
8566 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
8567};
8568
8569
8570
8571
8572
8573MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
8574
8575
8576
8577
8578
8579MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
8580
8581
8582
8583
8584
8585MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
8586
8587
8588
8589
8590
8591MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
8592MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
8593
8594
8595
8596
8597
8598MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
8599MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
8600
8601static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
8602 u16 system_port, bool e,
8603 enum mlxsw_reg_mpat_span_type span_type)
8604{
8605 MLXSW_REG_ZERO(mpat, payload);
8606 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
8607 mlxsw_reg_mpat_system_port_set(payload, system_port);
8608 mlxsw_reg_mpat_e_set(payload, e);
8609 mlxsw_reg_mpat_qos_set(payload, 1);
8610 mlxsw_reg_mpat_be_set(payload, 1);
8611 mlxsw_reg_mpat_span_type_set(payload, span_type);
8612}
8613
8614static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
8615{
8616 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
8617}
8618
8619static inline void
8620mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
8621 enum mlxsw_reg_mpat_eth_rspan_version version,
8622 const char *mac,
8623 bool tp)
8624{
8625 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
8626 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
8627 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
8628}
8629
8630static inline void
8631mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
8632 const char *smac,
8633 u32 sip, u32 dip)
8634{
8635 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8636 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8637 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8638 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
8639 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
8640 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
8641}
8642
8643static inline void
8644mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
8645 const char *smac,
8646 struct in6_addr sip, struct in6_addr dip)
8647{
8648 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8649 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8650 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8651 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
8652 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
8653 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
8654}
8655
8656
8657
8658
8659
8660
8661#define MLXSW_REG_MPAR_ID 0x901B
8662#define MLXSW_REG_MPAR_LEN 0x08
8663
8664MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
8665
8666
8667
8668
8669
8670MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
8671
8672enum mlxsw_reg_mpar_i_e {
8673 MLXSW_REG_MPAR_TYPE_EGRESS,
8674 MLXSW_REG_MPAR_TYPE_INGRESS,
8675};
8676
8677
8678
8679
8680
8681MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
8682
8683
8684
8685
8686
8687
8688MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
8689
8690
8691
8692
8693
8694MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
8695
8696static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
8697 enum mlxsw_reg_mpar_i_e i_e,
8698 bool enable, u8 pa_id)
8699{
8700 MLXSW_REG_ZERO(mpar, payload);
8701 mlxsw_reg_mpar_local_port_set(payload, local_port);
8702 mlxsw_reg_mpar_enable_set(payload, enable);
8703 mlxsw_reg_mpar_i_e_set(payload, i_e);
8704 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
8705}
8706
8707
8708
8709
8710
8711
8712#define MLXSW_REG_MGIR_ID 0x9020
8713#define MLXSW_REG_MGIR_LEN 0x9C
8714
8715MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
8716
8717
8718
8719
8720MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
8721
8722#define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
8723
8724
8725
8726
8727
8728MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
8729
8730
8731
8732
8733MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
8734
8735
8736
8737
8738MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
8739
8740
8741
8742
8743MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
8744
8745static inline void mlxsw_reg_mgir_pack(char *payload)
8746{
8747 MLXSW_REG_ZERO(mgir, payload);
8748}
8749
8750static inline void
8751mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
8752 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
8753{
8754 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
8755 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
8756 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
8757 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
8758 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
8759}
8760
8761
8762
8763
8764
8765
8766#define MLXSW_REG_MRSR_ID 0x9023
8767#define MLXSW_REG_MRSR_LEN 0x08
8768
8769MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8770
8771
8772
8773
8774
8775
8776
8777MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8778
8779static inline void mlxsw_reg_mrsr_pack(char *payload)
8780{
8781 MLXSW_REG_ZERO(mrsr, payload);
8782 mlxsw_reg_mrsr_command_set(payload, 1);
8783}
8784
8785
8786
8787
8788
8789#define MLXSW_REG_MLCR_ID 0x902B
8790#define MLXSW_REG_MLCR_LEN 0x0C
8791
8792MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8793
8794
8795
8796
8797
8798MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8799
8800#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8801
8802
8803
8804
8805
8806
8807
8808MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8809
8810
8811
8812
8813
8814
8815MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8816
8817static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8818 bool active)
8819{
8820 MLXSW_REG_ZERO(mlcr, payload);
8821 mlxsw_reg_mlcr_local_port_set(payload, local_port);
8822 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8823 MLXSW_REG_MLCR_DURATION_MAX : 0);
8824}
8825
8826
8827
8828
8829
8830
8831#define MLXSW_REG_MTPPS_ID 0x9053
8832#define MLXSW_REG_MTPPS_LEN 0x3C
8833
8834MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
8835
8836
8837
8838
8839
8840
8841MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
8842
8843enum mlxsw_reg_mtpps_pin_mode {
8844 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
8845};
8846
8847
8848
8849
8850
8851
8852MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
8853
8854#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
8855
8856
8857
8858
8859
8860MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
8861
8862
8863
8864
8865
8866
8867
8868
8869
8870MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
8871
8872static inline void
8873mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
8874{
8875 MLXSW_REG_ZERO(mtpps, payload);
8876 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
8877 mlxsw_reg_mtpps_pin_mode_set(payload,
8878 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
8879 mlxsw_reg_mtpps_enable_set(payload, true);
8880 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
8881}
8882
8883
8884
8885
8886
8887#define MLXSW_REG_MTUTC_ID 0x9055
8888#define MLXSW_REG_MTUTC_LEN 0x1C
8889
8890MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
8891
8892enum mlxsw_reg_mtutc_operation {
8893 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
8894 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
8895};
8896
8897
8898
8899
8900
8901MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
8902
8903
8904
8905
8906
8907
8908
8909MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
8910
8911
8912
8913
8914
8915MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
8916
8917static inline void
8918mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
8919 u32 freq_adj, u32 utc_sec)
8920{
8921 MLXSW_REG_ZERO(mtutc, payload);
8922 mlxsw_reg_mtutc_operation_set(payload, oper);
8923 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
8924 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
8925}
8926
8927
8928
8929
8930
8931#define MLXSW_REG_MCQI_ID 0x9061
8932#define MLXSW_REG_MCQI_BASE_LEN 0x18
8933#define MLXSW_REG_MCQI_CAP_LEN 0x14
8934#define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8935
8936MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8937
8938
8939
8940
8941
8942MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8943
8944enum mlxfw_reg_mcqi_info_type {
8945 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8946};
8947
8948
8949
8950
8951
8952MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8953
8954
8955
8956
8957
8958
8959MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8960
8961
8962
8963
8964
8965
8966MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8967
8968
8969
8970
8971
8972MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8973
8974
8975
8976
8977
8978
8979MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8980
8981
8982
8983
8984
8985MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8986
8987static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
8988{
8989 MLXSW_REG_ZERO(mcqi, payload);
8990 mlxsw_reg_mcqi_component_index_set(payload, component_index);
8991 mlxsw_reg_mcqi_info_type_set(payload,
8992 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
8993 mlxsw_reg_mcqi_offset_set(payload, 0);
8994 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
8995}
8996
8997static inline void mlxsw_reg_mcqi_unpack(char *payload,
8998 u32 *p_cap_max_component_size,
8999 u8 *p_cap_log_mcda_word_size,
9000 u16 *p_cap_mcda_max_write_size)
9001{
9002 *p_cap_max_component_size =
9003 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
9004 *p_cap_log_mcda_word_size =
9005 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
9006 *p_cap_mcda_max_write_size =
9007 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
9008}
9009
9010
9011
9012
9013
9014#define MLXSW_REG_MCC_ID 0x9062
9015#define MLXSW_REG_MCC_LEN 0x1C
9016
9017MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
9018
9019enum mlxsw_reg_mcc_instruction {
9020 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
9021 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
9022 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
9023 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
9024 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
9025 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
9026};
9027
9028
9029
9030
9031
9032
9033MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
9034
9035
9036
9037
9038
9039
9040MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
9041
9042
9043
9044
9045
9046MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
9047
9048
9049
9050
9051
9052
9053MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
9054
9055
9056
9057
9058
9059MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
9060
9061
9062
9063
9064
9065
9066
9067MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
9068
9069static inline void mlxsw_reg_mcc_pack(char *payload,
9070 enum mlxsw_reg_mcc_instruction instr,
9071 u16 component_index, u32 update_handle,
9072 u32 component_size)
9073{
9074 MLXSW_REG_ZERO(mcc, payload);
9075 mlxsw_reg_mcc_instruction_set(payload, instr);
9076 mlxsw_reg_mcc_component_index_set(payload, component_index);
9077 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
9078 mlxsw_reg_mcc_component_size_set(payload, component_size);
9079}
9080
9081static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
9082 u8 *p_error_code, u8 *p_control_state)
9083{
9084 if (p_update_handle)
9085 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
9086 if (p_error_code)
9087 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
9088 if (p_control_state)
9089 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
9090}
9091
9092
9093
9094
9095
9096#define MLXSW_REG_MCDA_ID 0x9063
9097#define MLXSW_REG_MCDA_BASE_LEN 0x10
9098#define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
9099#define MLXSW_REG_MCDA_LEN \
9100 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
9101
9102MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
9103
9104
9105
9106
9107
9108MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
9109
9110
9111
9112
9113
9114
9115MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
9116
9117
9118
9119
9120
9121MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
9122
9123
9124
9125
9126
9127MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
9128
9129static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
9130 u32 offset, u16 size, u8 *data)
9131{
9132 int i;
9133
9134 MLXSW_REG_ZERO(mcda, payload);
9135 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
9136 mlxsw_reg_mcda_offset_set(payload, offset);
9137 mlxsw_reg_mcda_size_set(payload, size);
9138
9139 for (i = 0; i < size / 4; i++)
9140 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
9141}
9142
9143
9144
9145
9146
9147#define MLXSW_REG_MPSC_ID 0x9080
9148#define MLXSW_REG_MPSC_LEN 0x1C
9149
9150MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
9151
9152
9153
9154
9155
9156
9157MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
9158
9159
9160
9161
9162
9163MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
9164
9165#define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
9166
9167
9168
9169
9170
9171
9172MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
9173
9174static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
9175 u32 rate)
9176{
9177 MLXSW_REG_ZERO(mpsc, payload);
9178 mlxsw_reg_mpsc_local_port_set(payload, local_port);
9179 mlxsw_reg_mpsc_e_set(payload, e);
9180 mlxsw_reg_mpsc_rate_set(payload, rate);
9181}
9182
9183
9184
9185
9186#define MLXSW_REG_MGPC_ID 0x9081
9187#define MLXSW_REG_MGPC_LEN 0x18
9188
9189MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
9190
9191
9192
9193
9194
9195MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
9196
9197
9198
9199
9200
9201MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
9202
9203enum mlxsw_reg_mgpc_opcode {
9204
9205 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
9206
9207 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
9208};
9209
9210
9211
9212
9213
9214MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
9215
9216
9217
9218
9219
9220MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
9221
9222
9223
9224
9225
9226MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
9227
9228static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
9229 enum mlxsw_reg_mgpc_opcode opcode,
9230 enum mlxsw_reg_flow_counter_set_type set_type)
9231{
9232 MLXSW_REG_ZERO(mgpc, payload);
9233 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
9234 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
9235 mlxsw_reg_mgpc_opcode_set(payload, opcode);
9236}
9237
9238
9239
9240
9241
9242
9243#define MLXSW_REG_MPRS_ID 0x9083
9244#define MLXSW_REG_MPRS_LEN 0x14
9245
9246MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
9247
9248
9249
9250
9251
9252
9253
9254MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
9255
9256
9257
9258
9259
9260
9261
9262MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
9263
9264
9265
9266
9267
9268
9269
9270MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
9271
9272static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
9273 u16 vxlan_udp_dport)
9274{
9275 MLXSW_REG_ZERO(mprs, payload);
9276 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
9277 mlxsw_reg_mprs_parsing_en_set(payload, true);
9278 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
9279}
9280
9281
9282
9283
9284#define MLXSW_REG_MOGCR_ID 0x9086
9285#define MLXSW_REG_MOGCR_LEN 0x20
9286
9287MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
9288
9289
9290
9291
9292
9293
9294
9295
9296MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
9297
9298
9299
9300
9301
9302
9303
9304
9305MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
9306
9307
9308
9309
9310
9311
9312
9313
9314#define MLXSW_REG_MTPPPC_ID 0x9090
9315#define MLXSW_REG_MTPPPC_LEN 0x28
9316
9317MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
9318
9319
9320
9321
9322
9323
9324
9325
9326MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
9327
9328
9329
9330
9331
9332
9333
9334
9335MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
9336
9337static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
9338{
9339 MLXSW_REG_ZERO(mtpppc, payload);
9340 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
9341 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
9342}
9343
9344
9345
9346
9347
9348
9349
9350
9351
9352
9353
9354#define MLXSW_REG_MTPPTR_ID 0x9091
9355#define MLXSW_REG_MTPPTR_BASE_LEN 0x10
9356#define MLXSW_REG_MTPPTR_REC_LEN 0x10
9357#define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
9358#define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
9359 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
9360
9361MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
9362
9363
9364
9365
9366
9367MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
9368
9369enum mlxsw_reg_mtpptr_dir {
9370 MLXSW_REG_MTPPTR_DIR_INGRESS,
9371 MLXSW_REG_MTPPTR_DIR_EGRESS,
9372};
9373
9374
9375
9376
9377
9378MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
9379
9380
9381
9382
9383
9384MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
9385
9386
9387
9388
9389
9390
9391MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
9392
9393
9394
9395
9396
9397
9398MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
9399 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
9400 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9401
9402
9403
9404
9405
9406MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
9407 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
9408 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9409
9410
9411
9412
9413
9414MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
9415 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
9416 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
9417
9418
9419
9420
9421
9422
9423
9424MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
9425 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9426 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
9427
9428
9429
9430
9431
9432MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
9433 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9434 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
9435
9436static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
9437 unsigned int rec,
9438 u8 *p_message_type,
9439 u8 *p_domain_number,
9440 u16 *p_sequence_id,
9441 u64 *p_timestamp)
9442{
9443 u32 timestamp_high, timestamp_low;
9444
9445 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
9446 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
9447 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
9448 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
9449 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
9450 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
9451}
9452
9453
9454
9455
9456
9457
9458#define MLXSW_REG_MTPTPT_ID 0x9092
9459#define MLXSW_REG_MTPTPT_LEN 0x08
9460
9461MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
9462
9463enum mlxsw_reg_mtptpt_trap_id {
9464 MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
9465 MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
9466};
9467
9468
9469
9470
9471
9472MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
9473
9474
9475
9476
9477
9478
9479
9480MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
9481
9482static inline void mlxsw_reg_mtptptp_pack(char *payload,
9483 enum mlxsw_reg_mtptpt_trap_id trap_id,
9484 u16 message_type)
9485{
9486 MLXSW_REG_ZERO(mtptpt, payload);
9487 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
9488 mlxsw_reg_mtptpt_message_type_set(payload, message_type);
9489}
9490
9491
9492
9493
9494
9495
9496#define MLXSW_REG_MGPIR_ID 0x9100
9497#define MLXSW_REG_MGPIR_LEN 0xA0
9498
9499MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
9500
9501enum mlxsw_reg_mgpir_device_type {
9502 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
9503 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
9504};
9505
9506
9507
9508
9509MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
9510
9511
9512
9513
9514
9515MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
9516
9517
9518
9519
9520
9521MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
9522
9523static inline void mlxsw_reg_mgpir_pack(char *payload)
9524{
9525 MLXSW_REG_ZERO(mgpir, payload);
9526}
9527
9528static inline void
9529mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
9530 enum mlxsw_reg_mgpir_device_type *device_type,
9531 u8 *devices_per_flash)
9532{
9533 if (num_of_devices)
9534 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
9535 if (device_type)
9536 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
9537 if (devices_per_flash)
9538 *devices_per_flash =
9539 mlxsw_reg_mgpir_devices_per_flash_get(payload);
9540}
9541
9542
9543
9544
9545
9546#define MLXSW_REG_TNGCR_ID 0xA001
9547#define MLXSW_REG_TNGCR_LEN 0x44
9548
9549MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
9550
9551enum mlxsw_reg_tngcr_type {
9552 MLXSW_REG_TNGCR_TYPE_VXLAN,
9553 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
9554 MLXSW_REG_TNGCR_TYPE_GENEVE,
9555 MLXSW_REG_TNGCR_TYPE_NVGRE,
9556};
9557
9558
9559
9560
9561
9562
9563
9564MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
9565
9566
9567
9568
9569
9570MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
9571
9572
9573
9574
9575
9576MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
9577
9578
9579
9580
9581
9582MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
9583
9584enum {
9585
9586 MLXSW_REG_TNGCR_FL_NO_COPY,
9587
9588
9589
9590
9591 MLXSW_REG_TNGCR_FL_COPY,
9592};
9593
9594
9595
9596
9597
9598MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
9599
9600enum {
9601
9602
9603
9604 MLXSW_REG_TNGCR_FL_NO_HASH,
9605
9606
9607
9608 MLXSW_REG_TNGCR_FL_HASH,
9609};
9610
9611
9612
9613
9614
9615MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
9616
9617
9618
9619
9620
9621MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
9622
9623
9624
9625
9626
9627
9628MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
9629
9630enum {
9631
9632 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
9633
9634 MLXSW_REG_TNGCR_UDP_SPORT_HASH,
9635};
9636
9637
9638
9639
9640
9641
9642
9643
9644
9645MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
9646
9647
9648
9649
9650
9651
9652MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
9653
9654
9655
9656
9657
9658
9659
9660
9661
9662MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
9663
9664
9665
9666
9667
9668
9669
9670
9671
9672MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
9673
9674
9675
9676
9677
9678
9679MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
9680
9681
9682
9683
9684
9685
9686MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
9687
9688
9689
9690
9691
9692
9693MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
9694
9695
9696
9697
9698
9699MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
9700
9701
9702
9703
9704
9705
9706MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
9707
9708static inline void mlxsw_reg_tngcr_pack(char *payload,
9709 enum mlxsw_reg_tngcr_type type,
9710 bool valid, u8 ttl)
9711{
9712 MLXSW_REG_ZERO(tngcr, payload);
9713 mlxsw_reg_tngcr_type_set(payload, type);
9714 mlxsw_reg_tngcr_nve_valid_set(payload, valid);
9715 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
9716 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
9717 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
9718 mlxsw_reg_tngcr_nve_flh_set(payload, 0);
9719 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
9720 MLXSW_REG_TNGCR_UDP_SPORT_HASH);
9721 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
9722 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
9723 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
9724}
9725
9726
9727
9728
9729
9730
9731#define MLXSW_REG_TNUMT_ID 0xA003
9732#define MLXSW_REG_TNUMT_LEN 0x20
9733
9734MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
9735
9736enum mlxsw_reg_tnumt_record_type {
9737 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
9738 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
9739 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
9740};
9741
9742
9743
9744
9745
9746MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
9747
9748enum mlxsw_reg_tnumt_tunnel_port {
9749 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
9750 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
9751 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
9752 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
9753};
9754
9755
9756
9757
9758
9759MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
9760
9761
9762
9763
9764
9765
9766MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
9767
9768
9769
9770
9771
9772MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
9773
9774
9775
9776
9777
9778MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
9779
9780
9781
9782
9783
9784
9785MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
9786
9787
9788
9789
9790
9791MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
9792
9793
9794
9795
9796
9797
9798MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
9799
9800static inline void mlxsw_reg_tnumt_pack(char *payload,
9801 enum mlxsw_reg_tnumt_record_type type,
9802 enum mlxsw_reg_tnumt_tunnel_port tport,
9803 u32 underlay_mc_ptr, bool vnext,
9804 u32 next_underlay_mc_ptr,
9805 u8 record_size)
9806{
9807 MLXSW_REG_ZERO(tnumt, payload);
9808 mlxsw_reg_tnumt_record_type_set(payload, type);
9809 mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
9810 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
9811 mlxsw_reg_tnumt_vnext_set(payload, vnext);
9812 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
9813 mlxsw_reg_tnumt_record_size_set(payload, record_size);
9814}
9815
9816
9817
9818
9819
9820
9821#define MLXSW_REG_TNQCR_ID 0xA010
9822#define MLXSW_REG_TNQCR_LEN 0x0C
9823
9824MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
9825
9826
9827
9828
9829
9830
9831
9832
9833MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
9834
9835static inline void mlxsw_reg_tnqcr_pack(char *payload)
9836{
9837 MLXSW_REG_ZERO(tnqcr, payload);
9838 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
9839}
9840
9841
9842
9843
9844
9845
9846#define MLXSW_REG_TNQDR_ID 0xA011
9847#define MLXSW_REG_TNQDR_LEN 0x08
9848
9849MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
9850
9851
9852
9853
9854
9855MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
9856
9857
9858
9859
9860
9861MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
9862
9863static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
9864{
9865 MLXSW_REG_ZERO(tnqdr, payload);
9866 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
9867 mlxsw_reg_tnqdr_dscp_set(payload, 0);
9868}
9869
9870
9871
9872
9873
9874
9875#define MLXSW_REG_TNEEM_ID 0xA012
9876#define MLXSW_REG_TNEEM_LEN 0x0C
9877
9878MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
9879
9880
9881
9882
9883
9884MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
9885
9886
9887
9888
9889
9890MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
9891
9892static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
9893 u8 underlay_ecn)
9894{
9895 MLXSW_REG_ZERO(tneem, payload);
9896 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
9897 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
9898}
9899
9900
9901
9902
9903
9904
9905#define MLXSW_REG_TNDEM_ID 0xA013
9906#define MLXSW_REG_TNDEM_LEN 0x0C
9907
9908MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
9909
9910
9911
9912
9913
9914MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
9915
9916
9917
9918
9919
9920MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
9921
9922
9923
9924
9925
9926
9927MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
9928
9929
9930
9931
9932
9933
9934
9935MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
9936
9937
9938
9939
9940
9941
9942MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
9943
9944static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
9945 u8 overlay_ecn, u8 ecn, bool trap_en,
9946 u16 trap_id)
9947{
9948 MLXSW_REG_ZERO(tndem, payload);
9949 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
9950 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
9951 mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
9952 mlxsw_reg_tndem_trap_en_set(payload, trap_en);
9953 mlxsw_reg_tndem_trap_id_set(payload, trap_id);
9954}
9955
9956
9957
9958
9959
9960
9961#define MLXSW_REG_TNPC_ID 0xA020
9962#define MLXSW_REG_TNPC_LEN 0x18
9963
9964MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
9965
9966enum mlxsw_reg_tnpc_tunnel_port {
9967 MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
9968 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
9969 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
9970 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
9971};
9972
9973
9974
9975
9976
9977MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
9978
9979
9980
9981
9982
9983MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
9984
9985
9986
9987
9988
9989MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
9990
9991static inline void mlxsw_reg_tnpc_pack(char *payload,
9992 enum mlxsw_reg_tnpc_tunnel_port tport,
9993 bool learn_enable)
9994{
9995 MLXSW_REG_ZERO(tnpc, payload);
9996 mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
9997 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
9998 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
9999}
10000
10001
10002
10003
10004
10005#define MLXSW_REG_TIGCR_ID 0xA801
10006#define MLXSW_REG_TIGCR_LEN 0x10
10007
10008MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
10009
10010
10011
10012
10013
10014
10015MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
10016
10017
10018
10019
10020
10021
10022MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
10023
10024static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
10025{
10026 MLXSW_REG_ZERO(tigcr, payload);
10027 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
10028 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
10029}
10030
10031
10032
10033
10034
10035#define MLXSW_REG_SBPR_ID 0xB001
10036#define MLXSW_REG_SBPR_LEN 0x14
10037
10038MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
10039
10040
10041enum mlxsw_reg_sbxx_dir {
10042 MLXSW_REG_SBXX_DIR_INGRESS,
10043 MLXSW_REG_SBXX_DIR_EGRESS,
10044};
10045
10046
10047
10048
10049
10050MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
10051
10052
10053
10054
10055
10056MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
10057
10058
10059
10060
10061
10062MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
10063
10064
10065
10066
10067
10068
10069MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
10070
10071enum mlxsw_reg_sbpr_mode {
10072 MLXSW_REG_SBPR_MODE_STATIC,
10073 MLXSW_REG_SBPR_MODE_DYNAMIC,
10074};
10075
10076
10077
10078
10079
10080MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
10081
10082static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
10083 enum mlxsw_reg_sbxx_dir dir,
10084 enum mlxsw_reg_sbpr_mode mode, u32 size,
10085 bool infi_size)
10086{
10087 MLXSW_REG_ZERO(sbpr, payload);
10088 mlxsw_reg_sbpr_pool_set(payload, pool);
10089 mlxsw_reg_sbpr_dir_set(payload, dir);
10090 mlxsw_reg_sbpr_mode_set(payload, mode);
10091 mlxsw_reg_sbpr_size_set(payload, size);
10092 mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
10093}
10094
10095
10096
10097
10098
10099
10100
10101#define MLXSW_REG_SBCM_ID 0xB002
10102#define MLXSW_REG_SBCM_LEN 0x28
10103
10104MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
10105
10106
10107
10108
10109
10110
10111
10112MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
10113
10114
10115
10116
10117
10118
10119
10120
10121
10122MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
10123
10124
10125
10126
10127
10128MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
10129
10130
10131
10132
10133
10134MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
10135
10136
10137#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
10138#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
10139
10140
10141
10142
10143
10144MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
10145
10146
10147
10148
10149
10150
10151
10152
10153
10154
10155
10156
10157
10158MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
10159
10160
10161
10162
10163
10164MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
10165
10166static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
10167 enum mlxsw_reg_sbxx_dir dir,
10168 u32 min_buff, u32 max_buff,
10169 bool infi_max, u8 pool)
10170{
10171 MLXSW_REG_ZERO(sbcm, payload);
10172 mlxsw_reg_sbcm_local_port_set(payload, local_port);
10173 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
10174 mlxsw_reg_sbcm_dir_set(payload, dir);
10175 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
10176 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
10177 mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
10178 mlxsw_reg_sbcm_pool_set(payload, pool);
10179}
10180
10181
10182
10183
10184
10185
10186
10187#define MLXSW_REG_SBPM_ID 0xB003
10188#define MLXSW_REG_SBPM_LEN 0x28
10189
10190MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
10191
10192
10193
10194
10195
10196
10197
10198MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
10199
10200
10201
10202
10203
10204MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
10205
10206
10207
10208
10209
10210MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
10211
10212
10213
10214
10215
10216MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
10217
10218
10219
10220
10221
10222
10223
10224MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
10225
10226
10227
10228
10229
10230
10231MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
10232
10233
10234
10235
10236
10237MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
10238
10239
10240
10241
10242
10243
10244
10245
10246
10247
10248
10249
10250MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
10251
10252static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
10253 enum mlxsw_reg_sbxx_dir dir, bool clr,
10254 u32 min_buff, u32 max_buff)
10255{
10256 MLXSW_REG_ZERO(sbpm, payload);
10257 mlxsw_reg_sbpm_local_port_set(payload, local_port);
10258 mlxsw_reg_sbpm_pool_set(payload, pool);
10259 mlxsw_reg_sbpm_dir_set(payload, dir);
10260 mlxsw_reg_sbpm_clr_set(payload, clr);
10261 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
10262 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
10263}
10264
10265static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
10266 u32 *p_max_buff_occupancy)
10267{
10268 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
10269 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
10270}
10271
10272
10273
10274
10275
10276
10277
10278#define MLXSW_REG_SBMM_ID 0xB004
10279#define MLXSW_REG_SBMM_LEN 0x28
10280
10281MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
10282
10283
10284
10285
10286
10287MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
10288
10289
10290
10291
10292
10293MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
10294
10295
10296
10297
10298
10299
10300
10301
10302
10303
10304
10305
10306MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
10307
10308
10309
10310
10311
10312MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
10313
10314static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
10315 u32 max_buff, u8 pool)
10316{
10317 MLXSW_REG_ZERO(sbmm, payload);
10318 mlxsw_reg_sbmm_prio_set(payload, prio);
10319 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
10320 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
10321 mlxsw_reg_sbmm_pool_set(payload, pool);
10322}
10323
10324
10325
10326
10327
10328
10329
10330
10331
10332#define MLXSW_REG_SBSR_ID 0xB005
10333#define MLXSW_REG_SBSR_BASE_LEN 0x5C
10334#define MLXSW_REG_SBSR_REC_LEN 0x8
10335#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
10336#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
10337 MLXSW_REG_SBSR_REC_LEN * \
10338 MLXSW_REG_SBSR_REC_MAX_COUNT)
10339
10340MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
10341
10342
10343
10344
10345
10346
10347
10348MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
10349
10350
10351
10352
10353
10354
10355
10356
10357MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
10358
10359
10360
10361
10362
10363
10364
10365
10366
10367MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
10368
10369
10370
10371
10372
10373
10374
10375
10376MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
10377
10378
10379
10380
10381
10382
10383
10384
10385
10386MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
10387
10388static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
10389{
10390 MLXSW_REG_ZERO(sbsr, payload);
10391 mlxsw_reg_sbsr_clr_set(payload, clr);
10392}
10393
10394
10395
10396
10397
10398MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10399 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
10400
10401
10402
10403
10404
10405
10406MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10407 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
10408
10409static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
10410 u32 *p_buff_occupancy,
10411 u32 *p_max_buff_occupancy)
10412{
10413 *p_buff_occupancy =
10414 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
10415 *p_max_buff_occupancy =
10416 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
10417}
10418
10419
10420
10421
10422
10423
10424
10425
10426
10427#define MLXSW_REG_SBIB_ID 0xB006
10428#define MLXSW_REG_SBIB_LEN 0x10
10429
10430MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
10431
10432
10433
10434
10435
10436
10437MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
10438
10439
10440
10441
10442
10443
10444
10445MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
10446
10447static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
10448 u32 buff_size)
10449{
10450 MLXSW_REG_ZERO(sbib, payload);
10451 mlxsw_reg_sbib_local_port_set(payload, local_port);
10452 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
10453}
10454
10455static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
10456 MLXSW_REG(sgcr),
10457 MLXSW_REG(spad),
10458 MLXSW_REG(smid),
10459 MLXSW_REG(sspr),
10460 MLXSW_REG(sfdat),
10461 MLXSW_REG(sfd),
10462 MLXSW_REG(sfn),
10463 MLXSW_REG(spms),
10464 MLXSW_REG(spvid),
10465 MLXSW_REG(spvm),
10466 MLXSW_REG(spaft),
10467 MLXSW_REG(sfgc),
10468 MLXSW_REG(sftr),
10469 MLXSW_REG(sfdf),
10470 MLXSW_REG(sldr),
10471 MLXSW_REG(slcr),
10472 MLXSW_REG(slcor),
10473 MLXSW_REG(spmlr),
10474 MLXSW_REG(svfa),
10475 MLXSW_REG(svpe),
10476 MLXSW_REG(sfmr),
10477 MLXSW_REG(spvmlr),
10478 MLXSW_REG(cwtp),
10479 MLXSW_REG(cwtpm),
10480 MLXSW_REG(pgcr),
10481 MLXSW_REG(ppbt),
10482 MLXSW_REG(pacl),
10483 MLXSW_REG(pagt),
10484 MLXSW_REG(ptar),
10485 MLXSW_REG(ppbs),
10486 MLXSW_REG(prcr),
10487 MLXSW_REG(pefa),
10488 MLXSW_REG(pemrbt),
10489 MLXSW_REG(ptce2),
10490 MLXSW_REG(perpt),
10491 MLXSW_REG(peabfe),
10492 MLXSW_REG(perar),
10493 MLXSW_REG(ptce3),
10494 MLXSW_REG(percr),
10495 MLXSW_REG(pererp),
10496 MLXSW_REG(iedr),
10497 MLXSW_REG(qpts),
10498 MLXSW_REG(qpcr),
10499 MLXSW_REG(qtct),
10500 MLXSW_REG(qeec),
10501 MLXSW_REG(qrwe),
10502 MLXSW_REG(qpdsm),
10503 MLXSW_REG(qpdpm),
10504 MLXSW_REG(qtctm),
10505 MLXSW_REG(qpsc),
10506 MLXSW_REG(pmlp),
10507 MLXSW_REG(pmtu),
10508 MLXSW_REG(ptys),
10509 MLXSW_REG(ppad),
10510 MLXSW_REG(paos),
10511 MLXSW_REG(pfcc),
10512 MLXSW_REG(ppcnt),
10513 MLXSW_REG(plib),
10514 MLXSW_REG(pptb),
10515 MLXSW_REG(pbmc),
10516 MLXSW_REG(pspa),
10517 MLXSW_REG(pplr),
10518 MLXSW_REG(htgt),
10519 MLXSW_REG(hpkt),
10520 MLXSW_REG(rgcr),
10521 MLXSW_REG(ritr),
10522 MLXSW_REG(rtar),
10523 MLXSW_REG(ratr),
10524 MLXSW_REG(rtdp),
10525 MLXSW_REG(rdpm),
10526 MLXSW_REG(ricnt),
10527 MLXSW_REG(rrcr),
10528 MLXSW_REG(ralta),
10529 MLXSW_REG(ralst),
10530 MLXSW_REG(raltb),
10531 MLXSW_REG(ralue),
10532 MLXSW_REG(rauht),
10533 MLXSW_REG(raleu),
10534 MLXSW_REG(rauhtd),
10535 MLXSW_REG(rigr2),
10536 MLXSW_REG(recr2),
10537 MLXSW_REG(rmft2),
10538 MLXSW_REG(mfcr),
10539 MLXSW_REG(mfsc),
10540 MLXSW_REG(mfsm),
10541 MLXSW_REG(mfsl),
10542 MLXSW_REG(fore),
10543 MLXSW_REG(mtcap),
10544 MLXSW_REG(mtmp),
10545 MLXSW_REG(mtbr),
10546 MLXSW_REG(mcia),
10547 MLXSW_REG(mpat),
10548 MLXSW_REG(mpar),
10549 MLXSW_REG(mgir),
10550 MLXSW_REG(mrsr),
10551 MLXSW_REG(mlcr),
10552 MLXSW_REG(mtpps),
10553 MLXSW_REG(mtutc),
10554 MLXSW_REG(mpsc),
10555 MLXSW_REG(mcqi),
10556 MLXSW_REG(mcc),
10557 MLXSW_REG(mcda),
10558 MLXSW_REG(mgpc),
10559 MLXSW_REG(mprs),
10560 MLXSW_REG(mogcr),
10561 MLXSW_REG(mtpppc),
10562 MLXSW_REG(mtpptr),
10563 MLXSW_REG(mtptpt),
10564 MLXSW_REG(mgpir),
10565 MLXSW_REG(tngcr),
10566 MLXSW_REG(tnumt),
10567 MLXSW_REG(tnqcr),
10568 MLXSW_REG(tnqdr),
10569 MLXSW_REG(tneem),
10570 MLXSW_REG(tndem),
10571 MLXSW_REG(tnpc),
10572 MLXSW_REG(tigcr),
10573 MLXSW_REG(sbpr),
10574 MLXSW_REG(sbcm),
10575 MLXSW_REG(sbpm),
10576 MLXSW_REG(sbmm),
10577 MLXSW_REG(sbsr),
10578 MLXSW_REG(sbib),
10579};
10580
10581static inline const char *mlxsw_reg_id_str(u16 reg_id)
10582{
10583 const struct mlxsw_reg_info *reg_info;
10584 int i;
10585
10586 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
10587 reg_info = mlxsw_reg_infos[i];
10588 if (reg_info->id == reg_id)
10589 return reg_info->name;
10590 }
10591 return "*UNKNOWN*";
10592}
10593
10594
10595
10596
10597
10598#define MLXSW_REG_PUDE_LEN 0x10
10599
10600
10601
10602
10603
10604MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
10605
10606
10607
10608
10609
10610MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
10611
10612
10613
10614
10615
10616
10617
10618
10619
10620
10621MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
10622
10623
10624
10625
10626
10627
10628
10629
10630
10631MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
10632
10633#endif
10634