LXR linux/drivers/net/ethernet/smsc/smc91x.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*------------------------------------------------------------------------
   3 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
   4 .
   5 . Copyright (C) 1996 by Erik Stahlman
   6 . Copyright (C) 2001 Standard Microsystems Corporation
   7 .      Developed by Simple Network Magic Corporation
   8 . Copyright (C) 2003 Monta Vista Software, Inc.
   9 .      Unified SMC91x driver by Nicolas Pitre
  10 .
  11 .
  12 . Information contained in this file was obtained from the LAN91C111
  13 . manual from SMC.  To get a copy, if you really want one, you can find
  14 . information under www.smsc.com.
  15 .
  16 . Authors
  17 .      Erik Stahlman           <erik@vt.edu>
  18 .      Daris A Nevil           <dnevil@snmc.com>
  19 .      Nicolas Pitre           <nico@fluxnic.net>
  20 .
  21 ---------------------------------------------------------------------------*/
  22#ifndef _SMC91X_H_
  23#define _SMC91X_H_
  24
  25#include <linux/dmaengine.h>
  26#include <linux/smc91x.h>
  27
  28/*
  29 * Any 16-bit access is performed with two 8-bit accesses if the hardware
  30 * can't do it directly. Most registers are 16-bit so those are mandatory.
  31 */
  32#define SMC_outw_b(x, a, r)                                             \
  33        do {                                                            \
  34                unsigned int __val16 = (x);                             \
  35                unsigned int __reg = (r);                               \
  36                SMC_outb(__val16, a, __reg);                            \
  37                SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
  38        } while (0)
  39
  40#define SMC_inw_b(a, r)                                                 \
  41        ({                                                              \
  42                unsigned int __val16;                                   \
  43                unsigned int __reg = r;                                 \
  44                __val16  = SMC_inb(a, __reg);                           \
  45                __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
  46                __val16;                                                \
  47        })
  48
  49/*
  50 * Define your architecture specific bus configuration parameters here.
  51 */
  52
  53#if defined(CONFIG_ARM)
  54
  55#include <asm/mach-types.h>
  56
  57/* Now the bus width is specified in the platform data
  58 * pretend here to support all I/O access types
  59 */
  60#define SMC_CAN_USE_8BIT        1
  61#define SMC_CAN_USE_16BIT       1
  62#define SMC_CAN_USE_32BIT       1
  63#define SMC_NOWAIT              1
  64
  65#define SMC_IO_SHIFT            (lp->io_shift)
  66
  67#define SMC_inb(a, r)           readb((a) + (r))
  68#define SMC_inw(a, r)                                                   \
  69        ({                                                              \
  70                unsigned int __smc_r = r;                               \
  71                SMC_16BIT(lp) ? readw((a) + __smc_r) :                  \
  72                SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) :                  \
  73                ({ BUG(); 0; });                                        \
  74        })
  75
  76#define SMC_inl(a, r)           readl((a) + (r))
  77#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
  78#define SMC_outw(lp, v, a, r)                                           \
  79        do {                                                            \
  80                unsigned int __v = v, __smc_r = r;                      \
  81                if (SMC_16BIT(lp))                                      \
  82                        __SMC_outw(lp, __v, a, __smc_r);                \
  83                else if (SMC_8BIT(lp))                                  \
  84                        SMC_outw_b(__v, a, __smc_r);                    \
  85                else                                                    \
  86                        BUG();                                          \
  87        } while (0)
  88
  89#define SMC_outl(v, a, r)       writel(v, (a) + (r))
  90#define SMC_insb(a, r, p, l)    readsb((a) + (r), p, l)
  91#define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, l)
  92#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
  93#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
  94#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
  95#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
  96#define SMC_IRQ_FLAGS           (-1)    /* from resource */
  97
  98/* We actually can't write halfwords properly if not word aligned */
  99static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg,
 100                                    bool use_align4_workaround)
 101{
 102        if (use_align4_workaround) {
 103                unsigned int v = val << 16;
 104                v |= readl(ioaddr + (reg & ~2)) & 0xffff;
 105                writel(v, ioaddr + (reg & ~2));
 106        } else {
 107                writew(val, ioaddr + reg);
 108        }
 109}
 110
 111#define __SMC_outw(lp, v, a, r)                                         \
 112        _SMC_outw_align4((v), (a), (r),                                 \
 113                         IS_BUILTIN(CONFIG_ARCH_PXA) && ((r) & 2) &&    \
 114                         (lp)->cfg.pxa_u16_align4)
 115
 116
 117#elif   defined(CONFIG_SH_SH4202_MICRODEV)
 118
 119#define SMC_CAN_USE_8BIT        0
 120#define SMC_CAN_USE_16BIT       1
 121#define SMC_CAN_USE_32BIT       0
 122
 123#define SMC_inb(a, r)           inb((a) + (r) - 0xa0000000)
 124#define SMC_inw(a, r)           inw((a) + (r) - 0xa0000000)
 125#define SMC_inl(a, r)           inl((a) + (r) - 0xa0000000)
 126#define SMC_outb(v, a, r)       outb(v, (a) + (r) - 0xa0000000)
 127#define SMC_outw(lp, v, a, r)   outw(v, (a) + (r) - 0xa0000000)
 128#define SMC_outl(v, a, r)       outl(v, (a) + (r) - 0xa0000000)
 129#define SMC_insl(a, r, p, l)    insl((a) + (r) - 0xa0000000, p, l)
 130#define SMC_outsl(a, r, p, l)   outsl((a) + (r) - 0xa0000000, p, l)
 131#define SMC_insw(a, r, p, l)    insw((a) + (r) - 0xa0000000, p, l)
 132#define SMC_outsw(a, r, p, l)   outsw((a) + (r) - 0xa0000000, p, l)
 133
 134#define SMC_IRQ_FLAGS           (0)
 135
 136#elif defined(CONFIG_ATARI)
 137
 138#define SMC_CAN_USE_8BIT        1
 139#define SMC_CAN_USE_16BIT       1
 140#define SMC_CAN_USE_32BIT       1
 141#define SMC_NOWAIT              1
 142
 143#define SMC_inb(a, r)           readb((a) + (r))
 144#define SMC_inw(a, r)           readw((a) + (r))
 145#define SMC_inl(a, r)           readl((a) + (r))
 146#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 147#define SMC_outw(lp, v, a, r)   writew(v, (a) + (r))
 148#define SMC_outl(v, a, r)       writel(v, (a) + (r))
 149#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 150#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 151#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 152#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 153
 154#define RPC_LSA_DEFAULT         RPC_LED_100_10
 155#define RPC_LSB_DEFAULT         RPC_LED_TX_RX
 156
 157#elif defined(CONFIG_COLDFIRE)
 158
 159#define SMC_CAN_USE_8BIT        0
 160#define SMC_CAN_USE_16BIT       1
 161#define SMC_CAN_USE_32BIT       0
 162#define SMC_NOWAIT              1
 163
 164static inline void mcf_insw(void *a, unsigned char *p, int l)
 165{
 166        u16 *wp = (u16 *) p;
 167        while (l-- > 0)
 168                *wp++ = readw(a);
 169}
 170
 171static inline void mcf_outsw(void *a, unsigned char *p, int l)
 172{
 173        u16 *wp = (u16 *) p;
 174        while (l-- > 0)
 175                writew(*wp++, a);
 176}
 177
 178#define SMC_inw(a, r)           _swapw(readw((a) + (r)))
 179#define SMC_outw(lp, v, a, r)   writew(_swapw(v), (a) + (r))
 180#define SMC_insw(a, r, p, l)    mcf_insw(a + r, p, l)
 181#define SMC_outsw(a, r, p, l)   mcf_outsw(a + r, p, l)
 182
 183#define SMC_IRQ_FLAGS           0
 184
 185#elif defined(CONFIG_H8300)
 186#define SMC_CAN_USE_8BIT        1
 187#define SMC_CAN_USE_16BIT       0
 188#define SMC_CAN_USE_32BIT       0
 189#define SMC_NOWAIT              0
 190
 191#define SMC_inb(a, r)           ioread8((a) + (r))
 192#define SMC_outb(v, a, r)       iowrite8(v, (a) + (r))
 193#define SMC_insb(a, r, p, l)    ioread8_rep((a) + (r), p, l)
 194#define SMC_outsb(a, r, p, l)   iowrite8_rep((a) + (r), p, l)
 195
 196#else
 197
 198/*
 199 * Default configuration
 200 */
 201
 202#define SMC_CAN_USE_8BIT        1
 203#define SMC_CAN_USE_16BIT       1
 204#define SMC_CAN_USE_32BIT       1
 205#define SMC_NOWAIT              1
 206
 207#define SMC_IO_SHIFT            (lp->io_shift)
 208
 209#define SMC_inb(a, r)           ioread8((a) + (r))
 210#define SMC_inw(a, r)           ioread16((a) + (r))
 211#define SMC_inl(a, r)           ioread32((a) + (r))
 212#define SMC_outb(v, a, r)       iowrite8(v, (a) + (r))
 213#define SMC_outw(lp, v, a, r)   iowrite16(v, (a) + (r))
 214#define SMC_outl(v, a, r)       iowrite32(v, (a) + (r))
 215#define SMC_insw(a, r, p, l)    ioread16_rep((a) + (r), p, l)
 216#define SMC_outsw(a, r, p, l)   iowrite16_rep((a) + (r), p, l)
 217#define SMC_insl(a, r, p, l)    ioread32_rep((a) + (r), p, l)
 218#define SMC_outsl(a, r, p, l)   iowrite32_rep((a) + (r), p, l)
 219
 220#define RPC_LSA_DEFAULT         RPC_LED_100_10
 221#define RPC_LSB_DEFAULT         RPC_LED_TX_RX
 222
 223#endif
 224
 225
 226/* store this information for the driver.. */
 227struct smc_local {
 228        /*
 229         * If I have to wait until memory is available to send a
 230         * packet, I will store the skbuff here, until I get the
 231         * desired memory.  Then, I'll send it out and free it.
 232         */
 233        struct sk_buff *pending_tx_skb;
 234        struct tasklet_struct tx_task;
 235
 236        struct gpio_desc *power_gpio;
 237        struct gpio_desc *reset_gpio;
 238
 239        /* version/revision of the SMC91x chip */
 240        int     version;
 241
 242        /* Contains the current active transmission mode */
 243        int     tcr_cur_mode;
 244
 245        /* Contains the current active receive mode */
 246        int     rcr_cur_mode;
 247
 248        /* Contains the current active receive/phy mode */
 249        int     rpc_cur_mode;
 250        int     ctl_rfduplx;
 251        int     ctl_rspeed;
 252
 253        u32     msg_enable;
 254        u32     phy_type;
 255        struct mii_if_info mii;
 256
 257        /* work queue */
 258        struct work_struct phy_configure;
 259        struct net_device *dev;
 260        int     work_pending;
 261
 262        spinlock_t lock;
 263
 264#ifdef CONFIG_ARCH_PXA
 265        /* DMA needs the physical address of the chip */
 266        u_long physaddr;
 267        struct device *device;
 268#endif
 269        struct dma_chan *dma_chan;
 270        void __iomem *base;
 271        void __iomem *datacs;
 272
 273        /* the low address lines on some platforms aren't connected... */
 274        int     io_shift;
 275        /* on some platforms a u16 write must be 4-bytes aligned */
 276        bool    half_word_align4;
 277
 278        struct smc91x_platdata cfg;
 279};
 280
 281#define SMC_8BIT(p)     ((p)->cfg.flags & SMC91X_USE_8BIT)
 282#define SMC_16BIT(p)    ((p)->cfg.flags & SMC91X_USE_16BIT)
 283#define SMC_32BIT(p)    ((p)->cfg.flags & SMC91X_USE_32BIT)
 284
 285#ifdef CONFIG_ARCH_PXA
 286/*
 287 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
 288 * always happening in irq context so no need to worry about races.  TX is
 289 * different and probably not worth it for that reason, and not as critical
 290 * as RX which can overrun memory and lose packets.
 291 */
 292#include <linux/dma-mapping.h>
 293
 294#ifdef SMC_insl
 295#undef SMC_insl
 296#define SMC_insl(a, r, p, l) \
 297        smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
 298static inline void
 299smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
 300{
 301        dma_addr_t dmabuf;
 302        struct dma_async_tx_descriptor *tx;
 303        dma_cookie_t cookie;
 304        enum dma_status status;
 305        struct dma_tx_state state;
 306
 307        dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 308        tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
 309                                         DMA_DEV_TO_MEM, 0);
 310        if (tx) {
 311                cookie = dmaengine_submit(tx);
 312                dma_async_issue_pending(lp->dma_chan);
 313                do {
 314                        status = dmaengine_tx_status(lp->dma_chan, cookie,
 315                                                     &state);
 316                        cpu_relax();
 317                } while (status != DMA_COMPLETE && status != DMA_ERROR &&
 318                         state.residue);
 319                dmaengine_terminate_all(lp->dma_chan);
 320        }
 321        dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 322}
 323
 324static inline void
 325smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 326                 u_char *buf, int len)
 327{
 328        struct dma_slave_config config;
 329        int ret;
 330
 331        /* fallback if no DMA available */
 332        if (!lp->dma_chan) {
 333                readsl(ioaddr + reg, buf, len);
 334                return;
 335        }
 336
 337        /* 64 bit alignment is required for memory to memory DMA */
 338        if ((long)buf & 4) {
 339                *((u32 *)buf) = SMC_inl(ioaddr, reg);
 340                buf += 4;
 341                len--;
 342        }
 343
 344        memset(&config, 0, sizeof(config));
 345        config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 346        config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 347        config.src_addr = lp->physaddr + reg;
 348        config.dst_addr = lp->physaddr + reg;
 349        config.src_maxburst = 32;
 350        config.dst_maxburst = 32;
 351        ret = dmaengine_slave_config(lp->dma_chan, &config);
 352        if (ret) {
 353                dev_err(lp->device, "dma channel configuration failed: %d\n",
 354                        ret);
 355                return;
 356        }
 357
 358        len *= 4;
 359        smc_pxa_dma_inpump(lp, buf, len);
 360}
 361#endif
 362
 363#ifdef SMC_insw
 364#undef SMC_insw
 365#define SMC_insw(a, r, p, l) \
 366        smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
 367static inline void
 368smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 369                 u_char *buf, int len)
 370{
 371        struct dma_slave_config config;
 372        int ret;
 373
 374        /* fallback if no DMA available */
 375        if (!lp->dma_chan) {
 376                readsw(ioaddr + reg, buf, len);
 377                return;
 378        }
 379
 380        /* 64 bit alignment is required for memory to memory DMA */
 381        while ((long)buf & 6) {
 382                *((u16 *)buf) = SMC_inw(ioaddr, reg);
 383                buf += 2;
 384                len--;
 385        }
 386
 387        memset(&config, 0, sizeof(config));
 388        config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 389        config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 390        config.src_addr = lp->physaddr + reg;
 391        config.dst_addr = lp->physaddr + reg;
 392        config.src_maxburst = 32;
 393        config.dst_maxburst = 32;
 394        ret = dmaengine_slave_config(lp->dma_chan, &config);
 395        if (ret) {
 396                dev_err(lp->device, "dma channel configuration failed: %d\n",
 397                        ret);
 398                return;
 399        }
 400
 401        len *= 2;
 402        smc_pxa_dma_inpump(lp, buf, len);
 403}
 404#endif
 405
 406#endif  /* CONFIG_ARCH_PXA */
 407
 408
 409/*
 410 * Everything a particular hardware setup needs should have been defined
 411 * at this point.  Add stubs for the undefined cases, mainly to avoid
 412 * compilation warnings since they'll be optimized away, or to prevent buggy
 413 * use of them.
 414 */
 415
 416#if ! SMC_CAN_USE_32BIT
 417#define SMC_inl(ioaddr, reg)            ({ BUG(); 0; })
 418#define SMC_outl(x, ioaddr, reg)        BUG()
 419#define SMC_insl(a, r, p, l)            BUG()
 420#define SMC_outsl(a, r, p, l)           BUG()
 421#endif
 422
 423#if !defined(SMC_insl) || !defined(SMC_outsl)
 424#define SMC_insl(a, r, p, l)            BUG()
 425#define SMC_outsl(a, r, p, l)           BUG()
 426#endif
 427
 428#if ! SMC_CAN_USE_16BIT
 429
 430#define SMC_outw(lp, x, ioaddr, reg)    SMC_outw_b(x, ioaddr, reg)
 431#define SMC_inw(ioaddr, reg)            SMC_inw_b(ioaddr, reg)
 432#define SMC_insw(a, r, p, l)            BUG()
 433#define SMC_outsw(a, r, p, l)           BUG()
 434
 435#endif
 436
 437#if !defined(SMC_insw) || !defined(SMC_outsw)
 438#define SMC_insw(a, r, p, l)            BUG()
 439#define SMC_outsw(a, r, p, l)           BUG()
 440#endif
 441
 442#if ! SMC_CAN_USE_8BIT
 443#undef SMC_inb
 444#define SMC_inb(ioaddr, reg)            ({ BUG(); 0; })
 445#undef SMC_outb
 446#define SMC_outb(x, ioaddr, reg)        BUG()
 447#define SMC_insb(a, r, p, l)            BUG()
 448#define SMC_outsb(a, r, p, l)           BUG()
 449#endif
 450
 451#if !defined(SMC_insb) || !defined(SMC_outsb)
 452#define SMC_insb(a, r, p, l)            BUG()
 453#define SMC_outsb(a, r, p, l)           BUG()
 454#endif
 455
 456#ifndef SMC_CAN_USE_DATACS
 457#define SMC_CAN_USE_DATACS      0
 458#endif
 459
 460#ifndef SMC_IO_SHIFT
 461#define SMC_IO_SHIFT    0
 462#endif
 463
 464#ifndef SMC_IRQ_FLAGS
 465#define SMC_IRQ_FLAGS           IRQF_TRIGGER_RISING
 466#endif
 467
 468#ifndef SMC_INTERRUPT_PREAMBLE
 469#define SMC_INTERRUPT_PREAMBLE
 470#endif
 471
 472
 473/* Because of bank switching, the LAN91x uses only 16 I/O ports */
 474#define SMC_IO_EXTENT   (16 << SMC_IO_SHIFT)
 475#define SMC_DATA_EXTENT (4)
 476
 477/*
 478 . Bank Select Register:
 479 .
 480 .              yyyy yyyy 0000 00xx
 481 .              xx              = bank number
 482 .              yyyy yyyy       = 0x33, for identification purposes.
 483*/
 484#define BANK_SELECT             (14 << SMC_IO_SHIFT)
 485
 486
 487// Transmit Control Register
 488/* BANK 0  */
 489#define TCR_REG(lp)     SMC_REG(lp, 0x0000, 0)
 490#define TCR_ENABLE      0x0001  // When 1 we can transmit
 491#define TCR_LOOP        0x0002  // Controls output pin LBK
 492#define TCR_FORCOL      0x0004  // When 1 will force a collision
 493#define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
 494#define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames
 495#define TCR_MON_CSN     0x0400  // When 1 tx monitors carrier
 496#define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
 497#define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
 498#define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
 499#define TCR_SWFDUP      0x8000  // When 1 enables Switched Full Duplex mode
 500
 501#define TCR_CLEAR       0       /* do NOTHING */
 502/* the default settings for the TCR register : */
 503#define TCR_DEFAULT     (TCR_ENABLE | TCR_PAD_EN)
 504
 505
 506// EPH Status Register
 507/* BANK 0  */
 508#define EPH_STATUS_REG(lp)      SMC_REG(lp, 0x0002, 0)
 509#define ES_TX_SUC       0x0001  // Last TX was successful
 510#define ES_SNGL_COL     0x0002  // Single collision detected for last tx
 511#define ES_MUL_COL      0x0004  // Multiple collisions detected for last tx
 512#define ES_LTX_MULT     0x0008  // Last tx was a multicast
 513#define ES_16COL        0x0010  // 16 Collisions Reached
 514#define ES_SQET         0x0020  // Signal Quality Error Test
 515#define ES_LTXBRD       0x0040  // Last tx was a broadcast
 516#define ES_TXDEFR       0x0080  // Transmit Deferred
 517#define ES_LATCOL       0x0200  // Late collision detected on last tx
 518#define ES_LOSTCARR     0x0400  // Lost Carrier Sense
 519#define ES_EXC_DEF      0x0800  // Excessive Deferral
 520#define ES_CTR_ROL      0x1000  // Counter Roll Over indication
 521#define ES_LINK_OK      0x4000  // Driven by inverted value of nLNK pin
 522#define ES_TXUNRN       0x8000  // Tx Underrun
 523
 524
 525// Receive Control Register
 526/* BANK 0  */
 527#define RCR_REG(lp)             SMC_REG(lp, 0x0004, 0)
 528#define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
 529#define RCR_PRMS        0x0002  // Enable promiscuous mode
 530#define RCR_ALMUL       0x0004  // When set accepts all multicast frames
 531#define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
 532#define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
 533#define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
 534#define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
 535#define RCR_SOFTRST     0x8000  // resets the chip
 536
 537/* the normal settings for the RCR register : */
 538#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
 539#define RCR_CLEAR       0x0     // set it to a base state
 540
 541
 542// Counter Register
 543/* BANK 0  */
 544#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
 545
 546
 547// Memory Information Register
 548/* BANK 0  */
 549#define MIR_REG(lp)             SMC_REG(lp, 0x0008, 0)
 550
 551
 552// Receive/Phy Control Register
 553/* BANK 0  */
 554#define RPC_REG(lp)             SMC_REG(lp, 0x000A, 0)
 555#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
 556#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
 557#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
 558#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
 559#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
 560
 561#ifndef RPC_LSA_DEFAULT
 562#define RPC_LSA_DEFAULT RPC_LED_100
 563#endif
 564#ifndef RPC_LSB_DEFAULT
 565#define RPC_LSB_DEFAULT RPC_LED_FD
 566#endif
 567
 568#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
 569
 570
 571/* Bank 0 0x0C is reserved */
 572
 573// Bank Select Register
 574/* All Banks */
 575#define BSR_REG         0x000E
 576
 577
 578// Configuration Reg
 579/* BANK 1 */
 580#define CONFIG_REG(lp)  SMC_REG(lp, 0x0000,     1)
 581#define CONFIG_EXT_PHY  0x0200  // 1=external MII, 0=internal Phy
 582#define CONFIG_GPCNTRL  0x0400  // Inverse value drives pin nCNTRL
 583#define CONFIG_NO_WAIT  0x1000  // When 1 no extra wait states on ISA bus
 584#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
 585
 586// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
 587#define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)
 588
 589
 590// Base Address Register
 591/* BANK 1 */
 592#define BASE_REG(lp)    SMC_REG(lp, 0x0002, 1)
 593
 594
 595// Individual Address Registers
 596/* BANK 1 */
 597#define ADDR0_REG(lp)   SMC_REG(lp, 0x0004, 1)
 598#define ADDR1_REG(lp)   SMC_REG(lp, 0x0006, 1)
 599#define ADDR2_REG(lp)   SMC_REG(lp, 0x0008, 1)
 600
 601
 602// General Purpose Register
 603/* BANK 1 */
 604#define GP_REG(lp)              SMC_REG(lp, 0x000A, 1)
 605
 606
 607// Control Register
 608/* BANK 1 */
 609#define CTL_REG(lp)             SMC_REG(lp, 0x000C, 1)
 610#define CTL_RCV_BAD     0x4000 // When 1 bad CRC packets are received
 611#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
 612#define CTL_LE_ENABLE   0x0080 // When 1 enables Link Error interrupt
 613#define CTL_CR_ENABLE   0x0040 // When 1 enables Counter Rollover interrupt
 614#define CTL_TE_ENABLE   0x0020 // When 1 enables Transmit Error interrupt
 615#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
 616#define CTL_RELOAD      0x0002 // When set reads EEPROM into registers
 617#define CTL_STORE       0x0001 // When set stores registers into EEPROM
 618
 619
 620// MMU Command Register
 621/* BANK 2 */
 622#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
 623#define MC_BUSY         1       // When 1 the last release has not completed
 624#define MC_NOP          (0<<5)  // No Op
 625#define MC_ALLOC        (1<<5)  // OR with number of 256 byte packets
 626#define MC_RESET        (2<<5)  // Reset MMU to initial state
 627#define MC_REMOVE       (3<<5)  // Remove the current rx packet
 628#define MC_RELEASE      (4<<5)  // Remove and release the current rx packet
 629#define MC_FREEPKT      (5<<5)  // Release packet in PNR register
 630#define MC_ENQUEUE      (6<<5)  // Enqueue the packet for transmit
 631#define MC_RSTTXFIFO    (7<<5)  // Reset the TX FIFOs
 632
 633
 634// Packet Number Register
 635/* BANK 2 */
 636#define PN_REG(lp)              SMC_REG(lp, 0x0002, 2)
 637
 638
 639// Allocation Result Register
 640/* BANK 2 */
 641#define AR_REG(lp)              SMC_REG(lp, 0x0003, 2)
 642#define AR_FAILED       0x80    // Alocation Failed
 643
 644
 645// TX FIFO Ports Register
 646/* BANK 2 */
 647#define TXFIFO_REG(lp)  SMC_REG(lp, 0x0004, 2)
 648#define TXFIFO_TEMPTY   0x80    // TX FIFO Empty
 649
 650// RX FIFO Ports Register
 651/* BANK 2 */
 652#define RXFIFO_REG(lp)  SMC_REG(lp, 0x0005, 2)
 653#define RXFIFO_REMPTY   0x80    // RX FIFO Empty
 654
 655#define FIFO_REG(lp)    SMC_REG(lp, 0x0004, 2)
 656
 657// Pointer Register
 658/* BANK 2 */
 659#define PTR_REG(lp)             SMC_REG(lp, 0x0006, 2)
 660#define PTR_RCV         0x8000 // 1=Receive area, 0=Transmit area
 661#define PTR_AUTOINC     0x4000 // Auto increment the pointer on each access
 662#define PTR_READ        0x2000 // When 1 the operation is a read
 663
 664
 665// Data Register
 666/* BANK 2 */
 667#define DATA_REG(lp)    SMC_REG(lp, 0x0008, 2)
 668
 669
 670// Interrupt Status/Acknowledge Register
 671/* BANK 2 */
 672#define INT_REG(lp)             SMC_REG(lp, 0x000C, 2)
 673
 674
 675// Interrupt Mask Register
 676/* BANK 2 */
 677#define IM_REG(lp)              SMC_REG(lp, 0x000D, 2)
 678#define IM_MDINT        0x80 // PHY MI Register 18 Interrupt
 679#define IM_ERCV_INT     0x40 // Early Receive Interrupt
 680#define IM_EPH_INT      0x20 // Set by Ethernet Protocol Handler section
 681#define IM_RX_OVRN_INT  0x10 // Set by Receiver Overruns
 682#define IM_ALLOC_INT    0x08 // Set when allocation request is completed
 683#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
 684#define IM_TX_INT       0x02 // Transmit Interrupt
 685#define IM_RCV_INT      0x01 // Receive Interrupt
 686
 687
 688// Multicast Table Registers
 689/* BANK 3 */
 690#define MCAST_REG1(lp)  SMC_REG(lp, 0x0000, 3)
 691#define MCAST_REG2(lp)  SMC_REG(lp, 0x0002, 3)
 692#define MCAST_REG3(lp)  SMC_REG(lp, 0x0004, 3)
 693#define MCAST_REG4(lp)  SMC_REG(lp, 0x0006, 3)
 694
 695
 696// Management Interface Register (MII)
 697/* BANK 3 */
 698#define MII_REG(lp)             SMC_REG(lp, 0x0008, 3)
 699#define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
 700#define MII_MDOE        0x0008 // MII Output Enable
 701#define MII_MCLK        0x0004 // MII Clock, pin MDCLK
 702#define MII_MDI         0x0002 // MII Input, pin MDI
 703#define MII_MDO         0x0001 // MII Output, pin MDO
 704
 705
 706// Revision Register
 707/* BANK 3 */
 708/* ( hi: chip id   low: rev # ) */
 709#define REV_REG(lp)             SMC_REG(lp, 0x000A, 3)
 710
 711
 712// Early RCV Register
 713/* BANK 3 */
 714/* this is NOT on SMC9192 */
 715#define ERCV_REG(lp)    SMC_REG(lp, 0x000C, 3)
 716#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
 717#define ERCV_THRESHOLD  0x001F // ERCV Threshold Mask
 718
 719
 720// External Register
 721/* BANK 7 */
 722#define EXT_REG(lp)             SMC_REG(lp, 0x0000, 7)
 723
 724
 725#define CHIP_9192       3
 726#define CHIP_9194       4
 727#define CHIP_9195       5
 728#define CHIP_9196       6
 729#define CHIP_91100      7
 730#define CHIP_91100FD    8
 731#define CHIP_91111FD    9
 732
 733static const char * chip_ids[ 16 ] =  {
 734        NULL, NULL, NULL,
 735        /* 3 */ "SMC91C90/91C92",
 736        /* 4 */ "SMC91C94",
 737        /* 5 */ "SMC91C95",
 738        /* 6 */ "SMC91C96",
 739        /* 7 */ "SMC91C100",
 740        /* 8 */ "SMC91C100FD",
 741        /* 9 */ "SMC91C11xFD",
 742        NULL, NULL, NULL,
 743        NULL, NULL, NULL};
 744
 745
 746/*
 747 . Receive status bits
 748*/
 749#define RS_ALGNERR      0x8000
 750#define RS_BRODCAST     0x4000
 751#define RS_BADCRC       0x2000
 752#define RS_ODDFRAME     0x1000
 753#define RS_TOOLONG      0x0800
 754#define RS_TOOSHORT     0x0400
 755#define RS_MULTICAST    0x0001
 756#define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 757
 758
 759/*
 760 * PHY IDs
 761 *  LAN83C183 == LAN91C111 Internal PHY
 762 */
 763#define PHY_LAN83C183   0x0016f840
 764#define PHY_LAN83C180   0x02821c50
 765
 766/*
 767 * PHY Register Addresses (LAN91C111 Internal PHY)
 768 *
 769 * Generic PHY registers can be found in <linux/mii.h>
 770 *
 771 * These phy registers are specific to our on-board phy.
 772 */
 773
 774// PHY Configuration Register 1
 775#define PHY_CFG1_REG            0x10
 776#define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
 777#define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
 778#define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
 779#define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
 780#define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
 781#define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
 782#define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
 783#define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
 784#define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
 785#define PHY_CFG1_TLVL_MASK      0x003C
 786#define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
 787
 788
 789// PHY Configuration Register 2
 790#define PHY_CFG2_REG            0x11
 791#define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
 792#define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
 793#define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
 794#define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
 795
 796// PHY Status Output (and Interrupt status) Register
 797#define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
 798#define PHY_INT_INT             0x8000  // 1=bits have changed since last read
 799#define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
 800#define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
 801#define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
 802#define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
 803#define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
 804#define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
 805#define PHY_INT_JAB             0x0100  // 1=Jabber detected
 806#define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
 807#define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
 808
 809// PHY Interrupt/Status Mask Register
 810#define PHY_MASK_REG            0x13    // Interrupt Mask
 811// Uses the same bit definitions as PHY_INT_REG
 812
 813
 814/*
 815 * SMC91C96 ethernet config and status registers.
 816 * These are in the "attribute" space.
 817 */
 818#define ECOR                    0x8000
 819#define ECOR_RESET              0x80
 820#define ECOR_LEVEL_IRQ          0x40
 821#define ECOR_WR_ATTRIB          0x04
 822#define ECOR_ENABLE             0x01
 823
 824#define ECSR                    0x8002
 825#define ECSR_IOIS8              0x20
 826#define ECSR_PWRDWN             0x04
 827#define ECSR_INT                0x02
 828
 829#define ATTRIB_SIZE             ((64*1024) << SMC_IO_SHIFT)
 830
 831
 832/*
 833 * Macros to abstract register access according to the data bus
 834 * capabilities.  Please use those and not the in/out primitives.
 835 * Note: the following macros do *not* select the bank -- this must
 836 * be done separately as needed in the main code.  The SMC_REG() macro
 837 * only uses the bank argument for debugging purposes (when enabled).
 838 *
 839 * Note: despite inline functions being safer, everything leading to this
 840 * should preferably be macros to let BUG() display the line number in
 841 * the core source code since we're interested in the top call site
 842 * not in any inline function location.
 843 */
 844
 845#if SMC_DEBUG > 0
 846#define SMC_REG(lp, reg, bank)                                  \
 847        ({                                                              \
 848                int __b = SMC_CURRENT_BANK(lp);                 \
 849                if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {       \
 850                        pr_err("%s: bank reg screwed (0x%04x)\n",       \
 851                               CARDNAME, __b);                          \
 852                        BUG();                                          \
 853                }                                                       \
 854                reg<<SMC_IO_SHIFT;                                      \
 855        })
 856#else
 857#define SMC_REG(lp, reg, bank)  (reg<<SMC_IO_SHIFT)
 858#endif
 859
 860/*
 861 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
 862 * aligned to a 32 bit boundary.  I tell you that does exist!
 863 * Fortunately the affected register accesses can be easily worked around
 864 * since we can write zeroes to the preceding 16 bits without adverse
 865 * effects and use a 32-bit access.
 866 *
 867 * Enforce it on any 32-bit capable setup for now.
 868 */
 869#define SMC_MUST_ALIGN_WRITE(lp)        SMC_32BIT(lp)
 870
 871#define SMC_GET_PN(lp)                                          \
 872        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, PN_REG(lp))) \
 873                                : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
 874
 875#define SMC_SET_PN(lp, x)                                               \
 876        do {                                                            \
 877                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 878                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));   \
 879                else if (SMC_8BIT(lp))                          \
 880                        SMC_outb(x, ioaddr, PN_REG(lp));                \
 881                else                                                    \
 882                        SMC_outw(lp, x, ioaddr, PN_REG(lp));            \
 883        } while (0)
 884
 885#define SMC_GET_AR(lp)                                          \
 886        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, AR_REG(lp))) \
 887                                : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
 888
 889#define SMC_GET_TXFIFO(lp)                                              \
 890        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, TXFIFO_REG(lp)))     \
 891                                : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
 892
 893#define SMC_GET_RXFIFO(lp)                                              \
 894        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, RXFIFO_REG(lp)))     \
 895                                : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
 896
 897#define SMC_GET_INT(lp)                                         \
 898        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, INT_REG(lp)))        \
 899                                : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
 900
 901#define SMC_ACK_INT(lp, x)                                              \
 902        do {                                                            \
 903                if (SMC_8BIT(lp))                                       \
 904                        SMC_outb(x, ioaddr, INT_REG(lp));               \
 905                else {                                                  \
 906                        unsigned long __flags;                          \
 907                        int __mask;                                     \
 908                        local_irq_save(__flags);                        \
 909                        __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
 910                        SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
 911                        local_irq_restore(__flags);                     \
 912                }                                                       \
 913        } while (0)
 914
 915#define SMC_GET_INT_MASK(lp)                                            \
 916        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, IM_REG(lp))) \
 917                                : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
 918
 919#define SMC_SET_INT_MASK(lp, x)                                 \
 920        do {                                                            \
 921                if (SMC_8BIT(lp))                                       \
 922                        SMC_outb(x, ioaddr, IM_REG(lp));                \
 923                else                                                    \
 924                        SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp));    \
 925        } while (0)
 926
 927#define SMC_CURRENT_BANK(lp)    SMC_inw(ioaddr, BANK_SELECT)
 928
 929#define SMC_SELECT_BANK(lp, x)                                  \
 930        do {                                                            \
 931                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 932                        SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);    \
 933                else                                                    \
 934                        SMC_outw(lp, x, ioaddr, BANK_SELECT);           \
 935        } while (0)
 936
 937#define SMC_GET_BASE(lp)                SMC_inw(ioaddr, BASE_REG(lp))
 938
 939#define SMC_SET_BASE(lp, x)     SMC_outw(lp, x, ioaddr, BASE_REG(lp))
 940
 941#define SMC_GET_CONFIG(lp)      SMC_inw(ioaddr, CONFIG_REG(lp))
 942
 943#define SMC_SET_CONFIG(lp, x)   SMC_outw(lp, x, ioaddr, CONFIG_REG(lp))
 944
 945#define SMC_GET_COUNTER(lp)     SMC_inw(ioaddr, COUNTER_REG(lp))
 946
 947#define SMC_GET_CTL(lp)         SMC_inw(ioaddr, CTL_REG(lp))
 948
 949#define SMC_SET_CTL(lp, x)      SMC_outw(lp, x, ioaddr, CTL_REG(lp))
 950
 951#define SMC_GET_MII(lp)         SMC_inw(ioaddr, MII_REG(lp))
 952
 953#define SMC_GET_GP(lp)          SMC_inw(ioaddr, GP_REG(lp))
 954
 955#define SMC_SET_GP(lp, x)                                               \
 956        do {                                                            \
 957                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 958                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));   \
 959                else                                                    \
 960                        SMC_outw(lp, x, ioaddr, GP_REG(lp));            \
 961        } while (0)
 962
 963#define SMC_SET_MII(lp, x)      SMC_outw(lp, x, ioaddr, MII_REG(lp))
 964
 965#define SMC_GET_MIR(lp)         SMC_inw(ioaddr, MIR_REG(lp))
 966
 967#define SMC_SET_MIR(lp, x)      SMC_outw(lp, x, ioaddr, MIR_REG(lp))
 968
 969#define SMC_GET_MMU_CMD(lp)     SMC_inw(ioaddr, MMU_CMD_REG(lp))
 970
 971#define SMC_SET_MMU_CMD(lp, x)  SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp))
 972
 973#define SMC_GET_FIFO(lp)        SMC_inw(ioaddr, FIFO_REG(lp))
 974
 975#define SMC_GET_PTR(lp)         SMC_inw(ioaddr, PTR_REG(lp))
 976
 977#define SMC_SET_PTR(lp, x)                                              \
 978        do {                                                            \
 979                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 980                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));   \
 981                else                                                    \
 982                        SMC_outw(lp, x, ioaddr, PTR_REG(lp));           \
 983        } while (0)
 984
 985#define SMC_GET_EPH_STATUS(lp)  SMC_inw(ioaddr, EPH_STATUS_REG(lp))
 986
 987#define SMC_GET_RCR(lp)         SMC_inw(ioaddr, RCR_REG(lp))
 988
 989#define SMC_SET_RCR(lp, x)              SMC_outw(lp, x, ioaddr, RCR_REG(lp))
 990
 991#define SMC_GET_REV(lp)         SMC_inw(ioaddr, REV_REG(lp))
 992
 993#define SMC_GET_RPC(lp)         SMC_inw(ioaddr, RPC_REG(lp))
 994
 995#define SMC_SET_RPC(lp, x)                                              \
 996        do {                                                            \
 997                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 998                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));   \
 999                else                                                    \
1000                        SMC_outw(lp, x, ioaddr, RPC_REG(lp));           \

1001        } while (0)
1002
1003#define SMC_GET_TCR(lp)         SMC_inw(ioaddr, TCR_REG(lp))
1004
1005#define SMC_SET_TCR(lp, x)      SMC_outw(lp, x, ioaddr, TCR_REG(lp))
1006
1007#ifndef SMC_GET_MAC_ADDR
1008#define SMC_GET_MAC_ADDR(lp, addr)                                      \
1009        do {                                                            \
1010                unsigned int __v;                                       \
1011                __v = SMC_inw(ioaddr, ADDR0_REG(lp));                   \
1012                addr[0] = __v; addr[1] = __v >> 8;                      \
1013                __v = SMC_inw(ioaddr, ADDR1_REG(lp));                   \
1014                addr[2] = __v; addr[3] = __v >> 8;                      \
1015                __v = SMC_inw(ioaddr, ADDR2_REG(lp));                   \
1016                addr[4] = __v; addr[5] = __v >> 8;                      \
1017        } while (0)
1018#endif
1019
1020#define SMC_SET_MAC_ADDR(lp, addr)                                      \
1021        do {                                                            \
1022                SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1023                SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1024                SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1025        } while (0)
1026
1027#define SMC_SET_MCAST(lp, x)                                            \
1028        do {                                                            \
1029                const unsigned char *mt = (x);                          \
1030                SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1031                SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1032                SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1033                SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1034        } while (0)
1035
1036#define SMC_PUT_PKT_HDR(lp, status, length)                             \
1037        do {                                                            \
1038                if (SMC_32BIT(lp))                                      \
1039                        SMC_outl((status) | (length)<<16, ioaddr,       \
1040                                 DATA_REG(lp));                 \
1041                else {                                                  \
1042                        SMC_outw(lp, status, ioaddr, DATA_REG(lp));     \
1043                        SMC_outw(lp, length, ioaddr, DATA_REG(lp));     \
1044                }                                                       \
1045        } while (0)
1046
1047#define SMC_GET_PKT_HDR(lp, status, length)                             \
1048        do {                                                            \
1049                if (SMC_32BIT(lp)) {                            \
1050                        unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1051                        (status) = __val & 0xffff;                      \
1052                        (length) = __val >> 16;                         \
1053                } else {                                                \
1054                        (status) = SMC_inw(ioaddr, DATA_REG(lp));       \
1055                        (length) = SMC_inw(ioaddr, DATA_REG(lp));       \
1056                }                                                       \
1057        } while (0)
1058
1059#define SMC_PUSH_DATA(lp, p, l)                                 \
1060        do {                                                            \
1061                if (SMC_32BIT(lp)) {                            \
1062                        void *__ptr = (p);                              \
1063                        int __len = (l);                                \
1064                        void __iomem *__ioaddr = ioaddr;                \
1065                        if (__len >= 2 && (unsigned long)__ptr & 2) {   \
1066                                __len -= 2;                             \
1067                                SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1068                                __ptr += 2;                             \
1069                        }                                               \
1070                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
1071                                __ioaddr = lp->datacs;                  \
1072                        SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1073                        if (__len & 2) {                                \
1074                                __ptr += (__len & ~3);                  \
1075                                SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1076                        }                                               \
1077                } else if (SMC_16BIT(lp))                               \
1078                        SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);   \
1079                else if (SMC_8BIT(lp))                          \
1080                        SMC_outsb(ioaddr, DATA_REG(lp), p, l);  \
1081        } while (0)
1082
1083#define SMC_PULL_DATA(lp, p, l)                                 \
1084        do {                                                            \
1085                if (SMC_32BIT(lp)) {                            \
1086                        void *__ptr = (p);                              \
1087                        int __len = (l);                                \
1088                        void __iomem *__ioaddr = ioaddr;                \
1089                        if ((unsigned long)__ptr & 2) {                 \
1090                                /*                                      \
1091                                 * We want 32bit alignment here.        \
1092                                 * Since some buses perform a full      \
1093                                 * 32bit fetch even for 16bit data      \
1094                                 * we can't use SMC_inw() here.         \
1095                                 * Back both source (on-chip) and       \
1096                                 * destination pointers of 2 bytes.     \
1097                                 * This is possible since the call to   \
1098                                 * SMC_GET_PKT_HDR() already advanced   \
1099                                 * the source pointer of 4 bytes, and   \
1100                                 * the skb_reserve(skb, 2) advanced     \
1101                                 * the destination pointer of 2 bytes.  \
1102                                 */                                     \
1103                                __ptr -= 2;                             \
1104                                __len += 2;                             \
1105                                SMC_SET_PTR(lp,                 \
1106                                        2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1107                        }                                               \
1108                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
1109                                __ioaddr = lp->datacs;                  \
1110                        __len += 2;                                     \
1111                        SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1112                } else if (SMC_16BIT(lp))                               \
1113                        SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);    \
1114                else if (SMC_8BIT(lp))                          \
1115                        SMC_insb(ioaddr, DATA_REG(lp), p, l);           \
1116        } while (0)
1117
1118#endif  /* _SMC91X_H_ */
1119