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9#ifndef __STMMAC_H__
10#define __STMMAC_H__
11
12#define STMMAC_RESOURCE_NAME "stmmaceth"
13#define DRV_MODULE_VERSION "Jan_2016"
14
15#include <linux/clk.h>
16#include <linux/stmmac.h>
17#include <linux/phylink.h>
18#include <linux/pci.h>
19#include "common.h"
20#include <linux/ptp_clock_kernel.h>
21#include <linux/net_tstamp.h>
22#include <linux/reset.h>
23#include <net/page_pool.h>
24
25struct stmmac_resources {
26 void __iomem *addr;
27 const char *mac;
28 int wol_irq;
29 int lpi_irq;
30 int irq;
31};
32
33struct stmmac_tx_info {
34 dma_addr_t buf;
35 bool map_as_page;
36 unsigned len;
37 bool last_segment;
38 bool is_jumbo;
39};
40
41
42struct stmmac_tx_queue {
43 u32 tx_count_frames;
44 struct timer_list txtimer;
45 u32 queue_index;
46 struct stmmac_priv *priv_data;
47 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
48 struct dma_desc *dma_tx;
49 struct sk_buff **tx_skbuff;
50 struct stmmac_tx_info *tx_skbuff_dma;
51 unsigned int cur_tx;
52 unsigned int dirty_tx;
53 dma_addr_t dma_tx_phy;
54 u32 tx_tail_addr;
55 u32 mss;
56};
57
58struct stmmac_rx_buffer {
59 struct page *page;
60 dma_addr_t addr;
61};
62
63struct stmmac_rx_queue {
64 u32 rx_count_frames;
65 u32 queue_index;
66 struct page_pool *page_pool;
67 struct stmmac_rx_buffer *buf_pool;
68 struct stmmac_priv *priv_data;
69 struct dma_extended_desc *dma_erx;
70 struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
71 unsigned int cur_rx;
72 unsigned int dirty_rx;
73 u32 rx_zeroc_thresh;
74 dma_addr_t dma_rx_phy;
75 u32 rx_tail_addr;
76};
77
78struct stmmac_channel {
79 struct napi_struct rx_napi ____cacheline_aligned_in_smp;
80 struct napi_struct tx_napi ____cacheline_aligned_in_smp;
81 struct stmmac_priv *priv_data;
82 u32 index;
83};
84
85struct stmmac_tc_entry {
86 bool in_use;
87 bool in_hw;
88 bool is_last;
89 bool is_frag;
90 void *frag_ptr;
91 unsigned int table_pos;
92 u32 handle;
93 u32 prio;
94 struct {
95 u32 match_data;
96 u32 match_en;
97 u8 af:1;
98 u8 rf:1;
99 u8 im:1;
100 u8 nc:1;
101 u8 res1:4;
102 u8 frame_offset;
103 u8 ok_index;
104 u8 dma_ch_no;
105 u32 res2;
106 } __packed val;
107};
108
109#define STMMAC_PPS_MAX 4
110struct stmmac_pps_cfg {
111 bool available;
112 struct timespec64 start;
113 struct timespec64 period;
114};
115
116struct stmmac_priv {
117
118 u32 tx_coal_frames;
119 u32 tx_coal_timer;
120 u32 rx_coal_frames;
121
122 int tx_coalesce;
123 int hwts_tx_en;
124 bool tx_path_in_lpi_mode;
125 bool tso;
126
127 unsigned int dma_buf_sz;
128 unsigned int rx_copybreak;
129 u32 rx_riwt;
130 int hwts_rx_en;
131
132 void __iomem *ioaddr;
133 struct net_device *dev;
134 struct device *device;
135 struct mac_device_info *hw;
136 int (*hwif_quirks)(struct stmmac_priv *priv);
137 struct mutex lock;
138
139
140 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
141
142
143 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
144
145
146 struct stmmac_channel channel[STMMAC_CH_MAX];
147
148 int speed;
149 unsigned int flow_ctrl;
150 unsigned int pause;
151 struct mii_bus *mii;
152 int mii_irq[PHY_MAX_ADDR];
153
154 struct phylink_config phylink_config;
155 struct phylink *phylink;
156
157 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
158 struct stmmac_safety_stats sstats;
159 struct plat_stmmacenet_data *plat;
160 struct dma_features dma_cap;
161 struct stmmac_counters mmc;
162 int hw_cap_support;
163 int synopsys_id;
164 u32 msg_enable;
165 int wolopts;
166 int wol_irq;
167 int clk_csr;
168 struct timer_list eee_ctrl_timer;
169 int lpi_irq;
170 int eee_enabled;
171 int eee_active;
172 int tx_lpi_timer;
173 unsigned int mode;
174 unsigned int chain_mode;
175 int extend_desc;
176 struct hwtstamp_config tstamp_config;
177 struct ptp_clock *ptp_clock;
178 struct ptp_clock_info ptp_clock_ops;
179 unsigned int default_addend;
180 u32 sub_second_inc;
181 u32 systime_flags;
182 u32 adv_ts;
183 int use_riwt;
184 int irq_wake;
185 spinlock_t ptp_lock;
186 void __iomem *mmcaddr;
187 void __iomem *ptpaddr;
188
189#ifdef CONFIG_DEBUG_FS
190 struct dentry *dbgfs_dir;
191 struct dentry *dbgfs_rings_status;
192 struct dentry *dbgfs_dma_cap;
193#endif
194
195 unsigned long state;
196 struct workqueue_struct *wq;
197 struct work_struct service_task;
198
199
200 unsigned int tc_entries_max;
201 unsigned int tc_off_max;
202 struct stmmac_tc_entry *tc_entries;
203
204
205 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
206};
207
208enum stmmac_state {
209 STMMAC_DOWN,
210 STMMAC_RESET_REQUESTED,
211 STMMAC_RESETING,
212 STMMAC_SERVICE_SCHED,
213};
214
215int stmmac_mdio_unregister(struct net_device *ndev);
216int stmmac_mdio_register(struct net_device *ndev);
217int stmmac_mdio_reset(struct mii_bus *mii);
218void stmmac_set_ethtool_ops(struct net_device *netdev);
219
220void stmmac_ptp_register(struct stmmac_priv *priv);
221void stmmac_ptp_unregister(struct stmmac_priv *priv);
222int stmmac_resume(struct device *dev);
223int stmmac_suspend(struct device *dev);
224int stmmac_dvr_remove(struct device *dev);
225int stmmac_dvr_probe(struct device *device,
226 struct plat_stmmacenet_data *plat_dat,
227 struct stmmac_resources *res);
228void stmmac_disable_eee_mode(struct stmmac_priv *priv);
229bool stmmac_eee_init(struct stmmac_priv *priv);
230
231#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
232void stmmac_selftest_run(struct net_device *dev,
233 struct ethtool_test *etest, u64 *buf);
234void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
235int stmmac_selftest_get_count(struct stmmac_priv *priv);
236#else
237static inline void stmmac_selftest_run(struct net_device *dev,
238 struct ethtool_test *etest, u64 *buf)
239{
240
241}
242static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
243 u8 *data)
244{
245
246}
247static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
248{
249 return -EOPNOTSUPP;
250}
251#endif
252
253#endif
254
