LXR linux/drivers/net/usb/asix.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * ASIX AX8817X based USB 2.0 Ethernet Devices
   4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
   5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
   6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
   7 * Copyright (c) 2002-2003 TiVo Inc.
   8 */
   9
  10#ifndef _ASIX_H
  11#define _ASIX_H
  12
  13// #define      DEBUG                   // error path messages, extra info
  14// #define      VERBOSE                 // more; success messages
  15
  16#include <linux/module.h>
  17#include <linux/kmod.h>
  18#include <linux/netdevice.h>
  19#include <linux/etherdevice.h>
  20#include <linux/ethtool.h>
  21#include <linux/workqueue.h>
  22#include <linux/mii.h>
  23#include <linux/usb.h>
  24#include <linux/crc32.h>
  25#include <linux/usb/usbnet.h>
  26#include <linux/slab.h>
  27#include <linux/if_vlan.h>
  28
  29#define DRIVER_VERSION "22-Dec-2011"
  30#define DRIVER_NAME "asix"
  31
  32/* ASIX AX8817X based USB 2.0 Ethernet Devices */
  33
  34#define AX_CMD_SET_SW_MII               0x06
  35#define AX_CMD_READ_MII_REG             0x07
  36#define AX_CMD_WRITE_MII_REG            0x08
  37#define AX_CMD_STATMNGSTS_REG           0x09
  38#define AX_CMD_SET_HW_MII               0x0a
  39#define AX_CMD_READ_EEPROM              0x0b
  40#define AX_CMD_WRITE_EEPROM             0x0c
  41#define AX_CMD_WRITE_ENABLE             0x0d
  42#define AX_CMD_WRITE_DISABLE            0x0e
  43#define AX_CMD_READ_RX_CTL              0x0f
  44#define AX_CMD_WRITE_RX_CTL             0x10
  45#define AX_CMD_READ_IPG012              0x11
  46#define AX_CMD_WRITE_IPG0               0x12
  47#define AX_CMD_WRITE_IPG1               0x13
  48#define AX_CMD_READ_NODE_ID             0x13
  49#define AX_CMD_WRITE_NODE_ID            0x14
  50#define AX_CMD_WRITE_IPG2               0x14
  51#define AX_CMD_WRITE_MULTI_FILTER       0x16
  52#define AX88172_CMD_READ_NODE_ID        0x17
  53#define AX_CMD_READ_PHY_ID              0x19
  54#define AX_CMD_READ_MEDIUM_STATUS       0x1a
  55#define AX_CMD_WRITE_MEDIUM_MODE        0x1b
  56#define AX_CMD_READ_MONITOR_MODE        0x1c
  57#define AX_CMD_WRITE_MONITOR_MODE       0x1d
  58#define AX_CMD_READ_GPIOS               0x1e
  59#define AX_CMD_WRITE_GPIOS              0x1f
  60#define AX_CMD_SW_RESET                 0x20
  61#define AX_CMD_SW_PHY_STATUS            0x21
  62#define AX_CMD_SW_PHY_SELECT            0x22
  63#define AX_QCTCTRL                      0x2A
  64
  65#define AX_CHIPCODE_MASK                0x70
  66#define AX_AX88772_CHIPCODE             0x00
  67#define AX_AX88772A_CHIPCODE            0x10
  68#define AX_AX88772B_CHIPCODE            0x20
  69#define AX_HOST_EN                      0x01
  70
  71#define AX_PHYSEL_PSEL                  0x01
  72#define AX_PHYSEL_SSMII                 0
  73#define AX_PHYSEL_SSEN                  0x10
  74
  75#define AX_PHY_SELECT_MASK              (BIT(3) | BIT(2))
  76#define AX_PHY_SELECT_INTERNAL          0
  77#define AX_PHY_SELECT_EXTERNAL          BIT(2)
  78
  79#define AX_MONITOR_MODE                 0x01
  80#define AX_MONITOR_LINK                 0x02
  81#define AX_MONITOR_MAGIC                0x04
  82#define AX_MONITOR_HSFS                 0x10
  83
  84/* AX88172 Medium Status Register values */
  85#define AX88172_MEDIUM_FD               0x02
  86#define AX88172_MEDIUM_TX               0x04
  87#define AX88172_MEDIUM_FC               0x10
  88#define AX88172_MEDIUM_DEFAULT \
  89                ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
  90
  91#define AX_MCAST_FILTER_SIZE            8
  92#define AX_MAX_MCAST                    64
  93
  94#define AX_SWRESET_CLEAR                0x00
  95#define AX_SWRESET_RR                   0x01
  96#define AX_SWRESET_RT                   0x02
  97#define AX_SWRESET_PRTE                 0x04
  98#define AX_SWRESET_PRL                  0x08
  99#define AX_SWRESET_BZ                   0x10
 100#define AX_SWRESET_IPRL                 0x20
 101#define AX_SWRESET_IPPD                 0x40
 102
 103#define AX88772_IPG0_DEFAULT            0x15
 104#define AX88772_IPG1_DEFAULT            0x0c
 105#define AX88772_IPG2_DEFAULT            0x12
 106
 107/* AX88772 & AX88178 Medium Mode Register */
 108#define AX_MEDIUM_PF            0x0080
 109#define AX_MEDIUM_JFE           0x0040
 110#define AX_MEDIUM_TFC           0x0020
 111#define AX_MEDIUM_RFC           0x0010
 112#define AX_MEDIUM_ENCK          0x0008
 113#define AX_MEDIUM_AC            0x0004
 114#define AX_MEDIUM_FD            0x0002
 115#define AX_MEDIUM_GM            0x0001
 116#define AX_MEDIUM_SM            0x1000
 117#define AX_MEDIUM_SBP           0x0800
 118#define AX_MEDIUM_PS            0x0200
 119#define AX_MEDIUM_RE            0x0100
 120
 121#define AX88178_MEDIUM_DEFAULT  \
 122        (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
 123         AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
 124         AX_MEDIUM_RE)
 125
 126#define AX88772_MEDIUM_DEFAULT  \
 127        (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
 128         AX_MEDIUM_TFC | AX_MEDIUM_PS | \
 129         AX_MEDIUM_AC | AX_MEDIUM_RE)
 130
 131/* AX88772 & AX88178 RX_CTL values */
 132#define AX_RX_CTL_SO            0x0080
 133#define AX_RX_CTL_AP            0x0020
 134#define AX_RX_CTL_AM            0x0010
 135#define AX_RX_CTL_AB            0x0008
 136#define AX_RX_CTL_SEP           0x0004
 137#define AX_RX_CTL_AMALL         0x0002
 138#define AX_RX_CTL_PRO           0x0001
 139#define AX_RX_CTL_MFB_2048      0x0000
 140#define AX_RX_CTL_MFB_4096      0x0100
 141#define AX_RX_CTL_MFB_8192      0x0200
 142#define AX_RX_CTL_MFB_16384     0x0300
 143
 144#define AX_DEFAULT_RX_CTL       (AX_RX_CTL_SO | AX_RX_CTL_AB)
 145
 146/* GPIO 0 .. 2 toggles */
 147#define AX_GPIO_GPO0EN          0x01    /* GPIO0 Output enable */
 148#define AX_GPIO_GPO_0           0x02    /* GPIO0 Output value */
 149#define AX_GPIO_GPO1EN          0x04    /* GPIO1 Output enable */
 150#define AX_GPIO_GPO_1           0x08    /* GPIO1 Output value */
 151#define AX_GPIO_GPO2EN          0x10    /* GPIO2 Output enable */
 152#define AX_GPIO_GPO_2           0x20    /* GPIO2 Output value */
 153#define AX_GPIO_RESERVED        0x40    /* Reserved */
 154#define AX_GPIO_RSE             0x80    /* Reload serial EEPROM */
 155
 156#define AX_EEPROM_MAGIC         0xdeadbeef
 157#define AX_EEPROM_LEN           0x200
 158
 159/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
 160struct asix_data {
 161        u8 multi_filter[AX_MCAST_FILTER_SIZE];
 162        u8 mac_addr[ETH_ALEN];
 163        u8 phymode;
 164        u8 ledmode;
 165        u8 res;
 166};
 167
 168struct asix_rx_fixup_info {
 169        struct sk_buff *ax_skb;
 170        u32 header;
 171        u16 remaining;
 172        bool split_head;
 173};
 174
 175struct asix_common_private {
 176        void (*resume)(struct usbnet *dev);
 177        void (*suspend)(struct usbnet *dev);
 178        u16 presvd_phy_advertise;
 179        u16 presvd_phy_bmcr;
 180        struct asix_rx_fixup_info rx_fixup_info;
 181};
 182
 183extern const struct driver_info ax88172a_info;
 184
 185/* ASIX specific flags */
 186#define FLAG_EEPROM_MAC         (1UL << 0)  /* init device MAC from eeprom */
 187
 188int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
 189                  u16 size, void *data, int in_pm);
 190
 191int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
 192                   u16 size, void *data, int in_pm);
 193
 194void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
 195                          u16 index, u16 size, void *data);
 196
 197int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb,
 198                           struct asix_rx_fixup_info *rx);
 199int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb);
 200void asix_rx_fixup_common_free(struct asix_common_private *dp);
 201
 202struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
 203                              gfp_t flags);
 204
 205int asix_set_sw_mii(struct usbnet *dev, int in_pm);
 206int asix_set_hw_mii(struct usbnet *dev, int in_pm);
 207
 208int asix_read_phy_addr(struct usbnet *dev, int internal);
 209int asix_get_phy_addr(struct usbnet *dev);
 210
 211int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm);
 212
 213u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm);
 214int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm);
 215
 216u16 asix_read_medium_status(struct usbnet *dev, int in_pm);
 217int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm);
 218
 219int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm);
 220
 221void asix_set_multicast(struct net_device *net);
 222
 223int asix_mdio_read(struct net_device *netdev, int phy_id, int loc);
 224void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val);
 225
 226int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc);
 227void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc,
 228                          int val);
 229
 230void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
 231int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
 232
 233int asix_get_eeprom_len(struct net_device *net);
 234int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
 235                    u8 *data);
 236int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
 237                    u8 *data);
 238
 239void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info);
 240
 241int asix_set_mac_address(struct net_device *net, void *p);
 242
 243#endif /* _ASIX_H */
 244