1
2
3
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/list.h>
8#include <linux/ssb/ssb_regs.h>
9#include <linux/bcma/bcma.h>
10#include <linux/bcma/bcma_regs.h>
11
12#include <defs.h>
13#include <soc.h>
14#include <brcm_hw_ids.h>
15#include <brcmu_utils.h>
16#include <chipcommon.h>
17#include "debug.h"
18#include "chip.h"
19
20
21#define SOCI_SB 0
22#define SOCI_AI 1
23
24
25#define DMP_DESC_TYPE_MSK 0x0000000F
26#define DMP_DESC_EMPTY 0x00000000
27#define DMP_DESC_VALID 0x00000001
28#define DMP_DESC_COMPONENT 0x00000001
29#define DMP_DESC_MASTER_PORT 0x00000003
30#define DMP_DESC_ADDRESS 0x00000005
31#define DMP_DESC_ADDRSIZE_GT32 0x00000008
32#define DMP_DESC_EOT 0x0000000F
33
34#define DMP_COMP_DESIGNER 0xFFF00000
35#define DMP_COMP_DESIGNER_S 20
36#define DMP_COMP_PARTNUM 0x000FFF00
37#define DMP_COMP_PARTNUM_S 8
38#define DMP_COMP_CLASS 0x000000F0
39#define DMP_COMP_CLASS_S 4
40#define DMP_COMP_REVISION 0xFF000000
41#define DMP_COMP_REVISION_S 24
42#define DMP_COMP_NUM_SWRAP 0x00F80000
43#define DMP_COMP_NUM_SWRAP_S 19
44#define DMP_COMP_NUM_MWRAP 0x0007C000
45#define DMP_COMP_NUM_MWRAP_S 14
46#define DMP_COMP_NUM_SPORT 0x00003E00
47#define DMP_COMP_NUM_SPORT_S 9
48#define DMP_COMP_NUM_MPORT 0x000001F0
49#define DMP_COMP_NUM_MPORT_S 4
50
51#define DMP_MASTER_PORT_UID 0x0000FF00
52#define DMP_MASTER_PORT_UID_S 8
53#define DMP_MASTER_PORT_NUM 0x000000F0
54#define DMP_MASTER_PORT_NUM_S 4
55
56#define DMP_SLAVE_ADDR_BASE 0xFFFFF000
57#define DMP_SLAVE_ADDR_BASE_S 12
58#define DMP_SLAVE_PORT_NUM 0x00000F00
59#define DMP_SLAVE_PORT_NUM_S 8
60#define DMP_SLAVE_TYPE 0x000000C0
61#define DMP_SLAVE_TYPE_S 6
62#define DMP_SLAVE_TYPE_SLAVE 0
63#define DMP_SLAVE_TYPE_BRIDGE 1
64#define DMP_SLAVE_TYPE_SWRAP 2
65#define DMP_SLAVE_TYPE_MWRAP 3
66#define DMP_SLAVE_SIZE_TYPE 0x00000030
67#define DMP_SLAVE_SIZE_TYPE_S 4
68#define DMP_SLAVE_SIZE_4K 0
69#define DMP_SLAVE_SIZE_8K 1
70#define DMP_SLAVE_SIZE_16K 2
71#define DMP_SLAVE_SIZE_DESC 3
72
73
74#define CIB_REV_MASK 0xff000000
75#define CIB_REV_SHIFT 24
76
77
78#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
79
80
81#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
82#define D11_BCMA_IOCTL_PHYRESET 0x0008
83
84
85
86
87#define BCM4329_CORE_BUS_BASE 0x18011000
88
89#define BCM4329_CORE_SOCRAM_BASE 0x18003000
90
91#define BCM4329_CORE_ARM_BASE 0x18002000
92
93
94#define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
95
96#define CORE_SB(base, field) \
97 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
98#define SBCOREREV(sbidh) \
99 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
100 ((sbidh) & SSB_IDHIGH_RCLO))
101
102struct sbconfig {
103 u32 PAD[2];
104 u32 sbipsflag;
105 u32 PAD[3];
106 u32 sbtpsflag;
107 u32 PAD[11];
108 u32 sbtmerrloga;
109 u32 PAD;
110 u32 sbtmerrlog;
111 u32 PAD[3];
112 u32 sbadmatch3;
113 u32 PAD;
114 u32 sbadmatch2;
115 u32 PAD;
116 u32 sbadmatch1;
117 u32 PAD[7];
118 u32 sbimstate;
119 u32 sbintvec;
120 u32 sbtmstatelow;
121 u32 sbtmstatehigh;
122 u32 sbbwa0;
123 u32 PAD;
124 u32 sbimconfiglow;
125 u32 sbimconfighigh;
126 u32 sbadmatch0;
127 u32 PAD;
128 u32 sbtmconfiglow;
129 u32 sbtmconfighigh;
130 u32 sbbconfig;
131 u32 PAD;
132 u32 sbbstate;
133 u32 PAD[3];
134 u32 sbactcnfg;
135 u32 PAD[3];
136 u32 sbflagst;
137 u32 PAD[3];
138 u32 sbidlow;
139 u32 sbidhigh;
140};
141
142
143#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
144#define SOCRAM_BANKINFO_SZMASK 0x0000007f
145#define SOCRAM_BANKIDX_ROM_MASK 0x00000100
146
147#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
148
149#define SOCRAM_MEMTYPE_RAM 0
150#define SOCRAM_MEMTYPE_R0M 1
151#define SOCRAM_MEMTYPE_DEVRAM 2
152
153#define SOCRAM_BANKINFO_SZBASE 8192
154#define SRCI_LSS_MASK 0x00f00000
155#define SRCI_LSS_SHIFT 20
156#define SRCI_SRNB_MASK 0xf0
157#define SRCI_SRNB_MASK_EXT 0x100
158#define SRCI_SRNB_SHIFT 4
159#define SRCI_SRBSZ_MASK 0xf
160#define SRCI_SRBSZ_SHIFT 0
161#define SR_BSZ_BASE 14
162
163struct sbsocramregs {
164 u32 coreinfo;
165 u32 bwalloc;
166 u32 extracoreinfo;
167 u32 biststat;
168 u32 bankidx;
169 u32 standbyctrl;
170
171 u32 errlogstatus;
172 u32 errlogaddr;
173
174 u32 cambankidx;
175 u32 cambankstandbyctrl;
176 u32 cambankpatchctrl;
177 u32 cambankpatchtblbaseaddr;
178 u32 cambankcmdreg;
179 u32 cambankdatareg;
180 u32 cambankmaskreg;
181 u32 PAD[1];
182 u32 bankinfo;
183 u32 bankpda;
184 u32 PAD[14];
185 u32 extmemconfig;
186 u32 extmemparitycsr;
187 u32 extmemparityerrdata;
188 u32 extmemparityerrcnt;
189 u32 extmemwrctrlandsize;
190 u32 PAD[84];
191 u32 workaround;
192 u32 pwrctl;
193 u32 PAD[133];
194 u32 sr_control;
195 u32 sr_status;
196 u32 sr_address;
197 u32 sr_data;
198};
199
200#define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
201#define SYSMEMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
202
203#define ARMCR4_CAP (0x04)
204#define ARMCR4_BANKIDX (0x40)
205#define ARMCR4_BANKINFO (0x44)
206#define ARMCR4_BANKPDA (0x4C)
207
208#define ARMCR4_TCBBNB_MASK 0xf0
209#define ARMCR4_TCBBNB_SHIFT 4
210#define ARMCR4_TCBANB_MASK 0xf
211#define ARMCR4_TCBANB_SHIFT 0
212
213#define ARMCR4_BSZ_MASK 0x3f
214#define ARMCR4_BSZ_MULT 8192
215
216struct brcmf_core_priv {
217 struct brcmf_core pub;
218 u32 wrapbase;
219 struct list_head list;
220 struct brcmf_chip_priv *chip;
221};
222
223struct brcmf_chip_priv {
224 struct brcmf_chip pub;
225 const struct brcmf_buscore_ops *ops;
226 void *ctx;
227
228 struct list_head cores;
229 u16 num_cores;
230
231 bool (*iscoreup)(struct brcmf_core_priv *core);
232 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
233 u32 reset);
234 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
235 u32 postreset);
236};
237
238static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
239 struct brcmf_core *core)
240{
241 u32 regdata;
242
243 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
244 core->rev = SBCOREREV(regdata);
245}
246
247static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
248{
249 struct brcmf_chip_priv *ci;
250 u32 regdata;
251 u32 address;
252
253 ci = core->chip;
254 address = CORE_SB(core->pub.base, sbtmstatelow);
255 regdata = ci->ops->read32(ci->ctx, address);
256 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
257 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
258 return SSB_TMSLOW_CLOCK == regdata;
259}
260
261static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
262{
263 struct brcmf_chip_priv *ci;
264 u32 regdata;
265 bool ret;
266
267 ci = core->chip;
268 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
269 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
270
271 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
272 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
273
274 return ret;
275}
276
277static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
278 u32 prereset, u32 reset)
279{
280 struct brcmf_chip_priv *ci;
281 u32 val, base;
282
283 ci = core->chip;
284 base = core->pub.base;
285 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
286 if (val & SSB_TMSLOW_RESET)
287 return;
288
289 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
290 if ((val & SSB_TMSLOW_CLOCK) != 0) {
291
292
293
294
295 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
296 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
297 val | SSB_TMSLOW_REJECT);
298
299 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
300 udelay(1);
301 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
302 & SSB_TMSHIGH_BUSY), 100000);
303
304 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
305 if (val & SSB_TMSHIGH_BUSY)
306 brcmf_err("core state still busy\n");
307
308 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
309 if (val & SSB_IDLOW_INITIATOR) {
310 val = ci->ops->read32(ci->ctx,
311 CORE_SB(base, sbimstate));
312 val |= SSB_IMSTATE_REJECT;
313 ci->ops->write32(ci->ctx,
314 CORE_SB(base, sbimstate), val);
315 val = ci->ops->read32(ci->ctx,
316 CORE_SB(base, sbimstate));
317 udelay(1);
318 SPINWAIT((ci->ops->read32(ci->ctx,
319 CORE_SB(base, sbimstate)) &
320 SSB_IMSTATE_BUSY), 100000);
321 }
322
323
324 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
325 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
326 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
327 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
328 udelay(10);
329
330
331 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
332 if (val & SSB_IDLOW_INITIATOR) {
333 val = ci->ops->read32(ci->ctx,
334 CORE_SB(base, sbimstate));
335 val &= ~SSB_IMSTATE_REJECT;
336 ci->ops->write32(ci->ctx,
337 CORE_SB(base, sbimstate), val);
338 }
339 }
340
341
342 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
343 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
344 udelay(1);
345}
346
347static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
348 u32 prereset, u32 reset)
349{
350 struct brcmf_chip_priv *ci;
351 u32 regdata;
352
353 ci = core->chip;
354
355
356 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
357 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
358 goto in_reset_configure;
359
360
361 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
362 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
363 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
364
365
366 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
367 BCMA_RESET_CTL_RESET);
368 usleep_range(10, 20);
369
370
371 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
372 BCMA_RESET_CTL_RESET, 300);
373
374in_reset_configure:
375
376 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
377 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
378 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
379}
380
381static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
382 u32 reset, u32 postreset)
383{
384 struct brcmf_chip_priv *ci;
385 u32 regdata;
386 u32 base;
387
388 ci = core->chip;
389 base = core->pub.base;
390
391
392
393
394 brcmf_chip_sb_coredisable(core, 0, 0);
395
396
397
398
399
400
401 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
402 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
403 SSB_TMSLOW_RESET);
404 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
405 udelay(1);
406
407
408 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
409 if (regdata & SSB_TMSHIGH_SERR)
410 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
411
412 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
413 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
414 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
415 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
416 }
417
418
419 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
420 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
421 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
422 udelay(1);
423
424
425 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
426 SSB_TMSLOW_CLOCK);
427 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
428 udelay(1);
429}
430
431static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
432 u32 reset, u32 postreset)
433{
434 struct brcmf_chip_priv *ci;
435 int count;
436
437 ci = core->chip;
438
439
440 brcmf_chip_ai_coredisable(core, prereset, reset);
441
442 count = 0;
443 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
444 BCMA_RESET_CTL_RESET) {
445 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
446 count++;
447 if (count > 50)
448 break;
449 usleep_range(40, 60);
450 }
451
452 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
453 postreset | BCMA_IOCTL_CLK);
454 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
455}
456
457char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len)
458{
459 const char *fmt;
460
461 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u";
462 snprintf(buf, len, fmt, id, rev);
463 return buf;
464}
465
466static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
467 u16 coreid, u32 base,
468 u32 wrapbase)
469{
470 struct brcmf_core_priv *core;
471
472 core = kzalloc(sizeof(*core), GFP_KERNEL);
473 if (!core)
474 return ERR_PTR(-ENOMEM);
475
476 core->pub.id = coreid;
477 core->pub.base = base;
478 core->chip = ci;
479 core->wrapbase = wrapbase;
480
481 list_add_tail(&core->list, &ci->cores);
482 return &core->pub;
483}
484
485
486static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
487{
488 struct brcmf_core_priv *core;
489 bool need_socram = false;
490 bool has_socram = false;
491 bool cpu_found = false;
492 int idx = 1;
493
494 list_for_each_entry(core, &ci->cores, list) {
495 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
496 idx++, core->pub.id, core->pub.rev, core->pub.base,
497 core->wrapbase);
498
499 switch (core->pub.id) {
500 case BCMA_CORE_ARM_CM3:
501 cpu_found = true;
502 need_socram = true;
503 break;
504 case BCMA_CORE_INTERNAL_MEM:
505 has_socram = true;
506 break;
507 case BCMA_CORE_ARM_CR4:
508 cpu_found = true;
509 break;
510 case BCMA_CORE_ARM_CA7:
511 cpu_found = true;
512 break;
513 default:
514 break;
515 }
516 }
517
518 if (!cpu_found) {
519 brcmf_err("CPU core not detected\n");
520 return -ENXIO;
521 }
522
523 if (need_socram && !has_socram) {
524 brcmf_err("RAM core not provided with ARM CM3 core\n");
525 return -ENODEV;
526 }
527 return 0;
528}
529
530static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
531{
532 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
533}
534
535static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
536 u16 reg, u32 val)
537{
538 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
539}
540
541static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
542 u32 *banksize)
543{
544 u32 bankinfo;
545 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
546
547 bankidx |= idx;
548 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
549 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
550 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
551 *banksize *= SOCRAM_BANKINFO_SZBASE;
552 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
553}
554
555static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
556 u32 *srsize)
557{
558 u32 coreinfo;
559 uint nb, banksize, lss;
560 bool retent;
561 int i;
562
563 *ramsize = 0;
564 *srsize = 0;
565
566 if (WARN_ON(sr->pub.rev < 4))
567 return;
568
569 if (!brcmf_chip_iscoreup(&sr->pub))
570 brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
571
572
573 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
574 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
575
576 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
577 banksize = (coreinfo & SRCI_SRBSZ_MASK);
578 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
579 if (lss != 0)
580 nb--;
581 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
582 if (lss != 0)
583 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
584 } else {
585
586 if (sr->pub.rev >= 23) {
587 nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT))
588 >> SRCI_SRNB_SHIFT;
589 } else {
590 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
591 }
592 for (i = 0; i < nb; i++) {
593 retent = brcmf_chip_socram_banksize(sr, i, &banksize);
594 *ramsize += banksize;
595 if (retent)
596 *srsize += banksize;
597 }
598 }
599
600
601 switch (sr->chip->pub.chip) {
602 case BRCM_CC_4334_CHIP_ID:
603 if (sr->chip->pub.chiprev < 2)
604 *srsize = (32 * 1024);
605 break;
606 case BRCM_CC_43430_CHIP_ID:
607
608
609
610 *srsize = (64 * 1024);
611 break;
612 default:
613 break;
614 }
615}
616
617
618static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem)
619{
620 u32 memsize = 0;
621 u32 coreinfo;
622 u32 idx;
623 u32 nb;
624 u32 banksize;
625
626 if (!brcmf_chip_iscoreup(&sysmem->pub))
627 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0);
628
629 coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo));
630 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
631
632 for (idx = 0; idx < nb; idx++) {
633 brcmf_chip_socram_banksize(sysmem, idx, &banksize);
634 memsize += banksize;
635 }
636
637 return memsize;
638}
639
640
641static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
642{
643 u32 corecap;
644 u32 memsize = 0;
645 u32 nab;
646 u32 nbb;
647 u32 totb;
648 u32 bxinfo;
649 u32 idx;
650
651 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
652
653 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
654 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
655 totb = nab + nbb;
656
657 for (idx = 0; idx < totb; idx++) {
658 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
659 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
660 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
661 }
662
663 return memsize;
664}
665
666static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
667{
668 switch (ci->pub.chip) {
669 case BRCM_CC_4345_CHIP_ID:
670 return 0x198000;
671 case BRCM_CC_4335_CHIP_ID:
672 case BRCM_CC_4339_CHIP_ID:
673 case BRCM_CC_4350_CHIP_ID:
674 case BRCM_CC_4354_CHIP_ID:
675 case BRCM_CC_4356_CHIP_ID:
676 case BRCM_CC_43567_CHIP_ID:
677 case BRCM_CC_43569_CHIP_ID:
678 case BRCM_CC_43570_CHIP_ID:
679 case BRCM_CC_4358_CHIP_ID:
680 case BRCM_CC_4359_CHIP_ID:
681 case BRCM_CC_43602_CHIP_ID:
682 case BRCM_CC_4371_CHIP_ID:
683 return 0x180000;
684 case BRCM_CC_43465_CHIP_ID:
685 case BRCM_CC_43525_CHIP_ID:
686 case BRCM_CC_4365_CHIP_ID:
687 case BRCM_CC_4366_CHIP_ID:
688 case BRCM_CC_43664_CHIP_ID:
689 return 0x200000;
690 case CY_CC_4373_CHIP_ID:
691 return 0x160000;
692 default:
693 brcmf_err("unknown chip: %s\n", ci->pub.name);
694 break;
695 }
696 return 0;
697}
698
699static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
700{
701 struct brcmf_core_priv *mem_core;
702 struct brcmf_core *mem;
703
704 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
705 if (mem) {
706 mem_core = container_of(mem, struct brcmf_core_priv, pub);
707 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
708 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
709 if (!ci->pub.rambase) {
710 brcmf_err("RAM base not provided with ARM CR4 core\n");
711 return -EINVAL;
712 }
713 } else {
714 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM);
715 if (mem) {
716 mem_core = container_of(mem, struct brcmf_core_priv,
717 pub);
718 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
719 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
720 if (!ci->pub.rambase) {
721 brcmf_err("RAM base not provided with ARM CA7 core\n");
722 return -EINVAL;
723 }
724 } else {
725 mem = brcmf_chip_get_core(&ci->pub,
726 BCMA_CORE_INTERNAL_MEM);
727 if (!mem) {
728 brcmf_err("No memory cores found\n");
729 return -ENOMEM;
730 }
731 mem_core = container_of(mem, struct brcmf_core_priv,
732 pub);
733 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
734 &ci->pub.srsize);
735 }
736 }
737 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
738 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
739 ci->pub.srsize, ci->pub.srsize);
740
741 if (!ci->pub.ramsize) {
742 brcmf_err("RAM size is undetermined\n");
743 return -ENOMEM;
744 }
745
746 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
747 brcmf_err("RAM size is incorrect\n");
748 return -ENOMEM;
749 }
750
751 return 0;
752}
753
754static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
755 u8 *type)
756{
757 u32 val;
758
759
760 val = ci->ops->read32(ci->ctx, *eromaddr);
761 *eromaddr += 4;
762
763 if (!type)
764 return val;
765
766
767 *type = (val & DMP_DESC_TYPE_MSK);
768 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
769 *type = DMP_DESC_ADDRESS;
770
771 return val;
772}
773
774static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
775 u32 *regbase, u32 *wrapbase)
776{
777 u8 desc;
778 u32 val, szdesc;
779 u8 mpnum = 0;
780 u8 stype, sztype, wraptype;
781
782 *regbase = 0;
783 *wrapbase = 0;
784
785 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
786 if (desc == DMP_DESC_MASTER_PORT) {
787 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
788 wraptype = DMP_SLAVE_TYPE_MWRAP;
789 } else if (desc == DMP_DESC_ADDRESS) {
790
791 *eromaddr -= 4;
792 wraptype = DMP_SLAVE_TYPE_SWRAP;
793 } else {
794 *eromaddr -= 4;
795 return -EILSEQ;
796 }
797
798 do {
799
800 do {
801 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
802
803 if (desc == DMP_DESC_EOT) {
804 *eromaddr -= 4;
805 return -EFAULT;
806 }
807 } while (desc != DMP_DESC_ADDRESS &&
808 desc != DMP_DESC_COMPONENT);
809
810
811 if (desc == DMP_DESC_COMPONENT) {
812 *eromaddr -= 4;
813 return 0;
814 }
815
816
817 if (val & DMP_DESC_ADDRSIZE_GT32)
818 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
819
820 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
821
822
823 if (sztype == DMP_SLAVE_SIZE_DESC) {
824 szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
825
826 if (szdesc & DMP_DESC_ADDRSIZE_GT32)
827 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
828 }
829
830
831 if (sztype != DMP_SLAVE_SIZE_4K &&
832 sztype != DMP_SLAVE_SIZE_8K)
833 continue;
834
835 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
836
837
838 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
839 *regbase = val & DMP_SLAVE_ADDR_BASE;
840 if (*wrapbase == 0 && stype == wraptype)
841 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
842 } while (*regbase == 0 || *wrapbase == 0);
843
844 return 0;
845}
846
847static
848int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
849{
850 struct brcmf_core *core;
851 u32 eromaddr;
852 u8 desc_type = 0;
853 u32 val;
854 u16 id;
855 u8 nmp, nsp, nmw, nsw, rev;
856 u32 base, wrap;
857 int err;
858
859 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
860
861 while (desc_type != DMP_DESC_EOT) {
862 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
863 if (!(val & DMP_DESC_VALID))
864 continue;
865
866 if (desc_type == DMP_DESC_EMPTY)
867 continue;
868
869
870 if (desc_type != DMP_DESC_COMPONENT)
871 continue;
872
873 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
874
875
876 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
877 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
878 return -EFAULT;
879
880
881 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
882 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
883 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
884 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
885 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
886
887
888 if (nmw + nsw == 0 &&
889 id != BCMA_CORE_PMU &&
890 id != BCMA_CORE_GCI)
891 continue;
892
893
894 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
895 if (err)
896 continue;
897
898
899 core = brcmf_chip_add_core(ci, id, base, wrap);
900 if (IS_ERR(core))
901 return PTR_ERR(core);
902
903 core->rev = rev;
904 }
905
906 return 0;
907}
908
909static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
910{
911 struct brcmf_core *core;
912 u32 regdata;
913 u32 socitype;
914 int ret;
915
916
917
918
919
920
921 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
922 ci->pub.chip = regdata & CID_ID_MASK;
923 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
924 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
925
926 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev,
927 ci->pub.name, sizeof(ci->pub.name));
928 brcmf_dbg(INFO, "found %s chip: %s\n",
929 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name);
930
931 if (socitype == SOCI_SB) {
932 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
933 brcmf_err("SB chip is not supported\n");
934 return -ENODEV;
935 }
936 ci->iscoreup = brcmf_chip_sb_iscoreup;
937 ci->coredisable = brcmf_chip_sb_coredisable;
938 ci->resetcore = brcmf_chip_sb_resetcore;
939
940 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
941 SI_ENUM_BASE, 0);
942 brcmf_chip_sb_corerev(ci, core);
943 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
944 BCM4329_CORE_BUS_BASE, 0);
945 brcmf_chip_sb_corerev(ci, core);
946 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
947 BCM4329_CORE_SOCRAM_BASE, 0);
948 brcmf_chip_sb_corerev(ci, core);
949 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
950 BCM4329_CORE_ARM_BASE, 0);
951 brcmf_chip_sb_corerev(ci, core);
952
953 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
954 brcmf_chip_sb_corerev(ci, core);
955 } else if (socitype == SOCI_AI) {
956 ci->iscoreup = brcmf_chip_ai_iscoreup;
957 ci->coredisable = brcmf_chip_ai_coredisable;
958 ci->resetcore = brcmf_chip_ai_resetcore;
959
960 brcmf_chip_dmp_erom_scan(ci);
961 } else {
962 brcmf_err("chip backplane type %u is not supported\n",
963 socitype);
964 return -ENODEV;
965 }
966
967 ret = brcmf_chip_cores_check(ci);
968 if (ret)
969 return ret;
970
971
972 brcmf_chip_set_passive(&ci->pub);
973
974
975
976
977 if (ci->ops->reset) {
978 ci->ops->reset(ci->ctx, &ci->pub);
979 brcmf_chip_set_passive(&ci->pub);
980 }
981
982 return brcmf_chip_get_raminfo(ci);
983}
984
985static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
986{
987 struct brcmf_core *core;
988 struct brcmf_core_priv *cpu;
989 u32 val;
990
991
992 core = brcmf_chip_get_core(&chip->pub, id);
993 if (!core)
994 return;
995
996 switch (id) {
997 case BCMA_CORE_ARM_CM3:
998 brcmf_chip_coredisable(core, 0, 0);
999 break;
1000 case BCMA_CORE_ARM_CR4:
1001 case BCMA_CORE_ARM_CA7:
1002 cpu = container_of(core, struct brcmf_core_priv, pub);
1003
1004
1005 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
1006 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
1007 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
1008 ARMCR4_BCMA_IOCTL_CPUHALT);
1009 break;
1010 default:
1011 brcmf_err("unknown id: %u\n", id);
1012 break;
1013 }
1014}
1015
1016static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
1017{
1018 struct brcmf_chip *pub;
1019 struct brcmf_core_priv *cc;
1020 struct brcmf_core *pmu;
1021 u32 base;
1022 u32 val;
1023 int ret = 0;
1024
1025 pub = &chip->pub;
1026 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1027 base = cc->pub.base;
1028
1029
1030 pub->cc_caps = chip->ops->read32(chip->ctx,
1031 CORE_CC_REG(base, capabilities));
1032 pub->cc_caps_ext = chip->ops->read32(chip->ctx,
1033 CORE_CC_REG(base,
1034 capabilities_ext));
1035
1036
1037 pmu = brcmf_chip_get_pmu(pub);
1038 if (pub->cc_caps & CC_CAP_PMU) {
1039 val = chip->ops->read32(chip->ctx,
1040 CORE_CC_REG(pmu->base, pmucapabilities));
1041 pub->pmurev = val & PCAP_REV_MASK;
1042 pub->pmucaps = val;
1043 }
1044
1045 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
1046 cc->pub.rev, pub->pmurev, pub->pmucaps);
1047
1048
1049 if (chip->ops->setup)
1050 ret = chip->ops->setup(chip->ctx, pub);
1051
1052 return ret;
1053}
1054
1055struct brcmf_chip *brcmf_chip_attach(void *ctx,
1056 const struct brcmf_buscore_ops *ops)
1057{
1058 struct brcmf_chip_priv *chip;
1059 int err = 0;
1060
1061 if (WARN_ON(!ops->read32))
1062 err = -EINVAL;
1063 if (WARN_ON(!ops->write32))
1064 err = -EINVAL;
1065 if (WARN_ON(!ops->prepare))
1066 err = -EINVAL;
1067 if (WARN_ON(!ops->activate))
1068 err = -EINVAL;
1069 if (err < 0)
1070 return ERR_PTR(-EINVAL);
1071
1072 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1073 if (!chip)
1074 return ERR_PTR(-ENOMEM);
1075
1076 INIT_LIST_HEAD(&chip->cores);
1077 chip->num_cores = 0;
1078 chip->ops = ops;
1079 chip->ctx = ctx;
1080
1081 err = ops->prepare(ctx);
1082 if (err < 0)
1083 goto fail;
1084
1085 err = brcmf_chip_recognition(chip);
1086 if (err < 0)
1087 goto fail;
1088
1089 err = brcmf_chip_setup(chip);
1090 if (err < 0)
1091 goto fail;
1092
1093 return &chip->pub;
1094
1095fail:
1096 brcmf_chip_detach(&chip->pub);
1097 return ERR_PTR(err);
1098}
1099
1100void brcmf_chip_detach(struct brcmf_chip *pub)
1101{
1102 struct brcmf_chip_priv *chip;
1103 struct brcmf_core_priv *core;
1104 struct brcmf_core_priv *tmp;
1105
1106 chip = container_of(pub, struct brcmf_chip_priv, pub);
1107 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
1108 list_del(&core->list);
1109 kfree(core);
1110 }
1111 kfree(chip);
1112}
1113
1114struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
1115{
1116 struct brcmf_chip_priv *chip;
1117 struct brcmf_core_priv *core;
1118
1119 chip = container_of(pub, struct brcmf_chip_priv, pub);
1120 list_for_each_entry(core, &chip->cores, list)
1121 if (core->pub.id == coreid)
1122 return &core->pub;
1123
1124 return NULL;
1125}
1126
1127struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
1128{
1129 struct brcmf_chip_priv *chip;
1130 struct brcmf_core_priv *cc;
1131
1132 chip = container_of(pub, struct brcmf_chip_priv, pub);
1133 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1134 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
1135 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
1136 return &cc->pub;
1137}
1138
1139struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub)
1140{
1141 struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub);
1142 struct brcmf_core *pmu;
1143
1144
1145 if (cc->rev >= 35 &&
1146 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
1147 pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU);
1148 if (pmu)
1149 return pmu;
1150 }
1151
1152
1153 return cc;
1154}
1155
1156bool brcmf_chip_iscoreup(struct brcmf_core *pub)
1157{
1158 struct brcmf_core_priv *core;
1159
1160 core = container_of(pub, struct brcmf_core_priv, pub);
1161 return core->chip->iscoreup(core);
1162}
1163
1164void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
1165{
1166 struct brcmf_core_priv *core;
1167
1168 core = container_of(pub, struct brcmf_core_priv, pub);
1169 core->chip->coredisable(core, prereset, reset);
1170}
1171
1172void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
1173 u32 postreset)
1174{
1175 struct brcmf_core_priv *core;
1176
1177 core = container_of(pub, struct brcmf_core_priv, pub);
1178 core->chip->resetcore(core, prereset, reset, postreset);
1179}
1180
1181static void
1182brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
1183{
1184 struct brcmf_core *core;
1185 struct brcmf_core_priv *sr;
1186
1187 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
1188 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1189 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1190 D11_BCMA_IOCTL_PHYCLOCKEN,
1191 D11_BCMA_IOCTL_PHYCLOCKEN,
1192 D11_BCMA_IOCTL_PHYCLOCKEN);
1193 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1194 brcmf_chip_resetcore(core, 0, 0, 0);
1195
1196
1197 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
1198 sr = container_of(core, struct brcmf_core_priv, pub);
1199 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
1200 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
1201 }
1202}
1203
1204static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
1205{
1206 struct brcmf_core *core;
1207
1208 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1209 if (!brcmf_chip_iscoreup(core)) {
1210 brcmf_err("SOCRAM core is down after reset?\n");
1211 return false;
1212 }
1213
1214 chip->ops->activate(chip->ctx, &chip->pub, 0);
1215
1216 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
1217 brcmf_chip_resetcore(core, 0, 0, 0);
1218
1219 return true;
1220}
1221
1222static inline void
1223brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
1224{
1225 struct brcmf_core *core;
1226
1227 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
1228
1229 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1230 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1231 D11_BCMA_IOCTL_PHYCLOCKEN,
1232 D11_BCMA_IOCTL_PHYCLOCKEN,
1233 D11_BCMA_IOCTL_PHYCLOCKEN);
1234}
1235
1236static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1237{
1238 struct brcmf_core *core;
1239
1240 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1241
1242
1243 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
1244 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1245
1246 return true;
1247}
1248
1249static inline void
1250brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip)
1251{
1252 struct brcmf_core *core;
1253
1254 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7);
1255
1256 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1257 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1258 D11_BCMA_IOCTL_PHYCLOCKEN,
1259 D11_BCMA_IOCTL_PHYCLOCKEN,
1260 D11_BCMA_IOCTL_PHYCLOCKEN);
1261}
1262
1263static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1264{
1265 struct brcmf_core *core;
1266
1267 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1268
1269
1270 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7);
1271 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1272
1273 return true;
1274}
1275
1276void brcmf_chip_set_passive(struct brcmf_chip *pub)
1277{
1278 struct brcmf_chip_priv *chip;
1279 struct brcmf_core *arm;
1280
1281 brcmf_dbg(TRACE, "Enter\n");
1282
1283 chip = container_of(pub, struct brcmf_chip_priv, pub);
1284 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1285 if (arm) {
1286 brcmf_chip_cr4_set_passive(chip);
1287 return;
1288 }
1289 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1290 if (arm) {
1291 brcmf_chip_ca7_set_passive(chip);
1292 return;
1293 }
1294 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1295 if (arm) {
1296 brcmf_chip_cm3_set_passive(chip);
1297 return;
1298 }
1299}
1300
1301bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
1302{
1303 struct brcmf_chip_priv *chip;
1304 struct brcmf_core *arm;
1305
1306 brcmf_dbg(TRACE, "Enter\n");
1307
1308 chip = container_of(pub, struct brcmf_chip_priv, pub);
1309 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1310 if (arm)
1311 return brcmf_chip_cr4_set_active(chip, rstvec);
1312 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1313 if (arm)
1314 return brcmf_chip_ca7_set_active(chip, rstvec);
1315 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1316 if (arm)
1317 return brcmf_chip_cm3_set_active(chip);
1318
1319 return false;
1320}
1321
1322bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1323{
1324 u32 base, addr, reg, pmu_cc3_mask = ~0;
1325 struct brcmf_chip_priv *chip;
1326 struct brcmf_core *pmu = brcmf_chip_get_pmu(pub);
1327
1328 brcmf_dbg(TRACE, "Enter\n");
1329
1330
1331 if (pub->pmurev < 17)
1332 return false;
1333
1334 base = brcmf_chip_get_chipcommon(pub)->base;
1335 chip = container_of(pub, struct brcmf_chip_priv, pub);
1336
1337 switch (pub->chip) {
1338 case BRCM_CC_4354_CHIP_ID:
1339 case BRCM_CC_4356_CHIP_ID:
1340 case BRCM_CC_4345_CHIP_ID:
1341
1342 pmu_cc3_mask = BIT(2);
1343
1344 case BRCM_CC_43241_CHIP_ID:
1345 case BRCM_CC_4335_CHIP_ID:
1346 case BRCM_CC_4339_CHIP_ID:
1347
1348 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
1349 chip->ops->write32(chip->ctx, addr, 3);
1350 addr = CORE_CC_REG(pmu->base, chipcontrol_data);
1351 reg = chip->ops->read32(chip->ctx, addr);
1352 return (reg & pmu_cc3_mask) != 0;
1353 case BRCM_CC_43430_CHIP_ID:
1354 addr = CORE_CC_REG(base, sr_control1);
1355 reg = chip->ops->read32(chip->ctx, addr);
1356 return reg != 0;
1357 case CY_CC_4373_CHIP_ID:
1358
1359 addr = CORE_CC_REG(base, sr_control0);
1360 reg = chip->ops->read32(chip->ctx, addr);
1361 return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
1362 case CY_CC_43012_CHIP_ID:
1363 addr = CORE_CC_REG(pmu->base, retention_ctl);
1364 reg = chip->ops->read32(chip->ctx, addr);
1365 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1366 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1367 default:
1368 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
1369 reg = chip->ops->read32(chip->ctx, addr);
1370 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1371 return false;
1372
1373 addr = CORE_CC_REG(pmu->base, retention_ctl);
1374 reg = chip->ops->read32(chip->ctx, addr);
1375 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1376 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1377 }
1378}
1379
