1
2
3
4
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/firmware.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/bcma/bcma.h>
14#include <linux/sched.h>
15#include <asm/unaligned.h>
16
17#include <soc.h>
18#include <chipcommon.h>
19#include <brcmu_utils.h>
20#include <brcmu_wifi.h>
21#include <brcm_hw_ids.h>
22
23
24#define brcmf_err(bus, fmt, ...) \
25 do { \
26 if (IS_ENABLED(CONFIG_BRCMDBG) || \
27 IS_ENABLED(CONFIG_BRCM_TRACING) || \
28 net_ratelimit()) \
29 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \
30 } while (0)
31
32#include "debug.h"
33#include "bus.h"
34#include "commonring.h"
35#include "msgbuf.h"
36#include "pcie.h"
37#include "firmware.h"
38#include "chip.h"
39#include "core.h"
40#include "common.h"
41
42
43enum brcmf_pcie_state {
44 BRCMFMAC_PCIE_STATE_DOWN,
45 BRCMFMAC_PCIE_STATE_UP
46};
47
48BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
49BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
50BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
51BRCMF_FW_DEF(4356, "brcmfmac4356-pcie");
52BRCMF_FW_DEF(43570, "brcmfmac43570-pcie");
53BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
54BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
55BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie");
56BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie");
57BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie");
58BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie");
59BRCMF_FW_DEF(4371, "brcmfmac4371-pcie");
60
61static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
62 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
63 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
64 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
65 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
66 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
67 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
68 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
69 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
70 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
71 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
72 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
73 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
74 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
75 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
76 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
77 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
78 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
79};
80
81#define BRCMF_PCIE_FW_UP_TIMEOUT 2000
82
83#define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
84
85
86#define BRCMF_PCIE_BAR0_WINDOW 0x80
87#define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
88#define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
89
90#define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
91#define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
92
93#define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
94#define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
95
96#define BRCMF_PCIE_REG_INTSTATUS 0x90
97#define BRCMF_PCIE_REG_INTMASK 0x94
98#define BRCMF_PCIE_REG_SBMBX 0x98
99
100#define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC
101
102#define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
103#define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
104#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
105#define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
106#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
107#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140
108#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144
109
110#define BRCMF_PCIE2_INTA 0x01
111#define BRCMF_PCIE2_INTB 0x02
112
113#define BRCMF_PCIE_INT_0 0x01
114#define BRCMF_PCIE_INT_1 0x02
115#define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
116 BRCMF_PCIE_INT_1)
117
118#define BRCMF_PCIE_MB_INT_FN0_0 0x0100
119#define BRCMF_PCIE_MB_INT_FN0_1 0x0200
120#define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
121#define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
122#define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
123#define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
124#define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
125#define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
126#define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
127#define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
128
129#define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
130 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
131 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
132 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
133 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
134 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
135 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
136 BRCMF_PCIE_MB_INT_D2H3_DB1)
137
138#define BRCMF_PCIE_SHARED_VERSION_7 7
139#define BRCMF_PCIE_MIN_SHARED_VERSION 5
140#define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7
141#define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
142#define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
143#define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
144#define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000
145
146#define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
147#define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
148
149#define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
150#define BRCMF_SHARED_RING_BASE_OFFSET 52
151#define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
152#define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
153#define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
154#define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
155#define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
156#define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
157#define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
158#define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
159#define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
160
161#define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
162#define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
163#define BRCMF_RING_H2D_RING_MEM_OFFSET 4
164#define BRCMF_RING_H2D_RING_STATE_OFFSET 8
165
166#define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
167#define BRCMF_RING_MAX_ITEM_OFFSET 4
168#define BRCMF_RING_LEN_ITEMS_OFFSET 6
169#define BRCMF_RING_MEM_SZ 16
170#define BRCMF_RING_STATE_SZ 8
171
172#define BRCMF_DEF_MAX_RXBUFPOST 255
173
174#define BRCMF_CONSOLE_BUFADDR_OFFSET 8
175#define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
176#define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
177
178#define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
179#define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
180
181#define BRCMF_D2H_DEV_D3_ACK 0x00000001
182#define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
183#define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
184#define BRCMF_D2H_DEV_FWHALT 0x10000000
185
186#define BRCMF_H2D_HOST_D3_INFORM 0x00000001
187#define BRCMF_H2D_HOST_DS_ACK 0x00000002
188#define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
189#define BRCMF_H2D_HOST_D0_INFORM 0x00000010
190
191#define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000)
192
193#define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
194#define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
195#define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
196#define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
197#define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
198#define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
199#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
200#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
201#define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
202#define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
203#define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
204#define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
205#define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
206
207
208#define BRCMF_RAMSIZE_MAGIC 0x534d4152
209#define BRCMF_RAMSIZE_OFFSET 0x6c
210
211
212struct brcmf_pcie_console {
213 u32 base_addr;
214 u32 buf_addr;
215 u32 bufsize;
216 u32 read_idx;
217 u8 log_str[256];
218 u8 log_idx;
219};
220
221struct brcmf_pcie_shared_info {
222 u32 tcm_base_address;
223 u32 flags;
224 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
225 struct brcmf_pcie_ringbuf *flowrings;
226 u16 max_rxbufpost;
227 u16 max_flowrings;
228 u16 max_submissionrings;
229 u16 max_completionrings;
230 u32 rx_dataoffset;
231 u32 htod_mb_data_addr;
232 u32 dtoh_mb_data_addr;
233 u32 ring_info_addr;
234 struct brcmf_pcie_console console;
235 void *scratch;
236 dma_addr_t scratch_dmahandle;
237 void *ringupd;
238 dma_addr_t ringupd_dmahandle;
239 u8 version;
240};
241
242struct brcmf_pcie_core_info {
243 u32 base;
244 u32 wrapbase;
245};
246
247struct brcmf_pciedev_info {
248 enum brcmf_pcie_state state;
249 bool in_irq;
250 struct pci_dev *pdev;
251 char fw_name[BRCMF_FW_NAME_LEN];
252 char nvram_name[BRCMF_FW_NAME_LEN];
253 void __iomem *regs;
254 void __iomem *tcm;
255 u32 ram_base;
256 u32 ram_size;
257 struct brcmf_chip *ci;
258 u32 coreid;
259 struct brcmf_pcie_shared_info shared;
260 wait_queue_head_t mbdata_resp_wait;
261 bool mbdata_completed;
262 bool irq_allocated;
263 bool wowl_enabled;
264 u8 dma_idx_sz;
265 void *idxbuf;
266 u32 idxbuf_sz;
267 dma_addr_t idxbuf_dmahandle;
268 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
269 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
270 u16 value);
271 struct brcmf_mp_device *settings;
272};
273
274struct brcmf_pcie_ringbuf {
275 struct brcmf_commonring commonring;
276 dma_addr_t dma_handle;
277 u32 w_idx_addr;
278 u32 r_idx_addr;
279 struct brcmf_pciedev_info *devinfo;
280 u8 id;
281};
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299struct brcmf_pcie_dhi_ringinfo {
300 __le32 ringmem;
301 __le32 h2d_w_idx_ptr;
302 __le32 h2d_r_idx_ptr;
303 __le32 d2h_w_idx_ptr;
304 __le32 d2h_r_idx_ptr;
305 struct msgbuf_buf_addr h2d_w_idx_hostaddr;
306 struct msgbuf_buf_addr h2d_r_idx_hostaddr;
307 struct msgbuf_buf_addr d2h_w_idx_hostaddr;
308 struct msgbuf_buf_addr d2h_r_idx_hostaddr;
309 __le16 max_flowrings;
310 __le16 max_submissionrings;
311 __le16 max_completionrings;
312};
313
314static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
315 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
316 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
317 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
318 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
319 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
320};
321
322static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
323 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
324 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
325 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
326 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
327 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
328};
329
330static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
331 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
332 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
333 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
334 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
335 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
336};
337
338static void brcmf_pcie_setup(struct device *dev, int ret,
339 struct brcmf_fw_request *fwreq);
340static struct brcmf_fw_request *
341brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo);
342
343static u32
344brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
345{
346 void __iomem *address = devinfo->regs + reg_offset;
347
348 return (ioread32(address));
349}
350
351
352static void
353brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
354 u32 value)
355{
356 void __iomem *address = devinfo->regs + reg_offset;
357
358 iowrite32(value, address);
359}
360
361
362static u8
363brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
364{
365 void __iomem *address = devinfo->tcm + mem_offset;
366
367 return (ioread8(address));
368}
369
370
371static u16
372brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
373{
374 void __iomem *address = devinfo->tcm + mem_offset;
375
376 return (ioread16(address));
377}
378
379
380static void
381brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
382 u16 value)
383{
384 void __iomem *address = devinfo->tcm + mem_offset;
385
386 iowrite16(value, address);
387}
388
389
390static u16
391brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
392{
393 u16 *address = devinfo->idxbuf + mem_offset;
394
395 return (*(address));
396}
397
398
399static void
400brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
401 u16 value)
402{
403 u16 *address = devinfo->idxbuf + mem_offset;
404
405 *(address) = value;
406}
407
408
409static u32
410brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
411{
412 void __iomem *address = devinfo->tcm + mem_offset;
413
414 return (ioread32(address));
415}
416
417
418static void
419brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
420 u32 value)
421{
422 void __iomem *address = devinfo->tcm + mem_offset;
423
424 iowrite32(value, address);
425}
426
427
428static u32
429brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
430{
431 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
432
433 return (ioread32(addr));
434}
435
436
437static void
438brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
439 u32 value)
440{
441 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
442
443 iowrite32(value, addr);
444}
445
446
447static void
448brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
449 void *srcaddr, u32 len)
450{
451 void __iomem *address = devinfo->tcm + mem_offset;
452 __le32 *src32;
453 __le16 *src16;
454 u8 *src8;
455
456 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
457 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
458 src8 = (u8 *)srcaddr;
459 while (len) {
460 iowrite8(*src8, address);
461 address++;
462 src8++;
463 len--;
464 }
465 } else {
466 len = len / 2;
467 src16 = (__le16 *)srcaddr;
468 while (len) {
469 iowrite16(le16_to_cpu(*src16), address);
470 address += 2;
471 src16++;
472 len--;
473 }
474 }
475 } else {
476 len = len / 4;
477 src32 = (__le32 *)srcaddr;
478 while (len) {
479 iowrite32(le32_to_cpu(*src32), address);
480 address += 4;
481 src32++;
482 len--;
483 }
484 }
485}
486
487
488static void
489brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
490 void *dstaddr, u32 len)
491{
492 void __iomem *address = devinfo->tcm + mem_offset;
493 __le32 *dst32;
494 __le16 *dst16;
495 u8 *dst8;
496
497 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
498 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
499 dst8 = (u8 *)dstaddr;
500 while (len) {
501 *dst8 = ioread8(address);
502 address++;
503 dst8++;
504 len--;
505 }
506 } else {
507 len = len / 2;
508 dst16 = (__le16 *)dstaddr;
509 while (len) {
510 *dst16 = cpu_to_le16(ioread16(address));
511 address += 2;
512 dst16++;
513 len--;
514 }
515 }
516 } else {
517 len = len / 4;
518 dst32 = (__le32 *)dstaddr;
519 while (len) {
520 *dst32 = cpu_to_le32(ioread32(address));
521 address += 4;
522 dst32++;
523 len--;
524 }
525 }
526}
527
528
529#define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
530 CHIPCREGOFFS(reg), value)
531
532
533static void
534brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
535{
536 const struct pci_dev *pdev = devinfo->pdev;
537 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
538 struct brcmf_core *core;
539 u32 bar0_win;
540
541 core = brcmf_chip_get_core(devinfo->ci, coreid);
542 if (core) {
543 bar0_win = core->base;
544 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
545 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
546 &bar0_win) == 0) {
547 if (bar0_win != core->base) {
548 bar0_win = core->base;
549 pci_write_config_dword(pdev,
550 BRCMF_PCIE_BAR0_WINDOW,
551 bar0_win);
552 }
553 }
554 } else {
555 brcmf_err(bus, "Unsupported core selected %x\n", coreid);
556 }
557}
558
559
560static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
561{
562 struct brcmf_core *core;
563 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
564 BRCMF_PCIE_CFGREG_PM_CSR,
565 BRCMF_PCIE_CFGREG_MSI_CAP,
566 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
567 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
568 BRCMF_PCIE_CFGREG_MSI_DATA,
569 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
570 BRCMF_PCIE_CFGREG_RBAR_CTRL,
571 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
572 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
573 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
574 u32 i;
575 u32 val;
576 u32 lsc;
577
578 if (!devinfo->ci)
579 return;
580
581
582 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
583 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
584 &lsc);
585 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
586 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
587 val);
588
589
590 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
591 WRITECC32(devinfo, watchdog, 4);
592 msleep(100);
593
594
595 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
596 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
597 lsc);
598
599 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
600 if (core->rev <= 13) {
601 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
602 brcmf_pcie_write_reg32(devinfo,
603 BRCMF_PCIE_PCIE2REG_CONFIGADDR,
604 cfg_offset[i]);
605 val = brcmf_pcie_read_reg32(devinfo,
606 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
607 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
608 cfg_offset[i], val);
609 brcmf_pcie_write_reg32(devinfo,
610 BRCMF_PCIE_PCIE2REG_CONFIGDATA,
611 val);
612 }
613 }
614}
615
616
617static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
618{
619 u32 config;
620
621
622 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
623 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
624 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
625 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
626
627 device_wakeup_enable(&devinfo->pdev->dev);
628}
629
630
631static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
632{
633 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
634 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
635 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
636 5);
637 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
638 0);
639 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
640 7);
641 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
642 0);
643 }
644 return 0;
645}
646
647
648static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
649 u32 resetintr)
650{
651 struct brcmf_core *core;
652
653 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
654 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
655 brcmf_chip_resetcore(core, 0, 0, 0);
656 }
657
658 if (!brcmf_chip_set_active(devinfo->ci, resetintr))
659 return -EINVAL;
660 return 0;
661}
662
663
664static int
665brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
666{
667 struct brcmf_pcie_shared_info *shared;
668 struct brcmf_core *core;
669 u32 addr;
670 u32 cur_htod_mb_data;
671 u32 i;
672
673 shared = &devinfo->shared;
674 addr = shared->htod_mb_data_addr;
675 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
676
677 if (cur_htod_mb_data != 0)
678 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
679 cur_htod_mb_data);
680
681 i = 0;
682 while (cur_htod_mb_data != 0) {
683 msleep(10);
684 i++;
685 if (i > 100)
686 return -EIO;
687 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
688 }
689
690 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
691 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
692
693
694 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
695 if (core->rev <= 13)
696 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
697
698 return 0;
699}
700
701
702static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
703{
704 struct brcmf_pcie_shared_info *shared;
705 u32 addr;
706 u32 dtoh_mb_data;
707
708 shared = &devinfo->shared;
709 addr = shared->dtoh_mb_data_addr;
710 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
711
712 if (!dtoh_mb_data)
713 return;
714
715 brcmf_pcie_write_tcm32(devinfo, addr, 0);
716
717 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
718 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
719 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
720 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
721 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
722 }
723 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
724 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
725 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
726 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
727 devinfo->mbdata_completed = true;
728 wake_up(&devinfo->mbdata_resp_wait);
729 }
730 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) {
731 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
732 brcmf_fw_crashed(&devinfo->pdev->dev);
733 }
734}
735
736
737static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
738{
739 struct brcmf_pcie_shared_info *shared;
740 struct brcmf_pcie_console *console;
741 u32 addr;
742
743 shared = &devinfo->shared;
744 console = &shared->console;
745 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
746 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
747
748 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
749 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
750 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
751 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
752
753 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
754 console->base_addr, console->buf_addr, console->bufsize);
755}
756
757
758
759
760
761
762static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
763 bool error)
764{
765 struct pci_dev *pdev = devinfo->pdev;
766 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
767 struct brcmf_pcie_console *console;
768 u32 addr;
769 u8 ch;
770 u32 newidx;
771
772 if (!error && !BRCMF_FWCON_ON())
773 return;
774
775 console = &devinfo->shared.console;
776 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
777 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
778 while (newidx != console->read_idx) {
779 addr = console->buf_addr + console->read_idx;
780 ch = brcmf_pcie_read_tcm8(devinfo, addr);
781 console->read_idx++;
782 if (console->read_idx == console->bufsize)
783 console->read_idx = 0;
784 if (ch == '\r')
785 continue;
786 console->log_str[console->log_idx] = ch;
787 console->log_idx++;
788 if ((ch != '\n') &&
789 (console->log_idx == (sizeof(console->log_str) - 2))) {
790 ch = '\n';
791 console->log_str[console->log_idx] = ch;
792 console->log_idx++;
793 }
794 if (ch == '\n') {
795 console->log_str[console->log_idx] = 0;
796 if (error)
797 brcmf_err(bus, "CONSOLE: %s", console->log_str);
798 else
799 pr_debug("CONSOLE: %s", console->log_str);
800 console->log_idx = 0;
801 }
802 }
803}
804
805
806static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
807{
808 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
809}
810
811
812static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
813{
814 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
815 BRCMF_PCIE_MB_INT_D2H_DB |
816 BRCMF_PCIE_MB_INT_FN0_0 |
817 BRCMF_PCIE_MB_INT_FN0_1);
818}
819
820static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
821{
822 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
823 brcmf_pcie_write_reg32(devinfo,
824 BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 1);
825}
826
827static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
828{
829 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
830
831 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
832 brcmf_pcie_intr_disable(devinfo);
833 brcmf_dbg(PCIE, "Enter\n");
834 return IRQ_WAKE_THREAD;
835 }
836 return IRQ_NONE;
837}
838
839
840static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
841{
842 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
843 u32 status;
844
845 devinfo->in_irq = true;
846 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
847 brcmf_dbg(PCIE, "Enter %x\n", status);
848 if (status) {
849 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
850 status);
851 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
852 BRCMF_PCIE_MB_INT_FN0_1))
853 brcmf_pcie_handle_mb_data(devinfo);
854 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
855 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
856 brcmf_proto_msgbuf_rx_trigger(
857 &devinfo->pdev->dev);
858 }
859 }
860 brcmf_pcie_bus_console_read(devinfo, false);
861 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
862 brcmf_pcie_intr_enable(devinfo);
863 devinfo->in_irq = false;
864 return IRQ_HANDLED;
865}
866
867
868static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
869{
870 struct pci_dev *pdev = devinfo->pdev;
871 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
872
873 brcmf_pcie_intr_disable(devinfo);
874
875 brcmf_dbg(PCIE, "Enter\n");
876
877 pci_enable_msi(pdev);
878 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
879 brcmf_pcie_isr_thread, IRQF_SHARED,
880 "brcmf_pcie_intr", devinfo)) {
881 pci_disable_msi(pdev);
882 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq);
883 return -EIO;
884 }
885 devinfo->irq_allocated = true;
886 return 0;
887}
888
889
890static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
891{
892 struct pci_dev *pdev = devinfo->pdev;
893 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
894 u32 status;
895 u32 count;
896
897 if (!devinfo->irq_allocated)
898 return;
899
900 brcmf_pcie_intr_disable(devinfo);
901 free_irq(pdev->irq, devinfo);
902 pci_disable_msi(pdev);
903
904 msleep(50);
905 count = 0;
906 while ((devinfo->in_irq) && (count < 20)) {
907 msleep(50);
908 count++;
909 }
910 if (devinfo->in_irq)
911 brcmf_err(bus, "Still in IRQ (processing) !!!\n");
912
913 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
914 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
915
916 devinfo->irq_allocated = false;
917}
918
919
920static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
921{
922 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
923 struct brcmf_pciedev_info *devinfo = ring->devinfo;
924 struct brcmf_commonring *commonring = &ring->commonring;
925
926 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
927 return -EIO;
928
929 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
930 commonring->w_ptr, ring->id);
931
932 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
933
934 return 0;
935}
936
937
938static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
939{
940 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
941 struct brcmf_pciedev_info *devinfo = ring->devinfo;
942 struct brcmf_commonring *commonring = &ring->commonring;
943
944 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
945 return -EIO;
946
947 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
948 commonring->r_ptr, ring->id);
949
950 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
951
952 return 0;
953}
954
955
956static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
957{
958 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
959 struct brcmf_pciedev_info *devinfo = ring->devinfo;
960
961 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
962 return -EIO;
963
964 brcmf_dbg(PCIE, "RING !\n");
965
966 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 1);
967
968 return 0;
969}
970
971
972static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
973{
974 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
975 struct brcmf_pciedev_info *devinfo = ring->devinfo;
976 struct brcmf_commonring *commonring = &ring->commonring;
977
978 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
979 return -EIO;
980
981 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
982
983 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
984 commonring->w_ptr, ring->id);
985
986 return 0;
987}
988
989
990static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
991{
992 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
993 struct brcmf_pciedev_info *devinfo = ring->devinfo;
994 struct brcmf_commonring *commonring = &ring->commonring;
995
996 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
997 return -EIO;
998
999 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1000
1001 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1002 commonring->r_ptr, ring->id);
1003
1004 return 0;
1005}
1006
1007
1008static void *
1009brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1010 u32 size, u32 tcm_dma_phys_addr,
1011 dma_addr_t *dma_handle)
1012{
1013 void *ring;
1014 u64 address;
1015
1016 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1017 GFP_KERNEL);
1018 if (!ring)
1019 return NULL;
1020
1021 address = (u64)*dma_handle;
1022 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1023 address & 0xffffffff);
1024 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1025
1026 memset(ring, 0, size);
1027
1028 return (ring);
1029}
1030
1031
1032static struct brcmf_pcie_ringbuf *
1033brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1034 u32 tcm_ring_phys_addr)
1035{
1036 void *dma_buf;
1037 dma_addr_t dma_handle;
1038 struct brcmf_pcie_ringbuf *ring;
1039 u32 size;
1040 u32 addr;
1041 const u32 *ring_itemsize_array;
1042
1043 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7)
1044 ring_itemsize_array = brcmf_ring_itemsize_pre_v7;
1045 else
1046 ring_itemsize_array = brcmf_ring_itemsize;
1047
1048 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id];
1049 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1050 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1051 &dma_handle);
1052 if (!dma_buf)
1053 return NULL;
1054
1055 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1056 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1057 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1058 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]);
1059
1060 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1061 if (!ring) {
1062 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1063 dma_handle);
1064 return NULL;
1065 }
1066 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1067 ring_itemsize_array[ring_id], dma_buf);
1068 ring->dma_handle = dma_handle;
1069 ring->devinfo = devinfo;
1070 brcmf_commonring_register_cb(&ring->commonring,
1071 brcmf_pcie_ring_mb_ring_bell,
1072 brcmf_pcie_ring_mb_update_rptr,
1073 brcmf_pcie_ring_mb_update_wptr,
1074 brcmf_pcie_ring_mb_write_rptr,
1075 brcmf_pcie_ring_mb_write_wptr, ring);
1076
1077 return (ring);
1078}
1079
1080
1081static void brcmf_pcie_release_ringbuffer(struct device *dev,
1082 struct brcmf_pcie_ringbuf *ring)
1083{
1084 void *dma_buf;
1085 u32 size;
1086
1087 if (!ring)
1088 return;
1089
1090 dma_buf = ring->commonring.buf_addr;
1091 if (dma_buf) {
1092 size = ring->commonring.depth * ring->commonring.item_len;
1093 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1094 }
1095 kfree(ring);
1096}
1097
1098
1099static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1100{
1101 u32 i;
1102
1103 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1104 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1105 devinfo->shared.commonrings[i]);
1106 devinfo->shared.commonrings[i] = NULL;
1107 }
1108 kfree(devinfo->shared.flowrings);
1109 devinfo->shared.flowrings = NULL;
1110 if (devinfo->idxbuf) {
1111 dma_free_coherent(&devinfo->pdev->dev,
1112 devinfo->idxbuf_sz,
1113 devinfo->idxbuf,
1114 devinfo->idxbuf_dmahandle);
1115 devinfo->idxbuf = NULL;
1116 }
1117}
1118
1119
1120static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1121{
1122 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1123 struct brcmf_pcie_ringbuf *ring;
1124 struct brcmf_pcie_ringbuf *rings;
1125 u32 d2h_w_idx_ptr;
1126 u32 d2h_r_idx_ptr;
1127 u32 h2d_w_idx_ptr;
1128 u32 h2d_r_idx_ptr;
1129 u32 ring_mem_ptr;
1130 u32 i;
1131 u64 address;
1132 u32 bufsz;
1133 u8 idx_offset;
1134 struct brcmf_pcie_dhi_ringinfo ringinfo;
1135 u16 max_flowrings;
1136 u16 max_submissionrings;
1137 u16 max_completionrings;
1138
1139 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1140 sizeof(ringinfo));
1141 if (devinfo->shared.version >= 6) {
1142 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1143 max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1144 max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1145 } else {
1146 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1147 max_flowrings = max_submissionrings -
1148 BRCMF_NROF_H2D_COMMON_MSGRINGS;
1149 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1150 }
1151
1152 if (devinfo->dma_idx_sz != 0) {
1153 bufsz = (max_submissionrings + max_completionrings) *
1154 devinfo->dma_idx_sz * 2;
1155 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1156 &devinfo->idxbuf_dmahandle,
1157 GFP_KERNEL);
1158 if (!devinfo->idxbuf)
1159 devinfo->dma_idx_sz = 0;
1160 }
1161
1162 if (devinfo->dma_idx_sz == 0) {
1163 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1164 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1165 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1166 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1167 idx_offset = sizeof(u32);
1168 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1169 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1170 brcmf_dbg(PCIE, "Using TCM indices\n");
1171 } else {
1172 memset(devinfo->idxbuf, 0, bufsz);
1173 devinfo->idxbuf_sz = bufsz;
1174 idx_offset = devinfo->dma_idx_sz;
1175 devinfo->write_ptr = brcmf_pcie_write_idx;
1176 devinfo->read_ptr = brcmf_pcie_read_idx;
1177
1178 h2d_w_idx_ptr = 0;
1179 address = (u64)devinfo->idxbuf_dmahandle;
1180 ringinfo.h2d_w_idx_hostaddr.low_addr =
1181 cpu_to_le32(address & 0xffffffff);
1182 ringinfo.h2d_w_idx_hostaddr.high_addr =
1183 cpu_to_le32(address >> 32);
1184
1185 h2d_r_idx_ptr = h2d_w_idx_ptr +
1186 max_submissionrings * idx_offset;
1187 address += max_submissionrings * idx_offset;
1188 ringinfo.h2d_r_idx_hostaddr.low_addr =
1189 cpu_to_le32(address & 0xffffffff);
1190 ringinfo.h2d_r_idx_hostaddr.high_addr =
1191 cpu_to_le32(address >> 32);
1192
1193 d2h_w_idx_ptr = h2d_r_idx_ptr +
1194 max_submissionrings * idx_offset;
1195 address += max_submissionrings * idx_offset;
1196 ringinfo.d2h_w_idx_hostaddr.low_addr =
1197 cpu_to_le32(address & 0xffffffff);
1198 ringinfo.d2h_w_idx_hostaddr.high_addr =
1199 cpu_to_le32(address >> 32);
1200
1201 d2h_r_idx_ptr = d2h_w_idx_ptr +
1202 max_completionrings * idx_offset;
1203 address += max_completionrings * idx_offset;
1204 ringinfo.d2h_r_idx_hostaddr.low_addr =
1205 cpu_to_le32(address & 0xffffffff);
1206 ringinfo.d2h_r_idx_hostaddr.high_addr =
1207 cpu_to_le32(address >> 32);
1208
1209 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1210 &ringinfo, sizeof(ringinfo));
1211 brcmf_dbg(PCIE, "Using host memory indices\n");
1212 }
1213
1214 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1215
1216 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1217 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1218 if (!ring)
1219 goto fail;
1220 ring->w_idx_addr = h2d_w_idx_ptr;
1221 ring->r_idx_addr = h2d_r_idx_ptr;
1222 ring->id = i;
1223 devinfo->shared.commonrings[i] = ring;
1224
1225 h2d_w_idx_ptr += idx_offset;
1226 h2d_r_idx_ptr += idx_offset;
1227 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1228 }
1229
1230 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1231 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1232 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1233 if (!ring)
1234 goto fail;
1235 ring->w_idx_addr = d2h_w_idx_ptr;
1236 ring->r_idx_addr = d2h_r_idx_ptr;
1237 ring->id = i;
1238 devinfo->shared.commonrings[i] = ring;
1239
1240 d2h_w_idx_ptr += idx_offset;
1241 d2h_r_idx_ptr += idx_offset;
1242 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1243 }
1244
1245 devinfo->shared.max_flowrings = max_flowrings;
1246 devinfo->shared.max_submissionrings = max_submissionrings;
1247 devinfo->shared.max_completionrings = max_completionrings;
1248 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1249 if (!rings)
1250 goto fail;
1251
1252 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1253
1254 for (i = 0; i < max_flowrings; i++) {
1255 ring = &rings[i];
1256 ring->devinfo = devinfo;
1257 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1258 brcmf_commonring_register_cb(&ring->commonring,
1259 brcmf_pcie_ring_mb_ring_bell,
1260 brcmf_pcie_ring_mb_update_rptr,
1261 brcmf_pcie_ring_mb_update_wptr,
1262 brcmf_pcie_ring_mb_write_rptr,
1263 brcmf_pcie_ring_mb_write_wptr,
1264 ring);
1265 ring->w_idx_addr = h2d_w_idx_ptr;
1266 ring->r_idx_addr = h2d_r_idx_ptr;
1267 h2d_w_idx_ptr += idx_offset;
1268 h2d_r_idx_ptr += idx_offset;
1269 }
1270 devinfo->shared.flowrings = rings;
1271
1272 return 0;
1273
1274fail:
1275 brcmf_err(bus, "Allocating ring buffers failed\n");
1276 brcmf_pcie_release_ringbuffers(devinfo);
1277 return -ENOMEM;
1278}
1279
1280
1281static void
1282brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1283{
1284 if (devinfo->shared.scratch)
1285 dma_free_coherent(&devinfo->pdev->dev,
1286 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1287 devinfo->shared.scratch,
1288 devinfo->shared.scratch_dmahandle);
1289 if (devinfo->shared.ringupd)
1290 dma_free_coherent(&devinfo->pdev->dev,
1291 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1292 devinfo->shared.ringupd,
1293 devinfo->shared.ringupd_dmahandle);
1294}
1295
1296static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1297{
1298 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1299 u64 address;
1300 u32 addr;
1301
1302 devinfo->shared.scratch =
1303 dma_alloc_coherent(&devinfo->pdev->dev,
1304 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1305 &devinfo->shared.scratch_dmahandle,
1306 GFP_KERNEL);
1307 if (!devinfo->shared.scratch)
1308 goto fail;
1309
1310 addr = devinfo->shared.tcm_base_address +
1311 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1312 address = (u64)devinfo->shared.scratch_dmahandle;
1313 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1314 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1315 addr = devinfo->shared.tcm_base_address +
1316 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1317 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1318
1319 devinfo->shared.ringupd =
1320 dma_alloc_coherent(&devinfo->pdev->dev,
1321 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1322 &devinfo->shared.ringupd_dmahandle,
1323 GFP_KERNEL);
1324 if (!devinfo->shared.ringupd)
1325 goto fail;
1326
1327 addr = devinfo->shared.tcm_base_address +
1328 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1329 address = (u64)devinfo->shared.ringupd_dmahandle;
1330 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1331 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1332 addr = devinfo->shared.tcm_base_address +
1333 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1334 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1335 return 0;
1336
1337fail:
1338 brcmf_err(bus, "Allocating scratch buffers failed\n");
1339 brcmf_pcie_release_scratchbuffers(devinfo);
1340 return -ENOMEM;
1341}
1342
1343
1344static void brcmf_pcie_down(struct device *dev)
1345{
1346}
1347
1348
1349static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1350{
1351 return 0;
1352}
1353
1354
1355static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1356 uint len)
1357{
1358 return 0;
1359}
1360
1361
1362static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1363 uint len)
1364{
1365 return 0;
1366}
1367
1368
1369static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1370{
1371 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1372 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1373 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1374
1375 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1376 devinfo->wowl_enabled = enabled;
1377}
1378
1379
1380static size_t brcmf_pcie_get_ramsize(struct device *dev)
1381{
1382 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1383 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1384 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1385
1386 return devinfo->ci->ramsize - devinfo->ci->srsize;
1387}
1388
1389
1390static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1391{
1392 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1393 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1394 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1395
1396 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1397 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1398 return 0;
1399}
1400
1401static
1402int brcmf_pcie_get_fwname(struct device *dev, const char *ext, u8 *fw_name)
1403{
1404 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1405 struct brcmf_fw_request *fwreq;
1406 struct brcmf_fw_name fwnames[] = {
1407 { ext, fw_name },
1408 };
1409
1410 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev,
1411 brcmf_pcie_fwnames,
1412 ARRAY_SIZE(brcmf_pcie_fwnames),
1413 fwnames, ARRAY_SIZE(fwnames));
1414 if (!fwreq)
1415 return -ENOMEM;
1416
1417 kfree(fwreq);
1418 return 0;
1419}
1420
1421static int brcmf_pcie_reset(struct device *dev)
1422{
1423 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1424 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1425 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1426 struct brcmf_fw_request *fwreq;
1427 int err;
1428
1429 brcmf_pcie_bus_console_read(devinfo, true);
1430
1431 brcmf_detach(dev);
1432
1433 brcmf_pcie_release_irq(devinfo);
1434 brcmf_pcie_release_scratchbuffers(devinfo);
1435 brcmf_pcie_release_ringbuffers(devinfo);
1436 brcmf_pcie_reset_device(devinfo);
1437
1438 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
1439 if (!fwreq) {
1440 dev_err(dev, "Failed to prepare FW request\n");
1441 return -ENOMEM;
1442 }
1443
1444 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup);
1445 if (err) {
1446 dev_err(dev, "Failed to prepare FW request\n");
1447 kfree(fwreq);
1448 }
1449
1450 return err;
1451}
1452
1453static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1454 .txdata = brcmf_pcie_tx,
1455 .stop = brcmf_pcie_down,
1456 .txctl = brcmf_pcie_tx_ctlpkt,
1457 .rxctl = brcmf_pcie_rx_ctlpkt,
1458 .wowl_config = brcmf_pcie_wowl_config,
1459 .get_ramsize = brcmf_pcie_get_ramsize,
1460 .get_memdump = brcmf_pcie_get_memdump,
1461 .get_fwname = brcmf_pcie_get_fwname,
1462 .reset = brcmf_pcie_reset,
1463};
1464
1465
1466static void
1467brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1468 u32 data_len)
1469{
1470 __le32 *field;
1471 u32 newsize;
1472
1473 if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1474 return;
1475
1476 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1477 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1478 return;
1479 field++;
1480 newsize = le32_to_cpup(field);
1481
1482 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1483 newsize);
1484 devinfo->ci->ramsize = newsize;
1485}
1486
1487
1488static int
1489brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1490 u32 sharedram_addr)
1491{
1492 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1493 struct brcmf_pcie_shared_info *shared;
1494 u32 addr;
1495
1496 shared = &devinfo->shared;
1497 shared->tcm_base_address = sharedram_addr;
1498
1499 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1500 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1501 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1502 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1503 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1504 brcmf_err(bus, "Unsupported PCIE version %d\n",
1505 shared->version);
1506 return -EINVAL;
1507 }
1508
1509
1510 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1511 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1512 devinfo->dma_idx_sz = sizeof(u16);
1513 else
1514 devinfo->dma_idx_sz = sizeof(u32);
1515 }
1516
1517 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1518 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1519 if (shared->max_rxbufpost == 0)
1520 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1521
1522 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1523 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1524
1525 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1526 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1527
1528 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1529 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1530
1531 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1532 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1533
1534 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1535 shared->max_rxbufpost, shared->rx_dataoffset);
1536
1537 brcmf_pcie_bus_console_init(devinfo);
1538
1539 return 0;
1540}
1541
1542
1543static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1544 const struct firmware *fw, void *nvram,
1545 u32 nvram_len)
1546{
1547 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1548 u32 sharedram_addr;
1549 u32 sharedram_addr_written;
1550 u32 loop_counter;
1551 int err;
1552 u32 address;
1553 u32 resetintr;
1554
1555 brcmf_dbg(PCIE, "Halt ARM.\n");
1556 err = brcmf_pcie_enter_download_state(devinfo);
1557 if (err)
1558 return err;
1559
1560 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1561 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1562 (void *)fw->data, fw->size);
1563
1564 resetintr = get_unaligned_le32(fw->data);
1565 release_firmware(fw);
1566
1567
1568
1569
1570 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1571
1572 if (nvram) {
1573 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1574 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1575 nvram_len;
1576 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1577 brcmf_fw_nvram_free(nvram);
1578 } else {
1579 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1580 devinfo->nvram_name);
1581 }
1582
1583 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1584 devinfo->ci->ramsize -
1585 4);
1586 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1587 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1588 if (err)
1589 return err;
1590
1591 brcmf_dbg(PCIE, "Wait for FW init\n");
1592 sharedram_addr = sharedram_addr_written;
1593 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1594 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1595 msleep(50);
1596 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1597 devinfo->ci->ramsize -
1598 4);
1599 loop_counter--;
1600 }
1601 if (sharedram_addr == sharedram_addr_written) {
1602 brcmf_err(bus, "FW failed to initialize\n");
1603 return -ENODEV;
1604 }
1605 if (sharedram_addr < devinfo->ci->rambase ||
1606 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) {
1607 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n",
1608 sharedram_addr);
1609 return -ENODEV;
1610 }
1611 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1612
1613 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1614}
1615
1616
1617static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1618{
1619 struct pci_dev *pdev = devinfo->pdev;
1620 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
1621 int err;
1622 phys_addr_t bar0_addr, bar1_addr;
1623 ulong bar1_size;
1624
1625 err = pci_enable_device(pdev);
1626 if (err) {
1627 brcmf_err(bus, "pci_enable_device failed err=%d\n", err);
1628 return err;
1629 }
1630
1631 pci_set_master(pdev);
1632
1633
1634 bar0_addr = pci_resource_start(pdev, 0);
1635
1636 bar1_addr = pci_resource_start(pdev, 2);
1637
1638 bar1_size = pci_resource_len(pdev, 2);
1639 if ((bar1_size == 0) || (bar1_addr == 0)) {
1640 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1641 bar1_size, (unsigned long long)bar1_addr);
1642 return -EINVAL;
1643 }
1644
1645 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1646 devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size);
1647
1648 if (!devinfo->regs || !devinfo->tcm) {
1649 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs,
1650 devinfo->tcm);
1651 return -EINVAL;
1652 }
1653 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1654 devinfo->regs, (unsigned long long)bar0_addr);
1655 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1656 devinfo->tcm, (unsigned long long)bar1_addr,
1657 (unsigned int)bar1_size);
1658
1659 return 0;
1660}
1661
1662
1663static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1664{
1665 if (devinfo->tcm)
1666 iounmap(devinfo->tcm);
1667 if (devinfo->regs)
1668 iounmap(devinfo->regs);
1669
1670 pci_disable_device(devinfo->pdev);
1671}
1672
1673
1674static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1675{
1676 u32 ret_addr;
1677
1678 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1679 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1680 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1681
1682 return ret_addr;
1683}
1684
1685
1686static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1687{
1688 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1689
1690 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1691 return brcmf_pcie_read_reg32(devinfo, addr);
1692}
1693
1694
1695static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1696{
1697 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1698
1699 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1700 brcmf_pcie_write_reg32(devinfo, addr, value);
1701}
1702
1703
1704static int brcmf_pcie_buscoreprep(void *ctx)
1705{
1706 return brcmf_pcie_get_resource(ctx);
1707}
1708
1709
1710static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1711{
1712 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1713 u32 val;
1714
1715 devinfo->ci = chip;
1716 brcmf_pcie_reset_device(devinfo);
1717
1718 val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1719 if (val != 0xffffffff)
1720 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1721 val);
1722
1723 return 0;
1724}
1725
1726
1727static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1728 u32 rstvec)
1729{
1730 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1731
1732 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1733}
1734
1735
1736static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1737 .prepare = brcmf_pcie_buscoreprep,
1738 .reset = brcmf_pcie_buscore_reset,
1739 .activate = brcmf_pcie_buscore_activate,
1740 .read32 = brcmf_pcie_buscore_read32,
1741 .write32 = brcmf_pcie_buscore_write32,
1742};
1743
1744#define BRCMF_PCIE_FW_CODE 0
1745#define BRCMF_PCIE_FW_NVRAM 1
1746
1747static void brcmf_pcie_setup(struct device *dev, int ret,
1748 struct brcmf_fw_request *fwreq)
1749{
1750 const struct firmware *fw;
1751 void *nvram;
1752 struct brcmf_bus *bus;
1753 struct brcmf_pciedev *pcie_bus_dev;
1754 struct brcmf_pciedev_info *devinfo;
1755 struct brcmf_commonring **flowrings;
1756 u32 i, nvram_len;
1757
1758
1759 if (ret)
1760 goto fail;
1761
1762 bus = dev_get_drvdata(dev);
1763 pcie_bus_dev = bus->bus_priv.pcie;
1764 devinfo = pcie_bus_dev->devinfo;
1765 brcmf_pcie_attach(devinfo);
1766
1767 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary;
1768 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data;
1769 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len;
1770 kfree(fwreq);
1771
1772
1773
1774
1775
1776
1777 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
1778
1779 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1780 if (ret)
1781 goto fail;
1782
1783 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1784
1785 ret = brcmf_pcie_init_ringbuffers(devinfo);
1786 if (ret)
1787 goto fail;
1788
1789 ret = brcmf_pcie_init_scratchbuffers(devinfo);
1790 if (ret)
1791 goto fail;
1792
1793 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1794 ret = brcmf_pcie_request_irq(devinfo);
1795 if (ret)
1796 goto fail;
1797
1798
1799 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1800 bus->msgbuf->commonrings[i] =
1801 &devinfo->shared.commonrings[i]->commonring;
1802
1803 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
1804 GFP_KERNEL);
1805 if (!flowrings)
1806 goto fail;
1807
1808 for (i = 0; i < devinfo->shared.max_flowrings; i++)
1809 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1810 bus->msgbuf->flowrings = flowrings;
1811
1812 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1813 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1814 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
1815
1816 init_waitqueue_head(&devinfo->mbdata_resp_wait);
1817
1818 brcmf_pcie_intr_enable(devinfo);
1819 brcmf_pcie_hostready(devinfo);
1820 if (brcmf_attach(&devinfo->pdev->dev, devinfo->settings) == 0)
1821 return;
1822
1823 brcmf_pcie_bus_console_read(devinfo, false);
1824
1825fail:
1826 device_release_driver(dev);
1827}
1828
1829static struct brcmf_fw_request *
1830brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo)
1831{
1832 struct brcmf_fw_request *fwreq;
1833 struct brcmf_fw_name fwnames[] = {
1834 { ".bin", devinfo->fw_name },
1835 { ".txt", devinfo->nvram_name },
1836 };
1837
1838 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev,
1839 brcmf_pcie_fwnames,
1840 ARRAY_SIZE(brcmf_pcie_fwnames),
1841 fwnames, ARRAY_SIZE(fwnames));
1842 if (!fwreq)
1843 return NULL;
1844
1845 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
1846 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
1847 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL;
1848 fwreq->board_type = devinfo->settings->board_type;
1849
1850 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1;
1851 fwreq->bus_nr = devinfo->pdev->bus->number;
1852
1853 return fwreq;
1854}
1855
1856static int
1857brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1858{
1859 int ret;
1860 struct brcmf_fw_request *fwreq;
1861 struct brcmf_pciedev_info *devinfo;
1862 struct brcmf_pciedev *pcie_bus_dev;
1863 struct brcmf_bus *bus;
1864
1865 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
1866
1867 ret = -ENOMEM;
1868 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1869 if (devinfo == NULL)
1870 return ret;
1871
1872 devinfo->pdev = pdev;
1873 pcie_bus_dev = NULL;
1874 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1875 if (IS_ERR(devinfo->ci)) {
1876 ret = PTR_ERR(devinfo->ci);
1877 devinfo->ci = NULL;
1878 goto fail;
1879 }
1880
1881 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1882 if (pcie_bus_dev == NULL) {
1883 ret = -ENOMEM;
1884 goto fail;
1885 }
1886
1887 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
1888 BRCMF_BUSTYPE_PCIE,
1889 devinfo->ci->chip,
1890 devinfo->ci->chiprev);
1891 if (!devinfo->settings) {
1892 ret = -ENOMEM;
1893 goto fail;
1894 }
1895
1896 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1897 if (!bus) {
1898 ret = -ENOMEM;
1899 goto fail;
1900 }
1901 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1902 if (!bus->msgbuf) {
1903 ret = -ENOMEM;
1904 kfree(bus);
1905 goto fail;
1906 }
1907
1908
1909 pcie_bus_dev->devinfo = devinfo;
1910 pcie_bus_dev->bus = bus;
1911 bus->dev = &pdev->dev;
1912 bus->bus_priv.pcie = pcie_bus_dev;
1913 bus->ops = &brcmf_pcie_bus_ops;
1914 bus->proto_type = BRCMF_PROTO_MSGBUF;
1915 bus->chip = devinfo->coreid;
1916 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1917 dev_set_drvdata(&pdev->dev, bus);
1918
1919 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
1920 if (!fwreq) {
1921 ret = -ENOMEM;
1922 goto fail_bus;
1923 }
1924
1925 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup);
1926 if (ret < 0) {
1927 kfree(fwreq);
1928 goto fail_bus;
1929 }
1930 return 0;
1931
1932fail_bus:
1933 kfree(bus->msgbuf);
1934 kfree(bus);
1935fail:
1936 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device);
1937 brcmf_pcie_release_resource(devinfo);
1938 if (devinfo->ci)
1939 brcmf_chip_detach(devinfo->ci);
1940 if (devinfo->settings)
1941 brcmf_release_module_param(devinfo->settings);
1942 kfree(pcie_bus_dev);
1943 kfree(devinfo);
1944 return ret;
1945}
1946
1947
1948static void
1949brcmf_pcie_remove(struct pci_dev *pdev)
1950{
1951 struct brcmf_pciedev_info *devinfo;
1952 struct brcmf_bus *bus;
1953
1954 brcmf_dbg(PCIE, "Enter\n");
1955
1956 bus = dev_get_drvdata(&pdev->dev);
1957 if (bus == NULL)
1958 return;
1959
1960 devinfo = bus->bus_priv.pcie->devinfo;
1961
1962 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1963 if (devinfo->ci)
1964 brcmf_pcie_intr_disable(devinfo);
1965
1966 brcmf_detach(&pdev->dev);
1967
1968 kfree(bus->bus_priv.pcie);
1969 kfree(bus->msgbuf->flowrings);
1970 kfree(bus->msgbuf);
1971 kfree(bus);
1972
1973 brcmf_pcie_release_irq(devinfo);
1974 brcmf_pcie_release_scratchbuffers(devinfo);
1975 brcmf_pcie_release_ringbuffers(devinfo);
1976 brcmf_pcie_reset_device(devinfo);
1977 brcmf_pcie_release_resource(devinfo);
1978
1979 if (devinfo->ci)
1980 brcmf_chip_detach(devinfo->ci);
1981 if (devinfo->settings)
1982 brcmf_release_module_param(devinfo->settings);
1983
1984 kfree(devinfo);
1985 dev_set_drvdata(&pdev->dev, NULL);
1986}
1987
1988
1989#ifdef CONFIG_PM
1990
1991
1992static int brcmf_pcie_pm_enter_D3(struct device *dev)
1993{
1994 struct brcmf_pciedev_info *devinfo;
1995 struct brcmf_bus *bus;
1996
1997 brcmf_dbg(PCIE, "Enter\n");
1998
1999 bus = dev_get_drvdata(dev);
2000 devinfo = bus->bus_priv.pcie->devinfo;
2001
2002 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
2003
2004 devinfo->mbdata_completed = false;
2005 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
2006
2007 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
2008 BRCMF_PCIE_MBDATA_TIMEOUT);
2009 if (!devinfo->mbdata_completed) {
2010 brcmf_err(bus, "Timeout on response for entering D3 substate\n");
2011 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2012 return -EIO;
2013 }
2014
2015 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2016
2017 return 0;
2018}
2019
2020
2021static int brcmf_pcie_pm_leave_D3(struct device *dev)
2022{
2023 struct brcmf_pciedev_info *devinfo;
2024 struct brcmf_bus *bus;
2025 struct pci_dev *pdev;
2026 int err;
2027
2028 brcmf_dbg(PCIE, "Enter\n");
2029
2030 bus = dev_get_drvdata(dev);
2031 devinfo = bus->bus_priv.pcie->devinfo;
2032 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
2033
2034
2035 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
2036 brcmf_dbg(PCIE, "Try to wakeup device....\n");
2037 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
2038 goto cleanup;
2039 brcmf_dbg(PCIE, "Hot resume, continue....\n");
2040 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2041 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2042 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2043 brcmf_pcie_intr_enable(devinfo);
2044 brcmf_pcie_hostready(devinfo);
2045 return 0;
2046 }
2047
2048cleanup:
2049 brcmf_chip_detach(devinfo->ci);
2050 devinfo->ci = NULL;
2051 pdev = devinfo->pdev;
2052 brcmf_pcie_remove(pdev);
2053
2054 err = brcmf_pcie_probe(pdev, NULL);
2055 if (err)
2056 brcmf_err(bus, "probe after resume failed, err=%d\n", err);
2057
2058 return err;
2059}
2060
2061
2062static const struct dev_pm_ops brcmf_pciedrvr_pm = {
2063 .suspend = brcmf_pcie_pm_enter_D3,
2064 .resume = brcmf_pcie_pm_leave_D3,
2065 .freeze = brcmf_pcie_pm_enter_D3,
2066 .restore = brcmf_pcie_pm_leave_D3,
2067};
2068
2069
2070#endif
2071
2072
2073#define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
2074 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
2075#define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev) { \
2076 BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
2077 subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
2078
2079static const struct pci_device_id brcmf_pcie_devid_table[] = {
2080 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
2081 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355),
2082 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID),
2083 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
2084 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
2085 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
2086 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
2087 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
2088 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
2089 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
2090 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
2091 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
2092 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
2093 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
2094 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
2095 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365),
2096 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
2097 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
2098 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
2099 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
2100 { }
2101};
2102
2103
2104MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2105
2106
2107static struct pci_driver brcmf_pciedrvr = {
2108 .node = {},
2109 .name = KBUILD_MODNAME,
2110 .id_table = brcmf_pcie_devid_table,
2111 .probe = brcmf_pcie_probe,
2112 .remove = brcmf_pcie_remove,
2113#ifdef CONFIG_PM
2114 .driver.pm = &brcmf_pciedrvr_pm,
2115#endif
2116 .driver.coredump = brcmf_dev_coredump,
2117};
2118
2119
2120void brcmf_pcie_register(void)
2121{
2122 int err;
2123
2124 brcmf_dbg(PCIE, "Enter\n");
2125 err = pci_register_driver(&brcmf_pciedrvr);
2126 if (err)
2127 brcmf_err(NULL, "PCIE driver registration failed, err=%d\n",
2128 err);
2129}
2130
2131
2132void brcmf_pcie_exit(void)
2133{
2134 brcmf_dbg(PCIE, "Enter\n");
2135 pci_unregister_driver(&brcmf_pciedrvr);
2136}
2137
