LXR linux/drivers/net/wireless/intel/iwlwifi/iwl-config.h

   1/******************************************************************************
   2 *
   3 * This file is provided under a dual BSD/GPLv2 license.  When using or
   4 * redistributing this file, you may do so under either license.
   5 *
   6 * GPL LICENSE SUMMARY
   7 *
   8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9 * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
  10 * Copyright(c) 2018 - 2019 Intel Corporation
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of version 2 of the GNU General Public License as
  14 * published by the Free Software Foundation.
  15 *
  16 * This program is distributed in the hope that it will be useful, but
  17 * WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 * General Public License for more details.
  20 *
  21 * The full GNU General Public License is included in this distribution
  22 * in the file called COPYING.
  23 *
  24 * Contact Information:
  25 *  Intel Linux Wireless <linuxwifi@intel.com>
  26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27 *
  28 * BSD LICENSE
  29 *
  30 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  31 * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
  32 * Copyright(c) 2018 - 2019 Intel Corporation
  33 * All rights reserved.
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  55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  61 *****************************************************************************/
  62#ifndef __IWL_CONFIG_H__
  63#define __IWL_CONFIG_H__
  64
  65#include <linux/types.h>
  66#include <linux/netdevice.h>
  67#include <linux/ieee80211.h>
  68#include <linux/nl80211.h>
  69#include "iwl-csr.h"
  70
  71enum iwl_device_family {
  72        IWL_DEVICE_FAMILY_UNDEFINED,
  73        IWL_DEVICE_FAMILY_1000,
  74        IWL_DEVICE_FAMILY_100,
  75        IWL_DEVICE_FAMILY_2000,
  76        IWL_DEVICE_FAMILY_2030,
  77        IWL_DEVICE_FAMILY_105,
  78        IWL_DEVICE_FAMILY_135,
  79        IWL_DEVICE_FAMILY_5000,
  80        IWL_DEVICE_FAMILY_5150,
  81        IWL_DEVICE_FAMILY_6000,
  82        IWL_DEVICE_FAMILY_6000i,
  83        IWL_DEVICE_FAMILY_6005,
  84        IWL_DEVICE_FAMILY_6030,
  85        IWL_DEVICE_FAMILY_6050,
  86        IWL_DEVICE_FAMILY_6150,
  87        IWL_DEVICE_FAMILY_7000,
  88        IWL_DEVICE_FAMILY_8000,
  89        IWL_DEVICE_FAMILY_9000,
  90        IWL_DEVICE_FAMILY_22000,
  91        IWL_DEVICE_FAMILY_22560,
  92        IWL_DEVICE_FAMILY_AX210,
  93};
  94
  95/*
  96 * LED mode
  97 *    IWL_LED_DEFAULT:  use device default
  98 *    IWL_LED_RF_STATE: turn LED on/off based on RF state
  99 *                      LED ON  = RF ON
 100 *                      LED OFF = RF OFF
 101 *    IWL_LED_BLINK:    adjust led blink rate based on blink table
 102 *    IWL_LED_DISABLE:  led disabled
 103 */
 104enum iwl_led_mode {
 105        IWL_LED_DEFAULT,
 106        IWL_LED_RF_STATE,
 107        IWL_LED_BLINK,
 108        IWL_LED_DISABLE,
 109};
 110
 111/**
 112 * enum iwl_nvm_type - nvm formats
 113 * @IWL_NVM: the regular format
 114 * @IWL_NVM_EXT: extended NVM format
 115 * @IWL_NVM_SDP: NVM format used by 3168 series
 116 */
 117enum iwl_nvm_type {
 118        IWL_NVM,
 119        IWL_NVM_EXT,
 120        IWL_NVM_SDP,
 121};
 122
 123/*
 124 * This is the threshold value of plcp error rate per 100mSecs.  It is
 125 * used to set and check for the validity of plcp_delta.
 126 */
 127#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN          1
 128#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF          50
 129#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF     100
 130#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF 200
 131#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX          255
 132#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE      0
 133
 134/* TX queue watchdog timeouts in mSecs */
 135#define IWL_WATCHDOG_DISABLED   0
 136#define IWL_DEF_WD_TIMEOUT      2500
 137#define IWL_LONG_WD_TIMEOUT     10000
 138#define IWL_MAX_WD_TIMEOUT      120000
 139
 140#define IWL_DEFAULT_MAX_TX_POWER 22
 141#define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\
 142                                 NETIF_F_TSO | NETIF_F_TSO6)
 143
 144/* Antenna presence definitions */
 145#define ANT_NONE        0x0
 146#define ANT_INVALID     0xff
 147#define ANT_A           BIT(0)
 148#define ANT_B           BIT(1)
 149#define ANT_C           BIT(2)
 150#define ANT_AB          (ANT_A | ANT_B)
 151#define ANT_AC          (ANT_A | ANT_C)
 152#define ANT_BC          (ANT_B | ANT_C)
 153#define ANT_ABC         (ANT_A | ANT_B | ANT_C)
 154#define MAX_ANT_NUM 3
 155
 156
 157static inline u8 num_of_ant(u8 mask)
 158{
 159        return  !!((mask) & ANT_A) +
 160                !!((mask) & ANT_B) +
 161                !!((mask) & ANT_C);
 162}
 163
 164/*
 165 * @max_ll_items: max number of OTP blocks
 166 * @shadow_ram_support: shadow support for OTP memory
 167 * @led_compensation: compensate on the led on/off time per HW according
 168 *      to the deviation to achieve the desired led frequency.
 169 *      The detail algorithm is described in iwl-led.c
 170 * @wd_timeout: TX queues watchdog timeout
 171 * @max_event_log_size: size of event log buffer size for ucode event logging
 172 * @shadow_reg_enable: HW shadow register support
 173 * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command
 174 *      is in flight. This is due to a HW bug in 7260, 3160 and 7265.
 175 * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled.
 176 * @max_tfd_queue_size: max number of entries in tfd queue.
 177 */
 178struct iwl_base_params {
 179        unsigned int wd_timeout;
 180
 181        u16 eeprom_size;
 182        u16 max_event_log_size;
 183
 184        u8 pll_cfg:1, /* for iwl_pcie_apm_init() */
 185           shadow_ram_support:1,
 186           shadow_reg_enable:1,
 187           pcie_l1_allowed:1,
 188           apmg_wake_up_wa:1,
 189           scd_chain_ext_wa:1;
 190
 191        u16 num_of_queues;      /* def: HW dependent */
 192        u32 max_tfd_queue_size; /* def: HW dependent */
 193
 194        u8 max_ll_items;
 195        u8 led_compensation;
 196};
 197
 198/*
 199 * @stbc: support Tx STBC and 1*SS Rx STBC
 200 * @ldpc: support Tx/Rx with LDPC
 201 * @use_rts_for_aggregation: use rts/cts protection for HT traffic
 202 * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40
 203 */
 204struct iwl_ht_params {
 205        u8 ht_greenfield_support:1,
 206           stbc:1,
 207           ldpc:1,
 208           use_rts_for_aggregation:1;
 209        u8 ht40_bands;
 210};
 211
 212/*
 213 * Tx-backoff threshold
 214 * @temperature: The threshold in Celsius
 215 * @backoff: The tx-backoff in uSec
 216 */
 217struct iwl_tt_tx_backoff {
 218        s32 temperature;
 219        u32 backoff;
 220};
 221
 222#define TT_TX_BACKOFF_SIZE 6
 223
 224/**
 225 * struct iwl_tt_params - thermal throttling parameters
 226 * @ct_kill_entry: CT Kill entry threshold
 227 * @ct_kill_exit: CT Kill exit threshold
 228 * @ct_kill_duration: The time  intervals (in uSec) in which the driver needs
 229 *      to checks whether to exit CT Kill.
 230 * @dynamic_smps_entry: Dynamic SMPS entry threshold
 231 * @dynamic_smps_exit: Dynamic SMPS exit threshold
 232 * @tx_protection_entry: TX protection entry threshold
 233 * @tx_protection_exit: TX protection exit threshold
 234 * @tx_backoff: Array of thresholds for tx-backoff , in ascending order.
 235 * @support_ct_kill: Support CT Kill?
 236 * @support_dynamic_smps: Support dynamic SMPS?
 237 * @support_tx_protection: Support tx protection?
 238 * @support_tx_backoff: Support tx-backoff?
 239 */
 240struct iwl_tt_params {
 241        u32 ct_kill_entry;
 242        u32 ct_kill_exit;
 243        u32 ct_kill_duration;
 244        u32 dynamic_smps_entry;
 245        u32 dynamic_smps_exit;
 246        u32 tx_protection_entry;
 247        u32 tx_protection_exit;
 248        struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE];
 249        u8 support_ct_kill:1,
 250           support_dynamic_smps:1,
 251           support_tx_protection:1,
 252           support_tx_backoff:1;
 253};
 254
 255/*
 256 * information on how to parse the EEPROM
 257 */
 258#define EEPROM_REG_BAND_1_CHANNELS              0x08
 259#define EEPROM_REG_BAND_2_CHANNELS              0x26
 260#define EEPROM_REG_BAND_3_CHANNELS              0x42
 261#define EEPROM_REG_BAND_4_CHANNELS              0x5C
 262#define EEPROM_REG_BAND_5_CHANNELS              0x74
 263#define EEPROM_REG_BAND_24_HT40_CHANNELS        0x82
 264#define EEPROM_REG_BAND_52_HT40_CHANNELS        0x92
 265#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS   0x80
 266#define EEPROM_REGULATORY_BAND_NO_HT40          0
 267
 268/* lower blocks contain EEPROM image and calibration data */
 269#define OTP_LOW_IMAGE_SIZE_2K           (2 * 512 * sizeof(u16))  /*  2 KB */
 270#define OTP_LOW_IMAGE_SIZE_16K          (16 * 512 * sizeof(u16)) /* 16 KB */
 271#define OTP_LOW_IMAGE_SIZE_32K          (32 * 512 * sizeof(u16)) /* 32 KB */
 272
 273struct iwl_eeprom_params {
 274        const u8 regulatory_bands[7];
 275        bool enhanced_txpower;
 276};
 277
 278/* Tx-backoff power threshold
 279 * @pwr: The power limit in mw
 280 * @backoff: The tx-backoff in uSec
 281 */
 282struct iwl_pwr_tx_backoff {
 283        u32 pwr;
 284        u32 backoff;
 285};
 286
 287/**
 288 * struct iwl_csr_params
 289 *
 290 * @flag_sw_reset: reset the device
 291 * @flag_mac_clock_ready:
 292 *      Indicates MAC (ucode processor, etc.) is powered up and can run.
 293 *      Internal resources are accessible.
 294 *      NOTE:  This does not indicate that the processor is actually running.
 295 *      NOTE:  This does not indicate that device has completed
 296 *             init or post-power-down restore of internal SRAM memory.
 297 *             Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
 298 *             SRAM is restored and uCode is in normal operation mode.
 299 *             This note is relevant only for pre 5xxx devices.
 300 *      NOTE:  After device reset, this bit remains "0" until host sets
 301 *             INIT_DONE
 302 * @flag_init_done: Host sets this to put device into fully operational
 303 *      D0 power mode. Host resets this after SW_RESET to put device into
 304 *      low power mode.
 305 * @flag_mac_access_req: Host sets this to request and maintain MAC wakeup,
 306 *      to allow host access to device-internal resources. Host must wait for
 307 *      mac_clock_ready (and !GOING_TO_SLEEP) before accessing non-CSR device
 308 *      registers.
 309 * @flag_val_mac_access_en: mac access is enabled
 310 * @flag_master_dis: disable master
 311 * @flag_stop_master: stop master
 312 * @addr_sw_reset: address for resetting the device
 313 * @mac_addr0_otp: first part of MAC address from OTP
 314 * @mac_addr1_otp: second part of MAC address from OTP
 315 * @mac_addr0_strap: first part of MAC address from strap
 316 * @mac_addr1_strap: second part of MAC address from strap
 317 */
 318struct iwl_csr_params {
 319        u8 flag_sw_reset;
 320        u8 flag_mac_clock_ready;
 321        u8 flag_init_done;
 322        u8 flag_mac_access_req;
 323        u8 flag_val_mac_access_en;
 324        u8 flag_master_dis;
 325        u8 flag_stop_master;
 326        u8 addr_sw_reset;
 327        u32 mac_addr0_otp;
 328        u32 mac_addr1_otp;
 329        u32 mac_addr0_strap;
 330        u32 mac_addr1_strap;
 331};
 332
 333/**
 334 * struct iwl_cfg
 335 * @name: Official name of the device
 336 * @fw_name_pre: Firmware filename prefix. The api version and extension
 337 *      (.ucode) will be added to filename before loading from disk. The
 338 *      filename is constructed as fw_name_pre<api>.ucode.
 339 * @ucode_api_max: Highest version of uCode API supported by driver.
 340 * @ucode_api_min: Lowest version of uCode API supported by driver.
 341 * @max_inst_size: The maximal length of the fw inst section (only DVM)
 342 * @max_data_size: The maximal length of the fw data section (only DVM)
 343 * @valid_tx_ant: valid transmit antenna
 344 * @valid_rx_ant: valid receive antenna
 345 * @non_shared_ant: the antenna that is for WiFi only
 346 * @nvm_ver: NVM version
 347 * @nvm_calib_ver: NVM calibration version
 348 * @lib: pointer to the lib ops
 349 * @base_params: pointer to basic parameters
 350 * @ht_params: point to ht parameters
 351 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
 352 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
 353 * @internal_wimax_coex: internal wifi/wimax combo device
 354 * @high_temp: Is this NIC is designated to be in high temperature.
 355 * @host_interrupt_operation_mode: device needs host interrupt operation
 356 *      mode set
 357 * @nvm_hw_section_num: the ID of the HW NVM section
 358 * @mac_addr_from_csr: read HW address from CSR registers
 359 * @features: hw features, any combination of feature_whitelist
 360 * @pwr_tx_backoffs: translation table between power limits and backoffs
 361 * @csr: csr flags and addresses that are different across devices
 362 * @max_rx_agg_size: max RX aggregation size of the ADDBA request/response
 363 * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
 364 * @max_ht_ampdu_factor: the exponent of the max length of A-MPDU that the
 365 *      station can receive in HT
 366 * @max_vht_ampdu_exponent: the exponent of the max length of A-MPDU that the
 367 *      station can receive in VHT
 368 * @dccm_offset: offset from which DCCM begins
 369 * @dccm_len: length of DCCM (including runtime stack CCM)
 370 * @dccm2_offset: offset from which the second DCCM begins
 371 * @dccm2_len: length of the second DCCM
 372 * @smem_offset: offset from which the SMEM begins
 373 * @smem_len: the length of SMEM
 374 * @mq_rx_supported: multi-queue rx support
 375 * @vht_mu_mimo_supported: VHT MU-MIMO support
 376 * @rf_id: need to read rf_id to determine the firmware image
 377 * @integrated: discrete or integrated
 378 * @gen2: 22000 and on transport operation
 379 * @cdb: CDB support
 380 * @nvm_type: see &enum iwl_nvm_type
 381 * @d3_debug_data_base_addr: base address where D3 debug data is stored
 382 * @d3_debug_data_length: length of the D3 debug data
 383 * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
 384 * @min_txq_size: minimum number of slots required in a TX queue
 385 * @umac_prph_offset: offset to add to UMAC periphery address
 386 * @uhb_supported: ultra high band channels supported
 387 * @min_256_ba_txq_size: minimum number of slots required in a TX queue which
 388 *      supports 256 BA aggregation
 389 *
 390 * We enable the driver to be backward compatible wrt. hardware features.
 391 * API differences in uCode shouldn't be handled here but through TLVs
 392 * and/or the uCode API version instead.
 393 */
 394struct iwl_cfg {
 395        /* params specific to an individual device within a device family */
 396        const char *name;
 397        const char *fw_name_pre;
 398        /* params not likely to change within a device family */
 399        const struct iwl_base_params *base_params;
 400        /* params likely to change within a device family */
 401        const struct iwl_ht_params *ht_params;
 402        const struct iwl_eeprom_params *eeprom_params;
 403        const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
 404        const char *default_nvm_file_C_step;
 405        const struct iwl_tt_params *thermal_params;
 406        const struct iwl_csr_params *csr;
 407        enum iwl_device_family device_family;
 408        enum iwl_led_mode led_mode;
 409        enum iwl_nvm_type nvm_type;
 410        u32 max_data_size;
 411        u32 max_inst_size;
 412        netdev_features_t features;
 413        u32 dccm_offset;
 414        u32 dccm_len;
 415        u32 dccm2_offset;
 416        u32 dccm2_len;
 417        u32 smem_offset;
 418        u32 smem_len;
 419        u32 soc_latency;
 420        u16 nvm_ver;
 421        u16 nvm_calib_ver;
 422        u32 rx_with_siso_diversity:1,
 423            bt_shared_single_ant:1,
 424            internal_wimax_coex:1,
 425            host_interrupt_operation_mode:1,
 426            high_temp:1,
 427            mac_addr_from_csr:1,
 428            lp_xtal_workaround:1,
 429            disable_dummy_notification:1,
 430            apmg_not_supported:1,
 431            mq_rx_supported:1,
 432            vht_mu_mimo_supported:1,
 433            rf_id:1,
 434            integrated:1,
 435            use_tfh:1,
 436            gen2:1,
 437            cdb:1,
 438            dbgc_supported:1,
 439            bisr_workaround:1,
 440            uhb_supported:1;
 441        u8 valid_tx_ant;
 442        u8 valid_rx_ant;
 443        u8 non_shared_ant;
 444        u8 nvm_hw_section_num;
 445        u8 max_rx_agg_size;
 446        u8 max_tx_agg_size;
 447        u8 max_ht_ampdu_exponent;
 448        u8 max_vht_ampdu_exponent;
 449        u8 ucode_api_max;
 450        u8 ucode_api_min;
 451        u32 min_umac_error_event_table;
 452        u32 extra_phy_cfg_flags;
 453        u32 d3_debug_data_base_addr;
 454        u32 d3_debug_data_length;
 455        u32 min_txq_size;
 456        u32 umac_prph_offset;
 457        u32 fw_mon_smem_write_ptr_addr;
 458        u32 fw_mon_smem_write_ptr_msk;
 459        u32 fw_mon_smem_cycle_cnt_ptr_addr;
 460        u32 fw_mon_smem_cycle_cnt_ptr_msk;
 461        u32 gp2_reg_addr;
 462        u32 min_256_ba_txq_size;
 463};
 464
 465extern const struct iwl_csr_params iwl_csr_v1;
 466extern const struct iwl_csr_params iwl_csr_v2;
 467
 468/*
 469 * This list declares the config structures for all devices.
 470 */
 471#if IS_ENABLED(CONFIG_IWLDVM)
 472extern const struct iwl_cfg iwl5300_agn_cfg;
 473extern const struct iwl_cfg iwl5100_agn_cfg;
 474extern const struct iwl_cfg iwl5350_agn_cfg;
 475extern const struct iwl_cfg iwl5100_bgn_cfg;
 476extern const struct iwl_cfg iwl5100_abg_cfg;
 477extern const struct iwl_cfg iwl5150_agn_cfg;
 478extern const struct iwl_cfg iwl5150_abg_cfg;
 479extern const struct iwl_cfg iwl6005_2agn_cfg;
 480extern const struct iwl_cfg iwl6005_2abg_cfg;
 481extern const struct iwl_cfg iwl6005_2bg_cfg;
 482extern const struct iwl_cfg iwl6005_2agn_sff_cfg;
 483extern const struct iwl_cfg iwl6005_2agn_d_cfg;
 484extern const struct iwl_cfg iwl6005_2agn_mow1_cfg;
 485extern const struct iwl_cfg iwl6005_2agn_mow2_cfg;
 486extern const struct iwl_cfg iwl1030_bgn_cfg;
 487extern const struct iwl_cfg iwl1030_bg_cfg;
 488extern const struct iwl_cfg iwl6030_2agn_cfg;
 489extern const struct iwl_cfg iwl6030_2abg_cfg;
 490extern const struct iwl_cfg iwl6030_2bgn_cfg;
 491extern const struct iwl_cfg iwl6030_2bg_cfg;
 492extern const struct iwl_cfg iwl6000i_2agn_cfg;
 493extern const struct iwl_cfg iwl6000i_2abg_cfg;
 494extern const struct iwl_cfg iwl6000i_2bg_cfg;
 495extern const struct iwl_cfg iwl6000_3agn_cfg;
 496extern const struct iwl_cfg iwl6050_2agn_cfg;
 497extern const struct iwl_cfg iwl6050_2abg_cfg;
 498extern const struct iwl_cfg iwl6150_bgn_cfg;
 499extern const struct iwl_cfg iwl6150_bg_cfg;
 500extern const struct iwl_cfg iwl1000_bgn_cfg;
 501extern const struct iwl_cfg iwl1000_bg_cfg;
 502extern const struct iwl_cfg iwl100_bgn_cfg;
 503extern const struct iwl_cfg iwl100_bg_cfg;
 504extern const struct iwl_cfg iwl130_bgn_cfg;
 505extern const struct iwl_cfg iwl130_bg_cfg;
 506extern const struct iwl_cfg iwl2000_2bgn_cfg;
 507extern const struct iwl_cfg iwl2000_2bgn_d_cfg;
 508extern const struct iwl_cfg iwl2030_2bgn_cfg;
 509extern const struct iwl_cfg iwl6035_2agn_cfg;
 510extern const struct iwl_cfg iwl6035_2agn_sff_cfg;
 511extern const struct iwl_cfg iwl105_bgn_cfg;
 512extern const struct iwl_cfg iwl105_bgn_d_cfg;
 513extern const struct iwl_cfg iwl135_bgn_cfg;
 514#endif /* CONFIG_IWLDVM */
 515#if IS_ENABLED(CONFIG_IWLMVM)
 516extern const struct iwl_cfg iwl7260_2ac_cfg;
 517extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp;
 518extern const struct iwl_cfg iwl7260_2n_cfg;
 519extern const struct iwl_cfg iwl7260_n_cfg;
 520extern const struct iwl_cfg iwl3160_2ac_cfg;
 521extern const struct iwl_cfg iwl3160_2n_cfg;
 522extern const struct iwl_cfg iwl3160_n_cfg;
 523extern const struct iwl_cfg iwl3165_2ac_cfg;
 524extern const struct iwl_cfg iwl3168_2ac_cfg;
 525extern const struct iwl_cfg iwl7265_2ac_cfg;
 526extern const struct iwl_cfg iwl7265_2n_cfg;
 527extern const struct iwl_cfg iwl7265_n_cfg;
 528extern const struct iwl_cfg iwl7265d_2ac_cfg;
 529extern const struct iwl_cfg iwl7265d_2n_cfg;
 530extern const struct iwl_cfg iwl7265d_n_cfg;
 531extern const struct iwl_cfg iwl8260_2n_cfg;
 532extern const struct iwl_cfg iwl8260_2ac_cfg;
 533extern const struct iwl_cfg iwl8265_2ac_cfg;
 534extern const struct iwl_cfg iwl8275_2ac_cfg;
 535extern const struct iwl_cfg iwl4165_2ac_cfg;
 536extern const struct iwl_cfg iwl9160_2ac_cfg;
 537extern const struct iwl_cfg iwl9260_2ac_cfg;
 538extern const struct iwl_cfg iwl9260_2ac_160_cfg;
 539extern const struct iwl_cfg iwl9260_killer_2ac_cfg;
 540extern const struct iwl_cfg iwl9270_2ac_cfg;
 541extern const struct iwl_cfg iwl9460_2ac_cfg;
 542extern const struct iwl_cfg iwl9560_2ac_cfg;
 543extern const struct iwl_cfg iwl9560_2ac_cfg_quz_a0_jf_b0_soc;
 544extern const struct iwl_cfg iwl9560_2ac_160_cfg;
 545extern const struct iwl_cfg iwl9560_2ac_160_cfg_quz_a0_jf_b0_soc;
 546extern const struct iwl_cfg iwl9460_2ac_cfg_soc;
 547extern const struct iwl_cfg iwl9461_2ac_cfg_soc;
 548extern const struct iwl_cfg iwl9461_2ac_cfg_quz_a0_jf_b0_soc;
 549extern const struct iwl_cfg iwl9462_2ac_cfg_soc;
 550extern const struct iwl_cfg iwl9462_2ac_cfg_quz_a0_jf_b0_soc;
 551extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
 552extern const struct iwl_cfg iwl9560_2ac_160_cfg_soc;
 553extern const struct iwl_cfg iwl9560_killer_2ac_cfg_soc;
 554extern const struct iwl_cfg iwl9560_killer_s_2ac_cfg_soc;
 555extern const struct iwl_cfg iwl9560_killer_i_2ac_cfg_quz_a0_jf_b0_soc;
 556extern const struct iwl_cfg iwl9560_killer_s_2ac_cfg_quz_a0_jf_b0_soc;
 557extern const struct iwl_cfg iwl9460_2ac_cfg_shared_clk;
 558extern const struct iwl_cfg iwl9461_2ac_cfg_shared_clk;
 559extern const struct iwl_cfg iwl9462_2ac_cfg_shared_clk;
 560extern const struct iwl_cfg iwl9560_2ac_cfg_shared_clk;
 561extern const struct iwl_cfg iwl9560_2ac_160_cfg_shared_clk;
 562extern const struct iwl_cfg iwl9560_killer_2ac_cfg_shared_clk;
 563extern const struct iwl_cfg iwl9560_killer_s_2ac_cfg_shared_clk;
 564extern const struct iwl_cfg iwl22000_2ac_cfg_hr;
 565extern const struct iwl_cfg iwl22000_2ac_cfg_hr_cdb;
 566extern const struct iwl_cfg iwl22000_2ac_cfg_jf;
 567extern const struct iwl_cfg iwl_ax101_cfg_qu_hr;
 568extern const struct iwl_cfg iwl_ax101_cfg_qu_c0_hr_b0;
 569extern const struct iwl_cfg iwl_ax101_cfg_quz_hr;
 570extern const struct iwl_cfg iwl22000_2ax_cfg_hr;
 571extern const struct iwl_cfg iwl_ax200_cfg_cc;
 572extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
 573extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
 574extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0;
 575extern const struct iwl_cfg iwl_ax201_cfg_quz_hr;
 576extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
 577extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
 578extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
 579extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
 580extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
 581extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
 582extern const struct iwl_cfg killer1650x_2ax_cfg;
 583extern const struct iwl_cfg killer1650w_2ax_cfg;
 584extern const struct iwl_cfg iwl9461_2ac_cfg_qu_b0_jf_b0;
 585extern const struct iwl_cfg iwl9462_2ac_cfg_qu_b0_jf_b0;
 586extern const struct iwl_cfg iwl9560_2ac_cfg_qu_b0_jf_b0;
 587extern const struct iwl_cfg iwl9560_2ac_160_cfg_qu_b0_jf_b0;
 588extern const struct iwl_cfg iwl9461_2ac_cfg_qu_c0_jf_b0;
 589extern const struct iwl_cfg iwl9462_2ac_cfg_qu_c0_jf_b0;
 590extern const struct iwl_cfg iwl9560_2ac_cfg_qu_c0_jf_b0;
 591extern const struct iwl_cfg iwl9560_2ac_160_cfg_qu_c0_jf_b0;
 592extern const struct iwl_cfg killer1550i_2ac_cfg_qu_b0_jf_b0;
 593extern const struct iwl_cfg killer1550s_2ac_cfg_qu_b0_jf_b0;
 594extern const struct iwl_cfg iwl22000_2ax_cfg_jf;
 595extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0_f0;
 596extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_b0_f0;
 597extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_b0;
 598extern const struct iwl_cfg iwl9560_2ac_cfg_qnj_jf_b0;
 599extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0;
 600extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0;
 601extern const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0;
 602extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
 603extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
 604extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
 605#endif /* CPTCFG_IWLMVM || CPTCFG_IWLFMAC */
 606
 607#endif /* __IWL_CONFIG_H__ */
 608