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64#ifndef __iwl_trans_h__
65#define __iwl_trans_h__
66
67#include <linux/ieee80211.h>
68#include <linux/mm.h>
69#include <linux/lockdep.h>
70#include <linux/kernel.h>
71
72#include "iwl-debug.h"
73#include "iwl-config.h"
74#include "fw/img.h"
75#include "iwl-op-mode.h"
76#include "fw/api/cmdhdr.h"
77#include "fw/api/txq.h"
78#include "fw/api/dbg-tlv.h"
79#include "iwl-dbg-tlv.h"
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115#define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF
116#define FH_RSCSR_FRAME_INVALID 0x55550000
117#define FH_RSCSR_FRAME_ALIGN 0x40
118#define FH_RSCSR_RPA_EN BIT(25)
119#define FH_RSCSR_RADA_EN BIT(26)
120#define FH_RSCSR_RXQ_POS 16
121#define FH_RSCSR_RXQ_MASK 0x3F0000
122
123struct iwl_rx_packet {
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141 __le32 len_n_flags;
142 struct iwl_cmd_header hdr;
143 u8 data[];
144} __packed;
145
146static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
147{
148 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
149}
150
151static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
152{
153 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
154}
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172enum CMD_MODE {
173 CMD_ASYNC = BIT(0),
174 CMD_WANT_SKB = BIT(1),
175 CMD_SEND_IN_RFKILL = BIT(2),
176 CMD_HIGH_PRIO = BIT(3),
177 CMD_SEND_IN_IDLE = BIT(4),
178 CMD_MAKE_TRANS_IDLE = BIT(5),
179 CMD_WAKE_UP_TRANS = BIT(6),
180 CMD_WANT_ASYNC_CALLBACK = BIT(7),
181};
182
183#define DEF_CMD_PAYLOAD_SIZE 320
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192struct iwl_device_cmd {
193 union {
194 struct {
195 struct iwl_cmd_header hdr;
196 u8 payload[DEF_CMD_PAYLOAD_SIZE];
197 };
198 struct {
199 struct iwl_cmd_header_wide hdr_wide;
200 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
201 sizeof(struct iwl_cmd_header_wide) +
202 sizeof(struct iwl_cmd_header)];
203 };
204 };
205} __packed;
206
207#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
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213#define IWL_MAX_CMD_TBS_PER_TFD 2
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230enum iwl_hcmd_dataflag {
231 IWL_HCMD_DFL_NOCOPY = BIT(0),
232 IWL_HCMD_DFL_DUP = BIT(1),
233};
234
235enum iwl_error_event_table_status {
236 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
237 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
238 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
239};
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254struct iwl_host_cmd {
255 const void *data[IWL_MAX_CMD_TBS_PER_TFD];
256 struct iwl_rx_packet *resp_pkt;
257 unsigned long _rx_page_addr;
258 u32 _rx_page_order;
259
260 u32 flags;
261 u32 id;
262 u16 len[IWL_MAX_CMD_TBS_PER_TFD];
263 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
264};
265
266static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
267{
268 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
269}
270
271struct iwl_rx_cmd_buffer {
272 struct page *_page;
273 int _offset;
274 bool _page_stolen;
275 u32 _rx_page_order;
276 unsigned int truesize;
277};
278
279static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
280{
281 return (void *)((unsigned long)page_address(r->_page) + r->_offset);
282}
283
284static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
285{
286 return r->_offset;
287}
288
289static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
290{
291 r->_page_stolen = true;
292 get_page(r->_page);
293 return r->_page;
294}
295
296static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
297{
298 __free_pages(r->_page, r->_rx_page_order);
299}
300
301#define MAX_NO_RECLAIM_CMDS 6
302
303#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
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309#define IWL_MAX_HW_QUEUES 32
310#define IWL_MAX_TVQM_QUEUES 512
311
312#define IWL_MAX_TID_COUNT 8
313#define IWL_MGMT_TID 15
314#define IWL_FRAME_LIMIT 64
315#define IWL_MAX_RX_HW_QUEUES 16
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322enum iwl_d3_status {
323 IWL_D3_STATUS_ALIVE,
324 IWL_D3_STATUS_RESET,
325};
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341enum iwl_trans_status {
342 STATUS_SYNC_HCMD_ACTIVE,
343 STATUS_DEVICE_ENABLED,
344 STATUS_TPOWER_PMI,
345 STATUS_INT_ENABLED,
346 STATUS_RFKILL_HW,
347 STATUS_RFKILL_OPMODE,
348 STATUS_FW_ERROR,
349 STATUS_TRANS_GOING_IDLE,
350 STATUS_TRANS_IDLE,
351 STATUS_TRANS_DEAD,
352};
353
354static inline int
355iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
356{
357 switch (rb_size) {
358 case IWL_AMSDU_2K:
359 return get_order(2 * 1024);
360 case IWL_AMSDU_4K:
361 return get_order(4 * 1024);
362 case IWL_AMSDU_8K:
363 return get_order(8 * 1024);
364 case IWL_AMSDU_12K:
365 return get_order(12 * 1024);
366 default:
367 WARN_ON(1);
368 return -1;
369 }
370}
371
372struct iwl_hcmd_names {
373 u8 cmd_id;
374 const char *const cmd_name;
375};
376
377#define HCMD_NAME(x) \
378 { .cmd_id = x, .cmd_name = #x }
379
380struct iwl_hcmd_arr {
381 const struct iwl_hcmd_names *arr;
382 int size;
383};
384
385#define HCMD_ARR(x) \
386 { .arr = x, .size = ARRAY_SIZE(x) }
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413struct iwl_trans_config {
414 struct iwl_op_mode *op_mode;
415
416 u8 cmd_queue;
417 u8 cmd_fifo;
418 unsigned int cmd_q_wdg_timeout;
419 const u8 *no_reclaim_cmds;
420 unsigned int n_no_reclaim_cmds;
421
422 enum iwl_amsdu_size rx_buf_size;
423 bool bc_table_dword;
424 bool scd_set_active;
425 bool sw_csum_tx;
426 const struct iwl_hcmd_arr *command_groups;
427 int command_groups_size;
428
429 u8 cb_data_offs;
430};
431
432struct iwl_trans_dump_data {
433 u32 len;
434 u8 data[];
435};
436
437struct iwl_trans;
438
439struct iwl_trans_txq_scd_cfg {
440 u8 fifo;
441 u8 sta_id;
442 u8 tid;
443 bool aggregate;
444 int frame_limit;
445};
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454struct iwl_trans_rxq_dma_data {
455 u64 fr_bd_cb;
456 u32 fr_bd_wid;
457 u64 urbd_stts_wrptr;
458 u64 ur_bd_cb;
459};
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549struct iwl_trans_ops {
550
551 int (*start_hw)(struct iwl_trans *iwl_trans, bool low_power);
552 void (*op_mode_leave)(struct iwl_trans *iwl_trans);
553 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
554 bool run_in_rfkill);
555 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
556 void (*stop_device)(struct iwl_trans *trans, bool low_power);
557
558 void (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
559 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
560 bool test, bool reset);
561
562 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
563
564 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
565 struct iwl_device_cmd *dev_cmd, int queue);
566 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
567 struct sk_buff_head *skbs);
568
569 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
570 const struct iwl_trans_txq_scd_cfg *cfg,
571 unsigned int queue_wdg_timeout);
572 void (*txq_disable)(struct iwl_trans *trans, int queue,
573 bool configure_scd);
574
575 int (*txq_alloc)(struct iwl_trans *trans,
576 __le16 flags, u8 sta_id, u8 tid,
577 int cmd_id, int size,
578 unsigned int queue_wdg_timeout);
579 void (*txq_free)(struct iwl_trans *trans, int queue);
580 int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
581 struct iwl_trans_rxq_dma_data *data);
582
583 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
584 bool shared);
585
586 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
587 int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
588 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
589 bool freeze);
590 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
591
592 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
593 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
594 u32 (*read32)(struct iwl_trans *trans, u32 ofs);
595 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
596 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
597 int (*read_mem)(struct iwl_trans *trans, u32 addr,
598 void *buf, int dwords);
599 int (*write_mem)(struct iwl_trans *trans, u32 addr,
600 const void *buf, int dwords);
601 void (*configure)(struct iwl_trans *trans,
602 const struct iwl_trans_config *trans_cfg);
603 void (*set_pmi)(struct iwl_trans *trans, bool state);
604 void (*sw_reset)(struct iwl_trans *trans);
605 bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags);
606 void (*release_nic_access)(struct iwl_trans *trans,
607 unsigned long *flags);
608 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
609 u32 value);
610 void (*ref)(struct iwl_trans *trans);
611 void (*unref)(struct iwl_trans *trans);
612 int (*suspend)(struct iwl_trans *trans);
613 void (*resume)(struct iwl_trans *trans);
614
615 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
616 u32 dump_mask);
617 void (*debugfs_cleanup)(struct iwl_trans *trans);
618 void (*sync_nmi)(struct iwl_trans *trans);
619};
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627enum iwl_trans_state {
628 IWL_TRANS_NO_FW = 0,
629 IWL_TRANS_FW_ALIVE = 1,
630};
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684enum iwl_plat_pm_mode {
685 IWL_PLAT_PM_MODE_DISABLED,
686 IWL_PLAT_PM_MODE_D3,
687 IWL_PLAT_PM_MODE_D0I3,
688};
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693#define IWL_TRANS_IDLE_TIMEOUT 2000
694
695
696#define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
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704struct iwl_dram_data {
705 dma_addr_t physical;
706 void *block;
707 int size;
708};
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717struct iwl_self_init_dram {
718 struct iwl_dram_data *fw;
719 int fw_cnt;
720 struct iwl_dram_data *paging;
721 int paging_cnt;
722};
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743struct iwl_trans_debug {
744 u8 n_dest_reg;
745 bool rec_on;
746
747 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
748 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
749 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
750
751 u32 lmac_error_event_table[2];
752 u32 umac_error_event_table;
753 unsigned int error_event_table_tlv_status;
754
755 bool external_ini_loaded;
756 bool ini_valid;
757
758 struct iwl_apply_point_data apply_points[IWL_FW_INI_APPLY_NUM];
759 struct iwl_apply_point_data apply_points_ext[IWL_FW_INI_APPLY_NUM];
760
761 int num_blocks;
762 struct iwl_dram_data fw_mon[IWL_FW_INI_APPLY_NUM];
763
764 bool hw_error;
765 enum iwl_fw_ini_buffer_location ini_dest;
766};
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804struct iwl_trans {
805 const struct iwl_trans_ops *ops;
806 struct iwl_op_mode *op_mode;
807 const struct iwl_cfg *cfg;
808 struct iwl_drv *drv;
809 enum iwl_trans_state state;
810 unsigned long status;
811
812 struct device *dev;
813 u32 max_skb_frags;
814 u32 hw_rev;
815 u32 hw_rf_id;
816 u32 hw_id;
817 char hw_id_str[52];
818
819 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
820
821 bool pm_support;
822 bool ltr_enabled;
823
824 const struct iwl_hcmd_arr *command_groups;
825 int command_groups_size;
826 bool wide_cmd_header;
827
828 u8 num_rx_queues;
829
830 size_t iml_len;
831 u8 *iml;
832
833
834 struct kmem_cache *dev_cmd_pool;
835 char dev_cmd_pool_name[50];
836
837 struct dentry *dbgfs_dir;
838
839#ifdef CONFIG_LOCKDEP
840 struct lockdep_map sync_cmd_lockdep_map;
841#endif
842
843 struct iwl_trans_debug dbg;
844 struct iwl_self_init_dram init_dram;
845
846 enum iwl_plat_pm_mode system_pm_mode;
847 enum iwl_plat_pm_mode runtime_pm_mode;
848 bool suspending;
849
850
851
852 char trans_specific[0] __aligned(sizeof(void *));
853};
854
855const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
856int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
857
858static inline void iwl_trans_configure(struct iwl_trans *trans,
859 const struct iwl_trans_config *trans_cfg)
860{
861 trans->op_mode = trans_cfg->op_mode;
862
863 trans->ops->configure(trans, trans_cfg);
864 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
865}
866
867static inline int _iwl_trans_start_hw(struct iwl_trans *trans, bool low_power)
868{
869 might_sleep();
870
871 return trans->ops->start_hw(trans, low_power);
872}
873
874static inline int iwl_trans_start_hw(struct iwl_trans *trans)
875{
876 return trans->ops->start_hw(trans, true);
877}
878
879static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
880{
881 might_sleep();
882
883 if (trans->ops->op_mode_leave)
884 trans->ops->op_mode_leave(trans);
885
886 trans->op_mode = NULL;
887
888 trans->state = IWL_TRANS_NO_FW;
889}
890
891static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
892{
893 might_sleep();
894
895 trans->state = IWL_TRANS_FW_ALIVE;
896
897 trans->ops->fw_alive(trans, scd_addr);
898}
899
900static inline int iwl_trans_start_fw(struct iwl_trans *trans,
901 const struct fw_img *fw,
902 bool run_in_rfkill)
903{
904 might_sleep();
905
906 WARN_ON_ONCE(!trans->rx_mpdu_cmd);
907
908 clear_bit(STATUS_FW_ERROR, &trans->status);
909 return trans->ops->start_fw(trans, fw, run_in_rfkill);
910}
911
912static inline void _iwl_trans_stop_device(struct iwl_trans *trans,
913 bool low_power)
914{
915 might_sleep();
916
917 trans->ops->stop_device(trans, low_power);
918
919 trans->state = IWL_TRANS_NO_FW;
920}
921
922static inline void iwl_trans_stop_device(struct iwl_trans *trans)
923{
924 _iwl_trans_stop_device(trans, true);
925}
926
927static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
928 bool reset)
929{
930 might_sleep();
931 if (trans->ops->d3_suspend)
932 trans->ops->d3_suspend(trans, test, reset);
933}
934
935static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
936 enum iwl_d3_status *status,
937 bool test, bool reset)
938{
939 might_sleep();
940 if (!trans->ops->d3_resume)
941 return 0;
942
943 return trans->ops->d3_resume(trans, status, test, reset);
944}
945
946static inline int iwl_trans_suspend(struct iwl_trans *trans)
947{
948 if (!trans->ops->suspend)
949 return 0;
950
951 return trans->ops->suspend(trans);
952}
953
954static inline void iwl_trans_resume(struct iwl_trans *trans)
955{
956 if (trans->ops->resume)
957 trans->ops->resume(trans);
958}
959
960static inline struct iwl_trans_dump_data *
961iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask)
962{
963 if (!trans->ops->dump_data)
964 return NULL;
965 return trans->ops->dump_data(trans, dump_mask);
966}
967
968static inline struct iwl_device_cmd *
969iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
970{
971 return kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC);
972}
973
974int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
975
976static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
977 struct iwl_device_cmd *dev_cmd)
978{
979 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
980}
981
982static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
983 struct iwl_device_cmd *dev_cmd, int queue)
984{
985 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
986 return -EIO;
987
988 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
989 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
990 return -EIO;
991 }
992
993 return trans->ops->tx(trans, skb, dev_cmd, queue);
994}
995
996static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
997 int ssn, struct sk_buff_head *skbs)
998{
999 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1000 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1001 return;
1002 }
1003
1004 trans->ops->reclaim(trans, queue, ssn, skbs);
1005}
1006
1007static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1008 bool configure_scd)
1009{
1010 trans->ops->txq_disable(trans, queue, configure_scd);
1011}
1012
1013static inline bool
1014iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1015 const struct iwl_trans_txq_scd_cfg *cfg,
1016 unsigned int queue_wdg_timeout)
1017{
1018 might_sleep();
1019
1020 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1021 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1022 return false;
1023 }
1024
1025 return trans->ops->txq_enable(trans, queue, ssn,
1026 cfg, queue_wdg_timeout);
1027}
1028
1029static inline int
1030iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
1031 struct iwl_trans_rxq_dma_data *data)
1032{
1033 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
1034 return -ENOTSUPP;
1035
1036 return trans->ops->rxq_dma_data(trans, queue, data);
1037}
1038
1039static inline void
1040iwl_trans_txq_free(struct iwl_trans *trans, int queue)
1041{
1042 if (WARN_ON_ONCE(!trans->ops->txq_free))
1043 return;
1044
1045 trans->ops->txq_free(trans, queue);
1046}
1047
1048static inline int
1049iwl_trans_txq_alloc(struct iwl_trans *trans,
1050 __le16 flags, u8 sta_id, u8 tid,
1051 int cmd_id, int size,
1052 unsigned int wdg_timeout)
1053{
1054 might_sleep();
1055
1056 if (WARN_ON_ONCE(!trans->ops->txq_alloc))
1057 return -ENOTSUPP;
1058
1059 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1060 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1061 return -EIO;
1062 }
1063
1064 return trans->ops->txq_alloc(trans, flags, sta_id, tid,
1065 cmd_id, size, wdg_timeout);
1066}
1067
1068static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1069 int queue, bool shared_mode)
1070{
1071 if (trans->ops->txq_set_shared_mode)
1072 trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
1073}
1074
1075static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1076 int fifo, int sta_id, int tid,
1077 int frame_limit, u16 ssn,
1078 unsigned int queue_wdg_timeout)
1079{
1080 struct iwl_trans_txq_scd_cfg cfg = {
1081 .fifo = fifo,
1082 .sta_id = sta_id,
1083 .tid = tid,
1084 .frame_limit = frame_limit,
1085 .aggregate = sta_id >= 0,
1086 };
1087
1088 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1089}
1090
1091static inline
1092void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1093 unsigned int queue_wdg_timeout)
1094{
1095 struct iwl_trans_txq_scd_cfg cfg = {
1096 .fifo = fifo,
1097 .sta_id = -1,
1098 .tid = IWL_MAX_TID_COUNT,
1099 .frame_limit = IWL_FRAME_LIMIT,
1100 .aggregate = false,
1101 };
1102
1103 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1104}
1105
1106static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1107 unsigned long txqs,
1108 bool freeze)
1109{
1110 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1111 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1112 return;
1113 }
1114
1115 if (trans->ops->freeze_txq_timer)
1116 trans->ops->freeze_txq_timer(trans, txqs, freeze);
1117}
1118
1119static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
1120 bool block)
1121{
1122 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1123 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1124 return;
1125 }
1126
1127 if (trans->ops->block_txq_ptrs)
1128 trans->ops->block_txq_ptrs(trans, block);
1129}
1130
1131static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1132 u32 txqs)
1133{
1134 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1135 return -ENOTSUPP;
1136
1137 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1138 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1139 return -EIO;
1140 }
1141
1142 return trans->ops->wait_tx_queues_empty(trans, txqs);
1143}
1144
1145static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1146{
1147 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1148 return -ENOTSUPP;
1149
1150 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1151 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1152 return -EIO;
1153 }
1154
1155 return trans->ops->wait_txq_empty(trans, queue);
1156}
1157
1158static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1159{
1160 trans->ops->write8(trans, ofs, val);
1161}
1162
1163static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1164{
1165 trans->ops->write32(trans, ofs, val);
1166}
1167
1168static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1169{
1170 return trans->ops->read32(trans, ofs);
1171}
1172
1173static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1174{
1175 return trans->ops->read_prph(trans, ofs);
1176}
1177
1178static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1179 u32 val)
1180{
1181 return trans->ops->write_prph(trans, ofs, val);
1182}
1183
1184static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1185 void *buf, int dwords)
1186{
1187 return trans->ops->read_mem(trans, addr, buf, dwords);
1188}
1189
1190#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
1191 do { \
1192 if (__builtin_constant_p(bufsize)) \
1193 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
1194 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1195 } while (0)
1196
1197static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1198{
1199 u32 value;
1200
1201 if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1202 return 0xa5a5a5a5;
1203
1204 return value;
1205}
1206
1207static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1208 const void *buf, int dwords)
1209{
1210 return trans->ops->write_mem(trans, addr, buf, dwords);
1211}
1212
1213static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1214 u32 val)
1215{
1216 return iwl_trans_write_mem(trans, addr, &val, 1);
1217}
1218
1219static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1220{
1221 if (trans->ops->set_pmi)
1222 trans->ops->set_pmi(trans, state);
1223}
1224
1225static inline void iwl_trans_sw_reset(struct iwl_trans *trans)
1226{
1227 if (trans->ops->sw_reset)
1228 trans->ops->sw_reset(trans);
1229}
1230
1231static inline void
1232iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1233{
1234 trans->ops->set_bits_mask(trans, reg, mask, value);
1235}
1236
1237#define iwl_trans_grab_nic_access(trans, flags) \
1238 __cond_lock(nic_access, \
1239 likely((trans)->ops->grab_nic_access(trans, flags)))
1240
1241static inline void __releases(nic_access)
1242iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
1243{
1244 trans->ops->release_nic_access(trans, flags);
1245 __release(nic_access);
1246}
1247
1248static inline void iwl_trans_fw_error(struct iwl_trans *trans)
1249{
1250 if (WARN_ON_ONCE(!trans->op_mode))
1251 return;
1252
1253
1254 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status))
1255 iwl_op_mode_nic_error(trans->op_mode);
1256}
1257
1258static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
1259{
1260 if (trans->ops->sync_nmi)
1261 trans->ops->sync_nmi(trans);
1262}
1263
1264
1265
1266
1267struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1268 struct device *dev,
1269 const struct iwl_cfg *cfg,
1270 const struct iwl_trans_ops *ops);
1271void iwl_trans_free(struct iwl_trans *trans);
1272void iwl_trans_ref(struct iwl_trans *trans);
1273void iwl_trans_unref(struct iwl_trans *trans);
1274
1275
1276
1277
1278int __must_check iwl_pci_register_driver(void);
1279void iwl_pci_unregister_driver(void);
1280
1281#endif
1282