1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64#include <linux/etherdevice.h>
65#include <linux/ieee80211.h>
66#include <linux/slab.h>
67#include <linux/sched.h>
68#include <linux/pm_runtime.h>
69#include <net/ip6_checksum.h>
70#include <net/tso.h>
71
72#include "iwl-debug.h"
73#include "iwl-csr.h"
74#include "iwl-prph.h"
75#include "iwl-io.h"
76#include "iwl-scd.h"
77#include "iwl-op-mode.h"
78#include "internal.h"
79#include "fw/api/tx.h"
80
81#define IWL_TX_CRC_SIZE 4
82#define IWL_TX_DELIMITER_SIZE 4
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q)
107{
108 unsigned int max;
109 unsigned int used;
110
111
112
113
114
115
116
117 if (q->n_window < trans->cfg->base_params->max_tfd_queue_size)
118 max = q->n_window;
119 else
120 max = trans->cfg->base_params->max_tfd_queue_size - 1;
121
122
123
124
125
126 used = (q->write_ptr - q->read_ptr) &
127 (trans->cfg->base_params->max_tfd_queue_size - 1);
128
129 if (WARN_ON(used > max))
130 return 0;
131
132 return max - used;
133}
134
135
136
137
138static int iwl_queue_init(struct iwl_txq *q, int slots_num)
139{
140 q->n_window = slots_num;
141
142
143
144 if (WARN_ON(!is_power_of_2(slots_num)))
145 return -EINVAL;
146
147 q->low_mark = q->n_window / 4;
148 if (q->low_mark < 4)
149 q->low_mark = 4;
150
151 q->high_mark = q->n_window / 8;
152 if (q->high_mark < 2)
153 q->high_mark = 2;
154
155 q->write_ptr = 0;
156 q->read_ptr = 0;
157
158 return 0;
159}
160
161int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
162 struct iwl_dma_ptr *ptr, size_t size)
163{
164 if (WARN_ON(ptr->addr))
165 return -EINVAL;
166
167 ptr->addr = dma_alloc_coherent(trans->dev, size,
168 &ptr->dma, GFP_KERNEL);
169 if (!ptr->addr)
170 return -ENOMEM;
171 ptr->size = size;
172 return 0;
173}
174
175void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
176{
177 if (unlikely(!ptr->addr))
178 return;
179
180 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
181 memset(ptr, 0, sizeof(*ptr));
182}
183
184static void iwl_pcie_txq_stuck_timer(struct timer_list *t)
185{
186 struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
187 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
188 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
189
190 spin_lock(&txq->lock);
191
192 if (txq->read_ptr == txq->write_ptr) {
193 spin_unlock(&txq->lock);
194 return;
195 }
196 spin_unlock(&txq->lock);
197
198 iwl_trans_pcie_log_scd_error(trans, txq);
199
200 iwl_force_nmi(trans);
201}
202
203
204
205
206static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
207 struct iwl_txq *txq, u16 byte_cnt,
208 int num_tbs)
209{
210 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
212 int write_ptr = txq->write_ptr;
213 int txq_id = txq->id;
214 u8 sec_ctl = 0;
215 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
216 __le16 bc_ent;
217 struct iwl_tx_cmd *tx_cmd =
218 (void *)txq->entries[txq->write_ptr].cmd->payload;
219 u8 sta_id = tx_cmd->sta_id;
220
221 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
222
223 sec_ctl = tx_cmd->sec_ctl;
224
225 switch (sec_ctl & TX_CMD_SEC_MSK) {
226 case TX_CMD_SEC_CCM:
227 len += IEEE80211_CCMP_MIC_LEN;
228 break;
229 case TX_CMD_SEC_TKIP:
230 len += IEEE80211_TKIP_ICV_LEN;
231 break;
232 case TX_CMD_SEC_WEP:
233 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
234 break;
235 }
236 if (trans_pcie->bc_table_dword)
237 len = DIV_ROUND_UP(len, 4);
238
239 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
240 return;
241
242 bc_ent = cpu_to_le16(len | (sta_id << 12));
243
244 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
245
246 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
247 scd_bc_tbl[txq_id].
248 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
249}
250
251static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
252 struct iwl_txq *txq)
253{
254 struct iwl_trans_pcie *trans_pcie =
255 IWL_TRANS_GET_PCIE_TRANS(trans);
256 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
257 int txq_id = txq->id;
258 int read_ptr = txq->read_ptr;
259 u8 sta_id = 0;
260 __le16 bc_ent;
261 struct iwl_tx_cmd *tx_cmd =
262 (void *)txq->entries[read_ptr].cmd->payload;
263
264 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
265
266 if (txq_id != trans_pcie->cmd_queue)
267 sta_id = tx_cmd->sta_id;
268
269 bc_ent = cpu_to_le16(1 | (sta_id << 12));
270
271 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
272
273 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
274 scd_bc_tbl[txq_id].
275 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
276}
277
278
279
280
281static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
282 struct iwl_txq *txq)
283{
284 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
285 u32 reg = 0;
286 int txq_id = txq->id;
287
288 lockdep_assert_held(&txq->lock);
289
290
291
292
293
294
295
296 if (!trans->cfg->base_params->shadow_reg_enable &&
297 txq_id != trans_pcie->cmd_queue &&
298 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
299
300
301
302
303
304 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
305
306 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
307 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
308 txq_id, reg);
309 iwl_set_bit(trans, CSR_GP_CNTRL,
310 BIT(trans->cfg->csr->flag_mac_access_req));
311 txq->need_update = true;
312 return;
313 }
314 }
315
316
317
318
319
320 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
321 if (!txq->block)
322 iwl_write32(trans, HBUS_TARG_WRPTR,
323 txq->write_ptr | (txq_id << 8));
324}
325
326void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
327{
328 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
329 int i;
330
331 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
332 struct iwl_txq *txq = trans_pcie->txq[i];
333
334 if (!test_bit(i, trans_pcie->queue_used))
335 continue;
336
337 spin_lock_bh(&txq->lock);
338 if (txq->need_update) {
339 iwl_pcie_txq_inc_wr_ptr(trans, txq);
340 txq->need_update = false;
341 }
342 spin_unlock_bh(&txq->lock);
343 }
344}
345
346static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
347 void *_tfd, u8 idx)
348{
349
350 if (trans->cfg->use_tfh) {
351 struct iwl_tfh_tfd *tfd = _tfd;
352 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
353
354 return (dma_addr_t)(le64_to_cpu(tb->addr));
355 } else {
356 struct iwl_tfd *tfd = _tfd;
357 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
358 dma_addr_t addr = get_unaligned_le32(&tb->lo);
359 dma_addr_t hi_len;
360
361 if (sizeof(dma_addr_t) <= sizeof(u32))
362 return addr;
363
364 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
365
366
367
368
369
370
371 return addr | ((hi_len << 16) << 16);
372 }
373}
374
375static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
376 u8 idx, dma_addr_t addr, u16 len)
377{
378 struct iwl_tfd *tfd_fh = (void *)tfd;
379 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
380
381 u16 hi_n_len = len << 4;
382
383 put_unaligned_le32(addr, &tb->lo);
384 hi_n_len |= iwl_get_dma_hi_addr(addr);
385
386 tb->hi_n_len = cpu_to_le16(hi_n_len);
387
388 tfd_fh->num_tbs = idx + 1;
389}
390
391static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
392{
393 if (trans->cfg->use_tfh) {
394 struct iwl_tfh_tfd *tfd = _tfd;
395
396 return le16_to_cpu(tfd->num_tbs) & 0x1f;
397 } else {
398 struct iwl_tfd *tfd = _tfd;
399
400 return tfd->num_tbs & 0x1f;
401 }
402}
403
404static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
405 struct iwl_cmd_meta *meta,
406 struct iwl_txq *txq, int index)
407{
408 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
409 int i, num_tbs;
410 void *tfd = iwl_pcie_get_tfd(trans, txq, index);
411
412
413 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
414
415 if (num_tbs > trans_pcie->max_tbs) {
416 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
417
418 return;
419 }
420
421
422
423 for (i = 1; i < num_tbs; i++) {
424 if (meta->tbs & BIT(i))
425 dma_unmap_page(trans->dev,
426 iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
427 iwl_pcie_tfd_tb_get_len(trans, tfd, i),
428 DMA_TO_DEVICE);
429 else
430 dma_unmap_single(trans->dev,
431 iwl_pcie_tfd_tb_get_addr(trans, tfd,
432 i),
433 iwl_pcie_tfd_tb_get_len(trans, tfd,
434 i),
435 DMA_TO_DEVICE);
436 }
437
438 meta->tbs = 0;
439
440 if (trans->cfg->use_tfh) {
441 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
442
443 tfd_fh->num_tbs = 0;
444 } else {
445 struct iwl_tfd *tfd_fh = (void *)tfd;
446
447 tfd_fh->num_tbs = 0;
448 }
449
450}
451
452
453
454
455
456
457
458
459
460
461void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
462{
463
464
465
466 int rd_ptr = txq->read_ptr;
467 int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
468
469 lockdep_assert_held(&txq->lock);
470
471
472
473
474 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
475
476
477 if (txq->entries) {
478 struct sk_buff *skb;
479
480 skb = txq->entries[idx].skb;
481
482
483
484
485
486 if (skb) {
487 iwl_op_mode_free_skb(trans->op_mode, skb);
488 txq->entries[idx].skb = NULL;
489 }
490 }
491}
492
493static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
494 dma_addr_t addr, u16 len, bool reset)
495{
496 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
497 void *tfd;
498 u32 num_tbs;
499
500 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
501
502 if (reset)
503 memset(tfd, 0, trans_pcie->tfd_size);
504
505 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
506
507
508 if (num_tbs >= trans_pcie->max_tbs) {
509 IWL_ERR(trans, "Error can not send more than %d chunks\n",
510 trans_pcie->max_tbs);
511 return -EINVAL;
512 }
513
514 if (WARN(addr & ~IWL_TX_DMA_MASK,
515 "Unaligned address = %llx\n", (unsigned long long)addr))
516 return -EINVAL;
517
518 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
519
520 return num_tbs;
521}
522
523int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
524 int slots_num, bool cmd_queue)
525{
526 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
527 size_t tfd_sz = trans_pcie->tfd_size *
528 trans->cfg->base_params->max_tfd_queue_size;
529 size_t tb0_buf_sz;
530 int i;
531
532 if (WARN_ON(txq->entries || txq->tfds))
533 return -EINVAL;
534
535 if (trans->cfg->use_tfh)
536 tfd_sz = trans_pcie->tfd_size * slots_num;
537
538 timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0);
539 txq->trans_pcie = trans_pcie;
540
541 txq->n_window = slots_num;
542
543 txq->entries = kcalloc(slots_num,
544 sizeof(struct iwl_pcie_txq_entry),
545 GFP_KERNEL);
546
547 if (!txq->entries)
548 goto error;
549
550 if (cmd_queue)
551 for (i = 0; i < slots_num; i++) {
552 txq->entries[i].cmd =
553 kmalloc(sizeof(struct iwl_device_cmd),
554 GFP_KERNEL);
555 if (!txq->entries[i].cmd)
556 goto error;
557 }
558
559
560
561 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
562 &txq->dma_addr, GFP_KERNEL);
563 if (!txq->tfds)
564 goto error;
565
566 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
567
568 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
569
570 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
571 &txq->first_tb_dma,
572 GFP_KERNEL);
573 if (!txq->first_tb_bufs)
574 goto err_free_tfds;
575
576 return 0;
577err_free_tfds:
578 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
579error:
580 if (txq->entries && cmd_queue)
581 for (i = 0; i < slots_num; i++)
582 kfree(txq->entries[i].cmd);
583 kfree(txq->entries);
584 txq->entries = NULL;
585
586 return -ENOMEM;
587
588}
589
590int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
591 int slots_num, bool cmd_queue)
592{
593 int ret;
594 u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size;
595
596 txq->need_update = false;
597
598
599
600 if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
601 "Max tfd queue size must be a power of two, but is %d",
602 tfd_queue_max_size))
603 return -EINVAL;
604
605
606 ret = iwl_queue_init(txq, slots_num);
607 if (ret)
608 return ret;
609
610 spin_lock_init(&txq->lock);
611
612 if (cmd_queue) {
613 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
614
615 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
616 }
617
618 __skb_queue_head_init(&txq->overflow_q);
619
620 return 0;
621}
622
623void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
624 struct sk_buff *skb)
625{
626 struct page **page_ptr;
627
628 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
629
630 if (*page_ptr) {
631 __free_page(*page_ptr);
632 *page_ptr = NULL;
633 }
634}
635
636static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
637{
638 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
639
640 lockdep_assert_held(&trans_pcie->reg_lock);
641
642 if (trans_pcie->ref_cmd_in_flight) {
643 trans_pcie->ref_cmd_in_flight = false;
644 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
645 iwl_trans_unref(trans);
646 }
647
648 if (!trans->cfg->base_params->apmg_wake_up_wa)
649 return;
650 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
651 return;
652
653 trans_pcie->cmd_hold_nic_awake = false;
654 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
655 BIT(trans->cfg->csr->flag_mac_access_req));
656}
657
658
659
660
661static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
662{
663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
664 struct iwl_txq *txq = trans_pcie->txq[txq_id];
665
666 spin_lock_bh(&txq->lock);
667 while (txq->write_ptr != txq->read_ptr) {
668 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
669 txq_id, txq->read_ptr);
670
671 if (txq_id != trans_pcie->cmd_queue) {
672 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
673
674 if (WARN_ON_ONCE(!skb))
675 continue;
676
677 iwl_pcie_free_tso_page(trans_pcie, skb);
678 }
679 iwl_pcie_txq_free_tfd(trans, txq);
680 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
681
682 if (txq->read_ptr == txq->write_ptr) {
683 unsigned long flags;
684
685 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
686 if (txq_id != trans_pcie->cmd_queue) {
687 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
688 txq->id);
689 iwl_trans_unref(trans);
690 } else {
691 iwl_pcie_clear_cmd_in_flight(trans);
692 }
693 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
694 }
695 }
696
697 while (!skb_queue_empty(&txq->overflow_q)) {
698 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
699
700 iwl_op_mode_free_skb(trans->op_mode, skb);
701 }
702
703 spin_unlock_bh(&txq->lock);
704
705
706 iwl_wake_queue(trans, txq);
707}
708
709
710
711
712
713
714
715
716
717static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
718{
719 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
720 struct iwl_txq *txq = trans_pcie->txq[txq_id];
721 struct device *dev = trans->dev;
722 int i;
723
724 if (WARN_ON(!txq))
725 return;
726
727 iwl_pcie_txq_unmap(trans, txq_id);
728
729
730 if (txq_id == trans_pcie->cmd_queue)
731 for (i = 0; i < txq->n_window; i++) {
732 kzfree(txq->entries[i].cmd);
733 kzfree(txq->entries[i].free_buf);
734 }
735
736
737 if (txq->tfds) {
738 dma_free_coherent(dev,
739 trans_pcie->tfd_size *
740 trans->cfg->base_params->max_tfd_queue_size,
741 txq->tfds, txq->dma_addr);
742 txq->dma_addr = 0;
743 txq->tfds = NULL;
744
745 dma_free_coherent(dev,
746 sizeof(*txq->first_tb_bufs) * txq->n_window,
747 txq->first_tb_bufs, txq->first_tb_dma);
748 }
749
750 kfree(txq->entries);
751 txq->entries = NULL;
752
753 del_timer_sync(&txq->stuck_timer);
754
755
756 memset(txq, 0, sizeof(*txq));
757}
758
759void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
760{
761 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
762 int nq = trans->cfg->base_params->num_of_queues;
763 int chan;
764 u32 reg_val;
765 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
766 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
767
768
769 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
770 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
771
772 trans_pcie->scd_base_addr =
773 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
774
775 WARN_ON(scd_base_addr != 0 &&
776 scd_base_addr != trans_pcie->scd_base_addr);
777
778
779 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
780 SCD_CONTEXT_MEM_LOWER_BOUND,
781 NULL, clear_dwords);
782
783 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
784 trans_pcie->scd_bc_tbls.dma >> 10);
785
786
787
788
789 if (trans->cfg->base_params->scd_chain_ext_wa)
790 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
791
792 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
793 trans_pcie->cmd_fifo,
794 trans_pcie->cmd_q_wdg_timeout);
795
796
797 iwl_scd_activate_fifos(trans);
798
799
800 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
801 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
802 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
803 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
804
805
806 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
807 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
808 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
809
810
811 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
812 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
813 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
814}
815
816void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
817{
818 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
819 int txq_id;
820
821
822
823
824
825 if (WARN_ON_ONCE(trans->cfg->gen2))
826 return;
827
828 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
829 txq_id++) {
830 struct iwl_txq *txq = trans_pcie->txq[txq_id];
831 if (trans->cfg->use_tfh)
832 iwl_write_direct64(trans,
833 FH_MEM_CBBC_QUEUE(trans, txq_id),
834 txq->dma_addr);
835 else
836 iwl_write_direct32(trans,
837 FH_MEM_CBBC_QUEUE(trans, txq_id),
838 txq->dma_addr >> 8);
839 iwl_pcie_txq_unmap(trans, txq_id);
840 txq->read_ptr = 0;
841 txq->write_ptr = 0;
842 }
843
844
845 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
846 trans_pcie->kw.dma >> 4);
847
848
849
850
851
852
853 iwl_pcie_tx_start(trans, 0);
854}
855
856static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
857{
858 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
859 unsigned long flags;
860 int ch, ret;
861 u32 mask = 0;
862
863 spin_lock(&trans_pcie->irq_lock);
864
865 if (!iwl_trans_grab_nic_access(trans, &flags))
866 goto out;
867
868
869 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
870 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
871 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
872 }
873
874
875 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
876 if (ret < 0)
877 IWL_ERR(trans,
878 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
879 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
880
881 iwl_trans_release_nic_access(trans, &flags);
882
883out:
884 spin_unlock(&trans_pcie->irq_lock);
885}
886
887
888
889
890int iwl_pcie_tx_stop(struct iwl_trans *trans)
891{
892 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
893 int txq_id;
894
895
896 iwl_scd_deactivate_fifos(trans);
897
898
899 iwl_pcie_tx_stop_fh(trans);
900
901
902
903
904
905
906 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
907 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
908
909
910 if (!trans_pcie->txq_memory)
911 return 0;
912
913
914 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
915 txq_id++)
916 iwl_pcie_txq_unmap(trans, txq_id);
917
918 return 0;
919}
920
921
922
923
924
925
926void iwl_pcie_tx_free(struct iwl_trans *trans)
927{
928 int txq_id;
929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
930
931 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
932
933
934 if (trans_pcie->txq_memory) {
935 for (txq_id = 0;
936 txq_id < trans->cfg->base_params->num_of_queues;
937 txq_id++) {
938 iwl_pcie_txq_free(trans, txq_id);
939 trans_pcie->txq[txq_id] = NULL;
940 }
941 }
942
943 kfree(trans_pcie->txq_memory);
944 trans_pcie->txq_memory = NULL;
945
946 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
947
948 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
949}
950
951
952
953
954
955static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
956{
957 int ret;
958 int txq_id, slots_num;
959 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
960 u16 bc_tbls_size = trans->cfg->base_params->num_of_queues;
961
962 bc_tbls_size *= (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ?
963 sizeof(struct iwl_gen3_bc_tbl) :
964 sizeof(struct iwlagn_scd_bc_tbl);
965
966
967
968 if (WARN_ON(trans_pcie->txq_memory)) {
969 ret = -EINVAL;
970 goto error;
971 }
972
973 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
974 bc_tbls_size);
975 if (ret) {
976 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
977 goto error;
978 }
979
980
981 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
982 if (ret) {
983 IWL_ERR(trans, "Keep Warm allocation failed\n");
984 goto error;
985 }
986
987 trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues,
988 sizeof(struct iwl_txq), GFP_KERNEL);
989 if (!trans_pcie->txq_memory) {
990 IWL_ERR(trans, "Not enough memory for txq\n");
991 ret = -ENOMEM;
992 goto error;
993 }
994
995
996 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
997 txq_id++) {
998 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
999
1000 if (cmd_queue)
1001 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
1002 trans->cfg->min_txq_size);
1003 else
1004 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
1005 trans->cfg->min_256_ba_txq_size);
1006 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
1007 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
1008 slots_num, cmd_queue);
1009 if (ret) {
1010 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1011 goto error;
1012 }
1013 trans_pcie->txq[txq_id]->id = txq_id;
1014 }
1015
1016 return 0;
1017
1018error:
1019 iwl_pcie_tx_free(trans);
1020
1021 return ret;
1022}
1023
1024int iwl_pcie_tx_init(struct iwl_trans *trans)
1025{
1026 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1027 int ret;
1028 int txq_id, slots_num;
1029 bool alloc = false;
1030
1031 if (!trans_pcie->txq_memory) {
1032 ret = iwl_pcie_tx_alloc(trans);
1033 if (ret)
1034 goto error;
1035 alloc = true;
1036 }
1037
1038 spin_lock(&trans_pcie->irq_lock);
1039
1040
1041 iwl_scd_deactivate_fifos(trans);
1042
1043
1044 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1045 trans_pcie->kw.dma >> 4);
1046
1047 spin_unlock(&trans_pcie->irq_lock);
1048
1049
1050 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1051 txq_id++) {
1052 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1053
1054 if (cmd_queue)
1055 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
1056 trans->cfg->min_txq_size);
1057 else
1058 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
1059 trans->cfg->min_256_ba_txq_size);
1060 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1061 slots_num, cmd_queue);
1062 if (ret) {
1063 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1064 goto error;
1065 }
1066
1067
1068
1069
1070
1071
1072
1073 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1074 trans_pcie->txq[txq_id]->dma_addr >> 8);
1075 }
1076
1077 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1078 if (trans->cfg->base_params->num_of_queues > 20)
1079 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1080 SCD_GP_CTRL_ENABLE_31_QUEUES);
1081
1082 return 0;
1083error:
1084
1085 if (alloc)
1086 iwl_pcie_tx_free(trans);
1087 return ret;
1088}
1089
1090static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1091{
1092 lockdep_assert_held(&txq->lock);
1093
1094 if (!txq->wd_timeout)
1095 return;
1096
1097
1098
1099
1100
1101 if (txq->frozen)
1102 return;
1103
1104
1105
1106
1107
1108 if (txq->read_ptr == txq->write_ptr)
1109 del_timer(&txq->stuck_timer);
1110 else
1111 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1112}
1113
1114
1115void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1116 struct sk_buff_head *skbs)
1117{
1118 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1119 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1120 int tfd_num = iwl_pcie_get_cmd_index(txq, ssn);
1121 int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1122 int last_to_free;
1123
1124
1125 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1126 return;
1127
1128 spin_lock_bh(&txq->lock);
1129
1130 if (!test_bit(txq_id, trans_pcie->queue_used)) {
1131 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1132 txq_id, ssn);
1133 goto out;
1134 }
1135
1136 if (read_ptr == tfd_num)
1137 goto out;
1138
1139 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1140 txq_id, txq->read_ptr, tfd_num, ssn);
1141
1142
1143
1144 last_to_free = iwl_queue_dec_wrap(trans, tfd_num);
1145
1146 if (!iwl_queue_used(txq, last_to_free)) {
1147 IWL_ERR(trans,
1148 "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1149 __func__, txq_id, last_to_free,
1150 trans->cfg->base_params->max_tfd_queue_size,
1151 txq->write_ptr, txq->read_ptr);
1152 goto out;
1153 }
1154
1155 if (WARN_ON(!skb_queue_empty(skbs)))
1156 goto out;
1157
1158 for (;
1159 read_ptr != tfd_num;
1160 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr),
1161 read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) {
1162 struct sk_buff *skb = txq->entries[read_ptr].skb;
1163
1164 if (WARN_ON_ONCE(!skb))
1165 continue;
1166
1167 iwl_pcie_free_tso_page(trans_pcie, skb);
1168
1169 __skb_queue_tail(skbs, skb);
1170
1171 txq->entries[read_ptr].skb = NULL;
1172
1173 if (!trans->cfg->use_tfh)
1174 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1175
1176 iwl_pcie_txq_free_tfd(trans, txq);
1177 }
1178
1179 iwl_pcie_txq_progress(txq);
1180
1181 if (iwl_queue_space(trans, txq) > txq->low_mark &&
1182 test_bit(txq_id, trans_pcie->queue_stopped)) {
1183 struct sk_buff_head overflow_skbs;
1184
1185 __skb_queue_head_init(&overflow_skbs);
1186 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1187
1188
1189
1190
1191
1192
1193
1194
1195 txq->overflow_tx = true;
1196
1197
1198
1199
1200
1201
1202
1203
1204 spin_unlock_bh(&txq->lock);
1205
1206 while (!skb_queue_empty(&overflow_skbs)) {
1207 struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1208 struct iwl_device_cmd *dev_cmd_ptr;
1209
1210 dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1211 trans_pcie->dev_cmd_offs);
1212
1213
1214
1215
1216
1217
1218 iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
1219 }
1220
1221 if (iwl_queue_space(trans, txq) > txq->low_mark)
1222 iwl_wake_queue(trans, txq);
1223
1224 spin_lock_bh(&txq->lock);
1225 txq->overflow_tx = false;
1226 }
1227
1228 if (txq->read_ptr == txq->write_ptr) {
1229 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id);
1230 iwl_trans_unref(trans);
1231 }
1232
1233out:
1234 spin_unlock_bh(&txq->lock);
1235}
1236
1237static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1238 const struct iwl_host_cmd *cmd)
1239{
1240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1241 const struct iwl_cfg *cfg = trans->cfg;
1242 int ret;
1243
1244 lockdep_assert_held(&trans_pcie->reg_lock);
1245
1246
1247 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1248 return -ENODEV;
1249
1250 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1251 !trans_pcie->ref_cmd_in_flight) {
1252 trans_pcie->ref_cmd_in_flight = true;
1253 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1254 iwl_trans_ref(trans);
1255 }
1256
1257
1258
1259
1260
1261
1262
1263 if (cfg->base_params->apmg_wake_up_wa &&
1264 !trans_pcie->cmd_hold_nic_awake) {
1265 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1266 BIT(cfg->csr->flag_mac_access_req));
1267
1268 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1269 BIT(cfg->csr->flag_val_mac_access_en),
1270 (BIT(cfg->csr->flag_mac_clock_ready) |
1271 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1272 15000);
1273 if (ret < 0) {
1274 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1275 BIT(cfg->csr->flag_mac_access_req));
1276 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1277 return -EIO;
1278 }
1279 trans_pcie->cmd_hold_nic_awake = true;
1280 }
1281
1282 return 0;
1283}
1284
1285
1286
1287
1288
1289
1290
1291
1292void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1293{
1294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1295 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1296 unsigned long flags;
1297 int nfreed = 0;
1298 u16 r;
1299
1300 lockdep_assert_held(&txq->lock);
1301
1302 idx = iwl_pcie_get_cmd_index(txq, idx);
1303 r = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1304
1305 if (idx >= trans->cfg->base_params->max_tfd_queue_size ||
1306 (!iwl_queue_used(txq, idx))) {
1307 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used),
1308 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1309 __func__, txq_id, idx,
1310 trans->cfg->base_params->max_tfd_queue_size,
1311 txq->write_ptr, txq->read_ptr);
1312 return;
1313 }
1314
1315 for (idx = iwl_queue_inc_wrap(trans, idx); r != idx;
1316 r = iwl_queue_inc_wrap(trans, r)) {
1317 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1318
1319 if (nfreed++ > 0) {
1320 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1321 idx, txq->write_ptr, r);
1322 iwl_force_nmi(trans);
1323 }
1324 }
1325
1326 if (txq->read_ptr == txq->write_ptr) {
1327 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1328 iwl_pcie_clear_cmd_in_flight(trans);
1329 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1330 }
1331
1332 iwl_pcie_txq_progress(txq);
1333}
1334
1335static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1336 u16 txq_id)
1337{
1338 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1339 u32 tbl_dw_addr;
1340 u32 tbl_dw;
1341 u16 scd_q2ratid;
1342
1343 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1344
1345 tbl_dw_addr = trans_pcie->scd_base_addr +
1346 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1347
1348 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1349
1350 if (txq_id & 0x1)
1351 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1352 else
1353 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1354
1355 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1356
1357 return 0;
1358}
1359
1360
1361
1362#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1363
1364bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1365 const struct iwl_trans_txq_scd_cfg *cfg,
1366 unsigned int wdg_timeout)
1367{
1368 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1369 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1370 int fifo = -1;
1371 bool scd_bug = false;
1372
1373 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1374 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1375
1376 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1377
1378 if (cfg) {
1379 fifo = cfg->fifo;
1380
1381
1382 if (txq_id == trans_pcie->cmd_queue &&
1383 trans_pcie->scd_set_active)
1384 iwl_scd_enable_set_active(trans, 0);
1385
1386
1387 iwl_scd_txq_set_inactive(trans, txq_id);
1388
1389
1390 if (txq_id != trans_pcie->cmd_queue)
1391 iwl_scd_txq_set_chain(trans, txq_id);
1392
1393 if (cfg->aggregate) {
1394 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1395
1396
1397 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1398
1399
1400 iwl_scd_txq_enable_agg(trans, txq_id);
1401 txq->ampdu = true;
1402 } else {
1403
1404
1405
1406
1407
1408 iwl_scd_txq_disable_agg(trans, txq_id);
1409
1410 ssn = txq->read_ptr;
1411 }
1412 } else {
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424 scd_bug = !trans->cfg->mq_rx_supported &&
1425 !((ssn - txq->write_ptr) & 0x3f) &&
1426 (ssn != txq->write_ptr);
1427 if (scd_bug)
1428 ssn++;
1429 }
1430
1431
1432
1433 txq->read_ptr = (ssn & 0xff);
1434 txq->write_ptr = (ssn & 0xff);
1435 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1436 (ssn & 0xff) | (txq_id << 8));
1437
1438 if (cfg) {
1439 u8 frame_limit = cfg->frame_limit;
1440
1441 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1442
1443
1444 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1445 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1446 iwl_trans_write_mem32(trans,
1447 trans_pcie->scd_base_addr +
1448 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1449 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1450 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1451
1452
1453 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1454 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1455 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1456 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1457 SCD_QUEUE_STTS_REG_MSK);
1458
1459
1460 if (txq_id == trans_pcie->cmd_queue &&
1461 trans_pcie->scd_set_active)
1462 iwl_scd_enable_set_active(trans, BIT(txq_id));
1463
1464 IWL_DEBUG_TX_QUEUES(trans,
1465 "Activate queue %d on FIFO %d WrPtr: %d\n",
1466 txq_id, fifo, ssn & 0xff);
1467 } else {
1468 IWL_DEBUG_TX_QUEUES(trans,
1469 "Activate queue %d WrPtr: %d\n",
1470 txq_id, ssn & 0xff);
1471 }
1472
1473 return scd_bug;
1474}
1475
1476void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1477 bool shared_mode)
1478{
1479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1480 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1481
1482 txq->ampdu = !shared_mode;
1483}
1484
1485void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1486 bool configure_scd)
1487{
1488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1489 u32 stts_addr = trans_pcie->scd_base_addr +
1490 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1491 static const u32 zero_val[4] = {};
1492
1493 trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1494 trans_pcie->txq[txq_id]->frozen = false;
1495
1496
1497
1498
1499
1500
1501
1502 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1503 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1504 "queue %d not used", txq_id);
1505 return;
1506 }
1507
1508 if (configure_scd) {
1509 iwl_scd_txq_set_inactive(trans, txq_id);
1510
1511 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1512 ARRAY_SIZE(zero_val));
1513 }
1514
1515 iwl_pcie_txq_unmap(trans, txq_id);
1516 trans_pcie->txq[txq_id]->ampdu = false;
1517
1518 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1519}
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1533 struct iwl_host_cmd *cmd)
1534{
1535 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1536 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1537 struct iwl_device_cmd *out_cmd;
1538 struct iwl_cmd_meta *out_meta;
1539 unsigned long flags;
1540 void *dup_buf = NULL;
1541 dma_addr_t phys_addr;
1542 int idx;
1543 u16 copy_size, cmd_size, tb0_size;
1544 bool had_nocopy = false;
1545 u8 group_id = iwl_cmd_groupid(cmd->id);
1546 int i, ret;
1547 u32 cmd_pos;
1548 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1549 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1550
1551 if (WARN(!trans->wide_cmd_header &&
1552 group_id > IWL_ALWAYS_LONG_GROUP,
1553 "unsupported wide command %#x\n", cmd->id))
1554 return -EINVAL;
1555
1556 if (group_id != 0) {
1557 copy_size = sizeof(struct iwl_cmd_header_wide);
1558 cmd_size = sizeof(struct iwl_cmd_header_wide);
1559 } else {
1560 copy_size = sizeof(struct iwl_cmd_header);
1561 cmd_size = sizeof(struct iwl_cmd_header);
1562 }
1563
1564
1565 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1566
1567 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1568 cmddata[i] = cmd->data[i];
1569 cmdlen[i] = cmd->len[i];
1570
1571 if (!cmd->len[i])
1572 continue;
1573
1574
1575 if (copy_size < IWL_FIRST_TB_SIZE) {
1576 int copy = IWL_FIRST_TB_SIZE - copy_size;
1577
1578 if (copy > cmdlen[i])
1579 copy = cmdlen[i];
1580 cmdlen[i] -= copy;
1581 cmddata[i] += copy;
1582 copy_size += copy;
1583 }
1584
1585 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1586 had_nocopy = true;
1587 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1588 idx = -EINVAL;
1589 goto free_dup_buf;
1590 }
1591 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1592
1593
1594
1595
1596 had_nocopy = true;
1597
1598
1599 if (WARN_ON(dup_buf)) {
1600 idx = -EINVAL;
1601 goto free_dup_buf;
1602 }
1603
1604 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1605 GFP_ATOMIC);
1606 if (!dup_buf)
1607 return -ENOMEM;
1608 } else {
1609
1610 if (WARN_ON(had_nocopy)) {
1611 idx = -EINVAL;
1612 goto free_dup_buf;
1613 }
1614 copy_size += cmdlen[i];
1615 }
1616 cmd_size += cmd->len[i];
1617 }
1618
1619
1620
1621
1622
1623
1624
1625 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1626 "Command %s (%#x) is too large (%d bytes)\n",
1627 iwl_get_cmd_string(trans, cmd->id),
1628 cmd->id, copy_size)) {
1629 idx = -EINVAL;
1630 goto free_dup_buf;
1631 }
1632
1633 spin_lock_bh(&txq->lock);
1634
1635 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1636 spin_unlock_bh(&txq->lock);
1637
1638 IWL_ERR(trans, "No space in command queue\n");
1639 iwl_op_mode_cmd_queue_full(trans->op_mode);
1640 idx = -ENOSPC;
1641 goto free_dup_buf;
1642 }
1643
1644 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1645 out_cmd = txq->entries[idx].cmd;
1646 out_meta = &txq->entries[idx].meta;
1647
1648 memset(out_meta, 0, sizeof(*out_meta));
1649 if (cmd->flags & CMD_WANT_SKB)
1650 out_meta->source = cmd;
1651
1652
1653 if (group_id != 0) {
1654 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1655 out_cmd->hdr_wide.group_id = group_id;
1656 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1657 out_cmd->hdr_wide.length =
1658 cpu_to_le16(cmd_size -
1659 sizeof(struct iwl_cmd_header_wide));
1660 out_cmd->hdr_wide.reserved = 0;
1661 out_cmd->hdr_wide.sequence =
1662 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1663 INDEX_TO_SEQ(txq->write_ptr));
1664
1665 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1666 copy_size = sizeof(struct iwl_cmd_header_wide);
1667 } else {
1668 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1669 out_cmd->hdr.sequence =
1670 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1671 INDEX_TO_SEQ(txq->write_ptr));
1672 out_cmd->hdr.group_id = 0;
1673
1674 cmd_pos = sizeof(struct iwl_cmd_header);
1675 copy_size = sizeof(struct iwl_cmd_header);
1676 }
1677
1678
1679 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1680 int copy;
1681
1682 if (!cmd->len[i])
1683 continue;
1684
1685
1686 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1687 IWL_HCMD_DFL_DUP))) {
1688 copy = cmd->len[i];
1689
1690 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1691 cmd_pos += copy;
1692 copy_size += copy;
1693 continue;
1694 }
1695
1696
1697
1698
1699
1700
1701 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1702
1703 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1704 cmd_pos += copy;
1705
1706
1707 if (copy_size < IWL_FIRST_TB_SIZE) {
1708 copy = IWL_FIRST_TB_SIZE - copy_size;
1709
1710 if (copy > cmd->len[i])
1711 copy = cmd->len[i];
1712 copy_size += copy;
1713 }
1714 }
1715
1716 IWL_DEBUG_HC(trans,
1717 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1718 iwl_get_cmd_string(trans, cmd->id),
1719 group_id, out_cmd->hdr.cmd,
1720 le16_to_cpu(out_cmd->hdr.sequence),
1721 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1722
1723
1724 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1725 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1726 iwl_pcie_txq_build_tfd(trans, txq,
1727 iwl_pcie_get_first_tb_dma(txq, idx),
1728 tb0_size, true);
1729
1730
1731 if (copy_size > tb0_size) {
1732 phys_addr = dma_map_single(trans->dev,
1733 ((u8 *)&out_cmd->hdr) + tb0_size,
1734 copy_size - tb0_size,
1735 DMA_TO_DEVICE);
1736 if (dma_mapping_error(trans->dev, phys_addr)) {
1737 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1738 txq->write_ptr);
1739 idx = -ENOMEM;
1740 goto out;
1741 }
1742
1743 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1744 copy_size - tb0_size, false);
1745 }
1746
1747
1748 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1749 const void *data = cmddata[i];
1750
1751 if (!cmdlen[i])
1752 continue;
1753 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1754 IWL_HCMD_DFL_DUP)))
1755 continue;
1756 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1757 data = dup_buf;
1758 phys_addr = dma_map_single(trans->dev, (void *)data,
1759 cmdlen[i], DMA_TO_DEVICE);
1760 if (dma_mapping_error(trans->dev, phys_addr)) {
1761 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1762 txq->write_ptr);
1763 idx = -ENOMEM;
1764 goto out;
1765 }
1766
1767 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1768 }
1769
1770 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1771 out_meta->flags = cmd->flags;
1772 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1773 kzfree(txq->entries[idx].free_buf);
1774 txq->entries[idx].free_buf = dup_buf;
1775
1776 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1777
1778
1779 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1780 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1781
1782 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1783 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1784 if (ret < 0) {
1785 idx = ret;
1786 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1787 goto out;
1788 }
1789
1790
1791 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
1792 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1793
1794 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1795
1796 out:
1797 spin_unlock_bh(&txq->lock);
1798 free_dup_buf:
1799 if (idx < 0)
1800 kfree(dup_buf);
1801 return idx;
1802}
1803
1804
1805
1806
1807
1808void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1809 struct iwl_rx_cmd_buffer *rxb)
1810{
1811 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1812 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1813 u8 group_id;
1814 u32 cmd_id;
1815 int txq_id = SEQ_TO_QUEUE(sequence);
1816 int index = SEQ_TO_INDEX(sequence);
1817 int cmd_index;
1818 struct iwl_device_cmd *cmd;
1819 struct iwl_cmd_meta *meta;
1820 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1821 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1822
1823
1824
1825
1826 if (WARN(txq_id != trans_pcie->cmd_queue,
1827 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1828 txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1829 txq->write_ptr)) {
1830 iwl_print_hex_error(trans, pkt, 32);
1831 return;
1832 }
1833
1834 spin_lock_bh(&txq->lock);
1835
1836 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1837 cmd = txq->entries[cmd_index].cmd;
1838 meta = &txq->entries[cmd_index].meta;
1839 group_id = cmd->hdr.group_id;
1840 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1841
1842 iwl_pcie_tfd_unmap(trans, meta, txq, index);
1843
1844
1845 if (meta->flags & CMD_WANT_SKB) {
1846 struct page *p = rxb_steal_page(rxb);
1847
1848 meta->source->resp_pkt = pkt;
1849 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1850 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1851 }
1852
1853 if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1854 iwl_op_mode_async_cb(trans->op_mode, cmd);
1855
1856 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1857
1858 if (!(meta->flags & CMD_ASYNC)) {
1859 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1860 IWL_WARN(trans,
1861 "HCMD_ACTIVE already clear for command %s\n",
1862 iwl_get_cmd_string(trans, cmd_id));
1863 }
1864 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1865 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1866 iwl_get_cmd_string(trans, cmd_id));
1867 wake_up(&trans_pcie->wait_command_queue);
1868 }
1869
1870 if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1871 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1872 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1873 set_bit(STATUS_TRANS_IDLE, &trans->status);
1874 wake_up(&trans_pcie->d0i3_waitq);
1875 }
1876
1877 if (meta->flags & CMD_WAKE_UP_TRANS) {
1878 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1879 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1880 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1881 wake_up(&trans_pcie->d0i3_waitq);
1882 }
1883
1884 meta->flags = 0;
1885
1886 spin_unlock_bh(&txq->lock);
1887}
1888
1889#define HOST_COMPLETE_TIMEOUT (2 * HZ)
1890
1891static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1892 struct iwl_host_cmd *cmd)
1893{
1894 int ret;
1895
1896
1897 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1898 return -EINVAL;
1899
1900 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1901 if (ret < 0) {
1902 IWL_ERR(trans,
1903 "Error sending %s: enqueue_hcmd failed: %d\n",
1904 iwl_get_cmd_string(trans, cmd->id), ret);
1905 return ret;
1906 }
1907 return 0;
1908}
1909
1910static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1911 struct iwl_host_cmd *cmd)
1912{
1913 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1914 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1915 int cmd_idx;
1916 int ret;
1917
1918 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1919 iwl_get_cmd_string(trans, cmd->id));
1920
1921 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1922 &trans->status),
1923 "Command %s: a command is already active!\n",
1924 iwl_get_cmd_string(trans, cmd->id)))
1925 return -EIO;
1926
1927 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1928 iwl_get_cmd_string(trans, cmd->id));
1929
1930 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1931 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1932 pm_runtime_active(&trans_pcie->pci_dev->dev),
1933 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1934 if (!ret) {
1935 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1936 return -ETIMEDOUT;
1937 }
1938 }
1939
1940 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1941 if (cmd_idx < 0) {
1942 ret = cmd_idx;
1943 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1944 IWL_ERR(trans,
1945 "Error sending %s: enqueue_hcmd failed: %d\n",
1946 iwl_get_cmd_string(trans, cmd->id), ret);
1947 return ret;
1948 }
1949
1950 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1951 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1952 &trans->status),
1953 HOST_COMPLETE_TIMEOUT);
1954 if (!ret) {
1955 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1956 iwl_get_cmd_string(trans, cmd->id),
1957 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1958
1959 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1960 txq->read_ptr, txq->write_ptr);
1961
1962 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1963 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1964 iwl_get_cmd_string(trans, cmd->id));
1965 ret = -ETIMEDOUT;
1966
1967 iwl_trans_pcie_sync_nmi(trans);
1968 goto cancel;
1969 }
1970
1971 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1972 iwl_trans_pcie_dump_regs(trans);
1973 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1974 iwl_get_cmd_string(trans, cmd->id));
1975 dump_stack();
1976 ret = -EIO;
1977 goto cancel;
1978 }
1979
1980 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1981 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1982 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1983 ret = -ERFKILL;
1984 goto cancel;
1985 }
1986
1987 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1988 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1989 iwl_get_cmd_string(trans, cmd->id));
1990 ret = -EIO;
1991 goto cancel;
1992 }
1993
1994 return 0;
1995
1996cancel:
1997 if (cmd->flags & CMD_WANT_SKB) {
1998
1999
2000
2001
2002
2003
2004 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
2005 }
2006
2007 if (cmd->resp_pkt) {
2008 iwl_free_resp(cmd);
2009 cmd->resp_pkt = NULL;
2010 }
2011
2012 return ret;
2013}
2014
2015int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
2016{
2017
2018 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2019 return -ENODEV;
2020
2021 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
2022 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
2023 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
2024 cmd->id);
2025 return -ERFKILL;
2026 }
2027
2028 if (cmd->flags & CMD_ASYNC)
2029 return iwl_pcie_send_hcmd_async(trans, cmd);
2030
2031
2032 return iwl_pcie_send_hcmd_sync(trans, cmd);
2033}
2034
2035static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
2036 struct iwl_txq *txq, u8 hdr_len,
2037 struct iwl_cmd_meta *out_meta)
2038{
2039 u16 head_tb_len;
2040 int i;
2041
2042
2043
2044
2045
2046 head_tb_len = skb_headlen(skb) - hdr_len;
2047
2048 if (head_tb_len > 0) {
2049 dma_addr_t tb_phys = dma_map_single(trans->dev,
2050 skb->data + hdr_len,
2051 head_tb_len, DMA_TO_DEVICE);
2052 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2053 return -EINVAL;
2054 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2055 skb->data + hdr_len,
2056 head_tb_len);
2057 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
2058 }
2059
2060
2061 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2062 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2063 dma_addr_t tb_phys;
2064 int tb_idx;
2065
2066 if (!skb_frag_size(frag))
2067 continue;
2068
2069 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2070 skb_frag_size(frag), DMA_TO_DEVICE);
2071
2072 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2073 return -EINVAL;
2074 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2075 skb_frag_address(frag),
2076 skb_frag_size(frag));
2077 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2078 skb_frag_size(frag), false);
2079 if (tb_idx < 0)
2080 return tb_idx;
2081
2082 out_meta->tbs |= BIT(tb_idx);
2083 }
2084
2085 return 0;
2086}
2087
2088#ifdef CONFIG_INET
2089struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2090{
2091 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2092 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2093
2094 if (!p->page)
2095 goto alloc;
2096
2097
2098 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2099 return p;
2100
2101
2102 __free_page(p->page);
2103
2104alloc:
2105 p->page = alloc_page(GFP_ATOMIC);
2106 if (!p->page)
2107 return NULL;
2108 p->pos = page_address(p->page);
2109 return p;
2110}
2111
2112static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2113 bool ipv6, unsigned int len)
2114{
2115 if (ipv6) {
2116 struct ipv6hdr *iphv6 = iph;
2117
2118 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2119 len + tcph->doff * 4,
2120 IPPROTO_TCP, 0);
2121 } else {
2122 struct iphdr *iphv4 = iph;
2123
2124 ip_send_check(iphv4);
2125 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2126 len + tcph->doff * 4,
2127 IPPROTO_TCP, 0);
2128 }
2129}
2130
2131static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2132 struct iwl_txq *txq, u8 hdr_len,
2133 struct iwl_cmd_meta *out_meta,
2134 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2135{
2136 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2137 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2138 struct ieee80211_hdr *hdr = (void *)skb->data;
2139 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2140 unsigned int mss = skb_shinfo(skb)->gso_size;
2141 u16 length, iv_len, amsdu_pad;
2142 u8 *start_hdr;
2143 struct iwl_tso_hdr_page *hdr_page;
2144 struct page **page_ptr;
2145 struct tso_t tso;
2146
2147
2148 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2149 iv_len = ieee80211_has_protected(hdr->frame_control) ?
2150 IEEE80211_CCMP_HDR_LEN : 0;
2151
2152 trace_iwlwifi_dev_tx(trans->dev, skb,
2153 iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2154 trans_pcie->tfd_size,
2155 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2156
2157 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2158 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2159 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2160 amsdu_pad = 0;
2161
2162
2163 hdr_room = DIV_ROUND_UP(total_len, mss) *
2164 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2165
2166
2167 hdr_page = get_page_hdr(trans, hdr_room);
2168 if (!hdr_page)
2169 return -ENOMEM;
2170
2171 get_page(hdr_page->page);
2172 start_hdr = hdr_page->pos;
2173 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2174 *page_ptr = hdr_page->page;
2175 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2176 hdr_page->pos += iv_len;
2177
2178
2179
2180
2181
2182 skb_pull(skb, hdr_len + iv_len);
2183
2184
2185
2186
2187
2188
2189 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2190
2191 tso_start(skb, &tso);
2192
2193 while (total_len) {
2194
2195 unsigned int data_left =
2196 min_t(unsigned int, mss, total_len);
2197 struct sk_buff *csum_skb = NULL;
2198 unsigned int hdr_tb_len;
2199 dma_addr_t hdr_tb_phys;
2200 struct tcphdr *tcph;
2201 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2202
2203 total_len -= data_left;
2204
2205 memset(hdr_page->pos, 0, amsdu_pad);
2206 hdr_page->pos += amsdu_pad;
2207 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2208 data_left)) & 0x3;
2209 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2210 hdr_page->pos += ETH_ALEN;
2211 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2212 hdr_page->pos += ETH_ALEN;
2213
2214 length = snap_ip_tcp_hdrlen + data_left;
2215 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2216 hdr_page->pos += sizeof(length);
2217
2218
2219
2220
2221
2222 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2223 iph = hdr_page->pos + 8;
2224 tcph = (void *)(iph + ip_hdrlen);
2225
2226
2227 if (trans_pcie->sw_csum_tx) {
2228 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2229 GFP_ATOMIC);
2230 if (!csum_skb)
2231 return -ENOMEM;
2232
2233 iwl_compute_pseudo_hdr_csum(iph, tcph,
2234 skb->protocol ==
2235 htons(ETH_P_IPV6),
2236 data_left);
2237
2238 skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2239 skb_reset_transport_header(csum_skb);
2240 csum_skb->csum_start =
2241 (unsigned char *)tcp_hdr(csum_skb) -
2242 csum_skb->head;
2243 }
2244
2245 hdr_page->pos += snap_ip_tcp_hdrlen;
2246
2247 hdr_tb_len = hdr_page->pos - start_hdr;
2248 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2249 hdr_tb_len, DMA_TO_DEVICE);
2250 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2251 dev_kfree_skb(csum_skb);
2252 return -EINVAL;
2253 }
2254 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2255 hdr_tb_len, false);
2256 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
2257 hdr_tb_len);
2258
2259 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2260
2261
2262 start_hdr = hdr_page->pos;
2263
2264
2265 while (data_left) {
2266 unsigned int size = min_t(unsigned int, tso.size,
2267 data_left);
2268 dma_addr_t tb_phys;
2269
2270 if (trans_pcie->sw_csum_tx)
2271 skb_put_data(csum_skb, tso.data, size);
2272
2273 tb_phys = dma_map_single(trans->dev, tso.data,
2274 size, DMA_TO_DEVICE);
2275 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2276 dev_kfree_skb(csum_skb);
2277 return -EINVAL;
2278 }
2279
2280 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2281 size, false);
2282 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
2283 size);
2284
2285 data_left -= size;
2286 tso_build_data(skb, &tso, size);
2287 }
2288
2289
2290 if (trans_pcie->sw_csum_tx) {
2291 __wsum csum;
2292
2293 csum = skb_checksum(csum_skb,
2294 skb_checksum_start_offset(csum_skb),
2295 csum_skb->len -
2296 skb_checksum_start_offset(csum_skb),
2297 0);
2298 dev_kfree_skb(csum_skb);
2299 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2300 hdr_tb_len, DMA_TO_DEVICE);
2301 tcph->check = csum_fold(csum);
2302 dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2303 hdr_tb_len, DMA_TO_DEVICE);
2304 }
2305 }
2306
2307
2308 skb_push(skb, hdr_len + iv_len);
2309
2310 return 0;
2311}
2312#else
2313static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2314 struct iwl_txq *txq, u8 hdr_len,
2315 struct iwl_cmd_meta *out_meta,
2316 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2317{
2318
2319 WARN_ON(1);
2320
2321 return -1;
2322}
2323#endif
2324
2325int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2326 struct iwl_device_cmd *dev_cmd, int txq_id)
2327{
2328 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2329 struct ieee80211_hdr *hdr;
2330 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2331 struct iwl_cmd_meta *out_meta;
2332 struct iwl_txq *txq;
2333 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2334 void *tb1_addr;
2335 void *tfd;
2336 u16 len, tb1_len;
2337 bool wait_write_ptr;
2338 __le16 fc;
2339 u8 hdr_len;
2340 u16 wifi_seq;
2341 bool amsdu;
2342
2343 txq = trans_pcie->txq[txq_id];
2344
2345 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2346 "TX on unused queue %d\n", txq_id))
2347 return -EINVAL;
2348
2349 if (unlikely(trans_pcie->sw_csum_tx &&
2350 skb->ip_summed == CHECKSUM_PARTIAL)) {
2351 int offs = skb_checksum_start_offset(skb);
2352 int csum_offs = offs + skb->csum_offset;
2353 __wsum csum;
2354
2355 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2356 return -1;
2357
2358 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2359 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2360
2361 skb->ip_summed = CHECKSUM_UNNECESSARY;
2362 }
2363
2364 if (skb_is_nonlinear(skb) &&
2365 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2366 __skb_linearize(skb))
2367 return -ENOMEM;
2368
2369
2370
2371
2372 hdr = (struct ieee80211_hdr *)skb->data;
2373 fc = hdr->frame_control;
2374 hdr_len = ieee80211_hdrlen(fc);
2375
2376 spin_lock(&txq->lock);
2377
2378 if (iwl_queue_space(trans, txq) < txq->high_mark) {
2379 iwl_stop_queue(trans, txq);
2380
2381
2382 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
2383 struct iwl_device_cmd **dev_cmd_ptr;
2384
2385 dev_cmd_ptr = (void *)((u8 *)skb->cb +
2386 trans_pcie->dev_cmd_offs);
2387
2388 *dev_cmd_ptr = dev_cmd;
2389 __skb_queue_tail(&txq->overflow_q, skb);
2390
2391 spin_unlock(&txq->lock);
2392 return 0;
2393 }
2394 }
2395
2396
2397
2398
2399
2400
2401 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2402 WARN_ONCE(txq->ampdu &&
2403 (wifi_seq & 0xff) != txq->write_ptr,
2404 "Q: %d WiFi Seq %d tfdNum %d",
2405 txq_id, wifi_seq, txq->write_ptr);
2406
2407
2408 txq->entries[txq->write_ptr].skb = skb;
2409 txq->entries[txq->write_ptr].cmd = dev_cmd;
2410
2411 dev_cmd->hdr.sequence =
2412 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2413 INDEX_TO_SEQ(txq->write_ptr)));
2414
2415 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2416 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2417 offsetof(struct iwl_tx_cmd, scratch);
2418
2419 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2420 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2421
2422
2423 out_meta = &txq->entries[txq->write_ptr].meta;
2424 out_meta->flags = 0;
2425
2426
2427
2428
2429
2430
2431
2432 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2433 hdr_len - IWL_FIRST_TB_SIZE;
2434
2435 amsdu = ieee80211_is_data_qos(fc) &&
2436 (*ieee80211_get_qos_ctl(hdr) &
2437 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2438 if (trans_pcie->sw_csum_tx || !amsdu) {
2439 tb1_len = ALIGN(len, 4);
2440
2441 if (tb1_len != len)
2442 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2443 } else {
2444 tb1_len = len;
2445 }
2446
2447
2448
2449
2450
2451 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2452 IWL_FIRST_TB_SIZE, true);
2453
2454
2455 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2456
2457
2458 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2459 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2460 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2461 goto out_err;
2462 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2463
2464 trace_iwlwifi_dev_tx(trans->dev, skb,
2465 iwl_pcie_get_tfd(trans, txq,
2466 txq->write_ptr),
2467 trans_pcie->tfd_size,
2468 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2469 hdr_len);
2470
2471
2472
2473
2474
2475
2476
2477 if (amsdu && skb_shinfo(skb)->gso_size) {
2478 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2479 out_meta, dev_cmd,
2480 tb1_len)))
2481 goto out_err;
2482 } else {
2483 struct sk_buff *frag;
2484
2485 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2486 out_meta)))
2487 goto out_err;
2488
2489 skb_walk_frags(skb, frag) {
2490 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
2491 out_meta)))
2492 goto out_err;
2493 }
2494 }
2495
2496
2497 memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
2498
2499 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2500
2501 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2502 iwl_pcie_tfd_get_num_tbs(trans, tfd));
2503
2504 wait_write_ptr = ieee80211_has_morefrags(fc);
2505
2506
2507 if (txq->read_ptr == txq->write_ptr) {
2508 if (txq->wd_timeout) {
2509
2510
2511
2512
2513
2514
2515 if (!txq->frozen)
2516 mod_timer(&txq->stuck_timer,
2517 jiffies + txq->wd_timeout);
2518 else
2519 txq->frozen_expiry_remainder = txq->wd_timeout;
2520 }
2521 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
2522 iwl_trans_ref(trans);
2523 }
2524
2525
2526 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
2527 if (!wait_write_ptr)
2528 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2529
2530
2531
2532
2533
2534 spin_unlock(&txq->lock);
2535 return 0;
2536out_err:
2537 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2538 spin_unlock(&txq->lock);
2539 return -1;
2540}
2541