linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4#include "../wifi.h"
   5#include "../pci.h"
   6#include "../ps.h"
   7#include "../core.h"
   8#include "reg.h"
   9#include "def.h"
  10#include "hw.h"
  11#include "phy.h"
  12#include "../rtl8192c/phy_common.h"
  13#include "rf.h"
  14#include "dm.h"
  15#include "../rtl8192c/dm_common.h"
  16#include "../rtl8192c/fw_common.h"
  17#include "table.h"
  18
  19static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  20
  21u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
  22                            enum radio_path rfpath, u32 regaddr, u32 bitmask)
  23{
  24        struct rtl_priv *rtlpriv = rtl_priv(hw);
  25        u32 original_value, readback_value, bitshift;
  26        struct rtl_phy *rtlphy = &(rtlpriv->phy);
  27
  28        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  29                 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
  30                 regaddr, rfpath, bitmask);
  31
  32        spin_lock(&rtlpriv->locks.rf_lock);
  33
  34        if (rtlphy->rf_mode != RF_OP_BY_FW) {
  35                original_value = _rtl92c_phy_rf_serial_read(hw,
  36                                                            rfpath, regaddr);
  37        } else {
  38                original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  39                                                               rfpath, regaddr);
  40        }
  41
  42        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  43        readback_value = (original_value & bitmask) >> bitshift;
  44
  45        spin_unlock(&rtlpriv->locks.rf_lock);
  46
  47        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  48                 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
  49                 regaddr, rfpath, bitmask, original_value);
  50
  51        return readback_value;
  52}
  53
  54bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
  55{
  56        struct rtl_priv *rtlpriv = rtl_priv(hw);
  57        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  58        bool is92c = IS_92C_SERIAL(rtlhal->version);
  59        bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
  60
  61        if (is92c)
  62                rtl_write_byte(rtlpriv, 0x14, 0x71);
  63        else
  64                rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
  65        return rtstatus;
  66}
  67
  68bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
  69{
  70        bool rtstatus = true;
  71        struct rtl_priv *rtlpriv = rtl_priv(hw);
  72        u16 regval;
  73        u32 regvaldw;
  74        u8 reg_hwparafile = 1;
  75
  76        _rtl92c_phy_init_bb_rf_register_definition(hw);
  77        regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
  78        rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
  79                       regval | BIT(13) | BIT(0) | BIT(1));
  80        rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
  81        rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
  82        rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
  83        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
  84                       FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
  85                       FEN_BB_GLB_RSTN | FEN_BBRSTB);
  86        rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
  87        regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
  88        rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
  89        if (reg_hwparafile == 1)
  90                rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
  91        return rtstatus;
  92}
  93
  94void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
  95                            enum radio_path rfpath,
  96                            u32 regaddr, u32 bitmask, u32 data)
  97{
  98        struct rtl_priv *rtlpriv = rtl_priv(hw);
  99        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 100        u32 original_value, bitshift;
 101
 102        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 103                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 104                 regaddr, bitmask, data, rfpath);
 105
 106        spin_lock(&rtlpriv->locks.rf_lock);
 107
 108        if (rtlphy->rf_mode != RF_OP_BY_FW) {
 109                if (bitmask != RFREG_OFFSET_MASK) {
 110                        original_value = _rtl92c_phy_rf_serial_read(hw,
 111                                                                    rfpath,
 112                                                                    regaddr);
 113                        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 114                        data =
 115                            ((original_value & (~bitmask)) |
 116                             (data << bitshift));
 117                }
 118
 119                _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
 120        } else {
 121                if (bitmask != RFREG_OFFSET_MASK) {
 122                        original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 123                                                                       rfpath,
 124                                                                       regaddr);
 125                        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 126                        data =
 127                            ((original_value & (~bitmask)) |
 128                             (data << bitshift));
 129                }
 130                _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 131        }
 132
 133        spin_unlock(&rtlpriv->locks.rf_lock);
 134
 135        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 136                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 137                 regaddr, bitmask, data, rfpath);
 138}
 139
 140static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 141{
 142        struct rtl_priv *rtlpriv = rtl_priv(hw);
 143        u32 i;
 144        u32 arraylength;
 145        u32 *ptrarray;
 146
 147        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
 148        arraylength = MAC_2T_ARRAYLENGTH;
 149        ptrarray = RTL8192CEMAC_2T_ARRAY;
 150        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
 151        for (i = 0; i < arraylength; i = i + 2)
 152                rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 153        return true;
 154}
 155
 156bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 157                                            u8 configtype)
 158{
 159        int i;
 160        u32 *phy_regarray_table;
 161        u32 *agctab_array_table;
 162        u16 phy_reg_arraylen, agctab_arraylen;
 163        struct rtl_priv *rtlpriv = rtl_priv(hw);
 164        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 165
 166        if (IS_92C_SERIAL(rtlhal->version)) {
 167                agctab_arraylen = AGCTAB_2TARRAYLENGTH;
 168                agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
 169                phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
 170                phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
 171        } else {
 172                agctab_arraylen = AGCTAB_1TARRAYLENGTH;
 173                agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
 174                phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
 175                phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
 176        }
 177        if (configtype == BASEBAND_CONFIG_PHY_REG) {
 178                for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 179                        rtl_addr_delay(phy_regarray_table[i]);
 180                        rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 181                                      phy_regarray_table[i + 1]);
 182                        udelay(1);
 183                        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 184                                 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 185                                 phy_regarray_table[i],
 186                                 phy_regarray_table[i + 1]);
 187                }
 188        } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 189                for (i = 0; i < agctab_arraylen; i = i + 2) {
 190                        rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 191                                      agctab_array_table[i + 1]);
 192                        udelay(1);
 193                        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 194                                 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 195                                 agctab_array_table[i],
 196                                 agctab_array_table[i + 1]);
 197                }
 198        }
 199        return true;
 200}
 201
 202bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 203                                              u8 configtype)
 204{
 205        struct rtl_priv *rtlpriv = rtl_priv(hw);
 206        int i;
 207        u32 *phy_regarray_table_pg;
 208        u16 phy_regarray_pg_len;
 209
 210        phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
 211        phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
 212
 213        if (configtype == BASEBAND_CONFIG_PHY_REG) {
 214                for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 215                        rtl_addr_delay(phy_regarray_table_pg[i]);
 216
 217                        _rtl92c_store_pwrindex_diffrate_offset(hw,
 218                                               phy_regarray_table_pg[i],
 219                                               phy_regarray_table_pg[i + 1],
 220                                               phy_regarray_table_pg[i + 2]);
 221                }
 222        } else {
 223
 224                RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 225                         "configtype != BaseBand_Config_PHY_REG\n");
 226        }
 227        return true;
 228}
 229
 230bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 231                                          enum radio_path rfpath)
 232{
 233
 234        int i;
 235        u32 *radioa_array_table;
 236        u32 *radiob_array_table;
 237        u16 radioa_arraylen, radiob_arraylen;
 238        struct rtl_priv *rtlpriv = rtl_priv(hw);
 239        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 240
 241        if (IS_92C_SERIAL(rtlhal->version)) {
 242                radioa_arraylen = RADIOA_2TARRAYLENGTH;
 243                radioa_array_table = RTL8192CERADIOA_2TARRAY;
 244                radiob_arraylen = RADIOB_2TARRAYLENGTH;
 245                radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
 246                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 247                         "Radio_A:RTL8192CERADIOA_2TARRAY\n");
 248                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 249                         "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
 250        } else {
 251                radioa_arraylen = RADIOA_1TARRAYLENGTH;
 252                radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
 253                radiob_arraylen = RADIOB_1TARRAYLENGTH;
 254                radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
 255                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 256                         "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
 257                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 258                         "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
 259        }
 260        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
 261        switch (rfpath) {
 262        case RF90_PATH_A:
 263                for (i = 0; i < radioa_arraylen; i = i + 2) {
 264                        rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
 265                                        RFREG_OFFSET_MASK,
 266                                        radioa_array_table[i + 1]);
 267                }
 268                break;
 269        case RF90_PATH_B:
 270                for (i = 0; i < radiob_arraylen; i = i + 2) {
 271                        rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
 272                                        RFREG_OFFSET_MASK,
 273                                        radiob_array_table[i + 1]);
 274                }
 275                break;
 276        case RF90_PATH_C:
 277        case RF90_PATH_D:
 278                pr_info("Incorrect rfpath %#x\n", rfpath);
 279                break;
 280        default:
 281                pr_info("switch case %#x not processed\n", rfpath);
 282                break;
 283        }
 284        return true;
 285}
 286
 287void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 288{
 289        struct rtl_priv *rtlpriv = rtl_priv(hw);
 290        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 291        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 292        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 293        u8 reg_bw_opmode;
 294        u8 reg_prsr_rsc;
 295
 296        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 297                 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 298                 "20MHz" : "40MHz");
 299
 300        if (is_hal_stop(rtlhal)) {
 301                rtlphy->set_bwmode_inprogress = false;
 302                return;
 303        }
 304
 305        reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 306        reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 307
 308        switch (rtlphy->current_chan_bw) {
 309        case HT_CHANNEL_WIDTH_20:
 310                reg_bw_opmode |= BW_OPMODE_20MHZ;
 311                rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 312                break;
 313        case HT_CHANNEL_WIDTH_20_40:
 314                reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 315                rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 316                reg_prsr_rsc =
 317                    (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 318                rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 319                break;
 320        default:
 321                pr_info("unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 322                break;
 323        }
 324
 325        switch (rtlphy->current_chan_bw) {
 326        case HT_CHANNEL_WIDTH_20:
 327                rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 328                rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 329                rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 330                break;
 331        case HT_CHANNEL_WIDTH_20_40:
 332                rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 333                rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 334
 335                rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 336                              (mac->cur_40_prime_sc >> 1));
 337                rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 338                rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
 339
 340                rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 341                              (mac->cur_40_prime_sc ==
 342                               HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 343                break;
 344        default:
 345                pr_err("unknown bandwidth: %#X\n",
 346                       rtlphy->current_chan_bw);
 347                break;
 348        }
 349        rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 350        rtlphy->set_bwmode_inprogress = false;
 351        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 352}
 353
 354void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 355{
 356        u8 tmpreg;
 357        u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 358        struct rtl_priv *rtlpriv = rtl_priv(hw);
 359
 360        tmpreg = rtl_read_byte(rtlpriv, 0xd03);
 361
 362        if ((tmpreg & 0x70) != 0)
 363                rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 364        else
 365                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 366
 367        if ((tmpreg & 0x70) != 0) {
 368                rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
 369
 370                if (is2t)
 371                        rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 372                                                  MASK12BITS);
 373
 374                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 375                              (rf_a_mode & 0x8FFFF) | 0x10000);
 376
 377                if (is2t)
 378                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 379                                      (rf_b_mode & 0x8FFFF) | 0x10000);
 380        }
 381        lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
 382
 383        rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
 384
 385        mdelay(100);
 386
 387        if ((tmpreg & 0x70) != 0) {
 388                rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 389                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
 390
 391                if (is2t)
 392                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 393                                      rf_b_mode);
 394        } else {
 395                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 396        }
 397}
 398
 399static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
 400{
 401        u32 u4b_tmp;
 402        u8 delay = 5;
 403        struct rtl_priv *rtlpriv = rtl_priv(hw);
 404
 405        rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 406        rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 407        rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 408        u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 409        while (u4b_tmp != 0 && delay > 0) {
 410                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
 411                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 412                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 413                u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 414                delay--;
 415        }
 416        if (delay == 0) {
 417                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
 418                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 419                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
 420                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 421                RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 422                         "Switch RF timeout !!!\n");
 423                return;
 424        }
 425        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 426        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
 427}
 428
 429static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
 430                                            enum rf_pwrstate rfpwr_state)
 431{
 432        struct rtl_priv *rtlpriv = rtl_priv(hw);
 433        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 434        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 435        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 436        bool bresult = true;
 437        u8 i, queue_id;
 438        struct rtl8192_tx_ring *ring = NULL;
 439
 440        switch (rfpwr_state) {
 441        case ERFON:{
 442                        if ((ppsc->rfpwr_state == ERFOFF) &&
 443                            RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 444                                bool rtstatus;
 445                                u32 initializecount = 0;
 446
 447                                do {
 448                                        initializecount++;
 449                                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 450                                                 "IPS Set eRf nic enable\n");
 451                                        rtstatus = rtl_ps_enable_nic(hw);
 452                                } while (!rtstatus && (initializecount < 10));
 453                                RT_CLEAR_PS_LEVEL(ppsc,
 454                                                  RT_RF_OFF_LEVL_HALT_NIC);
 455                        } else {
 456                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 457                                         "Set ERFON sleeped:%d ms\n",
 458                                         jiffies_to_msecs(jiffies -
 459                                                          ppsc->
 460                                                          last_sleep_jiffies));
 461                                ppsc->last_awake_jiffies = jiffies;
 462                                rtl92ce_phy_set_rf_on(hw);
 463                        }
 464                        if (mac->link_state == MAC80211_LINKED) {
 465                                rtlpriv->cfg->ops->led_control(hw,
 466                                                               LED_CTL_LINK);
 467                        } else {
 468                                rtlpriv->cfg->ops->led_control(hw,
 469                                                               LED_CTL_NO_LINK);
 470                        }
 471                        break;
 472                }
 473        case ERFOFF:{
 474                        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 475                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 476                                         "IPS Set eRf nic disable\n");
 477                                rtl_ps_disable_nic(hw);
 478                                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 479                        } else {
 480                                if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 481                                        rtlpriv->cfg->ops->led_control(hw,
 482                                                               LED_CTL_NO_LINK);
 483                                } else {
 484                                        rtlpriv->cfg->ops->led_control(hw,
 485                                                             LED_CTL_POWER_OFF);
 486                                }
 487                        }
 488                        break;
 489                }
 490        case ERFSLEEP:{
 491                        if (ppsc->rfpwr_state == ERFOFF)
 492                                break;
 493                        for (queue_id = 0, i = 0;
 494                             queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 495                                ring = &pcipriv->dev.tx_ring[queue_id];
 496                                if (queue_id == BEACON_QUEUE ||
 497                                    skb_queue_len(&ring->queue) == 0) {
 498                                        queue_id++;
 499                                        continue;
 500                                } else {
 501                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 502                                                 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
 503                                                 i + 1, queue_id,
 504                                                 skb_queue_len(&ring->queue));
 505
 506                                        udelay(10);
 507                                        i++;
 508                                }
 509                                if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 510                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 511                                                 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
 512                                                 MAX_DOZE_WAITING_TIMES_9x,
 513                                                 queue_id,
 514                                                 skb_queue_len(&ring->queue));
 515                                        break;
 516                                }
 517                        }
 518                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 519                                 "Set ERFSLEEP awaked:%d ms\n",
 520                                 jiffies_to_msecs(jiffies -
 521                                                  ppsc->last_awake_jiffies));
 522                        ppsc->last_sleep_jiffies = jiffies;
 523                        _rtl92ce_phy_set_rf_sleep(hw);
 524                        break;
 525                }
 526        default:
 527                pr_err("switch case %#x not processed\n",
 528                       rfpwr_state);
 529                bresult = false;
 530                break;
 531        }
 532        if (bresult)
 533                ppsc->rfpwr_state = rfpwr_state;
 534        return bresult;
 535}
 536
 537bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
 538                                   enum rf_pwrstate rfpwr_state)
 539{
 540        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 541
 542        bool bresult = false;
 543
 544        if (rfpwr_state == ppsc->rfpwr_state)
 545                return bresult;
 546        bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
 547        return bresult;
 548}
 549