linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4#include "../wifi.h"
   5#include "../core.h"
   6#include "../pci.h"
   7#include "../base.h"
   8#include "reg.h"
   9#include "def.h"
  10#include "phy.h"
  11#include "dm.h"
  12#include "../rtl8192c/dm_common.h"
  13#include "../rtl8192c/fw_common.h"
  14#include "../rtl8192c/phy_common.h"
  15#include "hw.h"
  16#include "rf.h"
  17#include "sw.h"
  18#include "trx.h"
  19#include "led.h"
  20
  21#include <linux/module.h>
  22
  23static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)
  24{
  25        struct rtl_priv *rtlpriv = rtl_priv(hw);
  26        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  27
  28        /*close ASPM for AMD defaultly */
  29        rtlpci->const_amdpci_aspm = 0;
  30
  31        /*
  32         * ASPM PS mode.
  33         * 0 - Disable ASPM,
  34         * 1 - Enable ASPM without Clock Req,
  35         * 2 - Enable ASPM with Clock Req,
  36         * 3 - Alwyas Enable ASPM with Clock Req,
  37         * 4 - Always Enable ASPM without Clock Req.
  38         * set defult to RTL8192CE:3 RTL8192E:2
  39         * */
  40        rtlpci->const_pci_aspm = 3;
  41
  42        /*Setting for PCI-E device */
  43        rtlpci->const_devicepci_aspm_setting = 0x03;
  44
  45        /*Setting for PCI-E bridge */
  46        rtlpci->const_hostpci_aspm_setting = 0x02;
  47
  48        /*
  49         * In Hw/Sw Radio Off situation.
  50         * 0 - Default,
  51         * 1 - From ASPM setting without low Mac Pwr,
  52         * 2 - From ASPM setting with low Mac Pwr,
  53         * 3 - Bus D3
  54         * set default to RTL8192CE:0 RTL8192SE:2
  55         */
  56        rtlpci->const_hwsw_rfoff_d3 = 0;
  57
  58        /*
  59         * This setting works for those device with
  60         * backdoor ASPM setting such as EPHY setting.
  61         * 0 - Not support ASPM,
  62         * 1 - Support ASPM,
  63         * 2 - According to chipset.
  64         */
  65        rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
  66}
  67
  68int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
  69{
  70        int err;
  71        struct rtl_priv *rtlpriv = rtl_priv(hw);
  72        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  73        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  74        char *fw_name;
  75
  76        rtl8192ce_bt_reg_init(hw);
  77
  78        rtlpriv->dm.dm_initialgain_enable = true;
  79        rtlpriv->dm.dm_flag = 0;
  80        rtlpriv->dm.disable_framebursting = false;
  81        rtlpriv->dm.thermalvalue = 0;
  82        rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
  83
  84        /* compatible 5G band 88ce just 2.4G band & smsp */
  85        rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
  86        rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
  87        rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
  88
  89        rtlpci->receive_config = (RCR_APPFCS |
  90                                  RCR_AMF |
  91                                  RCR_ADF |
  92                                  RCR_APP_MIC |
  93                                  RCR_APP_ICV |
  94                                  RCR_AICV |
  95                                  RCR_ACRC32 |
  96                                  RCR_AB |
  97                                  RCR_AM |
  98                                  RCR_APM |
  99                                  RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
 100
 101        rtlpci->irq_mask[0] =
 102            (u32) (IMR_ROK |
 103                   IMR_VODOK |
 104                   IMR_VIDOK |
 105                   IMR_BEDOK |
 106                   IMR_BKDOK |
 107                   IMR_MGNTDOK |
 108                   IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
 109
 110        rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
 111
 112        /* for LPS & IPS */
 113        rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 114        rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 115        rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 116        rtlpriv->cfg->mod_params->sw_crypto =
 117                rtlpriv->cfg->mod_params->sw_crypto;
 118        if (!rtlpriv->psc.inactiveps)
 119                pr_info("rtl8192ce: Power Save off (module option)\n");
 120        if (!rtlpriv->psc.fwctrl_lps)
 121                pr_info("rtl8192ce: FW Power Save off (module option)\n");
 122        rtlpriv->psc.reg_fwctrl_lps = 3;
 123        rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 124        /* for ASPM, you can close aspm through
 125         * set const_support_pciaspm = 0 */
 126        rtl92c_init_aspm_vars(hw);
 127
 128        if (rtlpriv->psc.reg_fwctrl_lps == 1)
 129                rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 130        else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 131                rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 132        else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 133                rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 134
 135        /* for firmware buf */
 136        rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
 137        if (!rtlpriv->rtlhal.pfirmware) {
 138                pr_err("Can't alloc buffer for fw\n");
 139                return 1;
 140        }
 141
 142        /* request fw */
 143        if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
 144            !IS_92C_SERIAL(rtlhal->version))
 145                fw_name = "rtlwifi/rtl8192cfwU.bin";
 146        else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
 147                fw_name = "rtlwifi/rtl8192cfwU_B.bin";
 148        else
 149                fw_name = "rtlwifi/rtl8192cfw.bin";
 150
 151        rtlpriv->max_fw_size = 0x4000;
 152        pr_info("Using firmware %s\n", fw_name);
 153        err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
 154                                      rtlpriv->io.dev, GFP_KERNEL, hw,
 155                                      rtl_fw_cb);
 156        if (err) {
 157                pr_err("Failed to request firmware!\n");
 158                vfree(rtlpriv->rtlhal.pfirmware);
 159                rtlpriv->rtlhal.pfirmware = NULL;
 160                return 1;
 161        }
 162
 163        return 0;
 164}
 165
 166void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
 167{
 168        struct rtl_priv *rtlpriv = rtl_priv(hw);
 169
 170        if (rtlpriv->rtlhal.pfirmware) {
 171                vfree(rtlpriv->rtlhal.pfirmware);
 172                rtlpriv->rtlhal.pfirmware = NULL;
 173        }
 174}
 175
 176static struct rtl_hal_ops rtl8192ce_hal_ops = {
 177        .init_sw_vars = rtl92c_init_sw_vars,
 178        .deinit_sw_vars = rtl92c_deinit_sw_vars,
 179        .read_eeprom_info = rtl92ce_read_eeprom_info,
 180        .interrupt_recognized = rtl92ce_interrupt_recognized,
 181        .hw_init = rtl92ce_hw_init,
 182        .hw_disable = rtl92ce_card_disable,
 183        .hw_suspend = rtl92ce_suspend,
 184        .hw_resume = rtl92ce_resume,
 185        .enable_interrupt = rtl92ce_enable_interrupt,
 186        .disable_interrupt = rtl92ce_disable_interrupt,
 187        .set_network_type = rtl92ce_set_network_type,
 188        .set_chk_bssid = rtl92ce_set_check_bssid,
 189        .set_qos = rtl92ce_set_qos,
 190        .set_bcn_reg = rtl92ce_set_beacon_related_registers,
 191        .set_bcn_intv = rtl92ce_set_beacon_interval,
 192        .update_interrupt_mask = rtl92ce_update_interrupt_mask,
 193        .get_hw_reg = rtl92ce_get_hw_reg,
 194        .set_hw_reg = rtl92ce_set_hw_reg,
 195        .update_rate_tbl = rtl92ce_update_hal_rate_tbl,
 196        .fill_tx_desc = rtl92ce_tx_fill_desc,
 197        .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
 198        .query_rx_desc = rtl92ce_rx_query_desc,
 199        .set_channel_access = rtl92ce_update_channel_access_setting,
 200        .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
 201        .set_bw_mode = rtl92c_phy_set_bw_mode,
 202        .switch_channel = rtl92c_phy_sw_chnl,
 203        .dm_watchdog = rtl92c_dm_watchdog,
 204        .scan_operation_backup = rtl_phy_scan_operation_backup,
 205        .set_rf_power_state = rtl92c_phy_set_rf_power_state,
 206        .led_control = rtl92ce_led_control,
 207        .set_desc = rtl92ce_set_desc,
 208        .get_desc = rtl92ce_get_desc,
 209        .is_tx_desc_closed = rtl92ce_is_tx_desc_closed,
 210        .tx_polling = rtl92ce_tx_polling,
 211        .enable_hw_sec = rtl92ce_enable_hw_security_config,
 212        .set_key = rtl92ce_set_key,
 213        .init_sw_leds = rtl92ce_init_sw_leds,
 214        .get_bbreg = rtl92c_phy_query_bb_reg,
 215        .set_bbreg = rtl92c_phy_set_bb_reg,
 216        .set_rfreg = rtl92ce_phy_set_rf_reg,
 217        .get_rfreg = rtl92c_phy_query_rf_reg,
 218        .phy_rf6052_config = rtl92ce_phy_rf6052_config,
 219        .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,
 220        .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,
 221        .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,
 222        .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,
 223        .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,
 224        .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,
 225        .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,
 226        .get_btc_status = rtl_btc_status_false,
 227};
 228
 229static struct rtl_mod_params rtl92ce_mod_params = {
 230        .sw_crypto = false,
 231        .inactiveps = true,
 232        .swctrl_lps = false,
 233        .fwctrl_lps = true,
 234        .aspm_support = 1,
 235        .debug_level = 0,
 236        .debug_mask = 0,
 237};
 238
 239static const struct rtl_hal_cfg rtl92ce_hal_cfg = {
 240        .bar_id = 2,
 241        .write_readback = true,
 242        .name = "rtl92c_pci",
 243        .ops = &rtl8192ce_hal_ops,
 244        .mod_params = &rtl92ce_mod_params,
 245
 246        .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 247        .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 248        .maps[SYS_CLK] = REG_SYS_CLKR,
 249        .maps[MAC_RCR_AM] = AM,
 250        .maps[MAC_RCR_AB] = AB,
 251        .maps[MAC_RCR_ACRC32] = ACRC32,
 252        .maps[MAC_RCR_ACF] = ACF,
 253        .maps[MAC_RCR_AAP] = AAP,
 254        .maps[MAC_HIMR] = REG_HIMR,
 255        .maps[MAC_HIMRE] = REG_HIMRE,
 256
 257        .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 258        .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 259        .maps[EFUSE_CLK] = 0,
 260        .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 261        .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 262        .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 263        .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 264        .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
 265        .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 266        .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 267        .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 268        .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 269
 270        .maps[RWCAM] = REG_CAMCMD,
 271        .maps[WCAMI] = REG_CAMWRITE,
 272        .maps[RCAMO] = REG_CAMREAD,
 273        .maps[CAMDBG] = REG_CAMDBG,
 274        .maps[SECR] = REG_SECCFG,
 275        .maps[SEC_CAM_NONE] = CAM_NONE,
 276        .maps[SEC_CAM_WEP40] = CAM_WEP40,
 277        .maps[SEC_CAM_TKIP] = CAM_TKIP,
 278        .maps[SEC_CAM_AES] = CAM_AES,
 279        .maps[SEC_CAM_WEP104] = CAM_WEP104,
 280
 281        .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 282        .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 283        .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 284        .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 285        .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 286        .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 287        .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 288        .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 289        .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 290        .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 291        .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 292        .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 293        .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 294        .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 295        .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 296        .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 297
 298        .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 299        .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 300        .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
 301        .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 302        .maps[RTL_IMR_RDU] = IMR_RDU,
 303        .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 304        .maps[RTL_IMR_BDOK] = IMR_BDOK,
 305        .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 306        .maps[RTL_IMR_TBDER] = IMR_TBDER,
 307        .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 308        .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 309        .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 310        .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 311        .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 312        .maps[RTL_IMR_VODOK] = IMR_VODOK,
 313        .maps[RTL_IMR_ROK] = IMR_ROK,
 314        .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
 315
 316        .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
 317        .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
 318        .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
 319        .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
 320        .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
 321        .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
 322        .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
 323        .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
 324        .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
 325        .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
 326        .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
 327        .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
 328
 329        .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
 330        .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
 331};
 332
 333static const struct pci_device_id rtl92ce_pci_ids[] = {
 334        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
 335        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
 336        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
 337        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
 338        {},
 339};
 340
 341MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
 342
 343MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 344MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 345MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 346MODULE_LICENSE("GPL");
 347MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
 348MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");
 349MODULE_FIRMWARE("rtlwifi/rtl8192cfwU.bin");
 350MODULE_FIRMWARE("rtlwifi/rtl8192cfwU_B.bin");
 351
 352module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
 353module_param_named(debug_level, rtl92ce_mod_params.debug_level, int, 0644);
 354module_param_named(debug_mask, rtl92ce_mod_params.debug_mask, ullong, 0644);
 355module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444);
 356module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444);
 357module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444);
 358module_param_named(aspm, rtl92ce_mod_params.aspm_support, int, 0444);
 359MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 360MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 361MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 362MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 363MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
 364MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
 365MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
 366
 367static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 368
 369static struct pci_driver rtl92ce_driver = {
 370        .name = KBUILD_MODNAME,
 371        .id_table = rtl92ce_pci_ids,
 372        .probe = rtl_pci_probe,
 373        .remove = rtl_pci_disconnect,
 374        .driver.pm = &rtlwifi_pm_ops,
 375};
 376
 377module_pci_driver(rtl92ce_driver);
 378