1
2
3
4
5#include <linux/bcd.h>
6
7#include "main.h"
8#include "reg.h"
9#include "fw.h"
10#include "phy.h"
11#include "debug.h"
12
13struct phy_cfg_pair {
14 u32 addr;
15 u32 data;
16};
17
18union phy_table_tile {
19 struct rtw_phy_cond cond;
20 struct phy_cfg_pair cfg;
21};
22
23struct phy_pg_cfg_pair {
24 u32 band;
25 u32 rf_path;
26 u32 tx_num;
27 u32 addr;
28 u32 bitmask;
29 u32 data;
30};
31
32struct txpwr_lmt_cfg_pair {
33 u8 regd;
34 u8 band;
35 u8 bw;
36 u8 rs;
37 u8 ch;
38 s8 txpwr_lmt;
39};
40
41static const u32 db_invert_table[12][8] = {
42 {10, 13, 16, 20,
43 25, 32, 40, 50},
44 {64, 80, 101, 128,
45 160, 201, 256, 318},
46 {401, 505, 635, 800,
47 1007, 1268, 1596, 2010},
48 {316, 398, 501, 631,
49 794, 1000, 1259, 1585},
50 {1995, 2512, 3162, 3981,
51 5012, 6310, 7943, 10000},
52 {12589, 15849, 19953, 25119,
53 31623, 39811, 50119, 63098},
54 {79433, 100000, 125893, 158489,
55 199526, 251189, 316228, 398107},
56 {501187, 630957, 794328, 1000000,
57 1258925, 1584893, 1995262, 2511886},
58 {3162278, 3981072, 5011872, 6309573,
59 7943282, 1000000, 12589254, 15848932},
60 {19952623, 25118864, 31622777, 39810717,
61 50118723, 63095734, 79432823, 100000000},
62 {125892541, 158489319, 199526232, 251188643,
63 316227766, 398107171, 501187234, 630957345},
64 {794328235, 1000000000, 1258925412, 1584893192,
65 1995262315, 2511886432U, 3162277660U, 3981071706U}
66};
67
68u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M };
69u8 rtw_ofdm_rates[] = {
70 DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
71 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
72 DESC_RATE48M, DESC_RATE54M
73};
74u8 rtw_ht_1s_rates[] = {
75 DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
76 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
77 DESC_RATEMCS6, DESC_RATEMCS7
78};
79u8 rtw_ht_2s_rates[] = {
80 DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10,
81 DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13,
82 DESC_RATEMCS14, DESC_RATEMCS15
83};
84u8 rtw_vht_1s_rates[] = {
85 DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
86 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
87 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
88 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
89 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9
90};
91u8 rtw_vht_2s_rates[] = {
92 DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
93 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
94 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
95 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
96 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9
97};
98u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = {
99 rtw_cck_rates, rtw_ofdm_rates,
100 rtw_ht_1s_rates, rtw_ht_2s_rates,
101 rtw_vht_1s_rates, rtw_vht_2s_rates
102};
103u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = {
104 ARRAY_SIZE(rtw_cck_rates),
105 ARRAY_SIZE(rtw_ofdm_rates),
106 ARRAY_SIZE(rtw_ht_1s_rates),
107 ARRAY_SIZE(rtw_ht_2s_rates),
108 ARRAY_SIZE(rtw_vht_1s_rates),
109 ARRAY_SIZE(rtw_vht_2s_rates)
110};
111static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates);
112static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates);
113static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates);
114static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates);
115static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates);
116static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates);
117
118enum rtw_phy_band_type {
119 PHY_BAND_2G = 0,
120 PHY_BAND_5G = 1,
121};
122
123void rtw_phy_init(struct rtw_dev *rtwdev)
124{
125 struct rtw_chip_info *chip = rtwdev->chip;
126 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
127 u32 addr, mask;
128
129 dm_info->fa_history[3] = 0;
130 dm_info->fa_history[2] = 0;
131 dm_info->fa_history[1] = 0;
132 dm_info->fa_history[0] = 0;
133 dm_info->igi_bitmap = 0;
134 dm_info->igi_history[3] = 0;
135 dm_info->igi_history[2] = 0;
136 dm_info->igi_history[1] = 0;
137
138 addr = chip->dig[0].addr;
139 mask = chip->dig[0].mask;
140 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
141}
142
143void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
144{
145 struct rtw_chip_info *chip = rtwdev->chip;
146 struct rtw_hal *hal = &rtwdev->hal;
147 u32 addr, mask;
148 u8 path;
149
150 for (path = 0; path < hal->rf_path_num; path++) {
151 addr = chip->dig[path].addr;
152 mask = chip->dig[path].mask;
153 rtw_write32_mask(rtwdev, addr, mask, igi);
154 }
155}
156
157static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)
158{
159 struct rtw_chip_info *chip = rtwdev->chip;
160
161 chip->ops->false_alarm_statistics(rtwdev);
162}
163
164#define RA_FLOOR_TABLE_SIZE 7
165#define RA_FLOOR_UP_GAP 3
166
167static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi)
168{
169 u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
170 u8 new_level = 0;
171 int i;
172
173 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
174 if (i >= old_level)
175 table[i] += RA_FLOOR_UP_GAP;
176
177 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
178 if (rssi < table[i]) {
179 new_level = i;
180 break;
181 }
182 }
183
184 return new_level;
185}
186
187struct rtw_phy_stat_iter_data {
188 struct rtw_dev *rtwdev;
189 u8 min_rssi;
190};
191
192static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta)
193{
194 struct rtw_phy_stat_iter_data *iter_data = data;
195 struct rtw_dev *rtwdev = iter_data->rtwdev;
196 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
197 u8 rssi;
198
199 rssi = ewma_rssi_read(&si->avg_rssi);
200 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi);
201
202 rtw_fw_send_rssi_info(rtwdev, si);
203
204 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi);
205}
206
207static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev)
208{
209 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
210 struct rtw_phy_stat_iter_data data = {};
211
212 data.rtwdev = rtwdev;
213 data.min_rssi = U8_MAX;
214 rtw_iterate_stas_atomic(rtwdev, rtw_phy_stat_rssi_iter, &data);
215
216 dm_info->pre_min_rssi = dm_info->min_rssi;
217 dm_info->min_rssi = data.min_rssi;
218}
219
220static void rtw_phy_statistics(struct rtw_dev *rtwdev)
221{
222 rtw_phy_stat_rssi(rtwdev);
223 rtw_phy_stat_false_alarm(rtwdev);
224}
225
226#define DIG_PERF_FA_TH_LOW 250
227#define DIG_PERF_FA_TH_HIGH 500
228#define DIG_PERF_FA_TH_EXTRA_HIGH 750
229#define DIG_PERF_MAX 0x5a
230#define DIG_PERF_MID 0x40
231#define DIG_CVRG_FA_TH_LOW 2000
232#define DIG_CVRG_FA_TH_HIGH 4000
233#define DIG_CVRG_FA_TH_EXTRA_HIGH 5000
234#define DIG_CVRG_MAX 0x2a
235#define DIG_CVRG_MID 0x26
236#define DIG_CVRG_MIN 0x1c
237#define DIG_RSSI_GAIN_OFFSET 15
238
239static bool
240rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info)
241{
242 u16 fa_lo = DIG_PERF_FA_TH_LOW;
243 u16 fa_hi = DIG_PERF_FA_TH_HIGH;
244 u16 *fa_history;
245 u8 *igi_history;
246 u8 damping_rssi;
247 u8 min_rssi;
248 u8 diff;
249 u8 igi_bitmap;
250 bool damping = false;
251
252 min_rssi = dm_info->min_rssi;
253 if (dm_info->damping) {
254 damping_rssi = dm_info->damping_rssi;
255 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi :
256 damping_rssi - min_rssi;
257 if (diff > 3 || dm_info->damping_cnt++ > 20) {
258 dm_info->damping = false;
259 return false;
260 }
261
262 return true;
263 }
264
265 igi_history = dm_info->igi_history;
266 fa_history = dm_info->fa_history;
267 igi_bitmap = dm_info->igi_bitmap & 0xf;
268 switch (igi_bitmap) {
269 case 5:
270
271 if (igi_history[0] > igi_history[1] &&
272 igi_history[2] > igi_history[3] &&
273 igi_history[0] - igi_history[1] >= 2 &&
274 igi_history[2] - igi_history[3] >= 2 &&
275 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
276 fa_history[2] > fa_hi && fa_history[3] < fa_lo)
277 damping = true;
278 break;
279 case 9:
280
281 if (igi_history[0] > igi_history[1] &&
282 igi_history[3] > igi_history[2] &&
283 igi_history[0] - igi_history[1] >= 4 &&
284 igi_history[3] - igi_history[2] >= 2 &&
285 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
286 fa_history[2] < fa_lo && fa_history[3] > fa_hi)
287 damping = true;
288 break;
289 default:
290 return false;
291 }
292
293 if (damping) {
294 dm_info->damping = true;
295 dm_info->damping_cnt = 0;
296 dm_info->damping_rssi = min_rssi;
297 }
298
299 return damping;
300}
301
302static void rtw_phy_dig_get_boundary(struct rtw_dm_info *dm_info,
303 u8 *upper, u8 *lower, bool linked)
304{
305 u8 dig_max, dig_min, dig_mid;
306 u8 min_rssi;
307
308 if (linked) {
309 dig_max = DIG_PERF_MAX;
310 dig_mid = DIG_PERF_MID;
311
312 dig_min = 0x1c;
313 min_rssi = max_t(u8, dm_info->min_rssi, dig_min);
314 } else {
315 dig_max = DIG_CVRG_MAX;
316 dig_mid = DIG_CVRG_MID;
317 dig_min = DIG_CVRG_MIN;
318 min_rssi = dig_min;
319 }
320
321
322 dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET);
323
324 *lower = clamp_t(u8, min_rssi, dig_min, dig_mid);
325 *upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max);
326}
327
328static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info,
329 u16 *fa_th, u8 *step, bool linked)
330{
331 u8 min_rssi, pre_min_rssi;
332
333 min_rssi = dm_info->min_rssi;
334 pre_min_rssi = dm_info->pre_min_rssi;
335 step[0] = 4;
336 step[1] = 3;
337 step[2] = 2;
338
339 if (linked) {
340 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
341 fa_th[1] = DIG_PERF_FA_TH_HIGH;
342 fa_th[2] = DIG_PERF_FA_TH_LOW;
343 if (pre_min_rssi > min_rssi) {
344 step[0] = 6;
345 step[1] = 4;
346 step[2] = 2;
347 }
348 } else {
349 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
350 fa_th[1] = DIG_CVRG_FA_TH_HIGH;
351 fa_th[2] = DIG_CVRG_FA_TH_LOW;
352 }
353}
354
355static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa)
356{
357 u8 *igi_history;
358 u16 *fa_history;
359 u8 igi_bitmap;
360 bool up;
361
362 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
363 igi_history = dm_info->igi_history;
364 fa_history = dm_info->fa_history;
365
366 up = igi > igi_history[0];
367 igi_bitmap |= up;
368
369 igi_history[3] = igi_history[2];
370 igi_history[2] = igi_history[1];
371 igi_history[1] = igi_history[0];
372 igi_history[0] = igi;
373
374 fa_history[3] = fa_history[2];
375 fa_history[2] = fa_history[1];
376 fa_history[1] = fa_history[0];
377 fa_history[0] = fa;
378
379 dm_info->igi_bitmap = igi_bitmap;
380}
381
382static void rtw_phy_dig(struct rtw_dev *rtwdev)
383{
384 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
385 u8 upper_bound, lower_bound;
386 u8 pre_igi, cur_igi;
387 u16 fa_th[3], fa_cnt;
388 u8 level;
389 u8 step[3];
390 bool linked;
391
392 if (rtw_flag_check(rtwdev, RTW_FLAG_DIG_DISABLE))
393 return;
394
395 if (rtw_phy_dig_check_damping(dm_info))
396 return;
397
398 linked = !!rtwdev->sta_cnt;
399
400 fa_cnt = dm_info->total_fa_cnt;
401 pre_igi = dm_info->igi_history[0];
402
403 rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked);
404
405
406
407
408
409
410 cur_igi = pre_igi;
411 for (level = 0; level < 3; level++) {
412 if (fa_cnt > fa_th[level]) {
413 cur_igi += step[level];
414 break;
415 }
416 }
417 cur_igi -= 2;
418
419
420
421
422
423 rtw_phy_dig_get_boundary(dm_info, &upper_bound, &lower_bound, linked);
424 cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound);
425
426
427
428
429 rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt);
430
431 if (cur_igi != pre_igi)
432 rtw_phy_dig_write(rtwdev, cur_igi);
433}
434
435static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta)
436{
437 struct rtw_dev *rtwdev = data;
438 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
439
440 rtw_update_sta_info(rtwdev, si);
441}
442
443static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev)
444{
445 if (rtwdev->watch_dog_cnt & 0x3)
446 return;
447
448 rtw_iterate_stas_atomic(rtwdev, rtw_phy_ra_info_update_iter, rtwdev);
449}
450
451void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev)
452{
453
454 rtw_phy_statistics(rtwdev);
455 rtw_phy_dig(rtwdev);
456 rtw_phy_ra_info_update(rtwdev);
457}
458
459#define FRAC_BITS 3
460
461static u8 rtw_phy_power_2_db(s8 power)
462{
463 if (power <= -100 || power >= 20)
464 return 0;
465 else if (power >= 0)
466 return 100;
467 else
468 return 100 + power;
469}
470
471static u64 rtw_phy_db_2_linear(u8 power_db)
472{
473 u8 i, j;
474 u64 linear;
475
476 if (power_db > 96)
477 power_db = 96;
478 else if (power_db < 1)
479 return 1;
480
481
482 i = (power_db - 1) >> 3;
483 j = (power_db - 1) - (i << 3);
484
485 linear = db_invert_table[i][j];
486 linear = i > 2 ? linear << FRAC_BITS : linear;
487
488 return linear;
489}
490
491static u8 rtw_phy_linear_2_db(u64 linear)
492{
493 u8 i;
494 u8 j;
495 u32 dB;
496
497 if (linear >= db_invert_table[11][7])
498 return 96;
499
500 for (i = 0; i < 12; i++) {
501 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7])
502 break;
503 else if (i > 2 && linear <= db_invert_table[i][7])
504 break;
505 }
506
507 for (j = 0; j < 8; j++) {
508 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
509 break;
510 else if (i > 2 && linear <= db_invert_table[i][j])
511 break;
512 }
513
514 if (j == 0 && i == 0)
515 goto end;
516
517 if (j == 0) {
518 if (i != 3) {
519 if (db_invert_table[i][0] - linear >
520 linear - db_invert_table[i - 1][7]) {
521 i = i - 1;
522 j = 7;
523 }
524 } else {
525 if (db_invert_table[3][0] - linear >
526 linear - db_invert_table[2][7]) {
527 i = 2;
528 j = 7;
529 }
530 }
531 } else {
532 if (db_invert_table[i][j] - linear >
533 linear - db_invert_table[i][j - 1]) {
534 j = j - 1;
535 }
536 }
537end:
538 dB = (i << 3) + j + 1;
539
540 return dB;
541}
542
543u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num)
544{
545 s8 power;
546 u8 power_db;
547 u64 linear;
548 u64 sum = 0;
549 u8 path;
550
551 for (path = 0; path < path_num; path++) {
552 power = rf_power[path];
553 power_db = rtw_phy_power_2_db(power);
554 linear = rtw_phy_db_2_linear(power_db);
555 sum += linear;
556 }
557
558 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
559 switch (path_num) {
560 case 2:
561 sum >>= 1;
562 break;
563 case 3:
564 sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5;
565 break;
566 case 4:
567 sum >>= 2;
568 break;
569 default:
570 break;
571 }
572
573 return rtw_phy_linear_2_db(sum);
574}
575
576u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
577 u32 addr, u32 mask)
578{
579 struct rtw_hal *hal = &rtwdev->hal;
580 struct rtw_chip_info *chip = rtwdev->chip;
581 const u32 *base_addr = chip->rf_base_addr;
582 u32 val, direct_addr;
583
584 if (rf_path >= hal->rf_path_num) {
585 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
586 return INV_RF_DATA;
587 }
588
589 addr &= 0xff;
590 direct_addr = base_addr[rf_path] + (addr << 2);
591 mask &= RFREG_MASK;
592
593 val = rtw_read32_mask(rtwdev, direct_addr, mask);
594
595 return val;
596}
597
598bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
599 u32 addr, u32 mask, u32 data)
600{
601 struct rtw_hal *hal = &rtwdev->hal;
602 struct rtw_chip_info *chip = rtwdev->chip;
603 u32 *sipi_addr = chip->rf_sipi_addr;
604 u32 data_and_addr;
605 u32 old_data = 0;
606 u32 shift;
607
608 if (rf_path >= hal->rf_path_num) {
609 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
610 return false;
611 }
612
613 addr &= 0xff;
614 mask &= RFREG_MASK;
615
616 if (mask != RFREG_MASK) {
617 old_data = rtw_phy_read_rf(rtwdev, rf_path, addr, RFREG_MASK);
618
619 if (old_data == INV_RF_DATA) {
620 rtw_err(rtwdev, "Write fail, rf is disabled\n");
621 return false;
622 }
623
624 shift = __ffs(mask);
625 data = ((old_data) & (~mask)) | (data << shift);
626 }
627
628 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
629
630 rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr);
631
632 udelay(13);
633
634 return true;
635}
636
637bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
638 u32 addr, u32 mask, u32 data)
639{
640 struct rtw_hal *hal = &rtwdev->hal;
641 struct rtw_chip_info *chip = rtwdev->chip;
642 const u32 *base_addr = chip->rf_base_addr;
643 u32 direct_addr;
644
645 if (rf_path >= hal->rf_path_num) {
646 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
647 return false;
648 }
649
650 addr &= 0xff;
651 direct_addr = base_addr[rf_path] + (addr << 2);
652 mask &= RFREG_MASK;
653
654 if (addr == RF_CFGCH) {
655 rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, DISABLE_PI);
656 rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, DISABLE_PI);
657 }
658
659 rtw_write32_mask(rtwdev, direct_addr, mask, data);
660
661 udelay(1);
662
663 if (addr == RF_CFGCH) {
664 rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, ENABLE_PI);
665 rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, ENABLE_PI);
666 }
667
668 return true;
669}
670
671bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
672 u32 addr, u32 mask, u32 data)
673{
674 if (addr != 0x00)
675 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data);
676
677 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data);
678}
679
680void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg)
681{
682 struct rtw_hal *hal = &rtwdev->hal;
683 struct rtw_efuse *efuse = &rtwdev->efuse;
684 struct rtw_phy_cond cond = {0};
685
686 cond.cut = hal->cut_version ? hal->cut_version : 15;
687 cond.pkg = pkg ? pkg : 15;
688 cond.plat = 0x04;
689 cond.rfe = efuse->rfe_option;
690
691 switch (rtw_hci_type(rtwdev)) {
692 case RTW_HCI_TYPE_USB:
693 cond.intf = INTF_USB;
694 break;
695 case RTW_HCI_TYPE_SDIO:
696 cond.intf = INTF_SDIO;
697 break;
698 case RTW_HCI_TYPE_PCIE:
699 default:
700 cond.intf = INTF_PCIE;
701 break;
702 }
703
704 hal->phy_cond = cond;
705
706 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond));
707}
708
709static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond)
710{
711 struct rtw_hal *hal = &rtwdev->hal;
712 struct rtw_phy_cond drv_cond = hal->phy_cond;
713
714 if (cond.cut && cond.cut != drv_cond.cut)
715 return false;
716
717 if (cond.pkg && cond.pkg != drv_cond.pkg)
718 return false;
719
720 if (cond.intf && cond.intf != drv_cond.intf)
721 return false;
722
723 if (cond.rfe != drv_cond.rfe)
724 return false;
725
726 return true;
727}
728
729void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
730{
731 const union phy_table_tile *p = tbl->data;
732 const union phy_table_tile *end = p + tbl->size / 2;
733 struct rtw_phy_cond pos_cond = {0};
734 bool is_matched = true, is_skipped = false;
735
736 BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair));
737
738 for (; p < end; p++) {
739 if (p->cond.pos) {
740 switch (p->cond.branch) {
741 case BRANCH_ENDIF:
742 is_matched = true;
743 is_skipped = false;
744 break;
745 case BRANCH_ELSE:
746 is_matched = is_skipped ? false : true;
747 break;
748 case BRANCH_IF:
749 case BRANCH_ELIF:
750 default:
751 pos_cond = p->cond;
752 break;
753 }
754 } else if (p->cond.neg) {
755 if (!is_skipped) {
756 if (check_positive(rtwdev, pos_cond)) {
757 is_matched = true;
758 is_skipped = true;
759 } else {
760 is_matched = false;
761 is_skipped = false;
762 }
763 } else {
764 is_matched = false;
765 }
766 } else if (is_matched) {
767 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data);
768 }
769 }
770}
771
772#define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8))
773
774static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i)
775{
776 if (rtwdev->chip->is_pwr_by_rate_dec)
777 return bcd_to_dec_pwr_by_rate(hex, i);
778
779 return (hex >> (i * 8)) & 0xFF;
780}
781
782static void
783rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev,
784 u32 addr, u32 mask, u32 val, u8 *rate,
785 u8 *pwr_by_rate, u8 *rate_num)
786{
787 int i;
788
789 switch (addr) {
790 case 0xE00:
791 case 0x830:
792 rate[0] = DESC_RATE6M;
793 rate[1] = DESC_RATE9M;
794 rate[2] = DESC_RATE12M;
795 rate[3] = DESC_RATE18M;
796 for (i = 0; i < 4; ++i)
797 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
798 *rate_num = 4;
799 break;
800 case 0xE04:
801 case 0x834:
802 rate[0] = DESC_RATE24M;
803 rate[1] = DESC_RATE36M;
804 rate[2] = DESC_RATE48M;
805 rate[3] = DESC_RATE54M;
806 for (i = 0; i < 4; ++i)
807 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
808 *rate_num = 4;
809 break;
810 case 0xE08:
811 rate[0] = DESC_RATE1M;
812 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1);
813 *rate_num = 1;
814 break;
815 case 0x86C:
816 if (mask == 0xffffff00) {
817 rate[0] = DESC_RATE2M;
818 rate[1] = DESC_RATE5_5M;
819 rate[2] = DESC_RATE11M;
820 for (i = 1; i < 4; ++i)
821 pwr_by_rate[i - 1] =
822 tbl_to_dec_pwr_by_rate(rtwdev, val, i);
823 *rate_num = 3;
824 } else if (mask == 0x000000ff) {
825 rate[0] = DESC_RATE11M;
826 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0);
827 *rate_num = 1;
828 }
829 break;
830 case 0xE10:
831 case 0x83C:
832 rate[0] = DESC_RATEMCS0;
833 rate[1] = DESC_RATEMCS1;
834 rate[2] = DESC_RATEMCS2;
835 rate[3] = DESC_RATEMCS3;
836 for (i = 0; i < 4; ++i)
837 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
838 *rate_num = 4;
839 break;
840 case 0xE14:
841 case 0x848:
842 rate[0] = DESC_RATEMCS4;
843 rate[1] = DESC_RATEMCS5;
844 rate[2] = DESC_RATEMCS6;
845 rate[3] = DESC_RATEMCS7;
846 for (i = 0; i < 4; ++i)
847 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
848 *rate_num = 4;
849 break;
850 case 0xE18:
851 case 0x84C:
852 rate[0] = DESC_RATEMCS8;
853 rate[1] = DESC_RATEMCS9;
854 rate[2] = DESC_RATEMCS10;
855 rate[3] = DESC_RATEMCS11;
856 for (i = 0; i < 4; ++i)
857 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
858 *rate_num = 4;
859 break;
860 case 0xE1C:
861 case 0x868:
862 rate[0] = DESC_RATEMCS12;
863 rate[1] = DESC_RATEMCS13;
864 rate[2] = DESC_RATEMCS14;
865 rate[3] = DESC_RATEMCS15;
866 for (i = 0; i < 4; ++i)
867 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
868 *rate_num = 4;
869 break;
870 case 0x838:
871 rate[0] = DESC_RATE1M;
872 rate[1] = DESC_RATE2M;
873 rate[2] = DESC_RATE5_5M;
874 for (i = 1; i < 4; ++i)
875 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev,
876 val, i);
877 *rate_num = 3;
878 break;
879 case 0xC20:
880 case 0xE20:
881 case 0x1820:
882 case 0x1A20:
883 rate[0] = DESC_RATE1M;
884 rate[1] = DESC_RATE2M;
885 rate[2] = DESC_RATE5_5M;
886 rate[3] = DESC_RATE11M;
887 for (i = 0; i < 4; ++i)
888 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
889 *rate_num = 4;
890 break;
891 case 0xC24:
892 case 0xE24:
893 case 0x1824:
894 case 0x1A24:
895 rate[0] = DESC_RATE6M;
896 rate[1] = DESC_RATE9M;
897 rate[2] = DESC_RATE12M;
898 rate[3] = DESC_RATE18M;
899 for (i = 0; i < 4; ++i)
900 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
901 *rate_num = 4;
902 break;
903 case 0xC28:
904 case 0xE28:
905 case 0x1828:
906 case 0x1A28:
907 rate[0] = DESC_RATE24M;
908 rate[1] = DESC_RATE36M;
909 rate[2] = DESC_RATE48M;
910 rate[3] = DESC_RATE54M;
911 for (i = 0; i < 4; ++i)
912 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
913 *rate_num = 4;
914 break;
915 case 0xC2C:
916 case 0xE2C:
917 case 0x182C:
918 case 0x1A2C:
919 rate[0] = DESC_RATEMCS0;
920 rate[1] = DESC_RATEMCS1;
921 rate[2] = DESC_RATEMCS2;
922 rate[3] = DESC_RATEMCS3;
923 for (i = 0; i < 4; ++i)
924 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
925 *rate_num = 4;
926 break;
927 case 0xC30:
928 case 0xE30:
929 case 0x1830:
930 case 0x1A30:
931 rate[0] = DESC_RATEMCS4;
932 rate[1] = DESC_RATEMCS5;
933 rate[2] = DESC_RATEMCS6;
934 rate[3] = DESC_RATEMCS7;
935 for (i = 0; i < 4; ++i)
936 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
937 *rate_num = 4;
938 break;
939 case 0xC34:
940 case 0xE34:
941 case 0x1834:
942 case 0x1A34:
943 rate[0] = DESC_RATEMCS8;
944 rate[1] = DESC_RATEMCS9;
945 rate[2] = DESC_RATEMCS10;
946 rate[3] = DESC_RATEMCS11;
947 for (i = 0; i < 4; ++i)
948 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
949 *rate_num = 4;
950 break;
951 case 0xC38:
952 case 0xE38:
953 case 0x1838:
954 case 0x1A38:
955 rate[0] = DESC_RATEMCS12;
956 rate[1] = DESC_RATEMCS13;
957 rate[2] = DESC_RATEMCS14;
958 rate[3] = DESC_RATEMCS15;
959 for (i = 0; i < 4; ++i)
960 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
961 *rate_num = 4;
962 break;
963 case 0xC3C:
964 case 0xE3C:
965 case 0x183C:
966 case 0x1A3C:
967 rate[0] = DESC_RATEVHT1SS_MCS0;
968 rate[1] = DESC_RATEVHT1SS_MCS1;
969 rate[2] = DESC_RATEVHT1SS_MCS2;
970 rate[3] = DESC_RATEVHT1SS_MCS3;
971 for (i = 0; i < 4; ++i)
972 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
973 *rate_num = 4;
974 break;
975 case 0xC40:
976 case 0xE40:
977 case 0x1840:
978 case 0x1A40:
979 rate[0] = DESC_RATEVHT1SS_MCS4;
980 rate[1] = DESC_RATEVHT1SS_MCS5;
981 rate[2] = DESC_RATEVHT1SS_MCS6;
982 rate[3] = DESC_RATEVHT1SS_MCS7;
983 for (i = 0; i < 4; ++i)
984 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
985 *rate_num = 4;
986 break;
987 case 0xC44:
988 case 0xE44:
989 case 0x1844:
990 case 0x1A44:
991 rate[0] = DESC_RATEVHT1SS_MCS8;
992 rate[1] = DESC_RATEVHT1SS_MCS9;
993 rate[2] = DESC_RATEVHT2SS_MCS0;
994 rate[3] = DESC_RATEVHT2SS_MCS1;
995 for (i = 0; i < 4; ++i)
996 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
997 *rate_num = 4;
998 break;
999 case 0xC48:
1000 case 0xE48:
1001 case 0x1848:
1002 case 0x1A48:
1003 rate[0] = DESC_RATEVHT2SS_MCS2;
1004 rate[1] = DESC_RATEVHT2SS_MCS3;
1005 rate[2] = DESC_RATEVHT2SS_MCS4;
1006 rate[3] = DESC_RATEVHT2SS_MCS5;
1007 for (i = 0; i < 4; ++i)
1008 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1009 *rate_num = 4;
1010 break;
1011 case 0xC4C:
1012 case 0xE4C:
1013 case 0x184C:
1014 case 0x1A4C:
1015 rate[0] = DESC_RATEVHT2SS_MCS6;
1016 rate[1] = DESC_RATEVHT2SS_MCS7;
1017 rate[2] = DESC_RATEVHT2SS_MCS8;
1018 rate[3] = DESC_RATEVHT2SS_MCS9;
1019 for (i = 0; i < 4; ++i)
1020 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1021 *rate_num = 4;
1022 break;
1023 case 0xCD8:
1024 case 0xED8:
1025 case 0x18D8:
1026 case 0x1AD8:
1027 rate[0] = DESC_RATEMCS16;
1028 rate[1] = DESC_RATEMCS17;
1029 rate[2] = DESC_RATEMCS18;
1030 rate[3] = DESC_RATEMCS19;
1031 for (i = 0; i < 4; ++i)
1032 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1033 *rate_num = 4;
1034 break;
1035 case 0xCDC:
1036 case 0xEDC:
1037 case 0x18DC:
1038 case 0x1ADC:
1039 rate[0] = DESC_RATEMCS20;
1040 rate[1] = DESC_RATEMCS21;
1041 rate[2] = DESC_RATEMCS22;
1042 rate[3] = DESC_RATEMCS23;
1043 for (i = 0; i < 4; ++i)
1044 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1045 *rate_num = 4;
1046 break;
1047 case 0xCE0:
1048 case 0xEE0:
1049 case 0x18E0:
1050 case 0x1AE0:
1051 rate[0] = DESC_RATEVHT3SS_MCS0;
1052 rate[1] = DESC_RATEVHT3SS_MCS1;
1053 rate[2] = DESC_RATEVHT3SS_MCS2;
1054 rate[3] = DESC_RATEVHT3SS_MCS3;
1055 for (i = 0; i < 4; ++i)
1056 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1057 *rate_num = 4;
1058 break;
1059 case 0xCE4:
1060 case 0xEE4:
1061 case 0x18E4:
1062 case 0x1AE4:
1063 rate[0] = DESC_RATEVHT3SS_MCS4;
1064 rate[1] = DESC_RATEVHT3SS_MCS5;
1065 rate[2] = DESC_RATEVHT3SS_MCS6;
1066 rate[3] = DESC_RATEVHT3SS_MCS7;
1067 for (i = 0; i < 4; ++i)
1068 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1069 *rate_num = 4;
1070 break;
1071 case 0xCE8:
1072 case 0xEE8:
1073 case 0x18E8:
1074 case 0x1AE8:
1075 rate[0] = DESC_RATEVHT3SS_MCS8;
1076 rate[1] = DESC_RATEVHT3SS_MCS9;
1077 for (i = 0; i < 2; ++i)
1078 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1079 *rate_num = 2;
1080 break;
1081 default:
1082 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1083 break;
1084 }
1085}
1086
1087static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev,
1088 u32 band, u32 rfpath, u32 txnum,
1089 u32 regaddr, u32 bitmask, u32 data)
1090{
1091 struct rtw_hal *hal = &rtwdev->hal;
1092 u8 rate_num = 0;
1093 u8 rate;
1094 u8 rates[RTW_RF_PATH_MAX] = {0};
1095 s8 offset;
1096 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0};
1097 int i;
1098
1099 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data,
1100 rates, pwr_by_rate, &rate_num);
1101
1102 if (WARN_ON(rfpath >= RTW_RF_PATH_MAX ||
1103 (band != PHY_BAND_2G && band != PHY_BAND_5G) ||
1104 rate_num > RTW_RF_PATH_MAX))
1105 return;
1106
1107 for (i = 0; i < rate_num; i++) {
1108 offset = pwr_by_rate[i];
1109 rate = rates[i];
1110 if (band == PHY_BAND_2G)
1111 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1112 else if (band == PHY_BAND_5G)
1113 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1114 else
1115 continue;
1116 }
1117}
1118
1119void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1120{
1121 const struct phy_pg_cfg_pair *p = tbl->data;
1122 const struct phy_pg_cfg_pair *end = p + tbl->size / 6;
1123
1124 BUILD_BUG_ON(sizeof(struct phy_pg_cfg_pair) != sizeof(u32) * 6);
1125
1126 for (; p < end; p++) {
1127 if (p->addr == 0xfe || p->addr == 0xffe) {
1128 msleep(50);
1129 continue;
1130 }
1131 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path,
1132 p->tx_num, p->addr, p->bitmask,
1133 p->data);
1134 }
1135}
1136
1137static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = {
1138 36, 38, 40, 42, 44, 46, 48,
1139 52, 54, 56, 58, 60, 62, 64,
1140 100, 102, 104, 106, 108, 110, 112,
1141 116, 118, 120, 122, 124, 126, 128,
1142 132, 134, 136, 138, 140, 142, 144,
1143 149, 151, 153, 155, 157, 159, 161,
1144 165, 167, 169, 171, 173, 175, 177};
1145
1146static int rtw_channel_to_idx(u8 band, u8 channel)
1147{
1148 int ch_idx;
1149 u8 n_channel;
1150
1151 if (band == PHY_BAND_2G) {
1152 ch_idx = channel - 1;
1153 n_channel = RTW_MAX_CHANNEL_NUM_2G;
1154 } else if (band == PHY_BAND_5G) {
1155 n_channel = RTW_MAX_CHANNEL_NUM_5G;
1156 for (ch_idx = 0; ch_idx < n_channel; ch_idx++)
1157 if (rtw_channel_idx_5g[ch_idx] == channel)
1158 break;
1159 } else {
1160 return -1;
1161 }
1162
1163 if (ch_idx >= n_channel)
1164 return -1;
1165
1166 return ch_idx;
1167}
1168
1169static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band,
1170 u8 bw, u8 rs, u8 ch, s8 pwr_limit)
1171{
1172 struct rtw_hal *hal = &rtwdev->hal;
1173 u8 max_power_index = rtwdev->chip->max_power_index;
1174 s8 ww;
1175 int ch_idx;
1176
1177 pwr_limit = clamp_t(s8, pwr_limit,
1178 -max_power_index, max_power_index);
1179 ch_idx = rtw_channel_to_idx(band, ch);
1180
1181 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1182 rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) {
1183 WARN(1,
1184 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1185 regd, band, bw, rs, ch_idx, pwr_limit);
1186 return;
1187 }
1188
1189 if (band == PHY_BAND_2G) {
1190 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1191 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1192 ww = min_t(s8, ww, pwr_limit);
1193 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1194 } else if (band == PHY_BAND_5G) {
1195 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1196 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1197 ww = min_t(s8, ww, pwr_limit);
1198 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1199 }
1200}
1201
1202
1203static void
1204rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd,
1205 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht)
1206{
1207 struct rtw_hal *hal = &rtwdev->hal;
1208 u8 max_power_index = rtwdev->chip->max_power_index;
1209 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1210 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1211
1212 if (lmt_ht == lmt_vht)
1213 return;
1214
1215 if (lmt_ht == max_power_index)
1216 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1217
1218 else if (lmt_vht == max_power_index)
1219 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1220}
1221
1222
1223static void
1224rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1225{
1226 u8 rs_idx, rs_ht, rs_vht;
1227 u8 rs_cmp[2][2] = {{RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S},
1228 {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S} };
1229
1230 for (rs_idx = 0; rs_idx < 2; rs_idx++) {
1231 rs_ht = rs_cmp[rs_idx][0];
1232 rs_vht = rs_cmp[rs_idx][1];
1233
1234 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1235 }
1236}
1237
1238
1239static void
1240rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1241{
1242 u8 ch_idx;
1243
1244 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++)
1245 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1246}
1247
1248
1249static void
1250rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd)
1251{
1252 u8 bw;
1253
1254 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++)
1255 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1256}
1257
1258
1259static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev)
1260{
1261 u8 regd;
1262
1263 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1264 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd);
1265}
1266
1267void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev,
1268 const struct rtw_table *tbl)
1269{
1270 const struct txpwr_lmt_cfg_pair *p = tbl->data;
1271 const struct txpwr_lmt_cfg_pair *end = p + tbl->size / 6;
1272
1273 BUILD_BUG_ON(sizeof(struct txpwr_lmt_cfg_pair) != sizeof(u8) * 6);
1274
1275 for (; p < end; p++) {
1276 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band,
1277 p->bw, p->rs, p->ch, p->txpwr_lmt);
1278 }
1279
1280 rtw_xref_txpwr_lmt(rtwdev);
1281}
1282
1283void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1284 u32 addr, u32 data)
1285{
1286 rtw_write8(rtwdev, addr, data);
1287}
1288
1289void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1290 u32 addr, u32 data)
1291{
1292 rtw_write32(rtwdev, addr, data);
1293}
1294
1295void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1296 u32 addr, u32 data)
1297{
1298 if (addr == 0xfe)
1299 msleep(50);
1300 else if (addr == 0xfd)
1301 mdelay(5);
1302 else if (addr == 0xfc)
1303 mdelay(1);
1304 else if (addr == 0xfb)
1305 usleep_range(50, 60);
1306 else if (addr == 0xfa)
1307 udelay(5);
1308 else if (addr == 0xf9)
1309 udelay(1);
1310 else
1311 rtw_write32(rtwdev, addr, data);
1312}
1313
1314void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1315 u32 addr, u32 data)
1316{
1317 if (addr == 0xffe) {
1318 msleep(50);
1319 } else if (addr == 0xfe) {
1320 usleep_range(100, 110);
1321 } else {
1322 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data);
1323 udelay(1);
1324 }
1325}
1326
1327static void rtw_load_rfk_table(struct rtw_dev *rtwdev)
1328{
1329 struct rtw_chip_info *chip = rtwdev->chip;
1330
1331 if (!chip->rfk_init_tbl)
1332 return;
1333
1334 rtw_load_table(rtwdev, chip->rfk_init_tbl);
1335}
1336
1337void rtw_phy_load_tables(struct rtw_dev *rtwdev)
1338{
1339 struct rtw_chip_info *chip = rtwdev->chip;
1340 u8 rf_path;
1341
1342 rtw_load_table(rtwdev, chip->mac_tbl);
1343 rtw_load_table(rtwdev, chip->bb_tbl);
1344 rtw_load_table(rtwdev, chip->agc_tbl);
1345 rtw_load_rfk_table(rtwdev);
1346
1347 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1348 const struct rtw_table *tbl;
1349
1350 tbl = chip->rf_tbl[rf_path];
1351 rtw_load_table(rtwdev, tbl);
1352 }
1353}
1354
1355static u8 rtw_get_channel_group(u8 channel)
1356{
1357 switch (channel) {
1358 default:
1359 WARN_ON(1);
1360
1361 case 1:
1362 case 2:
1363 case 36:
1364 case 38:
1365 case 40:
1366 case 42:
1367 return 0;
1368 case 3:
1369 case 4:
1370 case 5:
1371 case 44:
1372 case 46:
1373 case 48:
1374 case 50:
1375 return 1;
1376 case 6:
1377 case 7:
1378 case 8:
1379 case 52:
1380 case 54:
1381 case 56:
1382 case 58:
1383 return 2;
1384 case 9:
1385 case 10:
1386 case 11:
1387 case 60:
1388 case 62:
1389 case 64:
1390 return 3;
1391 case 12:
1392 case 13:
1393 case 100:
1394 case 102:
1395 case 104:
1396 case 106:
1397 return 4;
1398 case 14:
1399 case 108:
1400 case 110:
1401 case 112:
1402 case 114:
1403 return 5;
1404 case 116:
1405 case 118:
1406 case 120:
1407 case 122:
1408 return 6;
1409 case 124:
1410 case 126:
1411 case 128:
1412 case 130:
1413 return 7;
1414 case 132:
1415 case 134:
1416 case 136:
1417 case 138:
1418 return 8;
1419 case 140:
1420 case 142:
1421 case 144:
1422 return 9;
1423 case 149:
1424 case 151:
1425 case 153:
1426 case 155:
1427 return 10;
1428 case 157:
1429 case 159:
1430 case 161:
1431 return 11;
1432 case 165:
1433 case 167:
1434 case 169:
1435 case 171:
1436 return 12;
1437 case 173:
1438 case 175:
1439 case 177:
1440 return 13;
1441 }
1442}
1443
1444static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev,
1445 struct rtw_2g_txpwr_idx *pwr_idx_2g,
1446 enum rtw_bandwidth bandwidth,
1447 u8 rate, u8 group)
1448{
1449 struct rtw_chip_info *chip = rtwdev->chip;
1450 u8 tx_power;
1451 bool mcs_rate;
1452 bool above_2ss;
1453 u8 factor = chip->txgi_factor;
1454
1455 if (rate <= DESC_RATE11M)
1456 tx_power = pwr_idx_2g->cck_base[group];
1457 else
1458 tx_power = pwr_idx_2g->bw40_base[group];
1459
1460 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
1461 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor;
1462
1463 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
1464 (rate >= DESC_RATEVHT1SS_MCS0 &&
1465 rate <= DESC_RATEVHT2SS_MCS9);
1466 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
1467 (rate >= DESC_RATEVHT2SS_MCS0);
1468
1469 if (!mcs_rate)
1470 return tx_power;
1471
1472 switch (bandwidth) {
1473 default:
1474 WARN_ON(1);
1475
1476 case RTW_CHANNEL_WIDTH_20:
1477 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor;
1478 if (above_2ss)
1479 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor;
1480 break;
1481 case RTW_CHANNEL_WIDTH_40:
1482
1483 if (above_2ss)
1484 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor;
1485 break;
1486 }
1487
1488 return tx_power;
1489}
1490
1491static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev,
1492 struct rtw_5g_txpwr_idx *pwr_idx_5g,
1493 enum rtw_bandwidth bandwidth,
1494 u8 rate, u8 group)
1495{
1496 struct rtw_chip_info *chip = rtwdev->chip;
1497 u8 tx_power;
1498 u8 upper, lower;
1499 bool mcs_rate;
1500 bool above_2ss;
1501 u8 factor = chip->txgi_factor;
1502
1503 tx_power = pwr_idx_5g->bw40_base[group];
1504
1505 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
1506 (rate >= DESC_RATEVHT1SS_MCS0 &&
1507 rate <= DESC_RATEVHT2SS_MCS9);
1508 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
1509 (rate >= DESC_RATEVHT2SS_MCS0);
1510
1511 if (!mcs_rate) {
1512 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor;
1513 return tx_power;
1514 }
1515
1516 switch (bandwidth) {
1517 default:
1518 WARN_ON(1);
1519
1520 case RTW_CHANNEL_WIDTH_20:
1521 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor;
1522 if (above_2ss)
1523 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor;
1524 break;
1525 case RTW_CHANNEL_WIDTH_40:
1526
1527 if (above_2ss)
1528 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor;
1529 break;
1530 case RTW_CHANNEL_WIDTH_80:
1531
1532 lower = pwr_idx_5g->bw40_base[group];
1533 upper = pwr_idx_5g->bw40_base[group + 1];
1534
1535 tx_power = (lower + upper) / 2;
1536 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor;
1537 if (above_2ss)
1538 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor;
1539 break;
1540 }
1541
1542 return tx_power;
1543}
1544
1545static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band,
1546 enum rtw_bandwidth bw, u8 rf_path,
1547 u8 rate, u8 channel, u8 regd)
1548{
1549 struct rtw_hal *hal = &rtwdev->hal;
1550 u8 *cch_by_bw = hal->cch_by_bw;
1551 s8 power_limit = (s8)rtwdev->chip->max_power_index;
1552 u8 rs;
1553 int ch_idx;
1554 u8 cur_bw, cur_ch;
1555 s8 cur_lmt;
1556
1557 if (regd > RTW_REGD_WW)
1558 return power_limit;
1559
1560 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M)
1561 rs = RTW_RATE_SECTION_CCK;
1562 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
1563 rs = RTW_RATE_SECTION_OFDM;
1564 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7)
1565 rs = RTW_RATE_SECTION_HT_1S;
1566 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15)
1567 rs = RTW_RATE_SECTION_HT_2S;
1568 else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9)
1569 rs = RTW_RATE_SECTION_VHT_1S;
1570 else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9)
1571 rs = RTW_RATE_SECTION_VHT_2S;
1572 else
1573 goto err;
1574
1575
1576 if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM)
1577 bw = RTW_CHANNEL_WIDTH_20;
1578
1579
1580 if (rs == RTW_RATE_SECTION_HT_1S || rs == RTW_RATE_SECTION_HT_2S)
1581 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40);
1582
1583
1584 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) {
1585 cur_ch = cch_by_bw[cur_bw];
1586
1587 ch_idx = rtw_channel_to_idx(band, cur_ch);
1588 if (ch_idx < 0)
1589 goto err;
1590
1591 cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ?
1592 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
1593 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
1594
1595 power_limit = min_t(s8, cur_lmt, power_limit);
1596 }
1597
1598 return power_limit;
1599
1600err:
1601 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
1602 band, bw, rf_path, rate, channel);
1603 return (s8)rtwdev->chip->max_power_index;
1604}
1605
1606void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw,
1607 u8 ch, u8 regd, struct rtw_power_params *pwr_param)
1608{
1609 struct rtw_hal *hal = &rtwdev->hal;
1610 struct rtw_txpwr_idx *pwr_idx;
1611 u8 group, band;
1612 u8 *base = &pwr_param->pwr_base;
1613 s8 *offset = &pwr_param->pwr_offset;
1614 s8 *limit = &pwr_param->pwr_limit;
1615
1616 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path];
1617 group = rtw_get_channel_group(ch);
1618
1619
1620 if (ch <= 14) {
1621 band = PHY_BAND_2G;
1622 *base = rtw_phy_get_2g_tx_power_index(rtwdev,
1623 &pwr_idx->pwr_idx_2g,
1624 bw, rate, group);
1625 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
1626 } else {
1627 band = PHY_BAND_5G;
1628 *base = rtw_phy_get_5g_tx_power_index(rtwdev,
1629 &pwr_idx->pwr_idx_5g,
1630 bw, rate, group);
1631 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
1632 }
1633
1634 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path,
1635 rate, ch, regd);
1636}
1637
1638u8
1639rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
1640 enum rtw_bandwidth bandwidth, u8 channel, u8 regd)
1641{
1642 struct rtw_power_params pwr_param = {0};
1643 u8 tx_power;
1644 s8 offset;
1645
1646 rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth,
1647 channel, regd, &pwr_param);
1648
1649 tx_power = pwr_param.pwr_base;
1650 offset = min_t(s8, pwr_param.pwr_offset, pwr_param.pwr_limit);
1651
1652 tx_power += offset;
1653
1654 if (tx_power > rtwdev->chip->max_power_index)
1655 tx_power = rtwdev->chip->max_power_index;
1656
1657 return tx_power;
1658}
1659
1660static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev,
1661 u8 ch, u8 path, u8 rs)
1662{
1663 struct rtw_hal *hal = &rtwdev->hal;
1664 u8 regd = rtwdev->regd.txpwr_regd;
1665 u8 *rates;
1666 u8 size;
1667 u8 rate;
1668 u8 pwr_idx;
1669 u8 bw;
1670 int i;
1671
1672 if (rs >= RTW_RATE_SECTION_MAX)
1673 return;
1674
1675 rates = rtw_rate_section[rs];
1676 size = rtw_rate_size[rs];
1677 bw = hal->current_band_width;
1678 for (i = 0; i < size; i++) {
1679 rate = rates[i];
1680 pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate,
1681 bw, ch, regd);
1682 hal->tx_pwr_tbl[path][rate] = pwr_idx;
1683 }
1684}
1685
1686
1687
1688
1689
1690
1691static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev,
1692 u8 ch, u8 path)
1693{
1694 struct rtw_hal *hal = &rtwdev->hal;
1695 u8 rs;
1696
1697
1698 if (hal->current_band_type == RTW_BAND_2G)
1699 rs = RTW_RATE_SECTION_CCK;
1700 else
1701 rs = RTW_RATE_SECTION_OFDM;
1702
1703 for (; rs < RTW_RATE_SECTION_MAX; rs++)
1704 rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs);
1705}
1706
1707void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel)
1708{
1709 struct rtw_chip_info *chip = rtwdev->chip;
1710 struct rtw_hal *hal = &rtwdev->hal;
1711 u8 path;
1712
1713 mutex_lock(&hal->tx_power_mutex);
1714
1715 for (path = 0; path < hal->rf_path_num; path++)
1716 rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path);
1717
1718 chip->ops->set_tx_power_index(rtwdev);
1719 mutex_unlock(&hal->tx_power_mutex);
1720}
1721
1722static void
1723rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
1724 u8 rs, u8 size, u8 *rates)
1725{
1726 u8 rate;
1727 u8 base_idx, rate_idx;
1728 s8 base_2g, base_5g;
1729
1730 if (rs >= RTW_RATE_SECTION_VHT_1S)
1731 base_idx = rates[size - 3];
1732 else
1733 base_idx = rates[size - 1];
1734 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
1735 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
1736 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
1737 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
1738 for (rate = 0; rate < size; rate++) {
1739 rate_idx = rates[rate];
1740 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
1741 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
1742 }
1743}
1744
1745void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
1746{
1747 u8 path;
1748
1749 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
1750 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1751 RTW_RATE_SECTION_CCK,
1752 rtw_cck_size, rtw_cck_rates);
1753 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1754 RTW_RATE_SECTION_OFDM,
1755 rtw_ofdm_size, rtw_ofdm_rates);
1756 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1757 RTW_RATE_SECTION_HT_1S,
1758 rtw_ht_1s_size, rtw_ht_1s_rates);
1759 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1760 RTW_RATE_SECTION_HT_2S,
1761 rtw_ht_2s_size, rtw_ht_2s_rates);
1762 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1763 RTW_RATE_SECTION_VHT_1S,
1764 rtw_vht_1s_size, rtw_vht_1s_rates);
1765 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1766 RTW_RATE_SECTION_VHT_2S,
1767 rtw_vht_2s_size, rtw_vht_2s_rates);
1768 }
1769}
1770
1771static void
1772__rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
1773{
1774 s8 base;
1775 u8 ch;
1776
1777 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) {
1778 base = hal->tx_pwr_by_rate_base_2g[0][rs];
1779 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
1780 }
1781
1782 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) {
1783 base = hal->tx_pwr_by_rate_base_5g[0][rs];
1784 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
1785 }
1786}
1787
1788void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
1789{
1790 u8 regd, bw, rs;
1791
1792
1793 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
1794
1795 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1796 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1797 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
1798 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
1799}
1800
1801static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev,
1802 u8 regd, u8 bw, u8 rs)
1803{
1804 struct rtw_hal *hal = &rtwdev->hal;
1805 s8 max_power_index = (s8)rtwdev->chip->max_power_index;
1806 u8 ch;
1807
1808
1809 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
1810 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
1811
1812
1813 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
1814 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
1815}
1816
1817void rtw_phy_init_tx_power(struct rtw_dev *rtwdev)
1818{
1819 struct rtw_hal *hal = &rtwdev->hal;
1820 u8 regd, path, rate, rs, bw;
1821
1822
1823 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
1824 for (rate = 0; rate < DESC_RATE_MAX; rate++) {
1825 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
1826 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
1827 }
1828 }
1829
1830
1831 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1832 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1833 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
1834 rtw_phy_init_tx_power_limit(rtwdev, regd, bw,
1835 rs);
1836}
1837
