1
2
3
4
5#include "main.h"
6#include "fw.h"
7#include "tx.h"
8#include "rx.h"
9#include "phy.h"
10#include "rtw8822b.h"
11#include "rtw8822b_table.h"
12#include "mac.h"
13#include "reg.h"
14#include "debug.h"
15
16static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
17 u8 rx_path, bool is_tx2_path);
18
19static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse,
20 struct rtw8822b_efuse *map)
21{
22 ether_addr_copy(efuse->addr, map->e.mac_addr);
23}
24
25static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
26{
27 struct rtw_efuse *efuse = &rtwdev->efuse;
28 struct rtw8822b_efuse *map;
29 int i;
30
31 map = (struct rtw8822b_efuse *)log_map;
32
33 efuse->rfe_option = map->rfe_option;
34 efuse->crystal_cap = map->xtal_k;
35 efuse->pa_type_2g = map->pa_type;
36 efuse->pa_type_5g = map->pa_type;
37 efuse->lna_type_2g = map->lna_type_2g[0];
38 efuse->lna_type_5g = map->lna_type_5g[0];
39 efuse->channel_plan = map->channel_plan;
40 efuse->country_code[0] = map->country_code[0];
41 efuse->country_code[1] = map->country_code[1];
42 efuse->bt_setting = map->rf_bt_setting;
43 efuse->regd = map->rf_board_option & 0x7;
44
45 for (i = 0; i < 4; i++)
46 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
47
48 switch (rtw_hci_type(rtwdev)) {
49 case RTW_HCI_TYPE_PCIE:
50 rtw8822be_efuse_parsing(efuse, map);
51 break;
52 default:
53
54 return -ENOTSUPP;
55 }
56
57 return 0;
58}
59
60static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev)
61{
62
63 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
64 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
65 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
66
67
68 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30);
69 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
70
71
72 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f);
73 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
74}
75
76static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev)
77{
78 struct rtw_hal *hal = &rtwdev->hal;
79 u8 crystal_cap;
80 bool is_tx2_path;
81
82
83 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
84 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
85 rtw_write8_set(rtwdev, REG_RF_CTRL,
86 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
87 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
88
89
90 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
91
92 rtw_phy_load_tables(rtwdev);
93
94 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
95 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap);
96 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap);
97
98
99 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
100
101 is_tx2_path = false;
102 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
103 is_tx2_path);
104 rtw_phy_init(rtwdev);
105
106 rtw8822b_phy_rfe_init(rtwdev);
107
108
109 rtw_write32_mask(rtwdev, 0x70, 0x4000000, 1);
110
111 rtw_write32_mask(rtwdev, 0x4c, 0x01800000, 0x2);
112
113 rtw_write8(rtwdev, 0x974, 0xff);
114 rtw_write32_mask(rtwdev, 0x1990, 0x300, 0);
115 rtw_write32_mask(rtwdev, 0xcbc, 0x80000, 0x0);
116
117 rtw_write8(rtwdev, 0xcb4, 0x77);
118
119 rtw_write32_mask(rtwdev, 0x70, 0xff000000, 0x0e);
120
121 rtw_write32(rtwdev, 0x1704, 0x7700);
122 rtw_write32(rtwdev, 0x1700, 0xc00f0038);
123
124 rtw_write8(rtwdev, 0xcbd, 0x2);
125}
126
127#define WLAN_SLOT_TIME 0x09
128#define WLAN_PIFS_TIME 0x19
129#define WLAN_SIFS_CCK_CONT_TX 0xA
130#define WLAN_SIFS_OFDM_CONT_TX 0xE
131#define WLAN_SIFS_CCK_TRX 0x10
132#define WLAN_SIFS_OFDM_TRX 0x10
133#define WLAN_VO_TXOP_LIMIT 0x186
134#define WLAN_VI_TXOP_LIMIT 0x3BC
135#define WLAN_RDG_NAV 0x05
136#define WLAN_TXOP_NAV 0x1B
137#define WLAN_CCK_RX_TSF 0x30
138#define WLAN_OFDM_RX_TSF 0x30
139#define WLAN_TBTT_PROHIBIT 0x04
140#define WLAN_TBTT_HOLD_TIME 0x064
141#define WLAN_DRV_EARLY_INT 0x04
142#define WLAN_BCN_DMA_TIME 0x02
143
144#define WLAN_RX_FILTER0 0x0FFFFFFF
145#define WLAN_RX_FILTER2 0xFFFF
146#define WLAN_RCR_CFG 0xE400220E
147#define WLAN_RXPKT_MAX_SZ 12288
148#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
149
150#define WLAN_AMPDU_MAX_TIME 0x70
151#define WLAN_RTS_LEN_TH 0xFF
152#define WLAN_RTS_TX_TIME_TH 0x08
153#define WLAN_MAX_AGG_PKT_LIMIT 0x20
154#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
155#define FAST_EDCA_VO_TH 0x06
156#define FAST_EDCA_VI_TH 0x06
157#define FAST_EDCA_BE_TH 0x06
158#define FAST_EDCA_BK_TH 0x06
159#define WLAN_BAR_RETRY_LIMIT 0x01
160#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
161
162#define WLAN_TX_FUNC_CFG1 0x30
163#define WLAN_TX_FUNC_CFG2 0x30
164#define WLAN_MAC_OPT_NORM_FUNC1 0x98
165#define WLAN_MAC_OPT_LB_FUNC1 0x80
166#define WLAN_MAC_OPT_FUNC2 0x30810041
167
168#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
169 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
170 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
171 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
172
173#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
174 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
175
176#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
177#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
178
179static int rtw8822b_mac_init(struct rtw_dev *rtwdev)
180{
181 u32 value32;
182
183
184 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD);
185 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
186 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
187 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
188 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
189 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
190 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
191 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
192 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
193 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
194 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
195 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
196 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
197
198 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
199 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
200 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
201 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
202 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
203 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
204 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
205 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
206 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
207
208 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
209
210 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
211 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
212 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
213 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
214
215 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
216 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
217 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
218 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
219 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
220 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
221 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
222 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
223
224 return 0;
225}
226
227static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel)
228{
229 struct rtw_hal *hal = &rtwdev->hal;
230 bool is_channel_2g = (channel <= 14) ? true : false;
231
232 if (is_channel_2g) {
233 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770);
234 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
235 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
236 } else {
237 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517);
238 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
239 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
240 }
241
242 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
243
244 if (hal->antenna_rx == BB_PATH_AB ||
245 hal->antenna_tx == BB_PATH_AB) {
246
247 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
248 } else if (hal->antenna_rx == hal->antenna_tx) {
249
250 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
251 } else {
252
253 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
254 }
255}
256
257static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel)
258{
259 struct rtw_hal *hal = &rtwdev->hal;
260 bool is_channel_2g = (channel <= 14) ? true : false;
261
262 if (is_channel_2g) {
263
264 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774);
265 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
266 } else {
267
268 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547);
269 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
270 }
271
272 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
273
274 if (is_channel_2g) {
275 if (hal->antenna_rx == BB_PATH_AB ||
276 hal->antenna_tx == BB_PATH_AB) {
277
278 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
279 } else if (hal->antenna_rx == hal->antenna_tx) {
280
281 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
282 } else {
283
284 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
285 }
286 } else {
287 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);
288 }
289}
290
291enum {
292 CCUT_IDX_1R_2G,
293 CCUT_IDX_2R_2G,
294 CCUT_IDX_1R_5G,
295 CCUT_IDX_2R_5G,
296 CCUT_IDX_NR,
297};
298
299struct cca_ccut {
300 u32 reg82c[CCUT_IDX_NR];
301 u32 reg830[CCUT_IDX_NR];
302 u32 reg838[CCUT_IDX_NR];
303};
304
305static const struct cca_ccut cca_ifem_ccut = {
306 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010},
307 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa},
308 {0x87765541, 0x87746341, 0x87765541, 0x87746341},
309};
310
311static const struct cca_ccut cca_efem_ccut = {
312 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010},
313 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa},
314 {0x87766451, 0x87766431, 0x87766451, 0x87766431},
315};
316
317static const struct cca_ccut cca_ifem_ccut_ext = {
318 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010},
319 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa},
320 {0x87765541, 0x86666341, 0x87765561, 0x86666361},
321};
322
323static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col,
324 u32 *reg82c, u32 *reg830, u32 *reg838)
325{
326 *reg82c = cca_ccut->reg82c[col];
327 *reg830 = cca_ccut->reg830[col];
328 *reg838 = cca_ccut->reg838[col];
329}
330
331struct rtw8822b_rfe_info {
332 const struct cca_ccut *cca_ccut_2g;
333 const struct cca_ccut *cca_ccut_5g;
334 enum rtw_rfe_fem fem;
335 bool ifem_ext;
336 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel);
337};
338
339#define I2GE5G_CCUT(set_ch) { \
340 .cca_ccut_2g = &cca_ifem_ccut, \
341 .cca_ccut_5g = &cca_efem_ccut, \
342 .fem = RTW_RFE_IFEM2G_EFEM5G, \
343 .ifem_ext = false, \
344 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
345 }
346#define IFEM_EXT_CCUT(set_ch) { \
347 .cca_ccut_2g = &cca_ifem_ccut_ext, \
348 .cca_ccut_5g = &cca_ifem_ccut_ext, \
349 .fem = RTW_RFE_IFEM, \
350 .ifem_ext = true, \
351 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
352 }
353
354static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = {
355 [2] = I2GE5G_CCUT(efem),
356 [5] = IFEM_EXT_CCUT(ifem),
357};
358
359static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw,
360 const struct rtw8822b_rfe_info *rfe_info)
361{
362 struct rtw_hal *hal = &rtwdev->hal;
363 struct rtw_efuse *efuse = &rtwdev->efuse;
364 const struct cca_ccut *cca_ccut;
365 u8 col;
366 u32 reg82c, reg830, reg838;
367 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false;
368
369 if (channel <= 14) {
370 cca_ccut = rfe_info->cca_ccut_2g;
371
372 if (hal->antenna_rx == BB_PATH_A ||
373 hal->antenna_rx == BB_PATH_B)
374 col = CCUT_IDX_1R_2G;
375 else
376 col = CCUT_IDX_2R_2G;
377 } else {
378 cca_ccut = rfe_info->cca_ccut_5g;
379
380 if (hal->antenna_rx == BB_PATH_A ||
381 hal->antenna_rx == BB_PATH_B)
382 col = CCUT_IDX_1R_5G;
383 else
384 col = CCUT_IDX_2R_5G;
385 }
386
387 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838);
388
389 switch (rfe_info->fem) {
390 case RTW_RFE_IFEM:
391 default:
392 is_ifem_cca = true;
393 if (rfe_info->ifem_ext)
394 is_rfe_type = true;
395 break;
396 case RTW_RFE_EFEM:
397 is_efem_cca = true;
398 break;
399 case RTW_RFE_IFEM2G_EFEM5G:
400 if (channel <= 14)
401 is_ifem_cca = true;
402 else
403 is_efem_cca = true;
404 break;
405 }
406
407 if (is_ifem_cca) {
408 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
409 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) &&
410 bw == RTW_CHANNEL_WIDTH_40) ||
411 (!is_rfe_type && col == CCUT_IDX_2R_5G &&
412 bw == RTW_CHANNEL_WIDTH_40) ||
413 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
414 reg830 = 0x79a0ea28;
415 }
416
417 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c);
418 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830);
419 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838);
420
421 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
422 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9);
423
424 if (bw == RTW_CHANNEL_WIDTH_20 &&
425 ((channel >= 52 && channel <= 64) ||
426 (channel >= 100 && channel <= 144)))
427 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4);
428}
429
430static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
431 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
432static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
433 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
434 0x6, 0x5, 0x0, 0x0, 0x7};
435static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
436 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
437
438static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
439{
440#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
441#define RF18_BAND_2G (0)
442#define RF18_BAND_5G (BIT(16) | BIT(8))
443#define RF18_CHANNEL_MASK (MASKBYTE0)
444#define RF18_RFSI_MASK (BIT(18) | BIT(17))
445#define RF18_RFSI_GE_CH80 (BIT(17))
446#define RF18_RFSI_GT_CH144 (BIT(18))
447#define RF18_BW_MASK (BIT(11) | BIT(10))
448#define RF18_BW_20M (BIT(11) | BIT(10))
449#define RF18_BW_40M (BIT(11))
450#define RF18_BW_80M (BIT(10))
451#define RFBE_MASK (BIT(17) | BIT(16) | BIT(15))
452
453 struct rtw_hal *hal = &rtwdev->hal;
454 u32 rf_reg18, rf_reg_be;
455
456 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
457
458 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
459 RF18_BW_MASK);
460
461 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
462 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
463 if (channel > 144)
464 rf_reg18 |= RF18_RFSI_GT_CH144;
465 else if (channel >= 80)
466 rf_reg18 |= RF18_RFSI_GE_CH80;
467
468 switch (bw) {
469 case RTW_CHANNEL_WIDTH_5:
470 case RTW_CHANNEL_WIDTH_10:
471 case RTW_CHANNEL_WIDTH_20:
472 default:
473 rf_reg18 |= RF18_BW_20M;
474 break;
475 case RTW_CHANNEL_WIDTH_40:
476 rf_reg18 |= RF18_BW_40M;
477 break;
478 case RTW_CHANNEL_WIDTH_80:
479 rf_reg18 |= RF18_BW_80M;
480 break;
481 }
482
483 if (channel <= 14)
484 rf_reg_be = 0x0;
485 else if (channel >= 36 && channel <= 64)
486 rf_reg_be = low_band[(channel - 36) >> 1];
487 else if (channel >= 100 && channel <= 144)
488 rf_reg_be = middle_band[(channel - 100) >> 1];
489 else if (channel >= 149 && channel <= 177)
490 rf_reg_be = high_band[(channel - 149) >> 1];
491 else
492 goto err;
493
494 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be);
495
496
497 if (channel == 144)
498 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
499 else
500 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
501
502 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
503 if (hal->rf_type > RF_1T1R)
504 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18);
505
506 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
507 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
508
509 return;
510
511err:
512 WARN_ON(1);
513}
514
515static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev)
516{
517 struct rtw_hal *hal = &rtwdev->hal;
518 u32 igi;
519
520 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f);
521 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
522 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi);
523 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
524 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi);
525
526 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0);
527 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0,
528 hal->antenna_rx | (hal->antenna_rx << 4));
529}
530
531static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
532{
533 if (bw == RTW_CHANNEL_WIDTH_40) {
534
535 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
536 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
537 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
538 } else if (bw == RTW_CHANNEL_WIDTH_80) {
539
540 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
541 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
542 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
543 } else {
544
545 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
546 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
547 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
548 }
549}
550
551static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
552 u8 primary_ch_idx)
553{
554 struct rtw_efuse *efuse = &rtwdev->efuse;
555 u8 rfe_option = efuse->rfe_option;
556 u32 val32;
557
558 if (channel <= 14) {
559 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
560 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
561 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
562 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
563
564 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0);
565 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
566 if (channel == 14) {
567 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577);
568 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
569 } else {
570 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577);
571 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);
572 }
573
574 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2);
575 } else if (channel > 35) {
576 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
577 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
578 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
579 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34);
580
581 if (channel >= 36 && channel <= 64)
582 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1);
583 else if (channel >= 100 && channel <= 144)
584 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2);
585 else if (channel >= 149)
586 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3);
587
588 if (channel >= 36 && channel <= 48)
589 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
590 else if (channel >= 52 && channel <= 64)
591 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
592 else if (channel >= 100 && channel <= 116)
593 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
594 else if (channel >= 118 && channel <= 177)
595 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
596
597 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1);
598 }
599
600 switch (bw) {
601 case RTW_CHANNEL_WIDTH_20:
602 default:
603 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
604 val32 &= 0xFFCFFC00;
605 val32 |= (RTW_CHANNEL_WIDTH_20);
606 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
607
608 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
609 break;
610 case RTW_CHANNEL_WIDTH_40:
611 if (primary_ch_idx == 1)
612 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
613 else
614 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
615
616 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
617 val32 &= 0xFF3FF300;
618 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40);
619 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
620
621 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
622 break;
623 case RTW_CHANNEL_WIDTH_80:
624 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
625 val32 &= 0xFCEFCF00;
626 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80);
627 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
628
629 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
630
631 if (rfe_option == 2) {
632 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6);
633 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
634 }
635 break;
636 case RTW_CHANNEL_WIDTH_5:
637 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
638 val32 &= 0xEFEEFE00;
639 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20));
640 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
641
642 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
643 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
644 break;
645 case RTW_CHANNEL_WIDTH_10:
646 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
647 val32 &= 0xEFFEFF00;
648 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20));
649 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
650
651 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
652 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
653 break;
654 }
655}
656
657static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
658 u8 primary_chan_idx)
659{
660 struct rtw_efuse *efuse = &rtwdev->efuse;
661 const struct rtw8822b_rfe_info *rfe_info;
662
663 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
664 "rfe_option %d is out of boundary\n", efuse->rfe_option))
665 return;
666
667 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
668
669 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
670 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
671 rtw8822b_set_channel_rf(rtwdev, channel, bw);
672 rtw8822b_set_channel_rxdfir(rtwdev, bw);
673 rtw8822b_toggle_igi(rtwdev);
674 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info);
675 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
676}
677
678static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
679 u8 rx_path, bool is_tx2_path)
680{
681 struct rtw_efuse *efuse = &rtwdev->efuse;
682 const struct rtw8822b_rfe_info *rfe_info;
683 u8 ch = rtwdev->hal.current_channel;
684 u8 tx_path_sel, rx_path_sel;
685 int counter;
686
687 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
688 "rfe_option %d is out of boundary\n", efuse->rfe_option))
689 return;
690
691 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
692
693 if ((tx_path | rx_path) & BB_PATH_A)
694 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);
695 else
696 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);
697
698 if ((tx_path | rx_path) & BB_PATH_B)
699 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);
700 else
701 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);
702
703 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
704 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
705 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
706
707 if (tx_path & BB_PATH_A) {
708 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001);
709 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8);
710 } else if (tx_path & BB_PATH_B) {
711 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002);
712 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4);
713 }
714
715 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B)
716 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01);
717 else
718 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43);
719
720 tx_path_sel = (tx_path << 4) | tx_path;
721 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel);
722
723 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) {
724 if (is_tx2_path || rtwdev->mp_mode) {
725 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043);
726 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc);
727 }
728 }
729
730 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
731 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
732
733 if (rx_path & BB_PATH_A)
734 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0);
735 else if (rx_path & BB_PATH_B)
736 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5);
737
738 rx_path_sel = (rx_path << 4) | rx_path;
739 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel);
740
741 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
742 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
743 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
744 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
745 } else {
746 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
747 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
748 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
749 }
750
751 for (counter = 100; counter > 0; counter--) {
752 u32 rf_reg33;
753
754 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
755 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
756
757 udelay(2);
758 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK);
759
760 if (rf_reg33 == 0x00001)
761 break;
762 }
763
764 if (WARN(counter <= 0, "write RF mode table fail\n"))
765 return;
766
767 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
768 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
769 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034);
770 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c);
771 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
772 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
773
774 rtw8822b_toggle_igi(rtwdev);
775 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info);
776 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
777}
778
779static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
780 struct rtw_rx_pkt_stat *pkt_stat)
781{
782 s8 min_rx_power = -120;
783 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
784
785 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
786 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
787 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
788 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
789 min_rx_power);
790}
791
792static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
793 struct rtw_rx_pkt_stat *pkt_stat)
794{
795 u8 rxsc, bw;
796 s8 min_rx_power = -120;
797
798 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
799 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
800 else
801 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
802
803 if (rxsc >= 1 && rxsc <= 8)
804 bw = RTW_CHANNEL_WIDTH_20;
805 else if (rxsc >= 9 && rxsc <= 12)
806 bw = RTW_CHANNEL_WIDTH_40;
807 else if (rxsc >= 13)
808 bw = RTW_CHANNEL_WIDTH_80;
809 else
810 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
811
812 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
813 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
814 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
815 pkt_stat->bw = bw;
816 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
817 pkt_stat->rx_power[RF_PATH_B],
818 min_rx_power);
819}
820
821static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
822 struct rtw_rx_pkt_stat *pkt_stat)
823{
824 u8 page;
825
826 page = *phy_status & 0xf;
827
828 switch (page) {
829 case 0:
830 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
831 break;
832 case 1:
833 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
834 break;
835 default:
836 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
837 return;
838 }
839}
840
841static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
842 struct rtw_rx_pkt_stat *pkt_stat,
843 struct ieee80211_rx_status *rx_status)
844{
845 struct ieee80211_hdr *hdr;
846 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
847 u8 *phy_status = NULL;
848
849 memset(pkt_stat, 0, sizeof(*pkt_stat));
850
851 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
852 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
853 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
854 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc);
855 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
856 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
857 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
858 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
859 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
860 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
861 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
862 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
863
864
865 pkt_stat->drv_info_sz *= 8;
866
867
868 if (pkt_stat->is_c2h)
869 return;
870
871 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
872 pkt_stat->drv_info_sz);
873 if (pkt_stat->phy_status) {
874 phy_status = rx_desc + desc_sz + pkt_stat->shift;
875 query_phy_status(rtwdev, phy_status, pkt_stat);
876 }
877
878 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
879}
880
881static void
882rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
883{
884 struct rtw_hal *hal = &rtwdev->hal;
885 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
886 static u32 phy_pwr_idx;
887 u8 rate, rate_idx, pwr_index, shift;
888 int j;
889
890 for (j = 0; j < rtw_rate_size[rs]; j++) {
891 rate = rtw_rate_section[rs][j];
892 pwr_index = hal->tx_pwr_tbl[path][rate];
893 shift = rate & 0x3;
894 phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
895 if (shift == 0x3) {
896 rate_idx = rate & 0xfc;
897 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
898 phy_pwr_idx);
899 phy_pwr_idx = 0;
900 }
901 }
902}
903
904static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev)
905{
906 struct rtw_hal *hal = &rtwdev->hal;
907 int rs, path;
908
909 for (path = 0; path < hal->rf_path_num; path++) {
910 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
911 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs);
912 }
913}
914
915static bool rtw8822b_check_rf_path(u8 antenna)
916{
917 switch (antenna) {
918 case BB_PATH_A:
919 case BB_PATH_B:
920 case BB_PATH_AB:
921 return true;
922 default:
923 return false;
924 }
925}
926
927static void rtw8822b_set_antenna(struct rtw_dev *rtwdev, u8 antenna_tx,
928 u8 antenna_rx)
929{
930 struct rtw_hal *hal = &rtwdev->hal;
931
932 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n",
933 antenna_tx, antenna_rx);
934
935 if (!rtw8822b_check_rf_path(antenna_tx)) {
936 rtw_info(rtwdev, "unsupport tx path, set to default path ab\n");
937 antenna_tx = BB_PATH_AB;
938 }
939 if (!rtw8822b_check_rf_path(antenna_rx)) {
940 rtw_info(rtwdev, "unsupport rx path, set to default path ab\n");
941 antenna_rx = BB_PATH_AB;
942 }
943 hal->antenna_tx = antenna_tx;
944 hal->antenna_rx = antenna_rx;
945 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
946}
947
948static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
949{
950 u8 ldo_pwr;
951
952 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
953 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
954 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
955}
956
957static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
958{
959 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
960 u32 cck_enable;
961 u32 cck_fa_cnt;
962 u32 ofdm_fa_cnt;
963
964 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
965 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
966 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48);
967
968 dm_info->cck_fa_cnt = cck_fa_cnt;
969 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
970 dm_info->total_fa_cnt = ofdm_fa_cnt;
971 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
972
973 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
974 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
975 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
976 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
977 rtw_write32_set(rtwdev, 0xb58, BIT(0));
978 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
979}
980
981static void rtw8822b_do_iqk(struct rtw_dev *rtwdev)
982{
983 static int do_iqk_cnt;
984 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
985 u32 rf_reg, iqk_fail_mask;
986 int counter;
987 bool reload;
988
989 rtw_fw_do_iqk(rtwdev, ¶);
990
991 for (counter = 0; counter < 300; counter++) {
992 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
993 if (rf_reg == 0xabcde)
994 break;
995 msleep(20);
996 }
997 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
998
999 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
1000 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(0, 7));
1001 rtw_dbg(rtwdev, RTW_DBG_PHY,
1002 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
1003 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
1004}
1005
1006static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = {
1007 {0x0086,
1008 RTW_PWR_CUT_ALL_MSK,
1009 RTW_PWR_INTF_SDIO_MSK,
1010 RTW_PWR_ADDR_SDIO,
1011 RTW_PWR_CMD_WRITE, BIT(0), 0},
1012 {0x0086,
1013 RTW_PWR_CUT_ALL_MSK,
1014 RTW_PWR_INTF_SDIO_MSK,
1015 RTW_PWR_ADDR_SDIO,
1016 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1017 {0x004A,
1018 RTW_PWR_CUT_ALL_MSK,
1019 RTW_PWR_INTF_USB_MSK,
1020 RTW_PWR_ADDR_MAC,
1021 RTW_PWR_CMD_WRITE, BIT(0), 0},
1022 {0x0005,
1023 RTW_PWR_CUT_ALL_MSK,
1024 RTW_PWR_INTF_ALL_MSK,
1025 RTW_PWR_ADDR_MAC,
1026 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1027 {0x0300,
1028 RTW_PWR_CUT_ALL_MSK,
1029 RTW_PWR_INTF_PCI_MSK,
1030 RTW_PWR_ADDR_MAC,
1031 RTW_PWR_CMD_WRITE, 0xFF, 0},
1032 {0x0301,
1033 RTW_PWR_CUT_ALL_MSK,
1034 RTW_PWR_INTF_PCI_MSK,
1035 RTW_PWR_ADDR_MAC,
1036 RTW_PWR_CMD_WRITE, 0xFF, 0},
1037 {0xFFFF,
1038 RTW_PWR_CUT_ALL_MSK,
1039 RTW_PWR_INTF_ALL_MSK,
1040 0,
1041 RTW_PWR_CMD_END, 0, 0},
1042};
1043
1044static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = {
1045 {0x0012,
1046 RTW_PWR_CUT_ALL_MSK,
1047 RTW_PWR_INTF_ALL_MSK,
1048 RTW_PWR_ADDR_MAC,
1049 RTW_PWR_CMD_WRITE, BIT(1), 0},
1050 {0x0012,
1051 RTW_PWR_CUT_ALL_MSK,
1052 RTW_PWR_INTF_ALL_MSK,
1053 RTW_PWR_ADDR_MAC,
1054 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1055 {0x0020,
1056 RTW_PWR_CUT_ALL_MSK,
1057 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1058 RTW_PWR_ADDR_MAC,
1059 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1060 {0x0001,
1061 RTW_PWR_CUT_ALL_MSK,
1062 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1063 RTW_PWR_ADDR_MAC,
1064 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1065 {0x0000,
1066 RTW_PWR_CUT_ALL_MSK,
1067 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1068 RTW_PWR_ADDR_MAC,
1069 RTW_PWR_CMD_WRITE, BIT(5), 0},
1070 {0x0005,
1071 RTW_PWR_CUT_ALL_MSK,
1072 RTW_PWR_INTF_ALL_MSK,
1073 RTW_PWR_ADDR_MAC,
1074 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1075 {0x0075,
1076 RTW_PWR_CUT_ALL_MSK,
1077 RTW_PWR_INTF_PCI_MSK,
1078 RTW_PWR_ADDR_MAC,
1079 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1080 {0x0006,
1081 RTW_PWR_CUT_ALL_MSK,
1082 RTW_PWR_INTF_ALL_MSK,
1083 RTW_PWR_ADDR_MAC,
1084 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1085 {0x0075,
1086 RTW_PWR_CUT_ALL_MSK,
1087 RTW_PWR_INTF_PCI_MSK,
1088 RTW_PWR_ADDR_MAC,
1089 RTW_PWR_CMD_WRITE, BIT(0), 0},
1090 {0xFF1A,
1091 RTW_PWR_CUT_ALL_MSK,
1092 RTW_PWR_INTF_USB_MSK,
1093 RTW_PWR_ADDR_MAC,
1094 RTW_PWR_CMD_WRITE, 0xFF, 0},
1095 {0x0006,
1096 RTW_PWR_CUT_ALL_MSK,
1097 RTW_PWR_INTF_ALL_MSK,
1098 RTW_PWR_ADDR_MAC,
1099 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1100 {0x0005,
1101 RTW_PWR_CUT_ALL_MSK,
1102 RTW_PWR_INTF_ALL_MSK,
1103 RTW_PWR_ADDR_MAC,
1104 RTW_PWR_CMD_WRITE, BIT(7), 0},
1105 {0x0005,
1106 RTW_PWR_CUT_ALL_MSK,
1107 RTW_PWR_INTF_ALL_MSK,
1108 RTW_PWR_ADDR_MAC,
1109 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1110 {0x10C3,
1111 RTW_PWR_CUT_ALL_MSK,
1112 RTW_PWR_INTF_USB_MSK,
1113 RTW_PWR_ADDR_MAC,
1114 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1115 {0x0005,
1116 RTW_PWR_CUT_ALL_MSK,
1117 RTW_PWR_INTF_ALL_MSK,
1118 RTW_PWR_ADDR_MAC,
1119 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1120 {0x0005,
1121 RTW_PWR_CUT_ALL_MSK,
1122 RTW_PWR_INTF_ALL_MSK,
1123 RTW_PWR_ADDR_MAC,
1124 RTW_PWR_CMD_POLLING, BIT(0), 0},
1125 {0x0020,
1126 RTW_PWR_CUT_ALL_MSK,
1127 RTW_PWR_INTF_ALL_MSK,
1128 RTW_PWR_ADDR_MAC,
1129 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1130 {0x10A8,
1131 RTW_PWR_CUT_C_MSK,
1132 RTW_PWR_INTF_ALL_MSK,
1133 RTW_PWR_ADDR_MAC,
1134 RTW_PWR_CMD_WRITE, 0xFF, 0},
1135 {0x10A9,
1136 RTW_PWR_CUT_C_MSK,
1137 RTW_PWR_INTF_ALL_MSK,
1138 RTW_PWR_ADDR_MAC,
1139 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1140 {0x10AA,
1141 RTW_PWR_CUT_C_MSK,
1142 RTW_PWR_INTF_ALL_MSK,
1143 RTW_PWR_ADDR_MAC,
1144 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1145 {0x0068,
1146 RTW_PWR_CUT_C_MSK,
1147 RTW_PWR_INTF_SDIO_MSK,
1148 RTW_PWR_ADDR_MAC,
1149 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1150 {0x0029,
1151 RTW_PWR_CUT_ALL_MSK,
1152 RTW_PWR_INTF_ALL_MSK,
1153 RTW_PWR_ADDR_MAC,
1154 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1155 {0x0024,
1156 RTW_PWR_CUT_ALL_MSK,
1157 RTW_PWR_INTF_ALL_MSK,
1158 RTW_PWR_ADDR_MAC,
1159 RTW_PWR_CMD_WRITE, BIT(2), 0},
1160 {0x0074,
1161 RTW_PWR_CUT_ALL_MSK,
1162 RTW_PWR_INTF_PCI_MSK,
1163 RTW_PWR_ADDR_MAC,
1164 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1165 {0x00AF,
1166 RTW_PWR_CUT_ALL_MSK,
1167 RTW_PWR_INTF_ALL_MSK,
1168 RTW_PWR_ADDR_MAC,
1169 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1170 {0xFFFF,
1171 RTW_PWR_CUT_ALL_MSK,
1172 RTW_PWR_INTF_ALL_MSK,
1173 0,
1174 RTW_PWR_CMD_END, 0, 0},
1175};
1176
1177static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = {
1178 {0x0003,
1179 RTW_PWR_CUT_ALL_MSK,
1180 RTW_PWR_INTF_SDIO_MSK,
1181 RTW_PWR_ADDR_MAC,
1182 RTW_PWR_CMD_WRITE, BIT(2), 0},
1183 {0x0093,
1184 RTW_PWR_CUT_ALL_MSK,
1185 RTW_PWR_INTF_ALL_MSK,
1186 RTW_PWR_ADDR_MAC,
1187 RTW_PWR_CMD_WRITE, BIT(3), 0},
1188 {0x001F,
1189 RTW_PWR_CUT_ALL_MSK,
1190 RTW_PWR_INTF_ALL_MSK,
1191 RTW_PWR_ADDR_MAC,
1192 RTW_PWR_CMD_WRITE, 0xFF, 0},
1193 {0x00EF,
1194 RTW_PWR_CUT_ALL_MSK,
1195 RTW_PWR_INTF_ALL_MSK,
1196 RTW_PWR_ADDR_MAC,
1197 RTW_PWR_CMD_WRITE, 0xFF, 0},
1198 {0xFF1A,
1199 RTW_PWR_CUT_ALL_MSK,
1200 RTW_PWR_INTF_USB_MSK,
1201 RTW_PWR_ADDR_MAC,
1202 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1203 {0x0049,
1204 RTW_PWR_CUT_ALL_MSK,
1205 RTW_PWR_INTF_ALL_MSK,
1206 RTW_PWR_ADDR_MAC,
1207 RTW_PWR_CMD_WRITE, BIT(1), 0},
1208 {0x0006,
1209 RTW_PWR_CUT_ALL_MSK,
1210 RTW_PWR_INTF_ALL_MSK,
1211 RTW_PWR_ADDR_MAC,
1212 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1213 {0x0002,
1214 RTW_PWR_CUT_ALL_MSK,
1215 RTW_PWR_INTF_ALL_MSK,
1216 RTW_PWR_ADDR_MAC,
1217 RTW_PWR_CMD_WRITE, BIT(1), 0},
1218 {0x10C3,
1219 RTW_PWR_CUT_ALL_MSK,
1220 RTW_PWR_INTF_USB_MSK,
1221 RTW_PWR_ADDR_MAC,
1222 RTW_PWR_CMD_WRITE, BIT(0), 0},
1223 {0x0005,
1224 RTW_PWR_CUT_ALL_MSK,
1225 RTW_PWR_INTF_ALL_MSK,
1226 RTW_PWR_ADDR_MAC,
1227 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1228 {0x0005,
1229 RTW_PWR_CUT_ALL_MSK,
1230 RTW_PWR_INTF_ALL_MSK,
1231 RTW_PWR_ADDR_MAC,
1232 RTW_PWR_CMD_POLLING, BIT(1), 0},
1233 {0x0020,
1234 RTW_PWR_CUT_ALL_MSK,
1235 RTW_PWR_INTF_ALL_MSK,
1236 RTW_PWR_ADDR_MAC,
1237 RTW_PWR_CMD_WRITE, BIT(3), 0},
1238 {0x0000,
1239 RTW_PWR_CUT_ALL_MSK,
1240 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1241 RTW_PWR_ADDR_MAC,
1242 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1243 {0xFFFF,
1244 RTW_PWR_CUT_ALL_MSK,
1245 RTW_PWR_INTF_ALL_MSK,
1246 0,
1247 RTW_PWR_CMD_END, 0, 0},
1248};
1249
1250static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = {
1251 {0x0005,
1252 RTW_PWR_CUT_ALL_MSK,
1253 RTW_PWR_INTF_SDIO_MSK,
1254 RTW_PWR_ADDR_MAC,
1255 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1256 {0x0007,
1257 RTW_PWR_CUT_ALL_MSK,
1258 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1259 RTW_PWR_ADDR_MAC,
1260 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1261 {0x0067,
1262 RTW_PWR_CUT_ALL_MSK,
1263 RTW_PWR_INTF_ALL_MSK,
1264 RTW_PWR_ADDR_MAC,
1265 RTW_PWR_CMD_WRITE, BIT(5), 0},
1266 {0x0005,
1267 RTW_PWR_CUT_ALL_MSK,
1268 RTW_PWR_INTF_PCI_MSK,
1269 RTW_PWR_ADDR_MAC,
1270 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1271 {0x004A,
1272 RTW_PWR_CUT_ALL_MSK,
1273 RTW_PWR_INTF_USB_MSK,
1274 RTW_PWR_ADDR_MAC,
1275 RTW_PWR_CMD_WRITE, BIT(0), 0},
1276 {0x0067,
1277 RTW_PWR_CUT_ALL_MSK,
1278 RTW_PWR_INTF_SDIO_MSK,
1279 RTW_PWR_ADDR_MAC,
1280 RTW_PWR_CMD_WRITE, BIT(5), 0},
1281 {0x0067,
1282 RTW_PWR_CUT_ALL_MSK,
1283 RTW_PWR_INTF_SDIO_MSK,
1284 RTW_PWR_ADDR_MAC,
1285 RTW_PWR_CMD_WRITE, BIT(4), 0},
1286 {0x004F,
1287 RTW_PWR_CUT_ALL_MSK,
1288 RTW_PWR_INTF_SDIO_MSK,
1289 RTW_PWR_ADDR_MAC,
1290 RTW_PWR_CMD_WRITE, BIT(0), 0},
1291 {0x0067,
1292 RTW_PWR_CUT_ALL_MSK,
1293 RTW_PWR_INTF_SDIO_MSK,
1294 RTW_PWR_ADDR_MAC,
1295 RTW_PWR_CMD_WRITE, BIT(1), 0},
1296 {0x0046,
1297 RTW_PWR_CUT_ALL_MSK,
1298 RTW_PWR_INTF_SDIO_MSK,
1299 RTW_PWR_ADDR_MAC,
1300 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1301 {0x0067,
1302 RTW_PWR_CUT_ALL_MSK,
1303 RTW_PWR_INTF_SDIO_MSK,
1304 RTW_PWR_ADDR_MAC,
1305 RTW_PWR_CMD_WRITE, BIT(2), 0},
1306 {0x0046,
1307 RTW_PWR_CUT_ALL_MSK,
1308 RTW_PWR_INTF_SDIO_MSK,
1309 RTW_PWR_ADDR_MAC,
1310 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1311 {0x0062,
1312 RTW_PWR_CUT_ALL_MSK,
1313 RTW_PWR_INTF_SDIO_MSK,
1314 RTW_PWR_ADDR_MAC,
1315 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1316 {0x0081,
1317 RTW_PWR_CUT_ALL_MSK,
1318 RTW_PWR_INTF_ALL_MSK,
1319 RTW_PWR_ADDR_MAC,
1320 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1321 {0x0005,
1322 RTW_PWR_CUT_ALL_MSK,
1323 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1324 RTW_PWR_ADDR_MAC,
1325 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1326 {0x0086,
1327 RTW_PWR_CUT_ALL_MSK,
1328 RTW_PWR_INTF_SDIO_MSK,
1329 RTW_PWR_ADDR_SDIO,
1330 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1331 {0x0086,
1332 RTW_PWR_CUT_ALL_MSK,
1333 RTW_PWR_INTF_SDIO_MSK,
1334 RTW_PWR_ADDR_SDIO,
1335 RTW_PWR_CMD_POLLING, BIT(1), 0},
1336 {0x0090,
1337 RTW_PWR_CUT_ALL_MSK,
1338 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1339 RTW_PWR_ADDR_MAC,
1340 RTW_PWR_CMD_WRITE, BIT(1), 0},
1341 {0x0044,
1342 RTW_PWR_CUT_ALL_MSK,
1343 RTW_PWR_INTF_SDIO_MSK,
1344 RTW_PWR_ADDR_SDIO,
1345 RTW_PWR_CMD_WRITE, 0xFF, 0},
1346 {0x0040,
1347 RTW_PWR_CUT_ALL_MSK,
1348 RTW_PWR_INTF_SDIO_MSK,
1349 RTW_PWR_ADDR_SDIO,
1350 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1351 {0x0041,
1352 RTW_PWR_CUT_ALL_MSK,
1353 RTW_PWR_INTF_SDIO_MSK,
1354 RTW_PWR_ADDR_SDIO,
1355 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1356 {0x0042,
1357 RTW_PWR_CUT_ALL_MSK,
1358 RTW_PWR_INTF_SDIO_MSK,
1359 RTW_PWR_ADDR_SDIO,
1360 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1361 {0xFFFF,
1362 RTW_PWR_CUT_ALL_MSK,
1363 RTW_PWR_INTF_ALL_MSK,
1364 0,
1365 RTW_PWR_CMD_END, 0, 0},
1366};
1367
1368static struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = {
1369 trans_carddis_to_cardemu_8822b,
1370 trans_cardemu_to_act_8822b,
1371 NULL
1372};
1373
1374static struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = {
1375 trans_act_to_cardemu_8822b,
1376 trans_cardemu_to_carddis_8822b,
1377 NULL
1378};
1379
1380static struct rtw_intf_phy_para usb2_param_8822b[] = {
1381 {0xFFFF, 0x00,
1382 RTW_IP_SEL_PHY,
1383 RTW_INTF_PHY_CUT_ALL,
1384 RTW_INTF_PHY_PLATFORM_ALL},
1385};
1386
1387static struct rtw_intf_phy_para usb3_param_8822b[] = {
1388 {0x0001, 0xA841,
1389 RTW_IP_SEL_PHY,
1390 RTW_INTF_PHY_CUT_D,
1391 RTW_INTF_PHY_PLATFORM_ALL},
1392 {0xFFFF, 0x0000,
1393 RTW_IP_SEL_PHY,
1394 RTW_INTF_PHY_CUT_ALL,
1395 RTW_INTF_PHY_PLATFORM_ALL},
1396};
1397
1398static struct rtw_intf_phy_para pcie_gen1_param_8822b[] = {
1399 {0x0001, 0xA841,
1400 RTW_IP_SEL_PHY,
1401 RTW_INTF_PHY_CUT_C,
1402 RTW_INTF_PHY_PLATFORM_ALL},
1403 {0x0002, 0x60C6,
1404 RTW_IP_SEL_PHY,
1405 RTW_INTF_PHY_CUT_C,
1406 RTW_INTF_PHY_PLATFORM_ALL},
1407 {0x0008, 0x3596,
1408 RTW_IP_SEL_PHY,
1409 RTW_INTF_PHY_CUT_C,
1410 RTW_INTF_PHY_PLATFORM_ALL},
1411 {0x0009, 0x321C,
1412 RTW_IP_SEL_PHY,
1413 RTW_INTF_PHY_CUT_C,
1414 RTW_INTF_PHY_PLATFORM_ALL},
1415 {0x000A, 0x9623,
1416 RTW_IP_SEL_PHY,
1417 RTW_INTF_PHY_CUT_C,
1418 RTW_INTF_PHY_PLATFORM_ALL},
1419 {0x0020, 0x94FF,
1420 RTW_IP_SEL_PHY,
1421 RTW_INTF_PHY_CUT_C,
1422 RTW_INTF_PHY_PLATFORM_ALL},
1423 {0x0021, 0xFFCF,
1424 RTW_IP_SEL_PHY,
1425 RTW_INTF_PHY_CUT_C,
1426 RTW_INTF_PHY_PLATFORM_ALL},
1427 {0x0026, 0xC006,
1428 RTW_IP_SEL_PHY,
1429 RTW_INTF_PHY_CUT_C,
1430 RTW_INTF_PHY_PLATFORM_ALL},
1431 {0x0029, 0xFF0E,
1432 RTW_IP_SEL_PHY,
1433 RTW_INTF_PHY_CUT_C,
1434 RTW_INTF_PHY_PLATFORM_ALL},
1435 {0x002A, 0x1840,
1436 RTW_IP_SEL_PHY,
1437 RTW_INTF_PHY_CUT_C,
1438 RTW_INTF_PHY_PLATFORM_ALL},
1439 {0xFFFF, 0x0000,
1440 RTW_IP_SEL_PHY,
1441 RTW_INTF_PHY_CUT_ALL,
1442 RTW_INTF_PHY_PLATFORM_ALL},
1443};
1444
1445static struct rtw_intf_phy_para pcie_gen2_param_8822b[] = {
1446 {0x0001, 0xA841,
1447 RTW_IP_SEL_PHY,
1448 RTW_INTF_PHY_CUT_C,
1449 RTW_INTF_PHY_PLATFORM_ALL},
1450 {0x0002, 0x60C6,
1451 RTW_IP_SEL_PHY,
1452 RTW_INTF_PHY_CUT_C,
1453 RTW_INTF_PHY_PLATFORM_ALL},
1454 {0x0008, 0x3597,
1455 RTW_IP_SEL_PHY,
1456 RTW_INTF_PHY_CUT_C,
1457 RTW_INTF_PHY_PLATFORM_ALL},
1458 {0x0009, 0x321C,
1459 RTW_IP_SEL_PHY,
1460 RTW_INTF_PHY_CUT_C,
1461 RTW_INTF_PHY_PLATFORM_ALL},
1462 {0x000A, 0x9623,
1463 RTW_IP_SEL_PHY,
1464 RTW_INTF_PHY_CUT_C,
1465 RTW_INTF_PHY_PLATFORM_ALL},
1466 {0x0020, 0x94FF,
1467 RTW_IP_SEL_PHY,
1468 RTW_INTF_PHY_CUT_C,
1469 RTW_INTF_PHY_PLATFORM_ALL},
1470 {0x0021, 0xFFCF,
1471 RTW_IP_SEL_PHY,
1472 RTW_INTF_PHY_CUT_C,
1473 RTW_INTF_PHY_PLATFORM_ALL},
1474 {0x0026, 0xC006,
1475 RTW_IP_SEL_PHY,
1476 RTW_INTF_PHY_CUT_C,
1477 RTW_INTF_PHY_PLATFORM_ALL},
1478 {0x0029, 0xFF0E,
1479 RTW_IP_SEL_PHY,
1480 RTW_INTF_PHY_CUT_C,
1481 RTW_INTF_PHY_PLATFORM_ALL},
1482 {0x002A, 0x3040,
1483 RTW_IP_SEL_PHY,
1484 RTW_INTF_PHY_CUT_C,
1485 RTW_INTF_PHY_PLATFORM_ALL},
1486 {0xFFFF, 0x0000,
1487 RTW_IP_SEL_PHY,
1488 RTW_INTF_PHY_CUT_ALL,
1489 RTW_INTF_PHY_PLATFORM_ALL},
1490};
1491
1492static struct rtw_intf_phy_para_table phy_para_table_8822b = {
1493 .usb2_para = usb2_param_8822b,
1494 .usb3_para = usb3_param_8822b,
1495 .gen1_para = pcie_gen1_param_8822b,
1496 .gen2_para = pcie_gen2_param_8822b,
1497 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b),
1498 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b),
1499 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b),
1500 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b),
1501};
1502
1503static const struct rtw_rfe_def rtw8822b_rfe_defs[] = {
1504 [2] = RTW_DEF_RFE(8822b, 2, 2),
1505 [5] = RTW_DEF_RFE(8822b, 5, 5),
1506};
1507
1508static struct rtw_hw_reg rtw8822b_dig[] = {
1509 [0] = { .addr = 0xc50, .mask = 0x7f },
1510 [1] = { .addr = 0xe50, .mask = 0x7f },
1511};
1512
1513static struct rtw_page_table page_table_8822b[] = {
1514 {64, 64, 64, 64, 1},
1515 {64, 64, 64, 64, 1},
1516 {64, 64, 0, 0, 1},
1517 {64, 64, 64, 0, 1},
1518 {64, 64, 64, 64, 1},
1519};
1520
1521static struct rtw_rqpn rqpn_table_8822b[] = {
1522 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1523 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1524 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1525 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1526 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1527 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1528 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1529 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1530 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1531 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1532 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1533 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1534 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1535 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1536 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1537};
1538
1539static struct rtw_chip_ops rtw8822b_ops = {
1540 .phy_set_param = rtw8822b_phy_set_param,
1541 .read_efuse = rtw8822b_read_efuse,
1542 .query_rx_desc = rtw8822b_query_rx_desc,
1543 .set_channel = rtw8822b_set_channel,
1544 .mac_init = rtw8822b_mac_init,
1545 .read_rf = rtw_phy_read_rf,
1546 .write_rf = rtw_phy_write_rf_reg_sipi,
1547 .set_tx_power_index = rtw8822b_set_tx_power_index,
1548 .set_antenna = rtw8822b_set_antenna,
1549 .cfg_ldo25 = rtw8822b_cfg_ldo25,
1550 .false_alarm_statistics = rtw8822b_false_alarm_statistics,
1551 .do_iqk = rtw8822b_do_iqk,
1552};
1553
1554struct rtw_chip_info rtw8822b_hw_spec = {
1555 .ops = &rtw8822b_ops,
1556 .id = RTW_CHIP_TYPE_8822B,
1557 .fw_name = "rtw88/rtw8822b_fw.bin",
1558 .tx_pkt_desc_sz = 48,
1559 .tx_buf_desc_sz = 16,
1560 .rx_pkt_desc_sz = 24,
1561 .rx_buf_desc_sz = 8,
1562 .phy_efuse_size = 1024,
1563 .log_efuse_size = 768,
1564 .ptct_efuse_size = 96,
1565 .txff_size = 262144,
1566 .rxff_size = 24576,
1567 .txgi_factor = 1,
1568 .is_pwr_by_rate_dec = true,
1569 .max_power_index = 0x3f,
1570 .csi_buf_pg_num = 0,
1571 .band = RTW_BAND_2G | RTW_BAND_5G,
1572 .page_size = 128,
1573 .dig_min = 0x1c,
1574 .ht_supported = true,
1575 .vht_supported = true,
1576 .sys_func_en = 0xDC,
1577 .pwr_on_seq = card_enable_flow_8822b,
1578 .pwr_off_seq = card_disable_flow_8822b,
1579 .page_table = page_table_8822b,
1580 .rqpn_table = rqpn_table_8822b,
1581 .intf_table = &phy_para_table_8822b,
1582 .dig = rtw8822b_dig,
1583 .rf_base_addr = {0x2800, 0x2c00},
1584 .rf_sipi_addr = {0xc90, 0xe90},
1585 .mac_tbl = &rtw8822b_mac_tbl,
1586 .agc_tbl = &rtw8822b_agc_tbl,
1587 .bb_tbl = &rtw8822b_bb_tbl,
1588 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl},
1589 .rfe_defs = rtw8822b_rfe_defs,
1590 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs),
1591};
1592EXPORT_SYMBOL(rtw8822b_hw_spec);
1593
1594MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin");
1595
