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5#ifndef __RTW8822C_H__
6#define __RTW8822C_H__
7
8#include <asm/byteorder.h>
9
10struct rtw8822cu_efuse {
11 u8 res0[0x30];
12 u8 vid[2];
13 u8 pid[2];
14 u8 res1[3];
15 u8 mac_addr[ETH_ALEN];
16 u8 res2[0x3d];
17};
18
19struct rtw8822ce_efuse {
20 u8 mac_addr[ETH_ALEN];
21 u8 vender_id[2];
22 u8 device_id[2];
23 u8 sub_vender_id[2];
24 u8 sub_device_id[2];
25 u8 pmc[2];
26 u8 exp_device_cap[2];
27 u8 msi_cap;
28 u8 ltr_cap;
29 u8 exp_link_control[2];
30 u8 link_cap[4];
31 u8 link_control[2];
32 u8 serial_number[8];
33 u8 res0:2;
34 u8 ltr_en:1;
35 u8 res1:2;
36 u8 obff:2;
37 u8 res2:3;
38 u8 obff_cap:2;
39 u8 res3:4;
40 u8 class_code[3];
41 u8 res4;
42 u8 pci_pm_L1_2_supp:1;
43 u8 pci_pm_L1_1_supp:1;
44 u8 aspm_pm_L1_2_supp:1;
45 u8 aspm_pm_L1_1_supp:1;
46 u8 L1_pm_substates_supp:1;
47 u8 res5:3;
48 u8 port_common_mode_restore_time;
49 u8 port_t_power_on_scale:2;
50 u8 res6:1;
51 u8 port_t_power_on_value:5;
52 u8 res7;
53};
54
55struct rtw8822c_efuse {
56 __le16 rtl_id;
57 u8 res0[0x0e];
58
59
60 struct rtw_txpwr_idx txpwr_idx_table[4];
61
62 u8 channel_plan;
63 u8 xtal_k;
64 u8 res1;
65 u8 iqk_lck;
66 u8 res2[5];
67 u8 rf_board_option;
68 u8 rf_feature_option;
69 u8 rf_bt_setting;
70 u8 eeprom_version;
71 u8 eeprom_customer_id;
72 u8 tx_bb_swing_setting_2g;
73 u8 tx_bb_swing_setting_5g;
74 u8 tx_pwr_calibrate_rate;
75 u8 rf_antenna_option;
76 u8 rfe_option;
77 u8 country_code[2];
78 u8 res3[3];
79 u8 path_a_thermal;
80 u8 path_b_thermal;
81 u8 res4[2];
82 u8 rx_gain_gap_2g_ofdm;
83 u8 res5;
84 u8 rx_gain_gap_2g_cck;
85 u8 res6;
86 u8 rx_gain_gap_5gl;
87 u8 res7;
88 u8 rx_gain_gap_5gm;
89 u8 res8;
90 u8 rx_gain_gap_5gh;
91 u8 res9;
92 u8 res10[0x42];
93 union {
94 struct rtw8822cu_efuse u;
95 struct rtw8822ce_efuse e;
96 };
97};
98
99#define DACK_PATH_8822C 2
100#define DACK_REG_8822C 16
101#define DACK_RF_8822C 1
102#define DACK_SN_8822C 100
103
104
105#define GET_PHY_STAT_P0_PWDB_A(phy_stat) \
106 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
107#define GET_PHY_STAT_P0_PWDB_B(phy_stat) \
108 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
109#define GET_PHY_STAT_P0_GAIN_A(phy_stat) \
110 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
111#define GET_PHY_STAT_P0_GAIN_B(phy_stat) \
112 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
113
114
115#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
116 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
117#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
118 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
119#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
120 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
121#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
122 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
123
124#define REG_ANAPARLDO_POW_MAC 0x0029
125#define BIT_LDOE25_PON BIT(0)
126#define REG_RRSR 0x0440
127#define BITS_RRSR_RSC (BIT(21) | BIT(22))
128
129#define REG_TXDFIR0 0x808
130#define REG_DFIRBW 0x810
131#define REG_ANTMAP0 0x820
132#define REG_ANTMAP 0x824
133#define REG_DYMPRITH 0x86c
134#define REG_DYMENTH0 0x870
135#define REG_DYMENTH 0x874
136#define REG_SBD 0x88c
137#define BITS_SUBTUNE GENMASK(15, 12)
138#define REG_DYMTHMIN 0x8a4
139#define REG_TXBWCTL 0x9b0
140#define REG_TXCLK 0x9b4
141#define REG_SCOTRK 0xc30
142#define REG_MRCM 0xc38
143#define REG_AGCSWSH 0xc44
144#define REG_ANTWTPD 0xc54
145#define REG_PT_CHSMO 0xcbc
146#define BIT_PT_OPT BIT(21)
147#define REG_ORITXCODE 0x1800
148#define REG_3WIRE 0x180c
149#define BIT_3WIRE_TX_EN BIT(0)
150#define BIT_3WIRE_RX_EN BIT(1)
151#define BIT_3WIRE_PI_ON BIT(28)
152#define REG_RXAGCCTL0 0x18ac
153#define BITS_RXAGC_CCK GENMASK(15, 12)
154#define BITS_RXAGC_OFDM GENMASK(8, 4)
155#define REG_DCKA_I_0 0x18bc
156#define REG_DCKA_I_1 0x18c0
157#define REG_DCKA_Q_0 0x18d8
158#define REG_DCKA_Q_1 0x18dc
159#define REG_CCKSB 0x1a00
160#define REG_RXCCKSEL 0x1a04
161#define REG_BGCTRL 0x1a14
162#define BITS_RX_IQ_WEIGHT (BIT(8) | BIT(9))
163#define REG_TXF0 0x1a20
164#define REG_TXF1 0x1a24
165#define REG_TXF2 0x1a28
166#define REG_CCANRX 0x1a2c
167#define BIT_CCK_FA_RST (BIT(14) | BIT(15))
168#define BIT_OFDM_FA_RST (BIT(12) | BIT(13))
169#define REG_CCK_FACNT 0x1a5c
170#define REG_CCKTXONLY 0x1a80
171#define BIT_BB_CCK_CHECK_EN BIT(18)
172#define REG_TXF3 0x1a98
173#define REG_TXF4 0x1a9c
174#define REG_TXF5 0x1aa0
175#define REG_TXF6 0x1aac
176#define REG_TXF7 0x1ab0
177#define REG_CCK_SOURCE 0x1abc
178#define BIT_NBI_EN BIT(30)
179#define REG_TXANT 0x1c28
180#define REG_ENCCK 0x1c3c
181#define BIT_CCK_BLK_EN BIT(1)
182#define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
183#define REG_CCAMSK 0x1c80
184#define REG_RX_BREAK 0x1d2c
185#define BIT_COM_RX_GCK_EN BIT(31)
186#define REG_RXFNCTL 0x1d30
187#define REG_RXIGI 0x1d70
188#define REG_ENFN 0x1e24
189#define REG_TXANTSEG 0x1e28
190#define REG_TXLGMAP 0x1e2c
191#define REG_CCKPATH 0x1e5c
192#define REG_CNT_CTRL 0x1eb4
193#define BIT_ALL_CNT_RST BIT(25)
194#define REG_OFDM_FACNT 0x2d00
195#define REG_OFDM_FACNT1 0x2d04
196#define REG_OFDM_FACNT2 0x2d08
197#define REG_OFDM_FACNT3 0x2d0c
198#define REG_OFDM_FACNT4 0x2d10
199#define REG_OFDM_FACNT5 0x2d20
200#define REG_OFDM_TXCNT 0x2de0
201#define REG_ORITXCODE2 0x4100
202#define REG_3WIRE2 0x410c
203#define REG_RXAGCCTL 0x41ac
204#define REG_DCKB_I_0 0x41bc
205#define REG_DCKB_I_1 0x41c0
206#define REG_DCKB_Q_0 0x41d8
207#define REG_DCKB_Q_1 0x41dc
208
209#endif
210
