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11#include <linux/bitfield.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/gpio.h>
15#include <linux/kernel.h>
16#include <linux/mfd/syscon.h>
17#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
19#include <linux/module.h>
20#include <linux/of_gpio.h>
21#include <linux/of_device.h>
22#include <linux/of_address.h>
23#include <linux/pci.h>
24#include <linux/platform_device.h>
25#include <linux/regmap.h>
26#include <linux/regulator/consumer.h>
27#include <linux/resource.h>
28#include <linux/signal.h>
29#include <linux/types.h>
30#include <linux/interrupt.h>
31#include <linux/reset.h>
32#include <linux/pm_domain.h>
33#include <linux/pm_runtime.h>
34
35#include "pcie-designware.h"
36
37#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
38#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
39#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
40#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
41#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
42
43#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
44
45enum imx6_pcie_variants {
46 IMX6Q,
47 IMX6SX,
48 IMX6QP,
49 IMX7D,
50 IMX8MQ,
51};
52
53#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
54#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
55#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
56
57struct imx6_pcie_drvdata {
58 enum imx6_pcie_variants variant;
59 u32 flags;
60};
61
62struct imx6_pcie {
63 struct dw_pcie *pci;
64 int reset_gpio;
65 bool gpio_active_high;
66 struct clk *pcie_bus;
67 struct clk *pcie_phy;
68 struct clk *pcie_inbound_axi;
69 struct clk *pcie;
70 struct clk *pcie_aux;
71 struct regmap *iomuxc_gpr;
72 u32 controller_id;
73 struct reset_control *pciephy_reset;
74 struct reset_control *apps_reset;
75 struct reset_control *turnoff_reset;
76 u32 tx_deemph_gen1;
77 u32 tx_deemph_gen2_3p5db;
78 u32 tx_deemph_gen2_6db;
79 u32 tx_swing_full;
80 u32 tx_swing_low;
81 int link_gen;
82 struct regulator *vpcie;
83 void __iomem *phy_base;
84
85
86 struct device *pd_pcie;
87
88 struct device *pd_pcie_phy;
89 const struct imx6_pcie_drvdata *drvdata;
90};
91
92
93#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
94#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
95
96
97#define PCIE_RC_IMX6_MSI_CAP 0x50
98#define PCIE_RC_LCR 0x7c
99#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
100#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
101#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
102
103#define PCIE_RC_LCSR 0x80
104
105
106#define PL_OFFSET 0x700
107
108#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
109#define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x))
110#define PCIE_PHY_CTRL_CAP_ADR BIT(16)
111#define PCIE_PHY_CTRL_CAP_DAT BIT(17)
112#define PCIE_PHY_CTRL_WR BIT(18)
113#define PCIE_PHY_CTRL_RD BIT(19)
114
115#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
116#define PCIE_PHY_STAT_ACK BIT(16)
117
118#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
119
120
121#define PCIE_PHY_ATEOVRD 0x10
122#define PCIE_PHY_ATEOVRD_EN BIT(2)
123#define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
124#define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
125
126#define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
127#define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
128#define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
129#define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9)
130
131#define PCIE_PHY_RX_ASIC_OUT 0x100D
132#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
133
134
135#define PCIE_PHY_CMN_REG4 0x14
136
137#define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29
138
139#define PCIE_PHY_CMN_REG15 0x54
140#define PCIE_PHY_CMN_REG15_DLY_4 BIT(2)
141#define PCIE_PHY_CMN_REG15_PLL_PD BIT(5)
142#define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7)
143
144#define PCIE_PHY_CMN_REG24 0x90
145#define PCIE_PHY_CMN_REG24_RX_EQ BIT(6)
146#define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3)
147
148#define PCIE_PHY_CMN_REG26 0x98
149#define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
150
151#define PHY_RX_OVRD_IN_LO 0x1005
152#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
153#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
154
155static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
156{
157 struct dw_pcie *pci = imx6_pcie->pci;
158 bool val;
159 u32 max_iterations = 10;
160 u32 wait_counter = 0;
161
162 do {
163 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
164 PCIE_PHY_STAT_ACK;
165 wait_counter++;
166
167 if (val == exp_val)
168 return 0;
169
170 udelay(1);
171 } while (wait_counter < max_iterations);
172
173 return -ETIMEDOUT;
174}
175
176static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
177{
178 struct dw_pcie *pci = imx6_pcie->pci;
179 u32 val;
180 int ret;
181
182 val = PCIE_PHY_CTRL_DATA(addr);
183 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
184
185 val |= PCIE_PHY_CTRL_CAP_ADR;
186 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
187
188 ret = pcie_phy_poll_ack(imx6_pcie, true);
189 if (ret)
190 return ret;
191
192 val = PCIE_PHY_CTRL_DATA(addr);
193 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
194
195 return pcie_phy_poll_ack(imx6_pcie, false);
196}
197
198
199static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
200{
201 struct dw_pcie *pci = imx6_pcie->pci;
202 u32 phy_ctl;
203 int ret;
204
205 ret = pcie_phy_wait_ack(imx6_pcie, addr);
206 if (ret)
207 return ret;
208
209
210 phy_ctl = PCIE_PHY_CTRL_RD;
211 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
212
213 ret = pcie_phy_poll_ack(imx6_pcie, true);
214 if (ret)
215 return ret;
216
217 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
218
219
220 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
221
222 return pcie_phy_poll_ack(imx6_pcie, false);
223}
224
225static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
226{
227 struct dw_pcie *pci = imx6_pcie->pci;
228 u32 var;
229 int ret;
230
231
232
233 ret = pcie_phy_wait_ack(imx6_pcie, addr);
234 if (ret)
235 return ret;
236
237 var = PCIE_PHY_CTRL_DATA(data);
238 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
239
240
241 var |= PCIE_PHY_CTRL_CAP_DAT;
242 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
243
244 ret = pcie_phy_poll_ack(imx6_pcie, true);
245 if (ret)
246 return ret;
247
248
249 var = PCIE_PHY_CTRL_DATA(data);
250 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
251
252
253 ret = pcie_phy_poll_ack(imx6_pcie, false);
254 if (ret)
255 return ret;
256
257
258 var = PCIE_PHY_CTRL_WR;
259 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
260
261
262 ret = pcie_phy_poll_ack(imx6_pcie, true);
263 if (ret)
264 return ret;
265
266
267 var = PCIE_PHY_CTRL_DATA(data);
268 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
269
270
271 ret = pcie_phy_poll_ack(imx6_pcie, false);
272 if (ret)
273 return ret;
274
275 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
276
277 return 0;
278}
279
280static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
281{
282 u16 tmp;
283
284 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
285 return;
286
287 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
288 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
289 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
290 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
291
292 usleep_range(2000, 3000);
293
294 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
295 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
296 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
297 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
298}
299
300#ifdef CONFIG_ARM
301
302static int imx6q_pcie_abort_handler(unsigned long addr,
303 unsigned int fsr, struct pt_regs *regs)
304{
305 unsigned long pc = instruction_pointer(regs);
306 unsigned long instr = *(unsigned long *)pc;
307 int reg = (instr >> 12) & 15;
308
309
310
311
312
313 if ((instr & 0x0c100000) == 0x04100000) {
314 unsigned long val;
315
316 if (instr & 0x00400000)
317 val = 255;
318 else
319 val = -1;
320
321 regs->uregs[reg] = val;
322 regs->ARM_pc += 4;
323 return 0;
324 }
325
326 if ((instr & 0x0e100090) == 0x00100090) {
327 regs->uregs[reg] = -1;
328 regs->ARM_pc += 4;
329 return 0;
330 }
331
332 return 1;
333}
334#endif
335
336static int imx6_pcie_attach_pd(struct device *dev)
337{
338 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
339 struct device_link *link;
340
341
342 if (dev->pm_domain)
343 return 0;
344
345 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
346 if (IS_ERR(imx6_pcie->pd_pcie))
347 return PTR_ERR(imx6_pcie->pd_pcie);
348
349 if (!imx6_pcie->pd_pcie)
350 return 0;
351 link = device_link_add(dev, imx6_pcie->pd_pcie,
352 DL_FLAG_STATELESS |
353 DL_FLAG_PM_RUNTIME |
354 DL_FLAG_RPM_ACTIVE);
355 if (!link) {
356 dev_err(dev, "Failed to add device_link to pcie pd.\n");
357 return -EINVAL;
358 }
359
360 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
361 if (IS_ERR(imx6_pcie->pd_pcie_phy))
362 return PTR_ERR(imx6_pcie->pd_pcie_phy);
363
364 link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
365 DL_FLAG_STATELESS |
366 DL_FLAG_PM_RUNTIME |
367 DL_FLAG_RPM_ACTIVE);
368 if (!link) {
369 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
370 return -EINVAL;
371 }
372
373 return 0;
374}
375
376static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
377{
378 struct device *dev = imx6_pcie->pci->dev;
379
380 switch (imx6_pcie->drvdata->variant) {
381 case IMX7D:
382 case IMX8MQ:
383 reset_control_assert(imx6_pcie->pciephy_reset);
384 reset_control_assert(imx6_pcie->apps_reset);
385 break;
386 case IMX6SX:
387 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
388 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
389 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
390
391 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
392 IMX6SX_GPR5_PCIE_BTNRST_RESET,
393 IMX6SX_GPR5_PCIE_BTNRST_RESET);
394 break;
395 case IMX6QP:
396 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
397 IMX6Q_GPR1_PCIE_SW_RST,
398 IMX6Q_GPR1_PCIE_SW_RST);
399 break;
400 case IMX6Q:
401 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
402 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
403 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
404 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
405 break;
406 }
407
408 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
409 int ret = regulator_disable(imx6_pcie->vpcie);
410
411 if (ret)
412 dev_err(dev, "failed to disable vpcie regulator: %d\n",
413 ret);
414 }
415}
416
417static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
418{
419 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
420 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
421}
422
423static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
424{
425 struct dw_pcie *pci = imx6_pcie->pci;
426 struct device *dev = pci->dev;
427 unsigned int offset;
428 int ret = 0;
429
430 switch (imx6_pcie->drvdata->variant) {
431 case IMX6SX:
432 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
433 if (ret) {
434 dev_err(dev, "unable to enable pcie_axi clock\n");
435 break;
436 }
437
438 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
439 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
440 break;
441 case IMX6QP:
442 case IMX6Q:
443
444 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
445 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
446
447
448
449
450
451
452 usleep_range(10, 100);
453 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
454 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
455 break;
456 case IMX7D:
457 break;
458 case IMX8MQ:
459 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
460 if (ret) {
461 dev_err(dev, "unable to enable pcie_aux clock\n");
462 break;
463 }
464
465 offset = imx6_pcie_grp_offset(imx6_pcie);
466
467
468
469
470 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
471 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
472 0);
473 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
474 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
475 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
476 break;
477 }
478
479 return ret;
480}
481
482static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
483{
484 u32 val;
485 struct device *dev = imx6_pcie->pci->dev;
486
487 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
488 IOMUXC_GPR22, val,
489 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
490 PHY_PLL_LOCK_WAIT_USLEEP_MAX,
491 PHY_PLL_LOCK_WAIT_TIMEOUT))
492 dev_err(dev, "PCIe PLL lock timeout\n");
493}
494
495static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
496{
497 struct dw_pcie *pci = imx6_pcie->pci;
498 struct device *dev = pci->dev;
499 int ret;
500
501 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
502 ret = regulator_enable(imx6_pcie->vpcie);
503 if (ret) {
504 dev_err(dev, "failed to enable vpcie regulator: %d\n",
505 ret);
506 return;
507 }
508 }
509
510 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
511 if (ret) {
512 dev_err(dev, "unable to enable pcie_phy clock\n");
513 goto err_pcie_phy;
514 }
515
516 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
517 if (ret) {
518 dev_err(dev, "unable to enable pcie_bus clock\n");
519 goto err_pcie_bus;
520 }
521
522 ret = clk_prepare_enable(imx6_pcie->pcie);
523 if (ret) {
524 dev_err(dev, "unable to enable pcie clock\n");
525 goto err_pcie;
526 }
527
528 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
529 if (ret) {
530 dev_err(dev, "unable to enable pcie ref clock\n");
531 goto err_ref_clk;
532 }
533
534
535 usleep_range(200, 500);
536
537
538 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
539 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
540 imx6_pcie->gpio_active_high);
541 msleep(100);
542 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
543 !imx6_pcie->gpio_active_high);
544 }
545
546 switch (imx6_pcie->drvdata->variant) {
547 case IMX8MQ:
548 reset_control_deassert(imx6_pcie->pciephy_reset);
549 break;
550 case IMX7D:
551 reset_control_deassert(imx6_pcie->pciephy_reset);
552
553
554
555
556
557 if (likely(imx6_pcie->phy_base)) {
558
559 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
560 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
561
562 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
563 | PCIE_PHY_CMN_REG24_RX_EQ,
564 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
565
566 writel(PCIE_PHY_CMN_REG26_ATT_MODE,
567 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
568 } else {
569 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
570 }
571
572 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
573 break;
574 case IMX6SX:
575 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
576 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
577 break;
578 case IMX6QP:
579 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
580 IMX6Q_GPR1_PCIE_SW_RST, 0);
581
582 usleep_range(200, 500);
583 break;
584 case IMX6Q:
585 break;
586 }
587
588 return;
589
590err_ref_clk:
591 clk_disable_unprepare(imx6_pcie->pcie);
592err_pcie:
593 clk_disable_unprepare(imx6_pcie->pcie_bus);
594err_pcie_bus:
595 clk_disable_unprepare(imx6_pcie->pcie_phy);
596err_pcie_phy:
597 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
598 ret = regulator_disable(imx6_pcie->vpcie);
599 if (ret)
600 dev_err(dev, "failed to disable vpcie regulator: %d\n",
601 ret);
602 }
603}
604
605static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
606{
607 unsigned int mask, val;
608
609 if (imx6_pcie->drvdata->variant == IMX8MQ &&
610 imx6_pcie->controller_id == 1) {
611 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
612 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
613 PCI_EXP_TYPE_ROOT_PORT);
614 } else {
615 mask = IMX6Q_GPR12_DEVICE_TYPE;
616 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
617 PCI_EXP_TYPE_ROOT_PORT);
618 }
619
620 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
621}
622
623static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
624{
625 switch (imx6_pcie->drvdata->variant) {
626 case IMX8MQ:
627
628
629
630
631 regmap_update_bits(imx6_pcie->iomuxc_gpr,
632 imx6_pcie_grp_offset(imx6_pcie),
633 IMX8MQ_GPR_PCIE_REF_USE_PAD,
634 IMX8MQ_GPR_PCIE_REF_USE_PAD);
635 break;
636 case IMX7D:
637 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
638 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
639 break;
640 case IMX6SX:
641 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
642 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
643 IMX6SX_GPR12_PCIE_RX_EQ_2);
644
645 default:
646 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
647 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
648
649
650 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
651 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
652
653 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
654 IMX6Q_GPR8_TX_DEEMPH_GEN1,
655 imx6_pcie->tx_deemph_gen1 << 0);
656 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
657 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
658 imx6_pcie->tx_deemph_gen2_3p5db << 6);
659 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
660 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
661 imx6_pcie->tx_deemph_gen2_6db << 12);
662 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
663 IMX6Q_GPR8_TX_SWING_FULL,
664 imx6_pcie->tx_swing_full << 18);
665 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
666 IMX6Q_GPR8_TX_SWING_LOW,
667 imx6_pcie->tx_swing_low << 25);
668 break;
669 }
670
671 imx6_pcie_configure_type(imx6_pcie);
672}
673
674static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
675{
676 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
677 int mult, div;
678 u16 val;
679
680 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
681 return 0;
682
683 switch (phy_rate) {
684 case 125000000:
685
686
687
688
689 return 0;
690 case 100000000:
691 mult = 25;
692 div = 0;
693 break;
694 case 200000000:
695 mult = 25;
696 div = 1;
697 break;
698 default:
699 dev_err(imx6_pcie->pci->dev,
700 "Unsupported PHY reference clock rate %lu\n", phy_rate);
701 return -EINVAL;
702 }
703
704 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
705 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
706 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
707 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
708 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
709 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
710
711 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
712 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
713 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
714 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
715 val |= PCIE_PHY_ATEOVRD_EN;
716 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
717
718 return 0;
719}
720
721static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
722{
723 struct dw_pcie *pci = imx6_pcie->pci;
724 struct device *dev = pci->dev;
725 u32 tmp;
726 unsigned int retries;
727
728 for (retries = 0; retries < 200; retries++) {
729 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
730
731 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
732 return 0;
733 usleep_range(100, 1000);
734 }
735
736 dev_err(dev, "Speed change timeout\n");
737 return -ETIMEDOUT;
738}
739
740static void imx6_pcie_ltssm_enable(struct device *dev)
741{
742 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
743
744 switch (imx6_pcie->drvdata->variant) {
745 case IMX6Q:
746 case IMX6SX:
747 case IMX6QP:
748 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
749 IMX6Q_GPR12_PCIE_CTL_2,
750 IMX6Q_GPR12_PCIE_CTL_2);
751 break;
752 case IMX7D:
753 case IMX8MQ:
754 reset_control_deassert(imx6_pcie->apps_reset);
755 break;
756 }
757}
758
759static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
760{
761 struct dw_pcie *pci = imx6_pcie->pci;
762 struct device *dev = pci->dev;
763 u32 tmp;
764 int ret;
765
766
767
768
769
770
771 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
772 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
773 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
774 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
775
776
777 imx6_pcie_ltssm_enable(dev);
778
779 ret = dw_pcie_wait_for_link(pci);
780 if (ret)
781 goto err_reset_phy;
782
783 if (imx6_pcie->link_gen == 2) {
784
785 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
786 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
787 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
788 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
789
790
791
792
793
794 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
795 tmp |= PORT_LOGIC_SPEED_CHANGE;
796 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
797
798 if (imx6_pcie->drvdata->flags &
799 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
800
801
802
803
804
805
806
807
808
809 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
810 if (ret) {
811 dev_err(dev, "Failed to bring link up!\n");
812 goto err_reset_phy;
813 }
814 }
815
816
817 ret = dw_pcie_wait_for_link(pci);
818 if (ret) {
819 dev_err(dev, "Failed to bring link up!\n");
820 goto err_reset_phy;
821 }
822 } else {
823 dev_info(dev, "Link: Gen2 disabled\n");
824 }
825
826 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
827 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
828 return 0;
829
830err_reset_phy:
831 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
832 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
833 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
834 imx6_pcie_reset_phy(imx6_pcie);
835 return ret;
836}
837
838static int imx6_pcie_host_init(struct pcie_port *pp)
839{
840 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
841 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
842
843 imx6_pcie_assert_core_reset(imx6_pcie);
844 imx6_pcie_init_phy(imx6_pcie);
845 imx6_pcie_deassert_core_reset(imx6_pcie);
846 imx6_setup_phy_mpll(imx6_pcie);
847 dw_pcie_setup_rc(pp);
848 imx6_pcie_establish_link(imx6_pcie);
849
850 if (IS_ENABLED(CONFIG_PCI_MSI))
851 dw_pcie_msi_init(pp);
852
853 return 0;
854}
855
856static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
857 .host_init = imx6_pcie_host_init,
858};
859
860static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
861 struct platform_device *pdev)
862{
863 struct dw_pcie *pci = imx6_pcie->pci;
864 struct pcie_port *pp = &pci->pp;
865 struct device *dev = &pdev->dev;
866 int ret;
867
868 if (IS_ENABLED(CONFIG_PCI_MSI)) {
869 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
870 if (pp->msi_irq <= 0) {
871 dev_err(dev, "failed to get MSI irq\n");
872 return -ENODEV;
873 }
874 }
875
876 pp->ops = &imx6_pcie_host_ops;
877
878 ret = dw_pcie_host_init(pp);
879 if (ret) {
880 dev_err(dev, "failed to initialize host\n");
881 return ret;
882 }
883
884 return 0;
885}
886
887static const struct dw_pcie_ops dw_pcie_ops = {
888
889};
890
891#ifdef CONFIG_PM_SLEEP
892static void imx6_pcie_ltssm_disable(struct device *dev)
893{
894 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
895
896 switch (imx6_pcie->drvdata->variant) {
897 case IMX6SX:
898 case IMX6QP:
899 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
900 IMX6Q_GPR12_PCIE_CTL_2, 0);
901 break;
902 case IMX7D:
903 reset_control_assert(imx6_pcie->apps_reset);
904 break;
905 default:
906 dev_err(dev, "ltssm_disable not supported\n");
907 }
908}
909
910static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
911{
912 struct device *dev = imx6_pcie->pci->dev;
913
914
915 if (imx6_pcie->turnoff_reset) {
916 reset_control_assert(imx6_pcie->turnoff_reset);
917 reset_control_deassert(imx6_pcie->turnoff_reset);
918 goto pm_turnoff_sleep;
919 }
920
921
922 switch (imx6_pcie->drvdata->variant) {
923 case IMX6SX:
924 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
925 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
926 IMX6SX_GPR12_PCIE_PM_TURN_OFF);
927 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
928 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
929 break;
930 default:
931 dev_err(dev, "PME_Turn_Off not implemented\n");
932 return;
933 }
934
935
936
937
938
939
940
941
942pm_turnoff_sleep:
943 usleep_range(1000, 10000);
944}
945
946static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
947{
948 clk_disable_unprepare(imx6_pcie->pcie);
949 clk_disable_unprepare(imx6_pcie->pcie_phy);
950 clk_disable_unprepare(imx6_pcie->pcie_bus);
951
952 switch (imx6_pcie->drvdata->variant) {
953 case IMX6SX:
954 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
955 break;
956 case IMX7D:
957 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
958 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
959 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
960 break;
961 case IMX8MQ:
962 clk_disable_unprepare(imx6_pcie->pcie_aux);
963 break;
964 default:
965 break;
966 }
967}
968
969static int imx6_pcie_suspend_noirq(struct device *dev)
970{
971 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
972
973 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
974 return 0;
975
976 imx6_pcie_pm_turnoff(imx6_pcie);
977 imx6_pcie_clk_disable(imx6_pcie);
978 imx6_pcie_ltssm_disable(dev);
979
980 return 0;
981}
982
983static int imx6_pcie_resume_noirq(struct device *dev)
984{
985 int ret;
986 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
987 struct pcie_port *pp = &imx6_pcie->pci->pp;
988
989 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
990 return 0;
991
992 imx6_pcie_assert_core_reset(imx6_pcie);
993 imx6_pcie_init_phy(imx6_pcie);
994 imx6_pcie_deassert_core_reset(imx6_pcie);
995 dw_pcie_setup_rc(pp);
996
997 ret = imx6_pcie_establish_link(imx6_pcie);
998 if (ret < 0)
999 dev_info(dev, "pcie link is down after resume.\n");
1000
1001 return 0;
1002}
1003#endif
1004
1005static const struct dev_pm_ops imx6_pcie_pm_ops = {
1006 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
1007 imx6_pcie_resume_noirq)
1008};
1009
1010static int imx6_pcie_probe(struct platform_device *pdev)
1011{
1012 struct device *dev = &pdev->dev;
1013 struct dw_pcie *pci;
1014 struct imx6_pcie *imx6_pcie;
1015 struct device_node *np;
1016 struct resource *dbi_base;
1017 struct device_node *node = dev->of_node;
1018 int ret;
1019 u16 val;
1020
1021 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
1022 if (!imx6_pcie)
1023 return -ENOMEM;
1024
1025 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1026 if (!pci)
1027 return -ENOMEM;
1028
1029 pci->dev = dev;
1030 pci->ops = &dw_pcie_ops;
1031
1032 imx6_pcie->pci = pci;
1033 imx6_pcie->drvdata = of_device_get_match_data(dev);
1034
1035
1036 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1037 if (np) {
1038 struct resource res;
1039
1040 ret = of_address_to_resource(np, 0, &res);
1041 if (ret) {
1042 dev_err(dev, "Unable to map PCIe PHY\n");
1043 return ret;
1044 }
1045 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1046 if (IS_ERR(imx6_pcie->phy_base)) {
1047 dev_err(dev, "Unable to map PCIe PHY\n");
1048 return PTR_ERR(imx6_pcie->phy_base);
1049 }
1050 }
1051
1052 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
1054 if (IS_ERR(pci->dbi_base))
1055 return PTR_ERR(pci->dbi_base);
1056
1057
1058 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1059 imx6_pcie->gpio_active_high = of_property_read_bool(node,
1060 "reset-gpio-active-high");
1061 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1062 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1063 imx6_pcie->gpio_active_high ?
1064 GPIOF_OUT_INIT_HIGH :
1065 GPIOF_OUT_INIT_LOW,
1066 "PCIe reset");
1067 if (ret) {
1068 dev_err(dev, "unable to get reset gpio\n");
1069 return ret;
1070 }
1071 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1072 return imx6_pcie->reset_gpio;
1073 }
1074
1075
1076 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1077 if (IS_ERR(imx6_pcie->pcie_phy)) {
1078 dev_err(dev, "pcie_phy clock source missing or invalid\n");
1079 return PTR_ERR(imx6_pcie->pcie_phy);
1080 }
1081
1082 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1083 if (IS_ERR(imx6_pcie->pcie_bus)) {
1084 dev_err(dev, "pcie_bus clock source missing or invalid\n");
1085 return PTR_ERR(imx6_pcie->pcie_bus);
1086 }
1087
1088 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1089 if (IS_ERR(imx6_pcie->pcie)) {
1090 dev_err(dev, "pcie clock source missing or invalid\n");
1091 return PTR_ERR(imx6_pcie->pcie);
1092 }
1093
1094 switch (imx6_pcie->drvdata->variant) {
1095 case IMX6SX:
1096 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1097 "pcie_inbound_axi");
1098 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
1099 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
1100 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
1101 }
1102 break;
1103 case IMX8MQ:
1104 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1105 if (IS_ERR(imx6_pcie->pcie_aux)) {
1106 dev_err(dev, "pcie_aux clock source missing or invalid\n");
1107 return PTR_ERR(imx6_pcie->pcie_aux);
1108 }
1109
1110 case IMX7D:
1111 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1112 imx6_pcie->controller_id = 1;
1113
1114 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1115 "pciephy");
1116 if (IS_ERR(imx6_pcie->pciephy_reset)) {
1117 dev_err(dev, "Failed to get PCIEPHY reset control\n");
1118 return PTR_ERR(imx6_pcie->pciephy_reset);
1119 }
1120
1121 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1122 "apps");
1123 if (IS_ERR(imx6_pcie->apps_reset)) {
1124 dev_err(dev, "Failed to get PCIE APPS reset control\n");
1125 return PTR_ERR(imx6_pcie->apps_reset);
1126 }
1127 break;
1128 default:
1129 break;
1130 }
1131
1132
1133 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1134 if (IS_ERR(imx6_pcie->turnoff_reset)) {
1135 dev_err(dev, "Failed to get TURNOFF reset control\n");
1136 return PTR_ERR(imx6_pcie->turnoff_reset);
1137 }
1138
1139
1140 imx6_pcie->iomuxc_gpr =
1141 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1142 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1143 dev_err(dev, "unable to find iomuxc registers\n");
1144 return PTR_ERR(imx6_pcie->iomuxc_gpr);
1145 }
1146
1147
1148 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1149 &imx6_pcie->tx_deemph_gen1))
1150 imx6_pcie->tx_deemph_gen1 = 0;
1151
1152 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1153 &imx6_pcie->tx_deemph_gen2_3p5db))
1154 imx6_pcie->tx_deemph_gen2_3p5db = 0;
1155
1156 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1157 &imx6_pcie->tx_deemph_gen2_6db))
1158 imx6_pcie->tx_deemph_gen2_6db = 20;
1159
1160 if (of_property_read_u32(node, "fsl,tx-swing-full",
1161 &imx6_pcie->tx_swing_full))
1162 imx6_pcie->tx_swing_full = 127;
1163
1164 if (of_property_read_u32(node, "fsl,tx-swing-low",
1165 &imx6_pcie->tx_swing_low))
1166 imx6_pcie->tx_swing_low = 127;
1167
1168
1169 ret = of_property_read_u32(node, "fsl,max-link-speed",
1170 &imx6_pcie->link_gen);
1171 if (ret)
1172 imx6_pcie->link_gen = 1;
1173
1174 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1175 if (IS_ERR(imx6_pcie->vpcie)) {
1176 if (PTR_ERR(imx6_pcie->vpcie) == -EPROBE_DEFER)
1177 return -EPROBE_DEFER;
1178 imx6_pcie->vpcie = NULL;
1179 }
1180
1181 platform_set_drvdata(pdev, imx6_pcie);
1182
1183 ret = imx6_pcie_attach_pd(dev);
1184 if (ret)
1185 return ret;
1186
1187 ret = imx6_add_pcie_port(imx6_pcie, pdev);
1188 if (ret < 0)
1189 return ret;
1190
1191 if (pci_msi_enabled()) {
1192 val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP +
1193 PCI_MSI_FLAGS);
1194 val |= PCI_MSI_FLAGS_ENABLE;
1195 dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP + PCI_MSI_FLAGS,
1196 val);
1197 }
1198
1199 return 0;
1200}
1201
1202static void imx6_pcie_shutdown(struct platform_device *pdev)
1203{
1204 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1205
1206
1207 imx6_pcie_assert_core_reset(imx6_pcie);
1208}
1209
1210static const struct imx6_pcie_drvdata drvdata[] = {
1211 [IMX6Q] = {
1212 .variant = IMX6Q,
1213 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1214 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1215 },
1216 [IMX6SX] = {
1217 .variant = IMX6SX,
1218 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1219 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1220 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1221 },
1222 [IMX6QP] = {
1223 .variant = IMX6QP,
1224 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1225 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1226 },
1227 [IMX7D] = {
1228 .variant = IMX7D,
1229 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1230 },
1231 [IMX8MQ] = {
1232 .variant = IMX8MQ,
1233 },
1234};
1235
1236static const struct of_device_id imx6_pcie_of_match[] = {
1237 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1238 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1239 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1240 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1241 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1242 {},
1243};
1244
1245static struct platform_driver imx6_pcie_driver = {
1246 .driver = {
1247 .name = "imx6q-pcie",
1248 .of_match_table = imx6_pcie_of_match,
1249 .suppress_bind_attrs = true,
1250 .pm = &imx6_pcie_pm_ops,
1251 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1252 },
1253 .probe = imx6_pcie_probe,
1254 .shutdown = imx6_pcie_shutdown,
1255};
1256
1257static int __init imx6_pcie_init(void)
1258{
1259#ifdef CONFIG_ARM
1260
1261
1262
1263
1264
1265
1266
1267 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1268 "external abort on non-linefetch");
1269#endif
1270
1271 return platform_driver_register(&imx6_pcie_driver);
1272}
1273device_initcall(imx6_pcie_init);
1274
