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11#include <linux/delay.h>
12#include <linux/of.h>
13#include <linux/types.h>
14
15#include "pcie-designware.h"
16
17int dw_pcie_read(void __iomem *addr, int size, u32 *val)
18{
19 if (!IS_ALIGNED((uintptr_t)addr, size)) {
20 *val = 0;
21 return PCIBIOS_BAD_REGISTER_NUMBER;
22 }
23
24 if (size == 4) {
25 *val = readl(addr);
26 } else if (size == 2) {
27 *val = readw(addr);
28 } else if (size == 1) {
29 *val = readb(addr);
30 } else {
31 *val = 0;
32 return PCIBIOS_BAD_REGISTER_NUMBER;
33 }
34
35 return PCIBIOS_SUCCESSFUL;
36}
37EXPORT_SYMBOL_GPL(dw_pcie_read);
38
39int dw_pcie_write(void __iomem *addr, int size, u32 val)
40{
41 if (!IS_ALIGNED((uintptr_t)addr, size))
42 return PCIBIOS_BAD_REGISTER_NUMBER;
43
44 if (size == 4)
45 writel(val, addr);
46 else if (size == 2)
47 writew(val, addr);
48 else if (size == 1)
49 writeb(val, addr);
50 else
51 return PCIBIOS_BAD_REGISTER_NUMBER;
52
53 return PCIBIOS_SUCCESSFUL;
54}
55EXPORT_SYMBOL_GPL(dw_pcie_write);
56
57u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
58{
59 int ret;
60 u32 val;
61
62 if (pci->ops->read_dbi)
63 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
64
65 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
66 if (ret)
67 dev_err(pci->dev, "Read DBI address failed\n");
68
69 return val;
70}
71EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
72
73void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
74{
75 int ret;
76
77 if (pci->ops->write_dbi) {
78 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
79 return;
80 }
81
82 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
83 if (ret)
84 dev_err(pci->dev, "Write DBI address failed\n");
85}
86EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
87
88u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size)
89{
90 int ret;
91 u32 val;
92
93 if (pci->ops->read_dbi2)
94 return pci->ops->read_dbi2(pci, pci->dbi_base2, reg, size);
95
96 ret = dw_pcie_read(pci->dbi_base2 + reg, size, &val);
97 if (ret)
98 dev_err(pci->dev, "read DBI address failed\n");
99
100 return val;
101}
102
103void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
104{
105 int ret;
106
107 if (pci->ops->write_dbi2) {
108 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
109 return;
110 }
111
112 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
113 if (ret)
114 dev_err(pci->dev, "write DBI address failed\n");
115}
116
117u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size)
118{
119 int ret;
120 u32 val;
121
122 if (pci->ops->read_dbi)
123 return pci->ops->read_dbi(pci, pci->atu_base, reg, size);
124
125 ret = dw_pcie_read(pci->atu_base + reg, size, &val);
126 if (ret)
127 dev_err(pci->dev, "Read ATU address failed\n");
128
129 return val;
130}
131
132void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
133{
134 int ret;
135
136 if (pci->ops->write_dbi) {
137 pci->ops->write_dbi(pci, pci->atu_base, reg, size, val);
138 return;
139 }
140
141 ret = dw_pcie_write(pci->atu_base + reg, size, val);
142 if (ret)
143 dev_err(pci->dev, "Write ATU address failed\n");
144}
145
146static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
147{
148 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
149
150 return dw_pcie_readl_atu(pci, offset + reg);
151}
152
153static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
154 u32 val)
155{
156 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
157
158 dw_pcie_writel_atu(pci, offset + reg, val);
159}
160
161static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
162 int type, u64 cpu_addr,
163 u64 pci_addr, u32 size)
164{
165 u32 retries, val;
166
167 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
168 lower_32_bits(cpu_addr));
169 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
170 upper_32_bits(cpu_addr));
171 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
172 lower_32_bits(cpu_addr + size - 1));
173 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
174 lower_32_bits(pci_addr));
175 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
176 upper_32_bits(pci_addr));
177 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
178 type);
179 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
180 PCIE_ATU_ENABLE);
181
182
183
184
185
186 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
187 val = dw_pcie_readl_ob_unroll(pci, index,
188 PCIE_ATU_UNR_REGION_CTRL2);
189 if (val & PCIE_ATU_ENABLE)
190 return;
191
192 mdelay(LINK_WAIT_IATU);
193 }
194 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
195}
196
197void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
198 u64 cpu_addr, u64 pci_addr, u32 size)
199{
200 u32 retries, val;
201
202 if (pci->ops->cpu_addr_fixup)
203 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
204
205 if (pci->iatu_unroll_enabled) {
206 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
207 pci_addr, size);
208 return;
209 }
210
211 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
212 PCIE_ATU_REGION_OUTBOUND | index);
213 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
214 lower_32_bits(cpu_addr));
215 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
216 upper_32_bits(cpu_addr));
217 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
218 lower_32_bits(cpu_addr + size - 1));
219 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
220 lower_32_bits(pci_addr));
221 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
222 upper_32_bits(pci_addr));
223 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
224 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
225
226
227
228
229
230 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
231 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
232 if (val & PCIE_ATU_ENABLE)
233 return;
234
235 mdelay(LINK_WAIT_IATU);
236 }
237 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
238}
239
240static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
241{
242 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
243
244 return dw_pcie_readl_atu(pci, offset + reg);
245}
246
247static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
248 u32 val)
249{
250 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
251
252 dw_pcie_writel_atu(pci, offset + reg, val);
253}
254
255static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
256 int bar, u64 cpu_addr,
257 enum dw_pcie_as_type as_type)
258{
259 int type;
260 u32 retries, val;
261
262 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
263 lower_32_bits(cpu_addr));
264 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
265 upper_32_bits(cpu_addr));
266
267 switch (as_type) {
268 case DW_PCIE_AS_MEM:
269 type = PCIE_ATU_TYPE_MEM;
270 break;
271 case DW_PCIE_AS_IO:
272 type = PCIE_ATU_TYPE_IO;
273 break;
274 default:
275 return -EINVAL;
276 }
277
278 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
279 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
280 PCIE_ATU_ENABLE |
281 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
282
283
284
285
286
287 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
288 val = dw_pcie_readl_ib_unroll(pci, index,
289 PCIE_ATU_UNR_REGION_CTRL2);
290 if (val & PCIE_ATU_ENABLE)
291 return 0;
292
293 mdelay(LINK_WAIT_IATU);
294 }
295 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
296
297 return -EBUSY;
298}
299
300int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
301 u64 cpu_addr, enum dw_pcie_as_type as_type)
302{
303 int type;
304 u32 retries, val;
305
306 if (pci->iatu_unroll_enabled)
307 return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
308 cpu_addr, as_type);
309
310 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
311 index);
312 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
313 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
314
315 switch (as_type) {
316 case DW_PCIE_AS_MEM:
317 type = PCIE_ATU_TYPE_MEM;
318 break;
319 case DW_PCIE_AS_IO:
320 type = PCIE_ATU_TYPE_IO;
321 break;
322 default:
323 return -EINVAL;
324 }
325
326 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
327 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
328 | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
329
330
331
332
333
334 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
335 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
336 if (val & PCIE_ATU_ENABLE)
337 return 0;
338
339 mdelay(LINK_WAIT_IATU);
340 }
341 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
342
343 return -EBUSY;
344}
345
346void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
347 enum dw_pcie_region_type type)
348{
349 int region;
350
351 switch (type) {
352 case DW_PCIE_REGION_INBOUND:
353 region = PCIE_ATU_REGION_INBOUND;
354 break;
355 case DW_PCIE_REGION_OUTBOUND:
356 region = PCIE_ATU_REGION_OUTBOUND;
357 break;
358 default:
359 return;
360 }
361
362 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
363 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, (u32)~PCIE_ATU_ENABLE);
364}
365
366int dw_pcie_wait_for_link(struct dw_pcie *pci)
367{
368 int retries;
369
370
371 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
372 if (dw_pcie_link_up(pci)) {
373 dev_info(pci->dev, "Link up\n");
374 return 0;
375 }
376 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
377 }
378
379 dev_err(pci->dev, "Phy link never came up\n");
380
381 return -ETIMEDOUT;
382}
383
384int dw_pcie_link_up(struct dw_pcie *pci)
385{
386 u32 val;
387
388 if (pci->ops->link_up)
389 return pci->ops->link_up(pci);
390
391 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
392 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
393 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
394}
395
396static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
397{
398 u32 val;
399
400 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
401 if (val == 0xffffffff)
402 return 1;
403
404 return 0;
405}
406
407void dw_pcie_setup(struct dw_pcie *pci)
408{
409 int ret;
410 u32 val;
411 u32 lanes;
412 struct device *dev = pci->dev;
413 struct device_node *np = dev->of_node;
414
415 if (pci->version >= 0x480A || (!pci->version &&
416 dw_pcie_iatu_unroll_enabled(pci))) {
417 pci->iatu_unroll_enabled = true;
418 if (!pci->atu_base)
419 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
420 }
421 dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
422 "enabled" : "disabled");
423
424
425 ret = of_property_read_u32(np, "num-lanes", &lanes);
426 if (ret)
427 lanes = 0;
428
429
430 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
431 val &= ~PORT_LINK_MODE_MASK;
432 switch (lanes) {
433 case 1:
434 val |= PORT_LINK_MODE_1_LANES;
435 break;
436 case 2:
437 val |= PORT_LINK_MODE_2_LANES;
438 break;
439 case 4:
440 val |= PORT_LINK_MODE_4_LANES;
441 break;
442 case 8:
443 val |= PORT_LINK_MODE_8_LANES;
444 break;
445 default:
446 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
447 return;
448 }
449 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
450
451
452 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
453 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
454 switch (lanes) {
455 case 1:
456 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
457 break;
458 case 2:
459 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
460 break;
461 case 4:
462 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
463 break;
464 case 8:
465 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
466 break;
467 }
468 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
469}
470
