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9#include <linux/acpi.h>
10#include <linux/bitops.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/property.h>
20#include <linux/seq_file.h>
21
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinconf-generic.h>
26
27#include "pinctrl-intel.h"
28
29
30#define BYT_CONF0_REG 0x000
31#define BYT_CONF1_REG 0x004
32#define BYT_VAL_REG 0x008
33#define BYT_DFT_REG 0x00c
34#define BYT_INT_STAT_REG 0x800
35#define BYT_DEBOUNCE_REG 0x9d0
36
37
38#define BYT_IODEN BIT(31)
39#define BYT_DIRECT_IRQ_EN BIT(27)
40#define BYT_TRIG_MASK GENMASK(26, 24)
41#define BYT_TRIG_NEG BIT(26)
42#define BYT_TRIG_POS BIT(25)
43#define BYT_TRIG_LVL BIT(24)
44#define BYT_DEBOUNCE_EN BIT(20)
45#define BYT_GLITCH_FILTER_EN BIT(19)
46#define BYT_GLITCH_F_SLOW_CLK BIT(17)
47#define BYT_GLITCH_F_FAST_CLK BIT(16)
48#define BYT_PULL_STR_SHIFT 9
49#define BYT_PULL_STR_MASK GENMASK(10, 9)
50#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
51#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
52#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
53#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
54#define BYT_PULL_ASSIGN_SHIFT 7
55#define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
56#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
57#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
58#define BYT_PIN_MUX GENMASK(2, 0)
59
60
61#define BYT_DIR_MASK GENMASK(2, 1)
62#define BYT_INPUT_EN BIT(2)
63#define BYT_OUTPUT_EN BIT(1)
64#define BYT_LEVEL BIT(0)
65
66#define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
67#define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
68
69
70#define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
71#define BYT_DEBOUNCE_PULSE_375US 1
72#define BYT_DEBOUNCE_PULSE_750US 2
73#define BYT_DEBOUNCE_PULSE_1500US 3
74#define BYT_DEBOUNCE_PULSE_3MS 4
75#define BYT_DEBOUNCE_PULSE_6MS 5
76#define BYT_DEBOUNCE_PULSE_12MS 6
77#define BYT_DEBOUNCE_PULSE_24MS 7
78
79#define BYT_NGPIO_SCORE 102
80#define BYT_NGPIO_NCORE 28
81#define BYT_NGPIO_SUS 44
82
83#define BYT_SCORE_ACPI_UID "1"
84#define BYT_NCORE_ACPI_UID "2"
85#define BYT_SUS_ACPI_UID "3"
86
87
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90
91
92
93#define BYT_DEFAULT_GPIO_MUX 0
94#define BYT_ALTER_GPIO_MUX 1
95
96struct byt_gpio_pin_context {
97 u32 conf0;
98 u32 val;
99};
100
101struct byt_community {
102 unsigned int pin_base;
103 size_t npins;
104 const unsigned int *pad_map;
105 void __iomem *reg_base;
106};
107
108#define COMMUNITY(p, n, map) \
109 { \
110 .pin_base = (p), \
111 .npins = (n), \
112 .pad_map = (map),\
113 }
114
115struct byt_pinctrl_soc_data {
116 const char *uid;
117 const struct pinctrl_pin_desc *pins;
118 size_t npins;
119 const struct intel_pingroup *groups;
120 size_t ngroups;
121 const struct intel_function *functions;
122 size_t nfunctions;
123 const struct byt_community *communities;
124 size_t ncommunities;
125};
126
127struct byt_gpio {
128 struct gpio_chip chip;
129 struct platform_device *pdev;
130 struct pinctrl_dev *pctl_dev;
131 struct pinctrl_desc pctl_desc;
132 raw_spinlock_t lock;
133 const struct byt_pinctrl_soc_data *soc_data;
134 struct byt_community *communities_copy;
135 struct byt_gpio_pin_context *saved_context;
136};
137
138
139static const struct pinctrl_pin_desc byt_score_pins[] = {
140 PINCTRL_PIN(0, "SATA_GP0"),
141 PINCTRL_PIN(1, "SATA_GP1"),
142 PINCTRL_PIN(2, "SATA_LED#"),
143 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
144 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
145 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
146 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
147 PINCTRL_PIN(7, "SD3_WP"),
148 PINCTRL_PIN(8, "HDA_RST"),
149 PINCTRL_PIN(9, "HDA_SYNC"),
150 PINCTRL_PIN(10, "HDA_CLK"),
151 PINCTRL_PIN(11, "HDA_SDO"),
152 PINCTRL_PIN(12, "HDA_SDI0"),
153 PINCTRL_PIN(13, "HDA_SDI1"),
154 PINCTRL_PIN(14, "GPIO_S0_SC14"),
155 PINCTRL_PIN(15, "GPIO_S0_SC15"),
156 PINCTRL_PIN(16, "MMC1_CLK"),
157 PINCTRL_PIN(17, "MMC1_D0"),
158 PINCTRL_PIN(18, "MMC1_D1"),
159 PINCTRL_PIN(19, "MMC1_D2"),
160 PINCTRL_PIN(20, "MMC1_D3"),
161 PINCTRL_PIN(21, "MMC1_D4"),
162 PINCTRL_PIN(22, "MMC1_D5"),
163 PINCTRL_PIN(23, "MMC1_D6"),
164 PINCTRL_PIN(24, "MMC1_D7"),
165 PINCTRL_PIN(25, "MMC1_CMD"),
166 PINCTRL_PIN(26, "MMC1_RST"),
167 PINCTRL_PIN(27, "SD2_CLK"),
168 PINCTRL_PIN(28, "SD2_D0"),
169 PINCTRL_PIN(29, "SD2_D1"),
170 PINCTRL_PIN(30, "SD2_D2"),
171 PINCTRL_PIN(31, "SD2_D3_CD"),
172 PINCTRL_PIN(32, "SD2_CMD"),
173 PINCTRL_PIN(33, "SD3_CLK"),
174 PINCTRL_PIN(34, "SD3_D0"),
175 PINCTRL_PIN(35, "SD3_D1"),
176 PINCTRL_PIN(36, "SD3_D2"),
177 PINCTRL_PIN(37, "SD3_D3"),
178 PINCTRL_PIN(38, "SD3_CD"),
179 PINCTRL_PIN(39, "SD3_CMD"),
180 PINCTRL_PIN(40, "SD3_1P8EN"),
181 PINCTRL_PIN(41, "SD3_PWREN#"),
182 PINCTRL_PIN(42, "ILB_LPC_AD0"),
183 PINCTRL_PIN(43, "ILB_LPC_AD1"),
184 PINCTRL_PIN(44, "ILB_LPC_AD2"),
185 PINCTRL_PIN(45, "ILB_LPC_AD3"),
186 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
187 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
188 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
189 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
190 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
191 PINCTRL_PIN(51, "PCU_SMB_DATA"),
192 PINCTRL_PIN(52, "PCU_SMB_CLK"),
193 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
194 PINCTRL_PIN(54, "ILB_8254_SPKR"),
195 PINCTRL_PIN(55, "GPIO_S0_SC55"),
196 PINCTRL_PIN(56, "GPIO_S0_SC56"),
197 PINCTRL_PIN(57, "GPIO_S0_SC57"),
198 PINCTRL_PIN(58, "GPIO_S0_SC58"),
199 PINCTRL_PIN(59, "GPIO_S0_SC59"),
200 PINCTRL_PIN(60, "GPIO_S0_SC60"),
201 PINCTRL_PIN(61, "GPIO_S0_SC61"),
202 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
203 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
204 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
205 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
206 PINCTRL_PIN(66, "SIO_SPI_CS"),
207 PINCTRL_PIN(67, "SIO_SPI_MISO"),
208 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
209 PINCTRL_PIN(69, "SIO_SPI_CLK"),
210 PINCTRL_PIN(70, "SIO_UART1_RXD"),
211 PINCTRL_PIN(71, "SIO_UART1_TXD"),
212 PINCTRL_PIN(72, "SIO_UART1_RTS"),
213 PINCTRL_PIN(73, "SIO_UART1_CTS"),
214 PINCTRL_PIN(74, "SIO_UART2_RXD"),
215 PINCTRL_PIN(75, "SIO_UART2_TXD"),
216 PINCTRL_PIN(76, "SIO_UART2_RTS"),
217 PINCTRL_PIN(77, "SIO_UART2_CTS"),
218 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
219 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
220 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
221 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
222 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
223 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
224 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
225 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
226 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
227 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
228 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
229 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
230 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
231 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
232 PINCTRL_PIN(92, "GPIO_S0_SC92"),
233 PINCTRL_PIN(93, "GPIO_S0_SC93"),
234 PINCTRL_PIN(94, "SIO_PWM0"),
235 PINCTRL_PIN(95, "SIO_PWM1"),
236 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
237 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
238 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
239 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
240 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
241 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
242};
243
244static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
245 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
246 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
247 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
248 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
249 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
250 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
251 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
252 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
253 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
254 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
255 97, 100,
256};
257
258
259static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
260static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
261
262static const unsigned int byt_score_pwm0_pins[] = { 94 };
263static const unsigned int byt_score_pwm1_pins[] = { 95 };
264
265static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
266
267static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
268static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
269static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
270static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
271static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
272static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
273static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
274
275static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
276static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
277static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
278
279static const unsigned int byt_score_sdcard_pins[] = {
280 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
281};
282static const unsigned int byt_score_sdcard_mux_values[] = {
283 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
284};
285
286static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
287
288static const unsigned int byt_score_emmc_pins[] = {
289 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
290};
291
292static const unsigned int byt_score_ilb_lpc_pins[] = {
293 42, 43, 44, 45, 46, 47, 48, 49, 50,
294};
295
296static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
297
298static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
299static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
300static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
301static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
302static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
303static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
304
305static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
306
307static const struct intel_pingroup byt_score_groups[] = {
308 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
309 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
310 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
311 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
312 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
313 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
314 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
315 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
316 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
317 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
318 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
319 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
320 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
321 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
322 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
323 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
324 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
325 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
326 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
327 PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
328 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
329 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
330 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
331 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
332 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
333 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
334 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
335};
336
337static const char * const byt_score_uart_groups[] = {
338 "uart1_grp", "uart2_grp",
339};
340static const char * const byt_score_pwm_groups[] = {
341 "pwm0_grp", "pwm1_grp",
342};
343static const char * const byt_score_ssp_groups[] = {
344 "ssp0_grp", "ssp1_grp", "ssp2_grp",
345};
346static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
347static const char * const byt_score_i2c_groups[] = {
348 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
349 "i2c6_grp",
350};
351static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
352static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
353static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
354static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
355static const char * const byt_score_sata_groups[] = { "sata_grp" };
356static const char * const byt_score_plt_clk_groups[] = {
357 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
358 "plt_clk4_grp", "plt_clk5_grp",
359};
360static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
361static const char * const byt_score_gpio_groups[] = {
362 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
363 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
364 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
365 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
366 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
367 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
368};
369
370static const struct intel_function byt_score_functions[] = {
371 FUNCTION("uart", byt_score_uart_groups),
372 FUNCTION("pwm", byt_score_pwm_groups),
373 FUNCTION("ssp", byt_score_ssp_groups),
374 FUNCTION("spi", byt_score_spi_groups),
375 FUNCTION("i2c", byt_score_i2c_groups),
376 FUNCTION("sdcard", byt_score_sdcard_groups),
377 FUNCTION("sdio", byt_score_sdio_groups),
378 FUNCTION("emmc", byt_score_emmc_groups),
379 FUNCTION("lpc", byt_score_lpc_groups),
380 FUNCTION("sata", byt_score_sata_groups),
381 FUNCTION("plt_clk", byt_score_plt_clk_groups),
382 FUNCTION("smbus", byt_score_smbus_groups),
383 FUNCTION("gpio", byt_score_gpio_groups),
384};
385
386static const struct byt_community byt_score_communities[] = {
387 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
388};
389
390static const struct byt_pinctrl_soc_data byt_score_soc_data = {
391 .uid = BYT_SCORE_ACPI_UID,
392 .pins = byt_score_pins,
393 .npins = ARRAY_SIZE(byt_score_pins),
394 .groups = byt_score_groups,
395 .ngroups = ARRAY_SIZE(byt_score_groups),
396 .functions = byt_score_functions,
397 .nfunctions = ARRAY_SIZE(byt_score_functions),
398 .communities = byt_score_communities,
399 .ncommunities = ARRAY_SIZE(byt_score_communities),
400};
401
402
403static const struct pinctrl_pin_desc byt_sus_pins[] = {
404 PINCTRL_PIN(0, "GPIO_S50"),
405 PINCTRL_PIN(1, "GPIO_S51"),
406 PINCTRL_PIN(2, "GPIO_S52"),
407 PINCTRL_PIN(3, "GPIO_S53"),
408 PINCTRL_PIN(4, "GPIO_S54"),
409 PINCTRL_PIN(5, "GPIO_S55"),
410 PINCTRL_PIN(6, "GPIO_S56"),
411 PINCTRL_PIN(7, "GPIO_S57"),
412 PINCTRL_PIN(8, "GPIO_S58"),
413 PINCTRL_PIN(9, "GPIO_S59"),
414 PINCTRL_PIN(10, "GPIO_S510"),
415 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
416 PINCTRL_PIN(12, "PMC_SUSCLK0"),
417 PINCTRL_PIN(13, "GPIO_S513"),
418 PINCTRL_PIN(14, "USB_ULPI_RST"),
419 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
420 PINCTRL_PIN(16, "PMC_PWRBTN"),
421 PINCTRL_PIN(17, "GPIO_S517"),
422 PINCTRL_PIN(18, "PMC_SUS_STAT"),
423 PINCTRL_PIN(19, "USB_OC0"),
424 PINCTRL_PIN(20, "USB_OC1"),
425 PINCTRL_PIN(21, "PCU_SPI_CS1"),
426 PINCTRL_PIN(22, "GPIO_S522"),
427 PINCTRL_PIN(23, "GPIO_S523"),
428 PINCTRL_PIN(24, "GPIO_S524"),
429 PINCTRL_PIN(25, "GPIO_S525"),
430 PINCTRL_PIN(26, "GPIO_S526"),
431 PINCTRL_PIN(27, "GPIO_S527"),
432 PINCTRL_PIN(28, "GPIO_S528"),
433 PINCTRL_PIN(29, "GPIO_S529"),
434 PINCTRL_PIN(30, "GPIO_S530"),
435 PINCTRL_PIN(31, "USB_ULPI_CLK"),
436 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
437 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
438 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
439 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
440 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
441 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
442 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
443 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
444 PINCTRL_PIN(40, "USB_ULPI_DIR"),
445 PINCTRL_PIN(41, "USB_ULPI_NXT"),
446 PINCTRL_PIN(42, "USB_ULPI_STP"),
447 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
448};
449
450static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
451 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
452 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
453 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
454 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
455 52, 53, 59, 40,
456};
457
458static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
459static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
460static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
461
462static const unsigned int byt_sus_usb_ulpi_pins[] = {
463 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
464};
465static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
466 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
467};
468static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
469 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
470};
471
472static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
473static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
474static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
475
476static const struct intel_pingroup byt_sus_groups[] = {
477 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
478 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
479 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
480 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
481 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
482 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
483};
484
485static const char * const byt_sus_usb_groups[] = {
486 "usb_oc_grp", "usb_ulpi_grp",
487};
488static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
489static const char * const byt_sus_gpio_groups[] = {
490 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
491};
492
493static const struct intel_function byt_sus_functions[] = {
494 FUNCTION("usb", byt_sus_usb_groups),
495 FUNCTION("spi", byt_sus_spi_groups),
496 FUNCTION("gpio", byt_sus_gpio_groups),
497};
498
499static const struct byt_community byt_sus_communities[] = {
500 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
501};
502
503static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
504 .uid = BYT_SUS_ACPI_UID,
505 .pins = byt_sus_pins,
506 .npins = ARRAY_SIZE(byt_sus_pins),
507 .groups = byt_sus_groups,
508 .ngroups = ARRAY_SIZE(byt_sus_groups),
509 .functions = byt_sus_functions,
510 .nfunctions = ARRAY_SIZE(byt_sus_functions),
511 .communities = byt_sus_communities,
512 .ncommunities = ARRAY_SIZE(byt_sus_communities),
513};
514
515static const struct pinctrl_pin_desc byt_ncore_pins[] = {
516 PINCTRL_PIN(0, "GPIO_NCORE0"),
517 PINCTRL_PIN(1, "GPIO_NCORE1"),
518 PINCTRL_PIN(2, "GPIO_NCORE2"),
519 PINCTRL_PIN(3, "GPIO_NCORE3"),
520 PINCTRL_PIN(4, "GPIO_NCORE4"),
521 PINCTRL_PIN(5, "GPIO_NCORE5"),
522 PINCTRL_PIN(6, "GPIO_NCORE6"),
523 PINCTRL_PIN(7, "GPIO_NCORE7"),
524 PINCTRL_PIN(8, "GPIO_NCORE8"),
525 PINCTRL_PIN(9, "GPIO_NCORE9"),
526 PINCTRL_PIN(10, "GPIO_NCORE10"),
527 PINCTRL_PIN(11, "GPIO_NCORE11"),
528 PINCTRL_PIN(12, "GPIO_NCORE12"),
529 PINCTRL_PIN(13, "GPIO_NCORE13"),
530 PINCTRL_PIN(14, "GPIO_NCORE14"),
531 PINCTRL_PIN(15, "GPIO_NCORE15"),
532 PINCTRL_PIN(16, "GPIO_NCORE16"),
533 PINCTRL_PIN(17, "GPIO_NCORE17"),
534 PINCTRL_PIN(18, "GPIO_NCORE18"),
535 PINCTRL_PIN(19, "GPIO_NCORE19"),
536 PINCTRL_PIN(20, "GPIO_NCORE20"),
537 PINCTRL_PIN(21, "GPIO_NCORE21"),
538 PINCTRL_PIN(22, "GPIO_NCORE22"),
539 PINCTRL_PIN(23, "GPIO_NCORE23"),
540 PINCTRL_PIN(24, "GPIO_NCORE24"),
541 PINCTRL_PIN(25, "GPIO_NCORE25"),
542 PINCTRL_PIN(26, "GPIO_NCORE26"),
543 PINCTRL_PIN(27, "GPIO_NCORE27"),
544};
545
546static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
547 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
548 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
549 3, 6, 10, 13, 2, 5, 9, 7,
550};
551
552static const struct byt_community byt_ncore_communities[] = {
553 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
554};
555
556static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
557 .uid = BYT_NCORE_ACPI_UID,
558 .pins = byt_ncore_pins,
559 .npins = ARRAY_SIZE(byt_ncore_pins),
560 .communities = byt_ncore_communities,
561 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
562};
563
564static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
565 &byt_score_soc_data,
566 &byt_sus_soc_data,
567 &byt_ncore_soc_data,
568 NULL
569};
570
571static struct byt_community *byt_get_community(struct byt_gpio *vg,
572 unsigned int pin)
573{
574 struct byt_community *comm;
575 int i;
576
577 for (i = 0; i < vg->soc_data->ncommunities; i++) {
578 comm = vg->communities_copy + i;
579 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
580 return comm;
581 }
582
583 return NULL;
584}
585
586static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
587 int reg)
588{
589 struct byt_community *comm = byt_get_community(vg, offset);
590 u32 reg_offset;
591
592 if (!comm)
593 return NULL;
594
595 offset -= comm->pin_base;
596 switch (reg) {
597 case BYT_INT_STAT_REG:
598 reg_offset = (offset / 32) * 4;
599 break;
600 case BYT_DEBOUNCE_REG:
601 reg_offset = 0;
602 break;
603 default:
604 reg_offset = comm->pad_map[offset] * 16;
605 break;
606 }
607
608 return comm->reg_base + reg_offset + reg;
609}
610
611static int byt_get_groups_count(struct pinctrl_dev *pctldev)
612{
613 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
614
615 return vg->soc_data->ngroups;
616}
617
618static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
619 unsigned int selector)
620{
621 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
622
623 return vg->soc_data->groups[selector].name;
624}
625
626static int byt_get_group_pins(struct pinctrl_dev *pctldev,
627 unsigned int selector,
628 const unsigned int **pins,
629 unsigned int *num_pins)
630{
631 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
632
633 *pins = vg->soc_data->groups[selector].pins;
634 *num_pins = vg->soc_data->groups[selector].npins;
635
636 return 0;
637}
638
639static const struct pinctrl_ops byt_pinctrl_ops = {
640 .get_groups_count = byt_get_groups_count,
641 .get_group_name = byt_get_group_name,
642 .get_group_pins = byt_get_group_pins,
643};
644
645static int byt_get_functions_count(struct pinctrl_dev *pctldev)
646{
647 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
648
649 return vg->soc_data->nfunctions;
650}
651
652static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
653 unsigned int selector)
654{
655 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
656
657 return vg->soc_data->functions[selector].name;
658}
659
660static int byt_get_function_groups(struct pinctrl_dev *pctldev,
661 unsigned int selector,
662 const char * const **groups,
663 unsigned int *num_groups)
664{
665 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
666
667 *groups = vg->soc_data->functions[selector].groups;
668 *num_groups = vg->soc_data->functions[selector].ngroups;
669
670 return 0;
671}
672
673static void byt_set_group_simple_mux(struct byt_gpio *vg,
674 const struct intel_pingroup group,
675 unsigned int func)
676{
677 unsigned long flags;
678 int i;
679
680 raw_spin_lock_irqsave(&vg->lock, flags);
681
682 for (i = 0; i < group.npins; i++) {
683 void __iomem *padcfg0;
684 u32 value;
685
686 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
687 if (!padcfg0) {
688 dev_warn(&vg->pdev->dev,
689 "Group %s, pin %i not muxed (no padcfg0)\n",
690 group.name, i);
691 continue;
692 }
693
694 value = readl(padcfg0);
695 value &= ~BYT_PIN_MUX;
696 value |= func;
697 writel(value, padcfg0);
698 }
699
700 raw_spin_unlock_irqrestore(&vg->lock, flags);
701}
702
703static void byt_set_group_mixed_mux(struct byt_gpio *vg,
704 const struct intel_pingroup group,
705 const unsigned int *func)
706{
707 unsigned long flags;
708 int i;
709
710 raw_spin_lock_irqsave(&vg->lock, flags);
711
712 for (i = 0; i < group.npins; i++) {
713 void __iomem *padcfg0;
714 u32 value;
715
716 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
717 if (!padcfg0) {
718 dev_warn(&vg->pdev->dev,
719 "Group %s, pin %i not muxed (no padcfg0)\n",
720 group.name, i);
721 continue;
722 }
723
724 value = readl(padcfg0);
725 value &= ~BYT_PIN_MUX;
726 value |= func[i];
727 writel(value, padcfg0);
728 }
729
730 raw_spin_unlock_irqrestore(&vg->lock, flags);
731}
732
733static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
734 unsigned int group_selector)
735{
736 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
737 const struct intel_function func = vg->soc_data->functions[func_selector];
738 const struct intel_pingroup group = vg->soc_data->groups[group_selector];
739
740 if (group.modes)
741 byt_set_group_mixed_mux(vg, group, group.modes);
742 else if (!strcmp(func.name, "gpio"))
743 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
744 else
745 byt_set_group_simple_mux(vg, group, group.mode);
746
747 return 0;
748}
749
750static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)
751{
752
753 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
754 offset >= 92 && offset <= 93)
755 return BYT_ALTER_GPIO_MUX;
756
757
758 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
759 offset >= 11 && offset <= 21)
760 return BYT_ALTER_GPIO_MUX;
761
762 return BYT_DEFAULT_GPIO_MUX;
763}
764
765static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
766{
767 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
768 unsigned long flags;
769 u32 value;
770
771 raw_spin_lock_irqsave(&vg->lock, flags);
772 value = readl(reg);
773 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
774 writel(value, reg);
775 raw_spin_unlock_irqrestore(&vg->lock, flags);
776}
777
778static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
779 struct pinctrl_gpio_range *range,
780 unsigned int offset)
781{
782 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
783 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
784 u32 value, gpio_mux;
785 unsigned long flags;
786
787 raw_spin_lock_irqsave(&vg->lock, flags);
788
789
790
791
792
793
794
795
796
797
798 value = readl(reg) & BYT_PIN_MUX;
799 gpio_mux = byt_get_gpio_mux(vg, offset);
800 if (gpio_mux != value) {
801 value = readl(reg) & ~BYT_PIN_MUX;
802 value |= gpio_mux;
803 writel(value, reg);
804
805 dev_warn(&vg->pdev->dev, FW_BUG
806 "pin %u forcibly re-configured as GPIO\n", offset);
807 }
808
809 raw_spin_unlock_irqrestore(&vg->lock, flags);
810
811 pm_runtime_get(&vg->pdev->dev);
812
813 return 0;
814}
815
816static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
817 struct pinctrl_gpio_range *range,
818 unsigned int offset)
819{
820 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
821
822 byt_gpio_clear_triggering(vg, offset);
823 pm_runtime_put(&vg->pdev->dev);
824}
825
826static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
827 struct pinctrl_gpio_range *range,
828 unsigned int offset,
829 bool input)
830{
831 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
832 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
833 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
834 unsigned long flags;
835 u32 value;
836
837 raw_spin_lock_irqsave(&vg->lock, flags);
838
839 value = readl(val_reg);
840 value &= ~BYT_DIR_MASK;
841 if (input)
842 value |= BYT_OUTPUT_EN;
843 else
844
845
846
847
848
849
850 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
851 "Potential Error: Setting GPIO with direct_irq_en to output");
852 writel(value, val_reg);
853
854 raw_spin_unlock_irqrestore(&vg->lock, flags);
855
856 return 0;
857}
858
859static const struct pinmux_ops byt_pinmux_ops = {
860 .get_functions_count = byt_get_functions_count,
861 .get_function_name = byt_get_function_name,
862 .get_function_groups = byt_get_function_groups,
863 .set_mux = byt_set_mux,
864 .gpio_request_enable = byt_gpio_request_enable,
865 .gpio_disable_free = byt_gpio_disable_free,
866 .gpio_set_direction = byt_gpio_set_direction,
867};
868
869static void byt_get_pull_strength(u32 reg, u16 *strength)
870{
871 switch (reg & BYT_PULL_STR_MASK) {
872 case BYT_PULL_STR_2K:
873 *strength = 2000;
874 break;
875 case BYT_PULL_STR_10K:
876 *strength = 10000;
877 break;
878 case BYT_PULL_STR_20K:
879 *strength = 20000;
880 break;
881 case BYT_PULL_STR_40K:
882 *strength = 40000;
883 break;
884 }
885}
886
887static int byt_set_pull_strength(u32 *reg, u16 strength)
888{
889 *reg &= ~BYT_PULL_STR_MASK;
890
891 switch (strength) {
892 case 2000:
893 *reg |= BYT_PULL_STR_2K;
894 break;
895 case 10000:
896 *reg |= BYT_PULL_STR_10K;
897 break;
898 case 20000:
899 *reg |= BYT_PULL_STR_20K;
900 break;
901 case 40000:
902 *reg |= BYT_PULL_STR_40K;
903 break;
904 default:
905 return -EINVAL;
906 }
907
908 return 0;
909}
910
911static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
912 unsigned long *config)
913{
914 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
915 enum pin_config_param param = pinconf_to_config_param(*config);
916 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
917 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
918 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
919 unsigned long flags;
920 u32 conf, pull, val, debounce;
921 u16 arg = 0;
922
923 raw_spin_lock_irqsave(&vg->lock, flags);
924 conf = readl(conf_reg);
925 pull = conf & BYT_PULL_ASSIGN_MASK;
926 val = readl(val_reg);
927 raw_spin_unlock_irqrestore(&vg->lock, flags);
928
929 switch (param) {
930 case PIN_CONFIG_BIAS_DISABLE:
931 if (pull)
932 return -EINVAL;
933 break;
934 case PIN_CONFIG_BIAS_PULL_DOWN:
935
936 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
937 return -EINVAL;
938
939 byt_get_pull_strength(conf, &arg);
940
941 break;
942 case PIN_CONFIG_BIAS_PULL_UP:
943
944 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
945 return -EINVAL;
946
947 byt_get_pull_strength(conf, &arg);
948
949 break;
950 case PIN_CONFIG_INPUT_DEBOUNCE:
951 if (!(conf & BYT_DEBOUNCE_EN))
952 return -EINVAL;
953
954 raw_spin_lock_irqsave(&vg->lock, flags);
955 debounce = readl(db_reg);
956 raw_spin_unlock_irqrestore(&vg->lock, flags);
957
958 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
959 case BYT_DEBOUNCE_PULSE_375US:
960 arg = 375;
961 break;
962 case BYT_DEBOUNCE_PULSE_750US:
963 arg = 750;
964 break;
965 case BYT_DEBOUNCE_PULSE_1500US:
966 arg = 1500;
967 break;
968 case BYT_DEBOUNCE_PULSE_3MS:
969 arg = 3000;
970 break;
971 case BYT_DEBOUNCE_PULSE_6MS:
972 arg = 6000;
973 break;
974 case BYT_DEBOUNCE_PULSE_12MS:
975 arg = 12000;
976 break;
977 case BYT_DEBOUNCE_PULSE_24MS:
978 arg = 24000;
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 break;
985 default:
986 return -ENOTSUPP;
987 }
988
989 *config = pinconf_to_config_packed(param, arg);
990
991 return 0;
992}
993
994static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
995 unsigned int offset,
996 unsigned long *configs,
997 unsigned int num_configs)
998{
999 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1000 unsigned int param, arg;
1001 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1002 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1003 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1004 unsigned long flags;
1005 u32 conf, val, debounce;
1006 int i, ret = 0;
1007
1008 raw_spin_lock_irqsave(&vg->lock, flags);
1009
1010 conf = readl(conf_reg);
1011 val = readl(val_reg);
1012
1013 for (i = 0; i < num_configs; i++) {
1014 param = pinconf_to_config_param(configs[i]);
1015 arg = pinconf_to_config_argument(configs[i]);
1016
1017 switch (param) {
1018 case PIN_CONFIG_BIAS_DISABLE:
1019 conf &= ~BYT_PULL_ASSIGN_MASK;
1020 break;
1021 case PIN_CONFIG_BIAS_PULL_DOWN:
1022
1023 if (arg == 1)
1024 arg = 2000;
1025
1026
1027
1028
1029
1030 if (val & BYT_INPUT_EN) {
1031 val &= ~BYT_INPUT_EN;
1032 writel(val, val_reg);
1033 dev_warn(&vg->pdev->dev,
1034 "pin %u forcibly set to input mode\n",
1035 offset);
1036 }
1037
1038 conf &= ~BYT_PULL_ASSIGN_MASK;
1039 conf |= BYT_PULL_ASSIGN_DOWN;
1040 ret = byt_set_pull_strength(&conf, arg);
1041
1042 break;
1043 case PIN_CONFIG_BIAS_PULL_UP:
1044
1045 if (arg == 1)
1046 arg = 2000;
1047
1048
1049
1050
1051
1052 if (val & BYT_INPUT_EN) {
1053 val &= ~BYT_INPUT_EN;
1054 writel(val, val_reg);
1055 dev_warn(&vg->pdev->dev,
1056 "pin %u forcibly set to input mode\n",
1057 offset);
1058 }
1059
1060 conf &= ~BYT_PULL_ASSIGN_MASK;
1061 conf |= BYT_PULL_ASSIGN_UP;
1062 ret = byt_set_pull_strength(&conf, arg);
1063
1064 break;
1065 case PIN_CONFIG_INPUT_DEBOUNCE:
1066 debounce = readl(db_reg);
1067 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1068
1069 if (arg)
1070 conf |= BYT_DEBOUNCE_EN;
1071 else
1072 conf &= ~BYT_DEBOUNCE_EN;
1073
1074 switch (arg) {
1075 case 375:
1076 debounce |= BYT_DEBOUNCE_PULSE_375US;
1077 break;
1078 case 750:
1079 debounce |= BYT_DEBOUNCE_PULSE_750US;
1080 break;
1081 case 1500:
1082 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1083 break;
1084 case 3000:
1085 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1086 break;
1087 case 6000:
1088 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1089 break;
1090 case 12000:
1091 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1092 break;
1093 case 24000:
1094 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1095 break;
1096 default:
1097 if (arg)
1098 ret = -EINVAL;
1099 break;
1100 }
1101
1102 if (!ret)
1103 writel(debounce, db_reg);
1104 break;
1105 default:
1106 ret = -ENOTSUPP;
1107 }
1108
1109 if (ret)
1110 break;
1111 }
1112
1113 if (!ret)
1114 writel(conf, conf_reg);
1115
1116 raw_spin_unlock_irqrestore(&vg->lock, flags);
1117
1118 return ret;
1119}
1120
1121static const struct pinconf_ops byt_pinconf_ops = {
1122 .is_generic = true,
1123 .pin_config_get = byt_pin_config_get,
1124 .pin_config_set = byt_pin_config_set,
1125};
1126
1127static const struct pinctrl_desc byt_pinctrl_desc = {
1128 .pctlops = &byt_pinctrl_ops,
1129 .pmxops = &byt_pinmux_ops,
1130 .confops = &byt_pinconf_ops,
1131 .owner = THIS_MODULE,
1132};
1133
1134static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1135{
1136 struct byt_gpio *vg = gpiochip_get_data(chip);
1137 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1138 unsigned long flags;
1139 u32 val;
1140
1141 raw_spin_lock_irqsave(&vg->lock, flags);
1142 val = readl(reg);
1143 raw_spin_unlock_irqrestore(&vg->lock, flags);
1144
1145 return !!(val & BYT_LEVEL);
1146}
1147
1148static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1149{
1150 struct byt_gpio *vg = gpiochip_get_data(chip);
1151 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1152 unsigned long flags;
1153 u32 old_val;
1154
1155 if (!reg)
1156 return;
1157
1158 raw_spin_lock_irqsave(&vg->lock, flags);
1159 old_val = readl(reg);
1160 if (value)
1161 writel(old_val | BYT_LEVEL, reg);
1162 else
1163 writel(old_val & ~BYT_LEVEL, reg);
1164 raw_spin_unlock_irqrestore(&vg->lock, flags);
1165}
1166
1167static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1168{
1169 struct byt_gpio *vg = gpiochip_get_data(chip);
1170 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1171 unsigned long flags;
1172 u32 value;
1173
1174 if (!reg)
1175 return -EINVAL;
1176
1177 raw_spin_lock_irqsave(&vg->lock, flags);
1178 value = readl(reg);
1179 raw_spin_unlock_irqrestore(&vg->lock, flags);
1180
1181 if (!(value & BYT_OUTPUT_EN))
1182 return 0;
1183 if (!(value & BYT_INPUT_EN))
1184 return 1;
1185
1186 return -EINVAL;
1187}
1188
1189static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1190{
1191 return pinctrl_gpio_direction_input(chip->base + offset);
1192}
1193
1194static int byt_gpio_direction_output(struct gpio_chip *chip,
1195 unsigned int offset, int value)
1196{
1197 int ret = pinctrl_gpio_direction_output(chip->base + offset);
1198
1199 if (ret)
1200 return ret;
1201
1202 byt_gpio_set(chip, offset, value);
1203
1204 return 0;
1205}
1206
1207static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1208{
1209 struct byt_gpio *vg = gpiochip_get_data(chip);
1210 int i;
1211 u32 conf0, val;
1212
1213 for (i = 0; i < vg->soc_data->npins; i++) {
1214 const struct byt_community *comm;
1215 const char *pull_str = NULL;
1216 const char *pull = NULL;
1217 void __iomem *reg;
1218 unsigned long flags;
1219 const char *label;
1220 unsigned int pin;
1221
1222 raw_spin_lock_irqsave(&vg->lock, flags);
1223 pin = vg->soc_data->pins[i].number;
1224 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1225 if (!reg) {
1226 seq_printf(s,
1227 "Could not retrieve pin %i conf0 reg\n",
1228 pin);
1229 raw_spin_unlock_irqrestore(&vg->lock, flags);
1230 continue;
1231 }
1232 conf0 = readl(reg);
1233
1234 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1235 if (!reg) {
1236 seq_printf(s,
1237 "Could not retrieve pin %i val reg\n", pin);
1238 raw_spin_unlock_irqrestore(&vg->lock, flags);
1239 continue;
1240 }
1241 val = readl(reg);
1242 raw_spin_unlock_irqrestore(&vg->lock, flags);
1243
1244 comm = byt_get_community(vg, pin);
1245 if (!comm) {
1246 seq_printf(s,
1247 "Could not get community for pin %i\n", pin);
1248 continue;
1249 }
1250 label = gpiochip_is_requested(chip, i);
1251 if (!label)
1252 label = "Unrequested";
1253
1254 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1255 case BYT_PULL_ASSIGN_UP:
1256 pull = "up";
1257 break;
1258 case BYT_PULL_ASSIGN_DOWN:
1259 pull = "down";
1260 break;
1261 }
1262
1263 switch (conf0 & BYT_PULL_STR_MASK) {
1264 case BYT_PULL_STR_2K:
1265 pull_str = "2k";
1266 break;
1267 case BYT_PULL_STR_10K:
1268 pull_str = "10k";
1269 break;
1270 case BYT_PULL_STR_20K:
1271 pull_str = "20k";
1272 break;
1273 case BYT_PULL_STR_40K:
1274 pull_str = "40k";
1275 break;
1276 }
1277
1278 seq_printf(s,
1279 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1280 pin,
1281 label,
1282 val & BYT_INPUT_EN ? " " : "in",
1283 val & BYT_OUTPUT_EN ? " " : "out",
1284 val & BYT_LEVEL ? "hi" : "lo",
1285 comm->pad_map[i], comm->pad_map[i] * 16,
1286 conf0 & 0x7,
1287 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1288 conf0 & BYT_TRIG_POS ? " rise" : " ",
1289 conf0 & BYT_TRIG_LVL ? " level" : " ");
1290
1291 if (pull && pull_str)
1292 seq_printf(s, " %-4s %-3s", pull, pull_str);
1293 else
1294 seq_puts(s, " ");
1295
1296 if (conf0 & BYT_IODEN)
1297 seq_puts(s, " open-drain");
1298
1299 seq_puts(s, "\n");
1300 }
1301}
1302
1303static const struct gpio_chip byt_gpio_chip = {
1304 .owner = THIS_MODULE,
1305 .request = gpiochip_generic_request,
1306 .free = gpiochip_generic_free,
1307 .get_direction = byt_gpio_get_direction,
1308 .direction_input = byt_gpio_direction_input,
1309 .direction_output = byt_gpio_direction_output,
1310 .get = byt_gpio_get,
1311 .set = byt_gpio_set,
1312 .dbg_show = byt_gpio_dbg_show,
1313};
1314
1315static void byt_irq_ack(struct irq_data *d)
1316{
1317 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1318 struct byt_gpio *vg = gpiochip_get_data(gc);
1319 unsigned int offset = irqd_to_hwirq(d);
1320 void __iomem *reg;
1321
1322 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1323 if (!reg)
1324 return;
1325
1326 raw_spin_lock(&vg->lock);
1327 writel(BIT(offset % 32), reg);
1328 raw_spin_unlock(&vg->lock);
1329}
1330
1331static void byt_irq_mask(struct irq_data *d)
1332{
1333 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1334 struct byt_gpio *vg = gpiochip_get_data(gc);
1335
1336 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1337}
1338
1339static void byt_irq_unmask(struct irq_data *d)
1340{
1341 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1342 struct byt_gpio *vg = gpiochip_get_data(gc);
1343 unsigned int offset = irqd_to_hwirq(d);
1344 unsigned long flags;
1345 void __iomem *reg;
1346 u32 value;
1347
1348 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1349 if (!reg)
1350 return;
1351
1352 raw_spin_lock_irqsave(&vg->lock, flags);
1353 value = readl(reg);
1354
1355 switch (irqd_get_trigger_type(d)) {
1356 case IRQ_TYPE_LEVEL_HIGH:
1357 value |= BYT_TRIG_LVL;
1358
1359 case IRQ_TYPE_EDGE_RISING:
1360 value |= BYT_TRIG_POS;
1361 break;
1362 case IRQ_TYPE_LEVEL_LOW:
1363 value |= BYT_TRIG_LVL;
1364
1365 case IRQ_TYPE_EDGE_FALLING:
1366 value |= BYT_TRIG_NEG;
1367 break;
1368 case IRQ_TYPE_EDGE_BOTH:
1369 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1370 break;
1371 }
1372
1373 writel(value, reg);
1374
1375 raw_spin_unlock_irqrestore(&vg->lock, flags);
1376}
1377
1378static int byt_irq_type(struct irq_data *d, unsigned int type)
1379{
1380 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1381 u32 offset = irqd_to_hwirq(d);
1382 u32 value;
1383 unsigned long flags;
1384 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1385
1386 if (!reg || offset >= vg->chip.ngpio)
1387 return -EINVAL;
1388
1389 raw_spin_lock_irqsave(&vg->lock, flags);
1390 value = readl(reg);
1391
1392 WARN(value & BYT_DIRECT_IRQ_EN,
1393 "Bad pad config for io mode, force direct_irq_en bit clearing");
1394
1395
1396
1397
1398 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1399 BYT_TRIG_LVL);
1400
1401 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1402 BYT_GLITCH_F_FAST_CLK;
1403
1404 writel(value, reg);
1405
1406 if (type & IRQ_TYPE_EDGE_BOTH)
1407 irq_set_handler_locked(d, handle_edge_irq);
1408 else if (type & IRQ_TYPE_LEVEL_MASK)
1409 irq_set_handler_locked(d, handle_level_irq);
1410
1411 raw_spin_unlock_irqrestore(&vg->lock, flags);
1412
1413 return 0;
1414}
1415
1416static struct irq_chip byt_irqchip = {
1417 .name = "BYT-GPIO",
1418 .irq_ack = byt_irq_ack,
1419 .irq_mask = byt_irq_mask,
1420 .irq_unmask = byt_irq_unmask,
1421 .irq_set_type = byt_irq_type,
1422 .flags = IRQCHIP_SKIP_SET_WAKE,
1423};
1424
1425static void byt_gpio_irq_handler(struct irq_desc *desc)
1426{
1427 struct irq_data *data = irq_desc_get_irq_data(desc);
1428 struct byt_gpio *vg = gpiochip_get_data(
1429 irq_desc_get_handler_data(desc));
1430 struct irq_chip *chip = irq_data_get_irq_chip(data);
1431 u32 base, pin;
1432 void __iomem *reg;
1433 unsigned long pending;
1434 unsigned int virq;
1435
1436
1437 for (base = 0; base < vg->chip.ngpio; base += 32) {
1438 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1439
1440 if (!reg) {
1441 dev_warn(&vg->pdev->dev,
1442 "Pin %i: could not retrieve interrupt status register\n",
1443 base);
1444 continue;
1445 }
1446
1447 raw_spin_lock(&vg->lock);
1448 pending = readl(reg);
1449 raw_spin_unlock(&vg->lock);
1450 for_each_set_bit(pin, &pending, 32) {
1451 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1452 generic_handle_irq(virq);
1453 }
1454 }
1455 chip->irq_eoi(data);
1456}
1457
1458static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1459{
1460 struct gpio_chip *gc = &vg->chip;
1461 struct device *dev = &vg->pdev->dev;
1462 void __iomem *reg;
1463 u32 base, value;
1464 int i;
1465
1466
1467
1468
1469
1470
1471 for (i = 0; i < vg->soc_data->npins; i++) {
1472 unsigned int pin = vg->soc_data->pins[i].number;
1473
1474 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1475 if (!reg) {
1476 dev_warn(&vg->pdev->dev,
1477 "Pin %i: could not retrieve conf0 register\n",
1478 i);
1479 continue;
1480 }
1481
1482 value = readl(reg);
1483 if (value & BYT_DIRECT_IRQ_EN) {
1484 clear_bit(i, gc->irq.valid_mask);
1485 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1486 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1487 byt_gpio_clear_triggering(vg, i);
1488 dev_dbg(dev, "disabling GPIO %d\n", i);
1489 }
1490 }
1491
1492
1493 for (base = 0; base < vg->soc_data->npins; base += 32) {
1494 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1495
1496 if (!reg) {
1497 dev_warn(&vg->pdev->dev,
1498 "Pin %i: could not retrieve irq status reg\n",
1499 base);
1500 continue;
1501 }
1502
1503 writel(0xffffffff, reg);
1504
1505
1506 value = readl(reg);
1507 if (value)
1508 dev_err(&vg->pdev->dev,
1509 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1510 base / 32, value);
1511 }
1512}
1513
1514static int byt_gpio_probe(struct byt_gpio *vg)
1515{
1516 struct gpio_chip *gc;
1517 struct resource *irq_rc;
1518 int ret;
1519
1520
1521 vg->chip = byt_gpio_chip;
1522 gc = &vg->chip;
1523 gc->label = dev_name(&vg->pdev->dev);
1524 gc->base = -1;
1525 gc->can_sleep = false;
1526 gc->parent = &vg->pdev->dev;
1527 gc->ngpio = vg->soc_data->npins;
1528 gc->irq.need_valid_mask = true;
1529
1530#ifdef CONFIG_PM_SLEEP
1531 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1532 sizeof(*vg->saved_context), GFP_KERNEL);
1533 if (!vg->saved_context)
1534 return -ENOMEM;
1535#endif
1536 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1537 if (ret) {
1538 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1539 return ret;
1540 }
1541
1542 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1543 0, 0, vg->soc_data->npins);
1544 if (ret) {
1545 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1546 return ret;
1547 }
1548
1549
1550 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1551 if (irq_rc && irq_rc->start) {
1552 byt_gpio_irq_init_hw(vg);
1553 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1554 handle_bad_irq, IRQ_TYPE_NONE);
1555 if (ret) {
1556 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1557 return ret;
1558 }
1559
1560 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1561 (unsigned)irq_rc->start,
1562 byt_gpio_irq_handler);
1563 }
1564
1565 return ret;
1566}
1567
1568static int byt_set_soc_data(struct byt_gpio *vg,
1569 const struct byt_pinctrl_soc_data *soc_data)
1570{
1571 int i;
1572
1573 vg->soc_data = soc_data;
1574 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1575 soc_data->ncommunities,
1576 sizeof(*vg->communities_copy),
1577 GFP_KERNEL);
1578 if (!vg->communities_copy)
1579 return -ENOMEM;
1580
1581 for (i = 0; i < soc_data->ncommunities; i++) {
1582 struct byt_community *comm = vg->communities_copy + i;
1583 struct resource *mem_rc;
1584
1585 *comm = vg->soc_data->communities[i];
1586
1587 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1588 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1589 if (IS_ERR(comm->reg_base))
1590 return PTR_ERR(comm->reg_base);
1591 }
1592
1593 return 0;
1594}
1595
1596static const struct acpi_device_id byt_gpio_acpi_match[] = {
1597 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1598 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1599 { }
1600};
1601
1602static int byt_pinctrl_probe(struct platform_device *pdev)
1603{
1604 const struct byt_pinctrl_soc_data *soc_data = NULL;
1605 const struct byt_pinctrl_soc_data **soc_table;
1606 struct acpi_device *acpi_dev;
1607 struct byt_gpio *vg;
1608 int i, ret;
1609
1610 acpi_dev = ACPI_COMPANION(&pdev->dev);
1611 if (!acpi_dev)
1612 return -ENODEV;
1613
1614 soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
1615
1616 for (i = 0; soc_table[i]; i++) {
1617 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1618 soc_data = soc_table[i];
1619 break;
1620 }
1621 }
1622
1623 if (!soc_data)
1624 return -ENODEV;
1625
1626 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1627 if (!vg)
1628 return -ENOMEM;
1629
1630 vg->pdev = pdev;
1631 ret = byt_set_soc_data(vg, soc_data);
1632 if (ret) {
1633 dev_err(&pdev->dev, "failed to set soc data\n");
1634 return ret;
1635 }
1636
1637 vg->pctl_desc = byt_pinctrl_desc;
1638 vg->pctl_desc.name = dev_name(&pdev->dev);
1639 vg->pctl_desc.pins = vg->soc_data->pins;
1640 vg->pctl_desc.npins = vg->soc_data->npins;
1641
1642 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1643 if (IS_ERR(vg->pctl_dev)) {
1644 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1645 return PTR_ERR(vg->pctl_dev);
1646 }
1647
1648 raw_spin_lock_init(&vg->lock);
1649
1650 ret = byt_gpio_probe(vg);
1651 if (ret)
1652 return ret;
1653
1654 platform_set_drvdata(pdev, vg);
1655 pm_runtime_enable(&pdev->dev);
1656
1657 return 0;
1658}
1659
1660#ifdef CONFIG_PM_SLEEP
1661static int byt_gpio_suspend(struct device *dev)
1662{
1663 struct byt_gpio *vg = dev_get_drvdata(dev);
1664 int i;
1665
1666 for (i = 0; i < vg->soc_data->npins; i++) {
1667 void __iomem *reg;
1668 u32 value;
1669 unsigned int pin = vg->soc_data->pins[i].number;
1670
1671 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1672 if (!reg) {
1673 dev_warn(&vg->pdev->dev,
1674 "Pin %i: could not retrieve conf0 register\n",
1675 i);
1676 continue;
1677 }
1678 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1679 vg->saved_context[i].conf0 = value;
1680
1681 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1682 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1683 vg->saved_context[i].val = value;
1684 }
1685
1686 return 0;
1687}
1688
1689static int byt_gpio_resume(struct device *dev)
1690{
1691 struct byt_gpio *vg = dev_get_drvdata(dev);
1692 int i;
1693
1694 for (i = 0; i < vg->soc_data->npins; i++) {
1695 void __iomem *reg;
1696 u32 value;
1697 unsigned int pin = vg->soc_data->pins[i].number;
1698
1699 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1700 if (!reg) {
1701 dev_warn(&vg->pdev->dev,
1702 "Pin %i: could not retrieve conf0 register\n",
1703 i);
1704 continue;
1705 }
1706 value = readl(reg);
1707 if ((value & BYT_CONF0_RESTORE_MASK) !=
1708 vg->saved_context[i].conf0) {
1709 value &= ~BYT_CONF0_RESTORE_MASK;
1710 value |= vg->saved_context[i].conf0;
1711 writel(value, reg);
1712 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1713 }
1714
1715 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1716 value = readl(reg);
1717 if ((value & BYT_VAL_RESTORE_MASK) !=
1718 vg->saved_context[i].val) {
1719 u32 v;
1720
1721 v = value & ~BYT_VAL_RESTORE_MASK;
1722 v |= vg->saved_context[i].val;
1723 if (v != value) {
1724 writel(v, reg);
1725 dev_dbg(dev, "restored pin %d val %#08x\n",
1726 i, v);
1727 }
1728 }
1729 }
1730
1731 return 0;
1732}
1733#endif
1734
1735#ifdef CONFIG_PM
1736static int byt_gpio_runtime_suspend(struct device *dev)
1737{
1738 return 0;
1739}
1740
1741static int byt_gpio_runtime_resume(struct device *dev)
1742{
1743 return 0;
1744}
1745#endif
1746
1747static const struct dev_pm_ops byt_gpio_pm_ops = {
1748 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1749 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1750 NULL)
1751};
1752
1753static struct platform_driver byt_gpio_driver = {
1754 .probe = byt_pinctrl_probe,
1755 .driver = {
1756 .name = "byt_gpio",
1757 .pm = &byt_gpio_pm_ops,
1758 .suppress_bind_attrs = true,
1759
1760 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1761 },
1762};
1763
1764static int __init byt_gpio_init(void)
1765{
1766 return platform_driver_register(&byt_gpio_driver);
1767}
1768subsys_initcall(byt_gpio_init);
1769
