1
2
3
4
5
6
7
8
9#include <linux/mod_devicetable.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12
13#include <linux/pinctrl/pinctrl.h>
14
15#include "pinctrl-intel.h"
16
17#define DNV_PAD_OWN 0x020
18#define DNV_HOSTSW_OWN 0x0C0
19#define DNV_PADCFGLOCK 0x090
20#define DNV_GPI_IE 0x120
21
22#define DNV_GPP(n, s, e) \
23 { \
24 .reg_num = (n), \
25 .base = (s), \
26 .size = ((e) - (s) + 1), \
27 }
28
29#define DNV_COMMUNITY(b, s, e, g) \
30 { \
31 .barno = (b), \
32 .padown_offset = DNV_PAD_OWN, \
33 .padcfglock_offset = DNV_PADCFGLOCK, \
34 .hostown_offset = DNV_HOSTSW_OWN, \
35 .ie_offset = DNV_GPI_IE, \
36 .pin_base = (s), \
37 .npins = ((e) - (s) + 1), \
38 .gpps = (g), \
39 .ngpps = ARRAY_SIZE(g), \
40 }
41
42static const struct pinctrl_pin_desc dnv_pins[] = {
43
44 PINCTRL_PIN(0, "GBE0_SDP0"),
45 PINCTRL_PIN(1, "GBE1_SDP0"),
46 PINCTRL_PIN(2, "GBE0_SDP1"),
47 PINCTRL_PIN(3, "GBE1_SDP1"),
48 PINCTRL_PIN(4, "GBE0_SDP2"),
49 PINCTRL_PIN(5, "GBE1_SDP2"),
50 PINCTRL_PIN(6, "GBE0_SDP3"),
51 PINCTRL_PIN(7, "GBE1_SDP3"),
52 PINCTRL_PIN(8, "GBE2_LED0"),
53 PINCTRL_PIN(9, "GBE2_LED1"),
54 PINCTRL_PIN(10, "GBE0_I2C_CLK"),
55 PINCTRL_PIN(11, "GBE0_I2C_DATA"),
56 PINCTRL_PIN(12, "GBE1_I2C_CLK"),
57 PINCTRL_PIN(13, "GBE1_I2C_DATA"),
58 PINCTRL_PIN(14, "NCSI_RXD0"),
59 PINCTRL_PIN(15, "NCSI_CLK_IN"),
60 PINCTRL_PIN(16, "NCSI_RXD1"),
61 PINCTRL_PIN(17, "NCSI_CRS_DV"),
62 PINCTRL_PIN(18, "NCSI_ARB_IN"),
63 PINCTRL_PIN(19, "NCSI_TX_EN"),
64 PINCTRL_PIN(20, "NCSI_TXD0"),
65 PINCTRL_PIN(21, "NCSI_TXD1"),
66 PINCTRL_PIN(22, "NCSI_ARB_OUT"),
67 PINCTRL_PIN(23, "GBE0_LED0"),
68 PINCTRL_PIN(24, "GBE0_LED1"),
69 PINCTRL_PIN(25, "GBE1_LED0"),
70 PINCTRL_PIN(26, "GBE1_LED1"),
71 PINCTRL_PIN(27, "GPIO_0"),
72 PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
73 PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
74 PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
75 PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
76 PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
77 PINCTRL_PIN(33, "GPIO_1"),
78 PINCTRL_PIN(34, "GPIO_2"),
79 PINCTRL_PIN(35, "SVID_ALERT_N"),
80 PINCTRL_PIN(36, "SVID_DATA"),
81 PINCTRL_PIN(37, "SVID_CLK"),
82 PINCTRL_PIN(38, "THERMTRIP_N"),
83 PINCTRL_PIN(39, "PROCHOT_N"),
84 PINCTRL_PIN(40, "MEMHOT_N"),
85
86 PINCTRL_PIN(41, "DFX_PORT_CLK0"),
87 PINCTRL_PIN(42, "DFX_PORT_CLK1"),
88 PINCTRL_PIN(43, "DFX_PORT0"),
89 PINCTRL_PIN(44, "DFX_PORT1"),
90 PINCTRL_PIN(45, "DFX_PORT2"),
91 PINCTRL_PIN(46, "DFX_PORT3"),
92 PINCTRL_PIN(47, "DFX_PORT4"),
93 PINCTRL_PIN(48, "DFX_PORT5"),
94 PINCTRL_PIN(49, "DFX_PORT6"),
95 PINCTRL_PIN(50, "DFX_PORT7"),
96 PINCTRL_PIN(51, "DFX_PORT8"),
97 PINCTRL_PIN(52, "DFX_PORT9"),
98 PINCTRL_PIN(53, "DFX_PORT10"),
99 PINCTRL_PIN(54, "DFX_PORT11"),
100 PINCTRL_PIN(55, "DFX_PORT12"),
101 PINCTRL_PIN(56, "DFX_PORT13"),
102 PINCTRL_PIN(57, "DFX_PORT14"),
103 PINCTRL_PIN(58, "DFX_PORT15"),
104
105 PINCTRL_PIN(59, "GPIO_12"),
106 PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"),
107 PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
108 PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
109 PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
110 PINCTRL_PIN(64, "UART0_RXD"),
111 PINCTRL_PIN(65, "UART0_TXD"),
112 PINCTRL_PIN(66, "SMB5_GBE_CLK"),
113 PINCTRL_PIN(67, "SMB5_GBE_DATA"),
114 PINCTRL_PIN(68, "ERROR2_N"),
115 PINCTRL_PIN(69, "ERROR1_N"),
116 PINCTRL_PIN(70, "ERROR0_N"),
117 PINCTRL_PIN(71, "IERR_N"),
118 PINCTRL_PIN(72, "MCERR_N"),
119 PINCTRL_PIN(73, "SMB0_LEG_CLK"),
120 PINCTRL_PIN(74, "SMB0_LEG_DATA"),
121 PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
122 PINCTRL_PIN(76, "SMB1_HOST_DATA"),
123 PINCTRL_PIN(77, "SMB1_HOST_CLK"),
124 PINCTRL_PIN(78, "SMB2_PECI_DATA"),
125 PINCTRL_PIN(79, "SMB2_PECI_CLK"),
126 PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
127 PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
128 PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
129 PINCTRL_PIN(83, "USB_OC0_N"),
130 PINCTRL_PIN(84, "FLEX_CLK_SE0"),
131 PINCTRL_PIN(85, "FLEX_CLK_SE1"),
132 PINCTRL_PIN(86, "GPIO_4"),
133 PINCTRL_PIN(87, "GPIO_5"),
134 PINCTRL_PIN(88, "GPIO_6"),
135 PINCTRL_PIN(89, "GPIO_7"),
136 PINCTRL_PIN(90, "SATA0_LED_N"),
137 PINCTRL_PIN(91, "SATA1_LED_N"),
138 PINCTRL_PIN(92, "SATA_PDETECT0"),
139 PINCTRL_PIN(93, "SATA_PDETECT1"),
140 PINCTRL_PIN(94, "SATA0_SDOUT"),
141 PINCTRL_PIN(95, "SATA1_SDOUT"),
142 PINCTRL_PIN(96, "UART1_RXD"),
143 PINCTRL_PIN(97, "UART1_TXD"),
144 PINCTRL_PIN(98, "GPIO_8"),
145 PINCTRL_PIN(99, "GPIO_9"),
146 PINCTRL_PIN(100, "TCK"),
147 PINCTRL_PIN(101, "TRST_N"),
148 PINCTRL_PIN(102, "TMS"),
149 PINCTRL_PIN(103, "TDI"),
150 PINCTRL_PIN(104, "TDO"),
151 PINCTRL_PIN(105, "CX_PRDY_N"),
152 PINCTRL_PIN(106, "CX_PREQ_N"),
153 PINCTRL_PIN(107, "CTBTRIGINOUT"),
154 PINCTRL_PIN(108, "CTBTRIGOUT"),
155 PINCTRL_PIN(109, "DFX_SPARE2"),
156 PINCTRL_PIN(110, "DFX_SPARE3"),
157 PINCTRL_PIN(111, "DFX_SPARE4"),
158
159 PINCTRL_PIN(112, "SUSPWRDNACK"),
160 PINCTRL_PIN(113, "PMU_SUSCLK"),
161 PINCTRL_PIN(114, "ADR_TRIGGER"),
162 PINCTRL_PIN(115, "PMU_SLP_S45_N"),
163 PINCTRL_PIN(116, "PMU_SLP_S3_N"),
164 PINCTRL_PIN(117, "PMU_WAKE_N"),
165 PINCTRL_PIN(118, "PMU_PWRBTN_N"),
166 PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
167 PINCTRL_PIN(120, "PMU_PLTRST_N"),
168 PINCTRL_PIN(121, "SUS_STAT_N"),
169 PINCTRL_PIN(122, "SLP_S0IX_N"),
170 PINCTRL_PIN(123, "SPI_CS0_N"),
171 PINCTRL_PIN(124, "SPI_CS1_N"),
172 PINCTRL_PIN(125, "SPI_MOSI_IO0"),
173 PINCTRL_PIN(126, "SPI_MISO_IO1"),
174 PINCTRL_PIN(127, "SPI_IO2"),
175 PINCTRL_PIN(128, "SPI_IO3"),
176 PINCTRL_PIN(129, "SPI_CLK"),
177 PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
178 PINCTRL_PIN(131, "ESPI_IO0"),
179 PINCTRL_PIN(132, "ESPI_IO1"),
180 PINCTRL_PIN(133, "ESPI_IO2"),
181 PINCTRL_PIN(134, "ESPI_IO3"),
182 PINCTRL_PIN(135, "ESPI_CS0_N"),
183 PINCTRL_PIN(136, "ESPI_CLK"),
184 PINCTRL_PIN(137, "ESPI_RST_N"),
185 PINCTRL_PIN(138, "ESPI_ALRT0_N"),
186 PINCTRL_PIN(139, "GPIO_10"),
187 PINCTRL_PIN(140, "GPIO_11"),
188 PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
189 PINCTRL_PIN(142, "EMMC_CMD"),
190 PINCTRL_PIN(143, "EMMC_STROBE"),
191 PINCTRL_PIN(144, "EMMC_CLK"),
192 PINCTRL_PIN(145, "EMMC_D0"),
193 PINCTRL_PIN(146, "EMMC_D1"),
194 PINCTRL_PIN(147, "EMMC_D2"),
195 PINCTRL_PIN(148, "EMMC_D3"),
196 PINCTRL_PIN(149, "EMMC_D4"),
197 PINCTRL_PIN(150, "EMMC_D5"),
198 PINCTRL_PIN(151, "EMMC_D6"),
199 PINCTRL_PIN(152, "EMMC_D7"),
200 PINCTRL_PIN(153, "GPIO_3"),
201};
202
203static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
204static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
205static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
206static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
207static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };
208static const unsigned int dnv_emmc_pins[] = {
209 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
210};
211
212static const struct intel_pingroup dnv_groups[] = {
213 PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
214 PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
215 PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
216 PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
217};
218
219static const char * const dnv_uart0_groups[] = { "uart0_grp" };
220static const char * const dnv_uart1_groups[] = { "uart1_grp" };
221static const char * const dnv_uart2_groups[] = { "uart2_grp" };
222static const char * const dnv_emmc_groups[] = { "emmc_grp" };
223
224static const struct intel_function dnv_functions[] = {
225 FUNCTION("uart0", dnv_uart0_groups),
226 FUNCTION("uart1", dnv_uart1_groups),
227 FUNCTION("uart2", dnv_uart2_groups),
228 FUNCTION("emmc", dnv_emmc_groups),
229};
230
231static const struct intel_padgroup dnv_north_gpps[] = {
232 DNV_GPP(0, 0, 31),
233 DNV_GPP(1, 32, 40),
234};
235
236static const struct intel_padgroup dnv_south_gpps[] = {
237 DNV_GPP(0, 41, 58),
238 DNV_GPP(1, 59, 90),
239 DNV_GPP(2, 91, 111),
240 DNV_GPP(3, 112, 143),
241 DNV_GPP(4, 144, 153),
242};
243
244static const struct intel_community dnv_communities[] = {
245 DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
246 DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
247};
248
249static const struct intel_pinctrl_soc_data dnv_soc_data = {
250 .pins = dnv_pins,
251 .npins = ARRAY_SIZE(dnv_pins),
252 .groups = dnv_groups,
253 .ngroups = ARRAY_SIZE(dnv_groups),
254 .functions = dnv_functions,
255 .nfunctions = ARRAY_SIZE(dnv_functions),
256 .communities = dnv_communities,
257 .ncommunities = ARRAY_SIZE(dnv_communities),
258};
259
260static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
261
262static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
263 { "INTC3000", (kernel_ulong_t)&dnv_soc_data },
264 { }
265};
266MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
267
268static struct platform_driver dnv_pinctrl_driver = {
269 .probe = intel_pinctrl_probe_by_hid,
270 .driver = {
271 .name = "denverton-pinctrl",
272 .acpi_match_table = dnv_pinctrl_acpi_match,
273 .pm = &dnv_pinctrl_pm_ops,
274 },
275};
276
277static int __init dnv_pinctrl_init(void)
278{
279 return platform_driver_register(&dnv_pinctrl_driver);
280}
281subsys_initcall(dnv_pinctrl_init);
282
283static void __exit dnv_pinctrl_exit(void)
284{
285 platform_driver_unregister(&dnv_pinctrl_driver);
286}
287module_exit(dnv_pinctrl_exit);
288
289MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
290MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
291MODULE_LICENSE("GPL v2");
292
