LXR linux/drivers/pwm/pwm-brcmstb.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Broadcom BCM7038 PWM driver
   4 * Author: Florian Fainelli
   5 *
   6 * Copyright (C) 2015 Broadcom Corporation
   7 */
   8
   9#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
  10
  11#include <linux/clk.h>
  12#include <linux/export.h>
  13#include <linux/init.h>
  14#include <linux/io.h>
  15#include <linux/kernel.h>
  16#include <linux/module.h>
  17#include <linux/of.h>
  18#include <linux/platform_device.h>
  19#include <linux/pwm.h>
  20#include <linux/spinlock.h>
  21
  22#define PWM_CTRL                0x00
  23#define  CTRL_START             BIT(0)
  24#define  CTRL_OEB               BIT(1)
  25#define  CTRL_FORCE_HIGH        BIT(2)
  26#define  CTRL_OPENDRAIN         BIT(3)
  27#define  CTRL_CHAN_OFFS         4
  28
  29#define PWM_CTRL2               0x04
  30#define  CTRL2_OUT_SELECT       BIT(0)
  31
  32#define PWM_CH_SIZE             0x8
  33
  34#define PWM_CWORD_MSB(ch)       (0x08 + ((ch) * PWM_CH_SIZE))
  35#define PWM_CWORD_LSB(ch)       (0x0c + ((ch) * PWM_CH_SIZE))
  36
  37/* Number of bits for the CWORD value */
  38#define CWORD_BIT_SIZE          16
  39
  40/*
  41 * Maximum control word value allowed when variable-frequency PWM is used as a
  42 * clock for the constant-frequency PMW.
  43 */
  44#define CONST_VAR_F_MAX         32768
  45#define CONST_VAR_F_MIN         1
  46
  47#define PWM_ON(ch)              (0x18 + ((ch) * PWM_CH_SIZE))
  48#define  PWM_ON_MIN             1
  49#define PWM_PERIOD(ch)          (0x1c + ((ch) * PWM_CH_SIZE))
  50#define  PWM_PERIOD_MIN         0
  51
  52#define PWM_ON_PERIOD_MAX       0xff
  53
  54struct brcmstb_pwm {
  55        void __iomem *base;
  56        spinlock_t lock;
  57        struct clk *clk;
  58        struct pwm_chip chip;
  59};
  60
  61static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
  62                                    unsigned int offset)
  63{
  64        if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  65                return __raw_readl(p->base + offset);
  66        else
  67                return readl_relaxed(p->base + offset);
  68}
  69
  70static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
  71                                      unsigned int offset)
  72{
  73        if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  74                __raw_writel(value, p->base + offset);
  75        else
  76                writel_relaxed(value, p->base + offset);
  77}
  78
  79static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
  80{
  81        return container_of(chip, struct brcmstb_pwm, chip);
  82}
  83
  84/*
  85 * Fv is derived from the variable frequency output. The variable frequency
  86 * output is configured using this formula:
  87 *
  88 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
  89 *
  90 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
  91 *
  92 * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
  93 *
  94 * The PWM core framework specifies that the "duty_ns" parameter is in fact the
  95 * "on" time, so this translates directly into our HW programming here.
  96 */
  97static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  98                              int duty_ns, int period_ns)
  99{
 100        struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
 101        unsigned long pc, dc, cword = CONST_VAR_F_MAX;
 102        unsigned int channel = pwm->hwpwm;
 103        u32 value;
 104
 105        /*
 106         * If asking for a duty_ns equal to period_ns, we need to substract
 107         * the period value by 1 to make it shorter than the "on" time and
 108         * produce a flat 100% duty cycle signal, and max out the "on" time
 109         */
 110        if (duty_ns == period_ns) {
 111                dc = PWM_ON_PERIOD_MAX;
 112                pc = PWM_ON_PERIOD_MAX - 1;
 113                goto done;
 114        }
 115
 116        while (1) {
 117                u64 rate, tmp;
 118
 119                /*
 120                 * Calculate the base rate from base frequency and current
 121                 * cword
 122                 */
 123                rate = (u64)clk_get_rate(p->clk) * (u64)cword;
 124                do_div(rate, 1 << CWORD_BIT_SIZE);
 125
 126                tmp = period_ns * rate;
 127                do_div(tmp, NSEC_PER_SEC);
 128                pc = tmp;
 129
 130                tmp = (duty_ns + 1) * rate;
 131                do_div(tmp, NSEC_PER_SEC);
 132                dc = tmp;
 133
 134                /*
 135                 * We can be called with separate duty and period updates,
 136                 * so do not reject dc == 0 right away
 137                 */
 138                if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
 139                        return -EINVAL;
 140
 141                /* We converged on a calculation */
 142                if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
 143                        break;
 144
 145                /*
 146                 * The cword needs to be a power of 2 for the variable
 147                 * frequency generator to output a 50% duty cycle variable
 148                 * frequency which is used as input clock to the fixed
 149                 * frequency generator.
 150                 */
 151                cword >>= 1;
 152
 153                /*
 154                 * Desired periods are too large, we do not have a divider
 155                 * for them
 156                 */
 157                if (cword < CONST_VAR_F_MIN)
 158                        return -EINVAL;
 159        }
 160
 161done:
 162        /*
 163         * Configure the defined "cword" value to have the variable frequency
 164         * generator output a base frequency for the constant frequency
 165         * generator to derive from.
 166         */
 167        spin_lock(&p->lock);
 168        brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
 169        brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
 170
 171        /* Select constant frequency signal output */
 172        value = brcmstb_pwm_readl(p, PWM_CTRL2);
 173        value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
 174        brcmstb_pwm_writel(p, value, PWM_CTRL2);
 175
 176        /* Configure on and period value */
 177        brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
 178        brcmstb_pwm_writel(p, dc, PWM_ON(channel));
 179        spin_unlock(&p->lock);
 180
 181        return 0;
 182}
 183
 184static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
 185                                          unsigned int channel, bool enable)
 186{
 187        unsigned int shift = channel * CTRL_CHAN_OFFS;
 188        u32 value;
 189
 190        spin_lock(&p->lock);
 191        value = brcmstb_pwm_readl(p, PWM_CTRL);
 192
 193        if (enable) {
 194                value &= ~(CTRL_OEB << shift);
 195                value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
 196        } else {
 197                value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
 198                value |= CTRL_OEB << shift;
 199        }
 200
 201        brcmstb_pwm_writel(p, value, PWM_CTRL);
 202        spin_unlock(&p->lock);
 203}
 204
 205static int brcmstb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 206{
 207        struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
 208
 209        brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
 210
 211        return 0;
 212}
 213
 214static void brcmstb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 215{
 216        struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
 217
 218        brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
 219}
 220
 221static const struct pwm_ops brcmstb_pwm_ops = {
 222        .config = brcmstb_pwm_config,
 223        .enable = brcmstb_pwm_enable,
 224        .disable = brcmstb_pwm_disable,
 225        .owner = THIS_MODULE,
 226};
 227
 228static const struct of_device_id brcmstb_pwm_of_match[] = {
 229        { .compatible = "brcm,bcm7038-pwm", },
 230        { /* sentinel */ }
 231};
 232MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
 233
 234static int brcmstb_pwm_probe(struct platform_device *pdev)
 235{
 236        struct brcmstb_pwm *p;
 237        struct resource *res;
 238        int ret;
 239
 240        p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
 241        if (!p)
 242                return -ENOMEM;
 243
 244        spin_lock_init(&p->lock);
 245
 246        p->clk = devm_clk_get(&pdev->dev, NULL);
 247        if (IS_ERR(p->clk)) {
 248                dev_err(&pdev->dev, "failed to obtain clock\n");
 249                return PTR_ERR(p->clk);
 250        }
 251
 252        ret = clk_prepare_enable(p->clk);
 253        if (ret < 0) {
 254                dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
 255                return ret;
 256        }
 257
 258        platform_set_drvdata(pdev, p);
 259
 260        p->chip.dev = &pdev->dev;
 261        p->chip.ops = &brcmstb_pwm_ops;
 262        p->chip.base = -1;
 263        p->chip.npwm = 2;
 264
 265        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 266        p->base = devm_ioremap_resource(&pdev->dev, res);
 267        if (IS_ERR(p->base)) {
 268                ret = PTR_ERR(p->base);
 269                goto out_clk;
 270        }
 271
 272        ret = pwmchip_add(&p->chip);
 273        if (ret) {
 274                dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
 275                goto out_clk;
 276        }
 277
 278        return 0;
 279
 280out_clk:
 281        clk_disable_unprepare(p->clk);
 282        return ret;
 283}
 284
 285static int brcmstb_pwm_remove(struct platform_device *pdev)
 286{
 287        struct brcmstb_pwm *p = platform_get_drvdata(pdev);
 288        int ret;
 289
 290        ret = pwmchip_remove(&p->chip);
 291        clk_disable_unprepare(p->clk);
 292
 293        return ret;
 294}
 295
 296#ifdef CONFIG_PM_SLEEP
 297static int brcmstb_pwm_suspend(struct device *dev)
 298{
 299        struct brcmstb_pwm *p = dev_get_drvdata(dev);
 300
 301        clk_disable(p->clk);
 302
 303        return 0;
 304}
 305
 306static int brcmstb_pwm_resume(struct device *dev)
 307{
 308        struct brcmstb_pwm *p = dev_get_drvdata(dev);
 309
 310        clk_enable(p->clk);
 311
 312        return 0;
 313}
 314#endif
 315
 316static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
 317                         brcmstb_pwm_resume);
 318
 319static struct platform_driver brcmstb_pwm_driver = {
 320        .probe = brcmstb_pwm_probe,
 321        .remove = brcmstb_pwm_remove,
 322        .driver = {
 323                .name = "pwm-brcmstb",
 324                .of_match_table = brcmstb_pwm_of_match,
 325                .pm = &brcmstb_pwm_pm_ops,
 326        },
 327};
 328module_platform_driver(brcmstb_pwm_driver);
 329
 330MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
 331MODULE_DESCRIPTION("Broadcom STB PWM driver");
 332MODULE_ALIAS("platform:pwm-brcmstb");
 333MODULE_LICENSE("GPL");
 334