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9#include <linux/clk.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16#include <linux/time.h>
17
18#define PWM_CTRL_TIMER_EN (1 << 0)
19#define PWM_CTRL_OUTPUT_EN (1 << 3)
20
21#define PWM_ENABLE (1 << 0)
22#define PWM_CONTINUOUS (1 << 1)
23#define PWM_DUTY_POSITIVE (1 << 3)
24#define PWM_DUTY_NEGATIVE (0 << 3)
25#define PWM_INACTIVE_NEGATIVE (0 << 4)
26#define PWM_INACTIVE_POSITIVE (1 << 4)
27#define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
28#define PWM_OUTPUT_LEFT (0 << 5)
29#define PWM_LOCK_EN (1 << 6)
30#define PWM_LP_DISABLE (0 << 8)
31
32struct rockchip_pwm_chip {
33 struct pwm_chip chip;
34 struct clk *clk;
35 struct clk *pclk;
36 const struct rockchip_pwm_data *data;
37 void __iomem *base;
38};
39
40struct rockchip_pwm_regs {
41 unsigned long duty;
42 unsigned long period;
43 unsigned long cntr;
44 unsigned long ctrl;
45};
46
47struct rockchip_pwm_data {
48 struct rockchip_pwm_regs regs;
49 unsigned int prescaler;
50 bool supports_polarity;
51 bool supports_lock;
52 u32 enable_conf;
53};
54
55static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
56{
57 return container_of(c, struct rockchip_pwm_chip, chip);
58}
59
60static void rockchip_pwm_get_state(struct pwm_chip *chip,
61 struct pwm_device *pwm,
62 struct pwm_state *state)
63{
64 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
65 u32 enable_conf = pc->data->enable_conf;
66 unsigned long clk_rate;
67 u64 tmp;
68 u32 val;
69 int ret;
70
71 ret = clk_enable(pc->pclk);
72 if (ret)
73 return;
74
75 clk_rate = clk_get_rate(pc->clk);
76
77 tmp = readl_relaxed(pc->base + pc->data->regs.period);
78 tmp *= pc->data->prescaler * NSEC_PER_SEC;
79 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
80
81 tmp = readl_relaxed(pc->base + pc->data->regs.duty);
82 tmp *= pc->data->prescaler * NSEC_PER_SEC;
83 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
84
85 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
86 if (pc->data->supports_polarity)
87 state->enabled = ((val & enable_conf) != enable_conf) ?
88 false : true;
89 else
90 state->enabled = ((val & enable_conf) == enable_conf) ?
91 true : false;
92
93 if (pc->data->supports_polarity) {
94 if (!(val & PWM_DUTY_POSITIVE))
95 state->polarity = PWM_POLARITY_INVERSED;
96 }
97
98 clk_disable(pc->pclk);
99}
100
101static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
102 struct pwm_state *state)
103{
104 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
105 unsigned long period, duty;
106 u64 clk_rate, div;
107 u32 ctrl;
108
109 clk_rate = clk_get_rate(pc->clk);
110
111
112
113
114
115
116 div = clk_rate * state->period;
117 period = DIV_ROUND_CLOSEST_ULL(div,
118 pc->data->prescaler * NSEC_PER_SEC);
119
120 div = clk_rate * state->duty_cycle;
121 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
122
123
124
125
126
127 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
128 if (pc->data->supports_lock) {
129 ctrl |= PWM_LOCK_EN;
130 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
131 }
132
133 writel(period, pc->base + pc->data->regs.period);
134 writel(duty, pc->base + pc->data->regs.duty);
135
136 if (pc->data->supports_polarity) {
137 ctrl &= ~PWM_POLARITY_MASK;
138 if (state->polarity == PWM_POLARITY_INVERSED)
139 ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
140 else
141 ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
142 }
143
144
145
146
147
148
149 if (pc->data->supports_lock)
150 ctrl &= ~PWM_LOCK_EN;
151
152 writel(ctrl, pc->base + pc->data->regs.ctrl);
153}
154
155static int rockchip_pwm_enable(struct pwm_chip *chip,
156 struct pwm_device *pwm,
157 bool enable)
158{
159 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
160 u32 enable_conf = pc->data->enable_conf;
161 int ret;
162 u32 val;
163
164 if (enable) {
165 ret = clk_enable(pc->clk);
166 if (ret)
167 return ret;
168 }
169
170 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
171
172 if (enable)
173 val |= enable_conf;
174 else
175 val &= ~enable_conf;
176
177 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
178
179 if (!enable)
180 clk_disable(pc->clk);
181
182 return 0;
183}
184
185static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
186 struct pwm_state *state)
187{
188 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
189 struct pwm_state curstate;
190 bool enabled;
191 int ret = 0;
192
193 ret = clk_enable(pc->pclk);
194 if (ret)
195 return ret;
196
197 pwm_get_state(pwm, &curstate);
198 enabled = curstate.enabled;
199
200 if (state->polarity != curstate.polarity && enabled &&
201 !pc->data->supports_lock) {
202 ret = rockchip_pwm_enable(chip, pwm, false);
203 if (ret)
204 goto out;
205 enabled = false;
206 }
207
208 rockchip_pwm_config(chip, pwm, state);
209 if (state->enabled != enabled) {
210 ret = rockchip_pwm_enable(chip, pwm, state->enabled);
211 if (ret)
212 goto out;
213 }
214
215
216
217
218
219 rockchip_pwm_get_state(chip, pwm, state);
220
221out:
222 clk_disable(pc->pclk);
223
224 return ret;
225}
226
227static const struct pwm_ops rockchip_pwm_ops = {
228 .get_state = rockchip_pwm_get_state,
229 .apply = rockchip_pwm_apply,
230 .owner = THIS_MODULE,
231};
232
233static const struct rockchip_pwm_data pwm_data_v1 = {
234 .regs = {
235 .duty = 0x04,
236 .period = 0x08,
237 .cntr = 0x00,
238 .ctrl = 0x0c,
239 },
240 .prescaler = 2,
241 .supports_polarity = false,
242 .supports_lock = false,
243 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
244};
245
246static const struct rockchip_pwm_data pwm_data_v2 = {
247 .regs = {
248 .duty = 0x08,
249 .period = 0x04,
250 .cntr = 0x00,
251 .ctrl = 0x0c,
252 },
253 .prescaler = 1,
254 .supports_polarity = true,
255 .supports_lock = false,
256 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
257 PWM_CONTINUOUS,
258};
259
260static const struct rockchip_pwm_data pwm_data_vop = {
261 .regs = {
262 .duty = 0x08,
263 .period = 0x04,
264 .cntr = 0x0c,
265 .ctrl = 0x00,
266 },
267 .prescaler = 1,
268 .supports_polarity = true,
269 .supports_lock = false,
270 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
271 PWM_CONTINUOUS,
272};
273
274static const struct rockchip_pwm_data pwm_data_v3 = {
275 .regs = {
276 .duty = 0x08,
277 .period = 0x04,
278 .cntr = 0x00,
279 .ctrl = 0x0c,
280 },
281 .prescaler = 1,
282 .supports_polarity = true,
283 .supports_lock = true,
284 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
285 PWM_CONTINUOUS,
286};
287
288static const struct of_device_id rockchip_pwm_dt_ids[] = {
289 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
290 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
291 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
292 { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
293 { }
294};
295MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
296
297static int rockchip_pwm_probe(struct platform_device *pdev)
298{
299 const struct of_device_id *id;
300 struct rockchip_pwm_chip *pc;
301 struct resource *r;
302 int ret, count;
303
304 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
305 if (!id)
306 return -EINVAL;
307
308 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
309 if (!pc)
310 return -ENOMEM;
311
312 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
313 pc->base = devm_ioremap_resource(&pdev->dev, r);
314 if (IS_ERR(pc->base))
315 return PTR_ERR(pc->base);
316
317 pc->clk = devm_clk_get(&pdev->dev, "pwm");
318 if (IS_ERR(pc->clk)) {
319 pc->clk = devm_clk_get(&pdev->dev, NULL);
320 if (IS_ERR(pc->clk)) {
321 ret = PTR_ERR(pc->clk);
322 if (ret != -EPROBE_DEFER)
323 dev_err(&pdev->dev, "Can't get bus clk: %d\n",
324 ret);
325 return ret;
326 }
327 }
328
329 count = of_count_phandle_with_args(pdev->dev.of_node,
330 "clocks", "#clock-cells");
331 if (count == 2)
332 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
333 else
334 pc->pclk = pc->clk;
335
336 if (IS_ERR(pc->pclk)) {
337 ret = PTR_ERR(pc->pclk);
338 if (ret != -EPROBE_DEFER)
339 dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
340 return ret;
341 }
342
343 ret = clk_prepare_enable(pc->clk);
344 if (ret) {
345 dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
346 return ret;
347 }
348
349 ret = clk_prepare(pc->pclk);
350 if (ret) {
351 dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
352 goto err_clk;
353 }
354
355 platform_set_drvdata(pdev, pc);
356
357 pc->data = id->data;
358 pc->chip.dev = &pdev->dev;
359 pc->chip.ops = &rockchip_pwm_ops;
360 pc->chip.base = -1;
361 pc->chip.npwm = 1;
362
363 if (pc->data->supports_polarity) {
364 pc->chip.of_xlate = of_pwm_xlate_with_flags;
365 pc->chip.of_pwm_n_cells = 3;
366 }
367
368 ret = pwmchip_add(&pc->chip);
369 if (ret < 0) {
370 clk_unprepare(pc->clk);
371 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
372 goto err_pclk;
373 }
374
375
376 if (!pwm_is_enabled(pc->chip.pwms))
377 clk_disable(pc->clk);
378
379 return 0;
380
381err_pclk:
382 clk_unprepare(pc->pclk);
383err_clk:
384 clk_disable_unprepare(pc->clk);
385
386 return ret;
387}
388
389static int rockchip_pwm_remove(struct platform_device *pdev)
390{
391 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
392
393
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397
398
399
400
401
402
403
404 if (pwm_is_enabled(pc->chip.pwms))
405 clk_disable(pc->clk);
406
407 clk_unprepare(pc->pclk);
408 clk_unprepare(pc->clk);
409
410 return pwmchip_remove(&pc->chip);
411}
412
413static struct platform_driver rockchip_pwm_driver = {
414 .driver = {
415 .name = "rockchip-pwm",
416 .of_match_table = rockchip_pwm_dt_ids,
417 },
418 .probe = rockchip_pwm_probe,
419 .remove = rockchip_pwm_remove,
420};
421module_platform_driver(rockchip_pwm_driver);
422
423MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
424MODULE_DESCRIPTION("Rockchip SoC PWM driver");
425MODULE_LICENSE("GPL v2");
426
