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8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/err.h>
12#include <linux/platform_device.h>
13#include <linux/regulator/driver.h>
14#include <linux/regulator/machine.h>
15#include <linux/mfd/ezx-pcap.h>
16
17static const unsigned int V1_table[] = {
18 2775000, 1275000, 1600000, 1725000, 1825000, 1925000, 2075000, 2275000,
19};
20
21static const unsigned int V2_table[] = {
22 2500000, 2775000,
23};
24
25static const unsigned int V3_table[] = {
26 1075000, 1275000, 1550000, 1725000, 1876000, 1950000, 2075000, 2275000,
27};
28
29static const unsigned int V4_table[] = {
30 1275000, 1550000, 1725000, 1875000, 1950000, 2075000, 2275000, 2775000,
31};
32
33static const unsigned int V5_table[] = {
34 1875000, 2275000, 2475000, 2775000,
35};
36
37static const unsigned int V6_table[] = {
38 2475000, 2775000,
39};
40
41static const unsigned int V7_table[] = {
42 1875000, 2775000,
43};
44
45#define V8_table V4_table
46
47static const unsigned int V9_table[] = {
48 1575000, 1875000, 2475000, 2775000,
49};
50
51static const unsigned int V10_table[] = {
52 5000000,
53};
54
55static const unsigned int VAUX1_table[] = {
56 1875000, 2475000, 2775000, 3000000,
57};
58
59#define VAUX2_table VAUX1_table
60
61static const unsigned int VAUX3_table[] = {
62 1200000, 1200000, 1200000, 1200000, 1400000, 1600000, 1800000, 2000000,
63 2200000, 2400000, 2600000, 2800000, 3000000, 3200000, 3400000, 3600000,
64};
65
66static const unsigned int VAUX4_table[] = {
67 1800000, 1800000, 3000000, 5000000,
68};
69
70static const unsigned int VSIM_table[] = {
71 1875000, 3000000,
72};
73
74static const unsigned int VSIM2_table[] = {
75 1875000,
76};
77
78static const unsigned int VVIB_table[] = {
79 1300000, 1800000, 2000000, 3000000,
80};
81
82static const unsigned int SW1_table[] = {
83 900000, 950000, 1000000, 1050000, 1100000, 1150000, 1200000, 1250000,
84 1300000, 1350000, 1400000, 1450000, 1500000, 1600000, 1875000, 2250000,
85};
86
87#define SW2_table SW1_table
88
89static const unsigned int SW3_table[] = {
90 4000000, 4500000, 5000000, 5500000,
91};
92
93struct pcap_regulator {
94 const u8 reg;
95 const u8 en;
96 const u8 index;
97 const u8 stby;
98 const u8 lowpwr;
99};
100
101#define NA 0xff
102
103#define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \
104 [_vreg] = { \
105 .reg = _reg, \
106 .en = _en, \
107 .index = _index, \
108 .stby = _stby, \
109 .lowpwr = _lowpwr, \
110 }
111
112static struct pcap_regulator vreg_table[] = {
113 VREG_INFO(V1, PCAP_REG_VREG1, 1, 2, 18, 0),
114 VREG_INFO(V2, PCAP_REG_VREG1, 5, 6, 19, 22),
115 VREG_INFO(V3, PCAP_REG_VREG1, 7, 8, 20, 23),
116 VREG_INFO(V4, PCAP_REG_VREG1, 11, 12, 21, 24),
117
118 VREG_INFO(V5, PCAP_REG_VREG1, 15, 16, 12, 19),
119
120 VREG_INFO(V6, PCAP_REG_VREG2, 1, 2, 14, 20),
121 VREG_INFO(V7, PCAP_REG_VREG2, 3, 4, 15, 21),
122 VREG_INFO(V8, PCAP_REG_VREG2, 5, 6, 16, 22),
123 VREG_INFO(V9, PCAP_REG_VREG2, 9, 10, 17, 23),
124 VREG_INFO(V10, PCAP_REG_VREG2, 10, NA, 18, 24),
125
126 VREG_INFO(VAUX1, PCAP_REG_AUXVREG, 1, 2, 22, 23),
127
128 VREG_INFO(VAUX2, PCAP_REG_AUXVREG, 4, 5, 0, 1),
129 VREG_INFO(VAUX3, PCAP_REG_AUXVREG, 7, 8, 2, 3),
130 VREG_INFO(VAUX4, PCAP_REG_AUXVREG, 12, 13, 4, 5),
131 VREG_INFO(VSIM, PCAP_REG_AUXVREG, 17, 18, NA, 6),
132 VREG_INFO(VSIM2, PCAP_REG_AUXVREG, 16, NA, NA, 7),
133 VREG_INFO(VVIB, PCAP_REG_AUXVREG, 19, 20, NA, NA),
134
135 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
136 VREG_INFO(SW2, PCAP_REG_SWCTRL, 6, 7, NA, NA),
137
138 VREG_INFO(SW3, PCAP_REG_SWCTRL, 11, 12, 24, NA),
139
140
141
142
143};
144
145static int pcap_regulator_set_voltage_sel(struct regulator_dev *rdev,
146 unsigned selector)
147{
148 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
149 void *pcap = rdev_get_drvdata(rdev);
150
151
152 if (rdev->desc->n_voltages == 1)
153 return -EINVAL;
154
155 return ezx_pcap_set_bits(pcap, vreg->reg,
156 (rdev->desc->n_voltages - 1) << vreg->index,
157 selector << vreg->index);
158}
159
160static int pcap_regulator_get_voltage_sel(struct regulator_dev *rdev)
161{
162 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
163 void *pcap = rdev_get_drvdata(rdev);
164 u32 tmp;
165
166 if (rdev->desc->n_voltages == 1)
167 return 0;
168
169 ezx_pcap_read(pcap, vreg->reg, &tmp);
170 tmp = ((tmp >> vreg->index) & (rdev->desc->n_voltages - 1));
171 return tmp;
172}
173
174static int pcap_regulator_enable(struct regulator_dev *rdev)
175{
176 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
177 void *pcap = rdev_get_drvdata(rdev);
178
179 if (vreg->en == NA)
180 return -EINVAL;
181
182 return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 1 << vreg->en);
183}
184
185static int pcap_regulator_disable(struct regulator_dev *rdev)
186{
187 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
188 void *pcap = rdev_get_drvdata(rdev);
189
190 if (vreg->en == NA)
191 return -EINVAL;
192
193 return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 0);
194}
195
196static int pcap_regulator_is_enabled(struct regulator_dev *rdev)
197{
198 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
199 void *pcap = rdev_get_drvdata(rdev);
200 u32 tmp;
201
202 if (vreg->en == NA)
203 return -EINVAL;
204
205 ezx_pcap_read(pcap, vreg->reg, &tmp);
206 return (tmp >> vreg->en) & 1;
207}
208
209static const struct regulator_ops pcap_regulator_ops = {
210 .list_voltage = regulator_list_voltage_table,
211 .set_voltage_sel = pcap_regulator_set_voltage_sel,
212 .get_voltage_sel = pcap_regulator_get_voltage_sel,
213 .enable = pcap_regulator_enable,
214 .disable = pcap_regulator_disable,
215 .is_enabled = pcap_regulator_is_enabled,
216};
217
218#define VREG(_vreg) \
219 [_vreg] = { \
220 .name = #_vreg, \
221 .id = _vreg, \
222 .n_voltages = ARRAY_SIZE(_vreg##_table), \
223 .volt_table = _vreg##_table, \
224 .ops = &pcap_regulator_ops, \
225 .type = REGULATOR_VOLTAGE, \
226 .owner = THIS_MODULE, \
227 }
228
229static const struct regulator_desc pcap_regulators[] = {
230 VREG(V1), VREG(V2), VREG(V3), VREG(V4), VREG(V5), VREG(V6), VREG(V7),
231 VREG(V8), VREG(V9), VREG(V10), VREG(VAUX1), VREG(VAUX2), VREG(VAUX3),
232 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
233};
234
235static int pcap_regulator_probe(struct platform_device *pdev)
236{
237 struct regulator_dev *rdev;
238 void *pcap = dev_get_drvdata(pdev->dev.parent);
239 struct regulator_config config = { };
240
241 config.dev = &pdev->dev;
242 config.init_data = dev_get_platdata(&pdev->dev);
243 config.driver_data = pcap;
244
245 rdev = devm_regulator_register(&pdev->dev, &pcap_regulators[pdev->id],
246 &config);
247 if (IS_ERR(rdev))
248 return PTR_ERR(rdev);
249
250 platform_set_drvdata(pdev, rdev);
251
252 return 0;
253}
254
255static struct platform_driver pcap_regulator_driver = {
256 .driver = {
257 .name = "pcap-regulator",
258 },
259 .probe = pcap_regulator_probe,
260};
261
262static int __init pcap_regulator_init(void)
263{
264 return platform_driver_register(&pcap_regulator_driver);
265}
266
267static void __exit pcap_regulator_exit(void)
268{
269 platform_driver_unregister(&pcap_regulator_driver);
270}
271
272subsys_initcall(pcap_regulator_init);
273module_exit(pcap_regulator_exit);
274
275MODULE_AUTHOR("Daniel Ribeiro <drwyrm@gmail.com>");
276MODULE_DESCRIPTION("PCAP2 Regulator Driver");
277MODULE_LICENSE("GPL");
278
