linux/drivers/scsi/csiostor/csio_hw.c
<<
>>
Prefs
   1/*
   2 * This file is part of the Chelsio FCoE driver for Linux.
   3 *
   4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
   5 *
   6 * This software is available to you under a choice of one of two
   7 * licenses.  You may choose to be licensed under the terms of the GNU
   8 * General Public License (GPL) Version 2, available from the file
   9 * COPYING in the main directory of this source tree, or the
  10 * OpenIB.org BSD license below:
  11 *
  12 *     Redistribution and use in source and binary forms, with or
  13 *     without modification, are permitted provided that the following
  14 *     conditions are met:
  15 *
  16 *      - Redistributions of source code must retain the above
  17 *        copyright notice, this list of conditions and the following
  18 *        disclaimer.
  19 *
  20 *      - Redistributions in binary form must reproduce the above
  21 *        copyright notice, this list of conditions and the following
  22 *        disclaimer in the documentation and/or other materials
  23 *        provided with the distribution.
  24 *
  25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32 * SOFTWARE.
  33 */
  34
  35#include <linux/pci.h>
  36#include <linux/pci_regs.h>
  37#include <linux/firmware.h>
  38#include <linux/stddef.h>
  39#include <linux/delay.h>
  40#include <linux/string.h>
  41#include <linux/compiler.h>
  42#include <linux/jiffies.h>
  43#include <linux/kernel.h>
  44#include <linux/log2.h>
  45
  46#include "csio_hw.h"
  47#include "csio_lnode.h"
  48#include "csio_rnode.h"
  49
  50int csio_dbg_level = 0xFEFF;
  51unsigned int csio_port_mask = 0xf;
  52
  53/* Default FW event queue entries. */
  54static uint32_t csio_evtq_sz = CSIO_EVTQ_SIZE;
  55
  56/* Default MSI param level */
  57int csio_msi = 2;
  58
  59/* FCoE function instances */
  60static int dev_num;
  61
  62/* FCoE Adapter types & its description */
  63static const struct csio_adap_desc csio_t5_fcoe_adapters[] = {
  64        {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
  65        {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
  66        {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
  67        {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
  68        {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
  69        {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
  70        {"T540-CH 10G", "Chelsio T540-CH 10G [FCoE]"},
  71        {"T520-SO 10G", "Chelsio T520-SO 10G [FCoE]"},
  72        {"T520-CX4 10G", "Chelsio T520-CX4 10G [FCoE]"},
  73        {"T520-BT 10G", "Chelsio T520-BT 10G [FCoE]"},
  74        {"T504-BT 1G", "Chelsio T504-BT 1G [FCoE]"},
  75        {"B520-SR 10G", "Chelsio B520-SR 10G [FCoE]"},
  76        {"B504-BT 1G", "Chelsio B504-BT 1G [FCoE]"},
  77        {"T580-CR 10G", "Chelsio T580-CR 10G [FCoE]"},
  78        {"T540-LP-CR 10G", "Chelsio T540-LP-CR 10G [FCoE]"},
  79        {"AMSTERDAM 10G", "Chelsio AMSTERDAM 10G [FCoE]"},
  80        {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"},
  81        {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"},
  82        {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"},
  83        {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"},
  84        {"T580-SO 40G", "Chelsio T580-SO 40G [FCoE]"},
  85        {"T502-BT 1G", "Chelsio T502-BT 1G [FCoE]"}
  86};
  87
  88static void csio_mgmtm_cleanup(struct csio_mgmtm *);
  89static void csio_hw_mbm_cleanup(struct csio_hw *);
  90
  91/* State machine forward declarations */
  92static void csio_hws_uninit(struct csio_hw *, enum csio_hw_ev);
  93static void csio_hws_configuring(struct csio_hw *, enum csio_hw_ev);
  94static void csio_hws_initializing(struct csio_hw *, enum csio_hw_ev);
  95static void csio_hws_ready(struct csio_hw *, enum csio_hw_ev);
  96static void csio_hws_quiescing(struct csio_hw *, enum csio_hw_ev);
  97static void csio_hws_quiesced(struct csio_hw *, enum csio_hw_ev);
  98static void csio_hws_resetting(struct csio_hw *, enum csio_hw_ev);
  99static void csio_hws_removing(struct csio_hw *, enum csio_hw_ev);
 100static void csio_hws_pcierr(struct csio_hw *, enum csio_hw_ev);
 101
 102static void csio_hw_initialize(struct csio_hw *hw);
 103static void csio_evtq_stop(struct csio_hw *hw);
 104static void csio_evtq_start(struct csio_hw *hw);
 105
 106int csio_is_hw_ready(struct csio_hw *hw)
 107{
 108        return csio_match_state(hw, csio_hws_ready);
 109}
 110
 111int csio_is_hw_removing(struct csio_hw *hw)
 112{
 113        return csio_match_state(hw, csio_hws_removing);
 114}
 115
 116
 117/*
 118 *      csio_hw_wait_op_done_val - wait until an operation is completed
 119 *      @hw: the HW module
 120 *      @reg: the register to check for completion
 121 *      @mask: a single-bit field within @reg that indicates completion
 122 *      @polarity: the value of the field when the operation is completed
 123 *      @attempts: number of check iterations
 124 *      @delay: delay in usecs between iterations
 125 *      @valp: where to store the value of the register at completion time
 126 *
 127 *      Wait until an operation is completed by checking a bit in a register
 128 *      up to @attempts times.  If @valp is not NULL the value of the register
 129 *      at the time it indicated completion is stored there.  Returns 0 if the
 130 *      operation completes and -EAGAIN otherwise.
 131 */
 132int
 133csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask,
 134                         int polarity, int attempts, int delay, uint32_t *valp)
 135{
 136        uint32_t val;
 137        while (1) {
 138                val = csio_rd_reg32(hw, reg);
 139
 140                if (!!(val & mask) == polarity) {
 141                        if (valp)
 142                                *valp = val;
 143                        return 0;
 144                }
 145
 146                if (--attempts == 0)
 147                        return -EAGAIN;
 148                if (delay)
 149                        udelay(delay);
 150        }
 151}
 152
 153/*
 154 *      csio_hw_tp_wr_bits_indirect - set/clear bits in an indirect TP register
 155 *      @hw: the adapter
 156 *      @addr: the indirect TP register address
 157 *      @mask: specifies the field within the register to modify
 158 *      @val: new value for the field
 159 *
 160 *      Sets a field of an indirect TP register to the given value.
 161 */
 162void
 163csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr,
 164                        unsigned int mask, unsigned int val)
 165{
 166        csio_wr_reg32(hw, addr, TP_PIO_ADDR_A);
 167        val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
 168        csio_wr_reg32(hw, val, TP_PIO_DATA_A);
 169}
 170
 171void
 172csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask,
 173                   uint32_t value)
 174{
 175        uint32_t val = csio_rd_reg32(hw, reg) & ~mask;
 176
 177        csio_wr_reg32(hw, val | value, reg);
 178        /* Flush */
 179        csio_rd_reg32(hw, reg);
 180
 181}
 182
 183static int
 184csio_memory_write(struct csio_hw *hw, int mtype, u32 addr, u32 len, u32 *buf)
 185{
 186        return hw->chip_ops->chip_memory_rw(hw, MEMWIN_CSIOSTOR, mtype,
 187                                            addr, len, buf, 0);
 188}
 189
 190/*
 191 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
 192 */
 193#define EEPROM_MAX_RD_POLL      40
 194#define EEPROM_MAX_WR_POLL      6
 195#define EEPROM_STAT_ADDR        0x7bfc
 196#define VPD_BASE                0x400
 197#define VPD_BASE_OLD            0
 198#define VPD_LEN                 1024
 199#define VPD_INFO_FLD_HDR_SIZE   3
 200
 201/*
 202 *      csio_hw_seeprom_read - read a serial EEPROM location
 203 *      @hw: hw to read
 204 *      @addr: EEPROM virtual address
 205 *      @data: where to store the read data
 206 *
 207 *      Read a 32-bit word from a location in serial EEPROM using the card's PCI
 208 *      VPD capability.  Note that this function must be called with a virtual
 209 *      address.
 210 */
 211static int
 212csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data)
 213{
 214        uint16_t val = 0;
 215        int attempts = EEPROM_MAX_RD_POLL;
 216        uint32_t base = hw->params.pci.vpd_cap_addr;
 217
 218        if (addr >= EEPROMVSIZE || (addr & 3))
 219                return -EINVAL;
 220
 221        pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr);
 222
 223        do {
 224                udelay(10);
 225                pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val);
 226        } while (!(val & PCI_VPD_ADDR_F) && --attempts);
 227
 228        if (!(val & PCI_VPD_ADDR_F)) {
 229                csio_err(hw, "reading EEPROM address 0x%x failed\n", addr);
 230                return -EINVAL;
 231        }
 232
 233        pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data);
 234        *data = le32_to_cpu(*(__le32 *)data);
 235
 236        return 0;
 237}
 238
 239/*
 240 * Partial EEPROM Vital Product Data structure.  Includes only the ID and
 241 * VPD-R sections.
 242 */
 243struct t4_vpd_hdr {
 244        u8  id_tag;
 245        u8  id_len[2];
 246        u8  id_data[ID_LEN];
 247        u8  vpdr_tag;
 248        u8  vpdr_len[2];
 249};
 250
 251/*
 252 *      csio_hw_get_vpd_keyword_val - Locates an information field keyword in
 253 *                                    the VPD
 254 *      @v: Pointer to buffered vpd data structure
 255 *      @kw: The keyword to search for
 256 *
 257 *      Returns the value of the information field keyword or
 258 *      -EINVAL otherwise.
 259 */
 260static int
 261csio_hw_get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
 262{
 263        int32_t i;
 264        int32_t offset , len;
 265        const uint8_t *buf = &v->id_tag;
 266        const uint8_t *vpdr_len = &v->vpdr_tag;
 267        offset = sizeof(struct t4_vpd_hdr);
 268        len =  (uint16_t)vpdr_len[1] + ((uint16_t)vpdr_len[2] << 8);
 269
 270        if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN)
 271                return -EINVAL;
 272
 273        for (i = offset; (i + VPD_INFO_FLD_HDR_SIZE) <= (offset + len);) {
 274                if (memcmp(buf + i , kw, 2) == 0) {
 275                        i += VPD_INFO_FLD_HDR_SIZE;
 276                        return i;
 277                }
 278
 279                i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
 280        }
 281
 282        return -EINVAL;
 283}
 284
 285static int
 286csio_pci_capability(struct pci_dev *pdev, int cap, int *pos)
 287{
 288        *pos = pci_find_capability(pdev, cap);
 289        if (*pos)
 290                return 0;
 291
 292        return -1;
 293}
 294
 295/*
 296 *      csio_hw_get_vpd_params - read VPD parameters from VPD EEPROM
 297 *      @hw: HW module
 298 *      @p: where to store the parameters
 299 *
 300 *      Reads card parameters stored in VPD EEPROM.
 301 */
 302static int
 303csio_hw_get_vpd_params(struct csio_hw *hw, struct csio_vpd *p)
 304{
 305        int i, ret, ec, sn, addr;
 306        uint8_t *vpd, csum;
 307        const struct t4_vpd_hdr *v;
 308        /* To get around compilation warning from strstrip */
 309        char *s;
 310
 311        if (csio_is_valid_vpd(hw))
 312                return 0;
 313
 314        ret = csio_pci_capability(hw->pdev, PCI_CAP_ID_VPD,
 315                                  &hw->params.pci.vpd_cap_addr);
 316        if (ret)
 317                return -EINVAL;
 318
 319        vpd = kzalloc(VPD_LEN, GFP_ATOMIC);
 320        if (vpd == NULL)
 321                return -ENOMEM;
 322
 323        /*
 324         * Card information normally starts at VPD_BASE but early cards had
 325         * it at 0.
 326         */
 327        ret = csio_hw_seeprom_read(hw, VPD_BASE, (uint32_t *)(vpd));
 328        addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD;
 329
 330        for (i = 0; i < VPD_LEN; i += 4) {
 331                ret = csio_hw_seeprom_read(hw, addr + i, (uint32_t *)(vpd + i));
 332                if (ret) {
 333                        kfree(vpd);
 334                        return ret;
 335                }
 336        }
 337
 338        /* Reset the VPD flag! */
 339        hw->flags &= (~CSIO_HWF_VPD_VALID);
 340
 341        v = (const struct t4_vpd_hdr *)vpd;
 342
 343#define FIND_VPD_KW(var, name) do { \
 344        var = csio_hw_get_vpd_keyword_val(v, name); \
 345        if (var < 0) { \
 346                csio_err(hw, "missing VPD keyword " name "\n"); \
 347                kfree(vpd); \
 348                return -EINVAL; \
 349        } \
 350} while (0)
 351
 352        FIND_VPD_KW(i, "RV");
 353        for (csum = 0; i >= 0; i--)
 354                csum += vpd[i];
 355
 356        if (csum) {
 357                csio_err(hw, "corrupted VPD EEPROM, actual csum %u\n", csum);
 358                kfree(vpd);
 359                return -EINVAL;
 360        }
 361        FIND_VPD_KW(ec, "EC");
 362        FIND_VPD_KW(sn, "SN");
 363#undef FIND_VPD_KW
 364
 365        memcpy(p->id, v->id_data, ID_LEN);
 366        s = strstrip(p->id);
 367        memcpy(p->ec, vpd + ec, EC_LEN);
 368        s = strstrip(p->ec);
 369        i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
 370        memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
 371        s = strstrip(p->sn);
 372
 373        csio_valid_vpd_copied(hw);
 374
 375        kfree(vpd);
 376        return 0;
 377}
 378
 379/*
 380 *      csio_hw_sf1_read - read data from the serial flash
 381 *      @hw: the HW module
 382 *      @byte_cnt: number of bytes to read
 383 *      @cont: whether another operation will be chained
 384 *      @lock: whether to lock SF for PL access only
 385 *      @valp: where to store the read data
 386 *
 387 *      Reads up to 4 bytes of data from the serial flash.  The location of
 388 *      the read needs to be specified prior to calling this by issuing the
 389 *      appropriate commands to the serial flash.
 390 */
 391static int
 392csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont,
 393                 int32_t lock, uint32_t *valp)
 394{
 395        int ret;
 396
 397        if (!byte_cnt || byte_cnt > 4)
 398                return -EINVAL;
 399        if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
 400                return -EBUSY;
 401
 402        csio_wr_reg32(hw,  SF_LOCK_V(lock) | SF_CONT_V(cont) |
 403                      BYTECNT_V(byte_cnt - 1), SF_OP_A);
 404        ret = csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
 405                                       10, NULL);
 406        if (!ret)
 407                *valp = csio_rd_reg32(hw, SF_DATA_A);
 408        return ret;
 409}
 410
 411/*
 412 *      csio_hw_sf1_write - write data to the serial flash
 413 *      @hw: the HW module
 414 *      @byte_cnt: number of bytes to write
 415 *      @cont: whether another operation will be chained
 416 *      @lock: whether to lock SF for PL access only
 417 *      @val: value to write
 418 *
 419 *      Writes up to 4 bytes of data to the serial flash.  The location of
 420 *      the write needs to be specified prior to calling this by issuing the
 421 *      appropriate commands to the serial flash.
 422 */
 423static int
 424csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont,
 425                  int32_t lock, uint32_t val)
 426{
 427        if (!byte_cnt || byte_cnt > 4)
 428                return -EINVAL;
 429        if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
 430                return -EBUSY;
 431
 432        csio_wr_reg32(hw, val, SF_DATA_A);
 433        csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) |
 434                      OP_V(1) | SF_LOCK_V(lock), SF_OP_A);
 435
 436        return csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
 437                                        10, NULL);
 438}
 439
 440/*
 441 *      csio_hw_flash_wait_op - wait for a flash operation to complete
 442 *      @hw: the HW module
 443 *      @attempts: max number of polls of the status register
 444 *      @delay: delay between polls in ms
 445 *
 446 *      Wait for a flash operation to complete by polling the status register.
 447 */
 448static int
 449csio_hw_flash_wait_op(struct csio_hw *hw, int32_t attempts, int32_t delay)
 450{
 451        int ret;
 452        uint32_t status;
 453
 454        while (1) {
 455                ret = csio_hw_sf1_write(hw, 1, 1, 1, SF_RD_STATUS);
 456                if (ret != 0)
 457                        return ret;
 458
 459                ret = csio_hw_sf1_read(hw, 1, 0, 1, &status);
 460                if (ret != 0)
 461                        return ret;
 462
 463                if (!(status & 1))
 464                        return 0;
 465                if (--attempts == 0)
 466                        return -EAGAIN;
 467                if (delay)
 468                        msleep(delay);
 469        }
 470}
 471
 472/*
 473 *      csio_hw_read_flash - read words from serial flash
 474 *      @hw: the HW module
 475 *      @addr: the start address for the read
 476 *      @nwords: how many 32-bit words to read
 477 *      @data: where to store the read data
 478 *      @byte_oriented: whether to store data as bytes or as words
 479 *
 480 *      Read the specified number of 32-bit words from the serial flash.
 481 *      If @byte_oriented is set the read data is stored as a byte array
 482 *      (i.e., big-endian), otherwise as 32-bit words in the platform's
 483 *      natural endianess.
 484 */
 485static int
 486csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords,
 487                  uint32_t *data, int32_t byte_oriented)
 488{
 489        int ret;
 490
 491        if (addr + nwords * sizeof(uint32_t) > hw->params.sf_size || (addr & 3))
 492                return -EINVAL;
 493
 494        addr = swab32(addr) | SF_RD_DATA_FAST;
 495
 496        ret = csio_hw_sf1_write(hw, 4, 1, 0, addr);
 497        if (ret != 0)
 498                return ret;
 499
 500        ret = csio_hw_sf1_read(hw, 1, 1, 0, data);
 501        if (ret != 0)
 502                return ret;
 503
 504        for ( ; nwords; nwords--, data++) {
 505                ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data);
 506                if (nwords == 1)
 507                        csio_wr_reg32(hw, 0, SF_OP_A);    /* unlock SF */
 508                if (ret)
 509                        return ret;
 510                if (byte_oriented)
 511                        *data = (__force __u32) htonl(*data);
 512        }
 513        return 0;
 514}
 515
 516/*
 517 *      csio_hw_write_flash - write up to a page of data to the serial flash
 518 *      @hw: the hw
 519 *      @addr: the start address to write
 520 *      @n: length of data to write in bytes
 521 *      @data: the data to write
 522 *
 523 *      Writes up to a page of data (256 bytes) to the serial flash starting
 524 *      at the given address.  All the data must be written to the same page.
 525 */
 526static int
 527csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
 528                    uint32_t n, const uint8_t *data)
 529{
 530        int ret = -EINVAL;
 531        uint32_t buf[64];
 532        uint32_t i, c, left, val, offset = addr & 0xff;
 533
 534        if (addr >= hw->params.sf_size || offset + n > SF_PAGE_SIZE)
 535                return -EINVAL;
 536
 537        val = swab32(addr) | SF_PROG_PAGE;
 538
 539        ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE);
 540        if (ret != 0)
 541                goto unlock;
 542
 543        ret = csio_hw_sf1_write(hw, 4, 1, 1, val);
 544        if (ret != 0)
 545                goto unlock;
 546
 547        for (left = n; left; left -= c) {
 548                c = min(left, 4U);
 549                for (val = 0, i = 0; i < c; ++i)
 550                        val = (val << 8) + *data++;
 551
 552                ret = csio_hw_sf1_write(hw, c, c != left, 1, val);
 553                if (ret)
 554                        goto unlock;
 555        }
 556        ret = csio_hw_flash_wait_op(hw, 8, 1);
 557        if (ret)
 558                goto unlock;
 559
 560        csio_wr_reg32(hw, 0, SF_OP_A);    /* unlock SF */
 561
 562        /* Read the page to verify the write succeeded */
 563        ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
 564        if (ret)
 565                return ret;
 566
 567        if (memcmp(data - n, (uint8_t *)buf + offset, n)) {
 568                csio_err(hw,
 569                         "failed to correctly write the flash page at %#x\n",
 570                         addr);
 571                return -EINVAL;
 572        }
 573
 574        return 0;
 575
 576unlock:
 577        csio_wr_reg32(hw, 0, SF_OP_A);    /* unlock SF */
 578        return ret;
 579}
 580
 581/*
 582 *      csio_hw_flash_erase_sectors - erase a range of flash sectors
 583 *      @hw: the HW module
 584 *      @start: the first sector to erase
 585 *      @end: the last sector to erase
 586 *
 587 *      Erases the sectors in the given inclusive range.
 588 */
 589static int
 590csio_hw_flash_erase_sectors(struct csio_hw *hw, int32_t start, int32_t end)
 591{
 592        int ret = 0;
 593
 594        while (start <= end) {
 595
 596                ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE);
 597                if (ret != 0)
 598                        goto out;
 599
 600                ret = csio_hw_sf1_write(hw, 4, 0, 1,
 601                                        SF_ERASE_SECTOR | (start << 8));
 602                if (ret != 0)
 603                        goto out;
 604
 605                ret = csio_hw_flash_wait_op(hw, 14, 500);
 606                if (ret != 0)
 607                        goto out;
 608
 609                start++;
 610        }
 611out:
 612        if (ret)
 613                csio_err(hw, "erase of flash sector %d failed, error %d\n",
 614                         start, ret);
 615        csio_wr_reg32(hw, 0, SF_OP_A);    /* unlock SF */
 616        return 0;
 617}
 618
 619static void
 620csio_hw_print_fw_version(struct csio_hw *hw, char *str)
 621{
 622        csio_info(hw, "%s: %u.%u.%u.%u\n", str,
 623                    FW_HDR_FW_VER_MAJOR_G(hw->fwrev),
 624                    FW_HDR_FW_VER_MINOR_G(hw->fwrev),
 625                    FW_HDR_FW_VER_MICRO_G(hw->fwrev),
 626                    FW_HDR_FW_VER_BUILD_G(hw->fwrev));
 627}
 628
 629/*
 630 * csio_hw_get_fw_version - read the firmware version
 631 * @hw: HW module
 632 * @vers: where to place the version
 633 *
 634 * Reads the FW version from flash.
 635 */
 636static int
 637csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers)
 638{
 639        return csio_hw_read_flash(hw, FLASH_FW_START +
 640                                  offsetof(struct fw_hdr, fw_ver), 1,
 641                                  vers, 0);
 642}
 643
 644/*
 645 *      csio_hw_get_tp_version - read the TP microcode version
 646 *      @hw: HW module
 647 *      @vers: where to place the version
 648 *
 649 *      Reads the TP microcode version from flash.
 650 */
 651static int
 652csio_hw_get_tp_version(struct csio_hw *hw, u32 *vers)
 653{
 654        return csio_hw_read_flash(hw, FLASH_FW_START +
 655                        offsetof(struct fw_hdr, tp_microcode_ver), 1,
 656                        vers, 0);
 657}
 658
 659/*
 660 * csio_hw_fw_dload - download firmware.
 661 * @hw: HW module
 662 * @fw_data: firmware image to write.
 663 * @size: image size
 664 *
 665 * Write the supplied firmware image to the card's serial flash.
 666 */
 667static int
 668csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size)
 669{
 670        uint32_t csum;
 671        int32_t addr;
 672        int ret;
 673        uint32_t i;
 674        uint8_t first_page[SF_PAGE_SIZE];
 675        const __be32 *p = (const __be32 *)fw_data;
 676        struct fw_hdr *hdr = (struct fw_hdr *)fw_data;
 677        uint32_t sf_sec_size;
 678
 679        if ((!hw->params.sf_size) || (!hw->params.sf_nsec)) {
 680                csio_err(hw, "Serial Flash data invalid\n");
 681                return -EINVAL;
 682        }
 683
 684        if (!size) {
 685                csio_err(hw, "FW image has no data\n");
 686                return -EINVAL;
 687        }
 688
 689        if (size & 511) {
 690                csio_err(hw, "FW image size not multiple of 512 bytes\n");
 691                return -EINVAL;
 692        }
 693
 694        if (ntohs(hdr->len512) * 512 != size) {
 695                csio_err(hw, "FW image size differs from size in FW header\n");
 696                return -EINVAL;
 697        }
 698
 699        if (size > FLASH_FW_MAX_SIZE) {
 700                csio_err(hw, "FW image too large, max is %u bytes\n",
 701                            FLASH_FW_MAX_SIZE);
 702                return -EINVAL;
 703        }
 704
 705        for (csum = 0, i = 0; i < size / sizeof(csum); i++)
 706                csum += ntohl(p[i]);
 707
 708        if (csum != 0xffffffff) {
 709                csio_err(hw, "corrupted firmware image, checksum %#x\n", csum);
 710                return -EINVAL;
 711        }
 712
 713        sf_sec_size = hw->params.sf_size / hw->params.sf_nsec;
 714        i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
 715
 716        csio_dbg(hw, "Erasing sectors... start:%d end:%d\n",
 717                          FLASH_FW_START_SEC, FLASH_FW_START_SEC + i - 1);
 718
 719        ret = csio_hw_flash_erase_sectors(hw, FLASH_FW_START_SEC,
 720                                          FLASH_FW_START_SEC + i - 1);
 721        if (ret) {
 722                csio_err(hw, "Flash Erase failed\n");
 723                goto out;
 724        }
 725
 726        /*
 727         * We write the correct version at the end so the driver can see a bad
 728         * version if the FW write fails.  Start by writing a copy of the
 729         * first page with a bad version.
 730         */
 731        memcpy(first_page, fw_data, SF_PAGE_SIZE);
 732        ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
 733        ret = csio_hw_write_flash(hw, FLASH_FW_START, SF_PAGE_SIZE, first_page);
 734        if (ret)
 735                goto out;
 736
 737        csio_dbg(hw, "Writing Flash .. start:%d end:%d\n",
 738                    FW_IMG_START, FW_IMG_START + size);
 739
 740        addr = FLASH_FW_START;
 741        for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
 742                addr += SF_PAGE_SIZE;
 743                fw_data += SF_PAGE_SIZE;
 744                ret = csio_hw_write_flash(hw, addr, SF_PAGE_SIZE, fw_data);
 745                if (ret)
 746                        goto out;
 747        }
 748
 749        ret = csio_hw_write_flash(hw,
 750                                  FLASH_FW_START +
 751                                        offsetof(struct fw_hdr, fw_ver),
 752                                  sizeof(hdr->fw_ver),
 753                                  (const uint8_t *)&hdr->fw_ver);
 754
 755out:
 756        if (ret)
 757                csio_err(hw, "firmware download failed, error %d\n", ret);
 758        return ret;
 759}
 760
 761static int
 762csio_hw_get_flash_params(struct csio_hw *hw)
 763{
 764        /* Table for non-Numonix supported flash parts.  Numonix parts are left
 765         * to the preexisting code.  All flash parts have 64KB sectors.
 766         */
 767        static struct flash_desc {
 768                u32 vendor_and_model_id;
 769                u32 size_mb;
 770        } supported_flash[] = {
 771                { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
 772        };
 773
 774        u32 part, manufacturer;
 775        u32 density, size = 0;
 776        u32 flashid = 0;
 777        int ret;
 778
 779        ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID);
 780        if (!ret)
 781                ret = csio_hw_sf1_read(hw, 3, 0, 1, &flashid);
 782        csio_wr_reg32(hw, 0, SF_OP_A);    /* unlock SF */
 783        if (ret)
 784                return ret;
 785
 786        /* Check to see if it's one of our non-standard supported Flash parts.
 787         */
 788        for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
 789                if (supported_flash[part].vendor_and_model_id == flashid) {
 790                        hw->params.sf_size = supported_flash[part].size_mb;
 791                        hw->params.sf_nsec =
 792                                hw->params.sf_size / SF_SEC_SIZE;
 793                        goto found;
 794                }
 795
 796        /* Decode Flash part size.  The code below looks repetative with
 797         * common encodings, but that's not guaranteed in the JEDEC
 798         * specification for the Read JADEC ID command.  The only thing that
 799         * we're guaranteed by the JADEC specification is where the
 800         * Manufacturer ID is in the returned result.  After that each
 801         * Manufacturer ~could~ encode things completely differently.
 802         * Note, all Flash parts must have 64KB sectors.
 803         */
 804        manufacturer = flashid & 0xff;
 805        switch (manufacturer) {
 806        case 0x20: { /* Micron/Numonix */
 807                /* This Density -> Size decoding table is taken from Micron
 808                 * Data Sheets.
 809                 */
 810                density = (flashid >> 16) & 0xff;
 811                switch (density) {
 812                case 0x14 ... 0x19: /* 1MB - 32MB */
 813                        size = 1 << density;
 814                        break;
 815                case 0x20: /* 64MB */
 816                        size = 1 << 26;
 817                        break;
 818                case 0x21: /* 128MB */
 819                        size = 1 << 27;
 820                        break;
 821                case 0x22: /* 256MB */
 822                        size = 1 << 28;
 823                }
 824                break;
 825        }
 826        case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
 827                /* This Density -> Size decoding table is taken from ISSI
 828                 * Data Sheets.
 829                 */
 830                density = (flashid >> 16) & 0xff;
 831                switch (density) {
 832                case 0x16: /* 32 MB */
 833                        size = 1 << 25;
 834                        break;
 835                case 0x17: /* 64MB */
 836                        size = 1 << 26;
 837                }
 838                break;
 839        }
 840        case 0xc2: /* Macronix */
 841        case 0xef: /* Winbond */ {
 842                /* This Density -> Size decoding table is taken from
 843                 * Macronix and Winbond Data Sheets.
 844                 */
 845                density = (flashid >> 16) & 0xff;
 846                switch (density) {
 847                case 0x17: /* 8MB */
 848                case 0x18: /* 16MB */
 849                        size = 1 << density;
 850                }
 851        }
 852        }
 853
 854        /* If we didn't recognize the FLASH part, that's no real issue: the
 855         * Hardware/Software contract says that Hardware will _*ALWAYS*_
 856         * use a FLASH part which is at least 4MB in size and has 64KB
 857         * sectors.  The unrecognized FLASH part is likely to be much larger
 858         * than 4MB, but that's all we really need.
 859         */
 860        if (size == 0) {
 861                csio_warn(hw, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
 862                          flashid);
 863                size = 1 << 22;
 864        }
 865
 866        /* Store decoded Flash size */
 867        hw->params.sf_size = size;
 868        hw->params.sf_nsec = size / SF_SEC_SIZE;
 869
 870found:
 871        if (hw->params.sf_size < FLASH_MIN_SIZE)
 872                csio_warn(hw, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
 873                          flashid, hw->params.sf_size, FLASH_MIN_SIZE);
 874        return 0;
 875}
 876
 877/*****************************************************************************/
 878/* HW State machine assists                                                  */
 879/*****************************************************************************/
 880
 881static int
 882csio_hw_dev_ready(struct csio_hw *hw)
 883{
 884        uint32_t reg;
 885        int cnt = 6;
 886        int src_pf;
 887
 888        while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) &&
 889               (--cnt != 0))
 890                mdelay(100);
 891
 892        if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK))
 893                src_pf = SOURCEPF_G(reg);
 894        else
 895                src_pf = T6_SOURCEPF_G(reg);
 896
 897        if ((cnt == 0) && (((int32_t)(src_pf) < 0) ||
 898                           (src_pf >= CSIO_MAX_PFN))) {
 899                csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt);
 900                return -EIO;
 901        }
 902
 903        hw->pfn = src_pf;
 904
 905        return 0;
 906}
 907
 908/*
 909 * csio_do_hello - Perform the HELLO FW Mailbox command and process response.
 910 * @hw: HW module
 911 * @state: Device state
 912 *
 913 * FW_HELLO_CMD has to be polled for completion.
 914 */
 915static int
 916csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state)
 917{
 918        struct csio_mb  *mbp;
 919        int     rv = 0;
 920        enum fw_retval retval;
 921        uint8_t mpfn;
 922        char state_str[16];
 923        int retries = FW_CMD_HELLO_RETRIES;
 924
 925        memset(state_str, 0, sizeof(state_str));
 926
 927        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
 928        if (!mbp) {
 929                rv = -ENOMEM;
 930                CSIO_INC_STATS(hw, n_err_nomem);
 931                goto out;
 932        }
 933
 934retry:
 935        csio_mb_hello(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn,
 936                      hw->pfn, CSIO_MASTER_MAY, NULL);
 937
 938        rv = csio_mb_issue(hw, mbp);
 939        if (rv) {
 940                csio_err(hw, "failed to issue HELLO cmd. ret:%d.\n", rv);
 941                goto out_free_mb;
 942        }
 943
 944        csio_mb_process_hello_rsp(hw, mbp, &retval, state, &mpfn);
 945        if (retval != FW_SUCCESS) {
 946                csio_err(hw, "HELLO cmd failed with ret: %d\n", retval);
 947                rv = -EINVAL;
 948                goto out_free_mb;
 949        }
 950
 951        /* Firmware has designated us to be master */
 952        if (hw->pfn == mpfn) {
 953                hw->flags |= CSIO_HWF_MASTER;
 954        } else if (*state == CSIO_DEV_STATE_UNINIT) {
 955                /*
 956                 * If we're not the Master PF then we need to wait around for
 957                 * the Master PF Driver to finish setting up the adapter.
 958                 *
 959                 * Note that we also do this wait if we're a non-Master-capable
 960                 * PF and there is no current Master PF; a Master PF may show up
 961                 * momentarily and we wouldn't want to fail pointlessly.  (This
 962                 * can happen when an OS loads lots of different drivers rapidly
 963                 * at the same time). In this case, the Master PF returned by
 964                 * the firmware will be PCIE_FW_MASTER_MASK so the test below
 965                 * will work ...
 966                 */
 967
 968                int waiting = FW_CMD_HELLO_TIMEOUT;
 969
 970                /*
 971                 * Wait for the firmware to either indicate an error or
 972                 * initialized state.  If we see either of these we bail out
 973                 * and report the issue to the caller.  If we exhaust the
 974                 * "hello timeout" and we haven't exhausted our retries, try
 975                 * again.  Otherwise bail with a timeout error.
 976                 */
 977                for (;;) {
 978                        uint32_t pcie_fw;
 979
 980                        spin_unlock_irq(&hw->lock);
 981                        msleep(50);
 982                        spin_lock_irq(&hw->lock);
 983                        waiting -= 50;
 984
 985                        /*
 986                         * If neither Error nor Initialialized are indicated
 987                         * by the firmware keep waiting till we exaust our
 988                         * timeout ... and then retry if we haven't exhausted
 989                         * our retries ...
 990                         */
 991                        pcie_fw = csio_rd_reg32(hw, PCIE_FW_A);
 992                        if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
 993                                if (waiting <= 0) {
 994                                        if (retries-- > 0)
 995                                                goto retry;
 996
 997                                        rv = -ETIMEDOUT;
 998                                        break;
 999                                }
1000                                continue;
1001                        }
1002
1003                        /*
1004                         * We either have an Error or Initialized condition
1005                         * report errors preferentially.
1006                         */
1007                        if (state) {
1008                                if (pcie_fw & PCIE_FW_ERR_F) {
1009                                        *state = CSIO_DEV_STATE_ERR;
1010                                        rv = -ETIMEDOUT;
1011                                } else if (pcie_fw & PCIE_FW_INIT_F)
1012                                        *state = CSIO_DEV_STATE_INIT;
1013                        }
1014
1015                        /*
1016                         * If we arrived before a Master PF was selected and
1017                         * there's not a valid Master PF, grab its identity
1018                         * for our caller.
1019                         */
1020                        if (mpfn == PCIE_FW_MASTER_M &&
1021                            (pcie_fw & PCIE_FW_MASTER_VLD_F))
1022                                mpfn = PCIE_FW_MASTER_G(pcie_fw);
1023                        break;
1024                }
1025                hw->flags &= ~CSIO_HWF_MASTER;
1026        }
1027
1028        switch (*state) {
1029        case CSIO_DEV_STATE_UNINIT:
1030                strcpy(state_str, "Initializing");
1031                break;
1032        case CSIO_DEV_STATE_INIT:
1033                strcpy(state_str, "Initialized");
1034                break;
1035        case CSIO_DEV_STATE_ERR:
1036                strcpy(state_str, "Error");
1037                break;
1038        default:
1039                strcpy(state_str, "Unknown");
1040                break;
1041        }
1042
1043        if (hw->pfn == mpfn)
1044                csio_info(hw, "PF: %d, Coming up as MASTER, HW state: %s\n",
1045                        hw->pfn, state_str);
1046        else
1047                csio_info(hw,
1048                    "PF: %d, Coming up as SLAVE, Master PF: %d, HW state: %s\n",
1049                    hw->pfn, mpfn, state_str);
1050
1051out_free_mb:
1052        mempool_free(mbp, hw->mb_mempool);
1053out:
1054        return rv;
1055}
1056
1057/*
1058 * csio_do_bye - Perform the BYE FW Mailbox command and process response.
1059 * @hw: HW module
1060 *
1061 */
1062static int
1063csio_do_bye(struct csio_hw *hw)
1064{
1065        struct csio_mb  *mbp;
1066        enum fw_retval retval;
1067
1068        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1069        if (!mbp) {
1070                CSIO_INC_STATS(hw, n_err_nomem);
1071                return -ENOMEM;
1072        }
1073
1074        csio_mb_bye(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL);
1075
1076        if (csio_mb_issue(hw, mbp)) {
1077                csio_err(hw, "Issue of BYE command failed\n");
1078                mempool_free(mbp, hw->mb_mempool);
1079                return -EINVAL;
1080        }
1081
1082        retval = csio_mb_fw_retval(mbp);
1083        if (retval != FW_SUCCESS) {
1084                mempool_free(mbp, hw->mb_mempool);
1085                return -EINVAL;
1086        }
1087
1088        mempool_free(mbp, hw->mb_mempool);
1089
1090        return 0;
1091}
1092
1093/*
1094 * csio_do_reset- Perform the device reset.
1095 * @hw: HW module
1096 * @fw_rst: FW reset
1097 *
1098 * If fw_rst is set, issues FW reset mbox cmd otherwise
1099 * does PIO reset.
1100 * Performs reset of the function.
1101 */
1102static int
1103csio_do_reset(struct csio_hw *hw, bool fw_rst)
1104{
1105        struct csio_mb  *mbp;
1106        enum fw_retval retval;
1107
1108        if (!fw_rst) {
1109                /* PIO reset */
1110                csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
1111                mdelay(2000);
1112                return 0;
1113        }
1114
1115        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1116        if (!mbp) {
1117                CSIO_INC_STATS(hw, n_err_nomem);
1118                return -ENOMEM;
1119        }
1120
1121        csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
1122                      PIORSTMODE_F | PIORST_F, 0, NULL);
1123
1124        if (csio_mb_issue(hw, mbp)) {
1125                csio_err(hw, "Issue of RESET command failed.n");
1126                mempool_free(mbp, hw->mb_mempool);
1127                return -EINVAL;
1128        }
1129
1130        retval = csio_mb_fw_retval(mbp);
1131        if (retval != FW_SUCCESS) {
1132                csio_err(hw, "RESET cmd failed with ret:0x%x.\n", retval);
1133                mempool_free(mbp, hw->mb_mempool);
1134                return -EINVAL;
1135        }
1136
1137        mempool_free(mbp, hw->mb_mempool);
1138
1139        return 0;
1140}
1141
1142static int
1143csio_hw_validate_caps(struct csio_hw *hw, struct csio_mb *mbp)
1144{
1145        struct fw_caps_config_cmd *rsp = (struct fw_caps_config_cmd *)mbp->mb;
1146        uint16_t caps;
1147
1148        caps = ntohs(rsp->fcoecaps);
1149
1150        if (!(caps & FW_CAPS_CONFIG_FCOE_INITIATOR)) {
1151                csio_err(hw, "No FCoE Initiator capability in the firmware.\n");
1152                return -EINVAL;
1153        }
1154
1155        if (!(caps & FW_CAPS_CONFIG_FCOE_CTRL_OFLD)) {
1156                csio_err(hw, "No FCoE Control Offload capability\n");
1157                return -EINVAL;
1158        }
1159
1160        return 0;
1161}
1162
1163/*
1164 *      csio_hw_fw_halt - issue a reset/halt to FW and put uP into RESET
1165 *      @hw: the HW module
1166 *      @mbox: mailbox to use for the FW RESET command (if desired)
1167 *      @force: force uP into RESET even if FW RESET command fails
1168 *
1169 *      Issues a RESET command to firmware (if desired) with a HALT indication
1170 *      and then puts the microprocessor into RESET state.  The RESET command
1171 *      will only be issued if a legitimate mailbox is provided (mbox <=
1172 *      PCIE_FW_MASTER_MASK).
1173 *
1174 *      This is generally used in order for the host to safely manipulate the
1175 *      adapter without fear of conflicting with whatever the firmware might
1176 *      be doing.  The only way out of this state is to RESTART the firmware
1177 *      ...
1178 */
1179static int
1180csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1181{
1182        enum fw_retval retval = 0;
1183
1184        /*
1185         * If a legitimate mailbox is provided, issue a RESET command
1186         * with a HALT indication.
1187         */
1188        if (mbox <= PCIE_FW_MASTER_M) {
1189                struct csio_mb  *mbp;
1190
1191                mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1192                if (!mbp) {
1193                        CSIO_INC_STATS(hw, n_err_nomem);
1194                        return -ENOMEM;
1195                }
1196
1197                csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
1198                              PIORSTMODE_F | PIORST_F, FW_RESET_CMD_HALT_F,
1199                              NULL);
1200
1201                if (csio_mb_issue(hw, mbp)) {
1202                        csio_err(hw, "Issue of RESET command failed!\n");
1203                        mempool_free(mbp, hw->mb_mempool);
1204                        return -EINVAL;
1205                }
1206
1207                retval = csio_mb_fw_retval(mbp);
1208                mempool_free(mbp, hw->mb_mempool);
1209        }
1210
1211        /*
1212         * Normally we won't complete the operation if the firmware RESET
1213         * command fails but if our caller insists we'll go ahead and put the
1214         * uP into RESET.  This can be useful if the firmware is hung or even
1215         * missing ...  We'll have to take the risk of putting the uP into
1216         * RESET without the cooperation of firmware in that case.
1217         *
1218         * We also force the firmware's HALT flag to be on in case we bypassed
1219         * the firmware RESET command above or we're dealing with old firmware
1220         * which doesn't have the HALT capability.  This will serve as a flag
1221         * for the incoming firmware to know that it's coming out of a HALT
1222         * rather than a RESET ... if it's new enough to understand that ...
1223         */
1224        if (retval == 0 || force) {
1225                csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
1226                csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F,
1227                                   PCIE_FW_HALT_F);
1228        }
1229
1230        /*
1231         * And we always return the result of the firmware RESET command
1232         * even when we force the uP into RESET ...
1233         */
1234        return retval ? -EINVAL : 0;
1235}
1236
1237/*
1238 *      csio_hw_fw_restart - restart the firmware by taking the uP out of RESET
1239 *      @hw: the HW module
1240 *      @reset: if we want to do a RESET to restart things
1241 *
1242 *      Restart firmware previously halted by csio_hw_fw_halt().  On successful
1243 *      return the previous PF Master remains as the new PF Master and there
1244 *      is no need to issue a new HELLO command, etc.
1245 *
1246 *      We do this in two ways:
1247 *
1248 *       1. If we're dealing with newer firmware we'll simply want to take
1249 *          the chip's microprocessor out of RESET.  This will cause the
1250 *          firmware to start up from its start vector.  And then we'll loop
1251 *          until the firmware indicates it's started again (PCIE_FW.HALT
1252 *          reset to 0) or we timeout.
1253 *
1254 *       2. If we're dealing with older firmware then we'll need to RESET
1255 *          the chip since older firmware won't recognize the PCIE_FW.HALT
1256 *          flag and automatically RESET itself on startup.
1257 */
1258static int
1259csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1260{
1261        if (reset) {
1262                /*
1263                 * Since we're directing the RESET instead of the firmware
1264                 * doing it automatically, we need to clear the PCIE_FW.HALT
1265                 * bit.
1266                 */
1267                csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0);
1268
1269                /*
1270                 * If we've been given a valid mailbox, first try to get the
1271                 * firmware to do the RESET.  If that works, great and we can
1272                 * return success.  Otherwise, if we haven't been given a
1273                 * valid mailbox or the RESET command failed, fall back to
1274                 * hitting the chip with a hammer.
1275                 */
1276                if (mbox <= PCIE_FW_MASTER_M) {
1277                        csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
1278                        msleep(100);
1279                        if (csio_do_reset(hw, true) == 0)
1280                                return 0;
1281                }
1282
1283                csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
1284                msleep(2000);
1285        } else {
1286                int ms;
1287
1288                csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
1289                for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
1290                        if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F))
1291                                return 0;
1292                        msleep(100);
1293                        ms += 100;
1294                }
1295                return -ETIMEDOUT;
1296        }
1297        return 0;
1298}
1299
1300/*
1301 *      csio_hw_fw_upgrade - perform all of the steps necessary to upgrade FW
1302 *      @hw: the HW module
1303 *      @mbox: mailbox to use for the FW RESET command (if desired)
1304 *      @fw_data: the firmware image to write
1305 *      @size: image size
1306 *      @force: force upgrade even if firmware doesn't cooperate
1307 *
1308 *      Perform all of the steps necessary for upgrading an adapter's
1309 *      firmware image.  Normally this requires the cooperation of the
1310 *      existing firmware in order to halt all existing activities
1311 *      but if an invalid mailbox token is passed in we skip that step
1312 *      (though we'll still put the adapter microprocessor into RESET in
1313 *      that case).
1314 *
1315 *      On successful return the new firmware will have been loaded and
1316 *      the adapter will have been fully RESET losing all previous setup
1317 *      state.  On unsuccessful return the adapter may be completely hosed ...
1318 *      positive errno indicates that the adapter is ~probably~ intact, a
1319 *      negative errno indicates that things are looking bad ...
1320 */
1321static int
1322csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox,
1323                  const u8 *fw_data, uint32_t size, int32_t force)
1324{
1325        const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
1326        int reset, ret;
1327
1328        ret = csio_hw_fw_halt(hw, mbox, force);
1329        if (ret != 0 && !force)
1330                return ret;
1331
1332        ret = csio_hw_fw_dload(hw, (uint8_t *) fw_data, size);
1333        if (ret != 0)
1334                return ret;
1335
1336        /*
1337         * Older versions of the firmware don't understand the new
1338         * PCIE_FW.HALT flag and so won't know to perform a RESET when they
1339         * restart.  So for newly loaded older firmware we'll have to do the
1340         * RESET for it so it starts up on a clean slate.  We can tell if
1341         * the newly loaded firmware will handle this right by checking
1342         * its header flags to see if it advertises the capability.
1343         */
1344        reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
1345        return csio_hw_fw_restart(hw, mbox, reset);
1346}
1347
1348/*
1349 * csio_get_device_params - Get device parameters.
1350 * @hw: HW module
1351 *
1352 */
1353static int
1354csio_get_device_params(struct csio_hw *hw)
1355{
1356        struct csio_wrm *wrm    = csio_hw_to_wrm(hw);
1357        struct csio_mb  *mbp;
1358        enum fw_retval retval;
1359        u32 param[6];
1360        int i, j = 0;
1361
1362        /* Initialize portids to -1 */
1363        for (i = 0; i < CSIO_MAX_PPORTS; i++)
1364                hw->pport[i].portid = -1;
1365
1366        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1367        if (!mbp) {
1368                CSIO_INC_STATS(hw, n_err_nomem);
1369                return -ENOMEM;
1370        }
1371
1372        /* Get port vec information. */
1373        param[0] = FW_PARAM_DEV(PORTVEC);
1374
1375        /* Get Core clock. */
1376        param[1] = FW_PARAM_DEV(CCLK);
1377
1378        /* Get EQ id start and end. */
1379        param[2] = FW_PARAM_PFVF(EQ_START);
1380        param[3] = FW_PARAM_PFVF(EQ_END);
1381
1382        /* Get IQ id start and end. */
1383        param[4] = FW_PARAM_PFVF(IQFLINT_START);
1384        param[5] = FW_PARAM_PFVF(IQFLINT_END);
1385
1386        csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0,
1387                       ARRAY_SIZE(param), param, NULL, false, NULL);
1388        if (csio_mb_issue(hw, mbp)) {
1389                csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n");
1390                mempool_free(mbp, hw->mb_mempool);
1391                return -EINVAL;
1392        }
1393
1394        csio_mb_process_read_params_rsp(hw, mbp, &retval,
1395                        ARRAY_SIZE(param), param);
1396        if (retval != FW_SUCCESS) {
1397                csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n",
1398                                retval);
1399                mempool_free(mbp, hw->mb_mempool);
1400                return -EINVAL;
1401        }
1402
1403        /* cache the information. */
1404        hw->port_vec = param[0];
1405        hw->vpd.cclk = param[1];
1406        wrm->fw_eq_start = param[2];
1407        wrm->fw_iq_start = param[4];
1408
1409        /* Using FW configured max iqs & eqs */
1410        if ((hw->flags & CSIO_HWF_USING_SOFT_PARAMS) ||
1411                !csio_is_hw_master(hw)) {
1412                hw->cfg_niq = param[5] - param[4] + 1;
1413                hw->cfg_neq = param[3] - param[2] + 1;
1414                csio_dbg(hw, "Using fwconfig max niqs %d neqs %d\n",
1415                        hw->cfg_niq, hw->cfg_neq);
1416        }
1417
1418        hw->port_vec &= csio_port_mask;
1419
1420        hw->num_pports  = hweight32(hw->port_vec);
1421
1422        csio_dbg(hw, "Port vector: 0x%x, #ports: %d\n",
1423                    hw->port_vec, hw->num_pports);
1424
1425        for (i = 0; i < hw->num_pports; i++) {
1426                while ((hw->port_vec & (1 << j)) == 0)
1427                        j++;
1428                hw->pport[i].portid = j++;
1429                csio_dbg(hw, "Found Port:%d\n", hw->pport[i].portid);
1430        }
1431        mempool_free(mbp, hw->mb_mempool);
1432
1433        return 0;
1434}
1435
1436
1437/*
1438 * csio_config_device_caps - Get and set device capabilities.
1439 * @hw: HW module
1440 *
1441 */
1442static int
1443csio_config_device_caps(struct csio_hw *hw)
1444{
1445        struct csio_mb  *mbp;
1446        enum fw_retval retval;
1447        int rv = -EINVAL;
1448
1449        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1450        if (!mbp) {
1451                CSIO_INC_STATS(hw, n_err_nomem);
1452                return -ENOMEM;
1453        }
1454
1455        /* Get device capabilities */
1456        csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, 0, 0, 0, 0, NULL);
1457
1458        if (csio_mb_issue(hw, mbp)) {
1459                csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(r) failed!\n");
1460                goto out;
1461        }
1462
1463        retval = csio_mb_fw_retval(mbp);
1464        if (retval != FW_SUCCESS) {
1465                csio_err(hw, "FW_CAPS_CONFIG_CMD(r) returned %d!\n", retval);
1466                goto out;
1467        }
1468
1469        /* Validate device capabilities */
1470        rv = csio_hw_validate_caps(hw, mbp);
1471        if (rv != 0)
1472                goto out;
1473
1474        /* Don't config device capabilities if already configured */
1475        if (hw->fw_state == CSIO_DEV_STATE_INIT) {
1476                rv = 0;
1477                goto out;
1478        }
1479
1480        /* Write back desired device capabilities */
1481        csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, true, true,
1482                            false, true, NULL);
1483
1484        if (csio_mb_issue(hw, mbp)) {
1485                csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(w) failed!\n");
1486                goto out;
1487        }
1488
1489        retval = csio_mb_fw_retval(mbp);
1490        if (retval != FW_SUCCESS) {
1491                csio_err(hw, "FW_CAPS_CONFIG_CMD(w) returned %d!\n", retval);
1492                goto out;
1493        }
1494
1495        rv = 0;
1496out:
1497        mempool_free(mbp, hw->mb_mempool);
1498        return rv;
1499}
1500
1501static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
1502{
1503        enum cc_fec cc_fec = 0;
1504
1505        if (fw_fec & FW_PORT_CAP32_FEC_RS)
1506                cc_fec |= FEC_RS;
1507        if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
1508                cc_fec |= FEC_BASER_RS;
1509
1510        return cc_fec;
1511}
1512
1513static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
1514{
1515        fw_port_cap32_t fw_pause = 0;
1516
1517        if (cc_pause & PAUSE_RX)
1518                fw_pause |= FW_PORT_CAP32_FC_RX;
1519        if (cc_pause & PAUSE_TX)
1520                fw_pause |= FW_PORT_CAP32_FC_TX;
1521
1522        return fw_pause;
1523}
1524
1525static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
1526{
1527        fw_port_cap32_t fw_fec = 0;
1528
1529        if (cc_fec & FEC_RS)
1530                fw_fec |= FW_PORT_CAP32_FEC_RS;
1531        if (cc_fec & FEC_BASER_RS)
1532                fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
1533
1534        return fw_fec;
1535}
1536
1537/**
1538 * fwcap_to_fwspeed - return highest speed in Port Capabilities
1539 * @acaps: advertised Port Capabilities
1540 *
1541 * Get the highest speed for the port from the advertised Port
1542 * Capabilities.
1543 */
1544fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
1545{
1546        #define TEST_SPEED_RETURN(__caps_speed) \
1547                do { \
1548                        if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
1549                                return FW_PORT_CAP32_SPEED_##__caps_speed; \
1550                } while (0)
1551
1552        TEST_SPEED_RETURN(400G);
1553        TEST_SPEED_RETURN(200G);
1554        TEST_SPEED_RETURN(100G);
1555        TEST_SPEED_RETURN(50G);
1556        TEST_SPEED_RETURN(40G);
1557        TEST_SPEED_RETURN(25G);
1558        TEST_SPEED_RETURN(10G);
1559        TEST_SPEED_RETURN(1G);
1560        TEST_SPEED_RETURN(100M);
1561
1562        #undef TEST_SPEED_RETURN
1563
1564        return 0;
1565}
1566
1567/**
1568 *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
1569 *      @caps16: a 16-bit Port Capabilities value
1570 *
1571 *      Returns the equivalent 32-bit Port Capabilities value.
1572 */
1573fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
1574{
1575        fw_port_cap32_t caps32 = 0;
1576
1577        #define CAP16_TO_CAP32(__cap) \
1578                do { \
1579                        if (caps16 & FW_PORT_CAP_##__cap) \
1580                                caps32 |= FW_PORT_CAP32_##__cap; \
1581                } while (0)
1582
1583        CAP16_TO_CAP32(SPEED_100M);
1584        CAP16_TO_CAP32(SPEED_1G);
1585        CAP16_TO_CAP32(SPEED_25G);
1586        CAP16_TO_CAP32(SPEED_10G);
1587        CAP16_TO_CAP32(SPEED_40G);
1588        CAP16_TO_CAP32(SPEED_100G);
1589        CAP16_TO_CAP32(FC_RX);
1590        CAP16_TO_CAP32(FC_TX);
1591        CAP16_TO_CAP32(ANEG);
1592        CAP16_TO_CAP32(MDIAUTO);
1593        CAP16_TO_CAP32(MDISTRAIGHT);
1594        CAP16_TO_CAP32(FEC_RS);
1595        CAP16_TO_CAP32(FEC_BASER_RS);
1596        CAP16_TO_CAP32(802_3_PAUSE);
1597        CAP16_TO_CAP32(802_3_ASM_DIR);
1598
1599        #undef CAP16_TO_CAP32
1600
1601        return caps32;
1602}
1603
1604/**
1605 *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
1606 *      @caps32: a 32-bit Port Capabilities value
1607 *
1608 *      Returns the equivalent 16-bit Port Capabilities value.  Note that
1609 *      not all 32-bit Port Capabilities can be represented in the 16-bit
1610 *      Port Capabilities and some fields/values may not make it.
1611 */
1612fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
1613{
1614        fw_port_cap16_t caps16 = 0;
1615
1616        #define CAP32_TO_CAP16(__cap) \
1617                do { \
1618                        if (caps32 & FW_PORT_CAP32_##__cap) \
1619                                caps16 |= FW_PORT_CAP_##__cap; \
1620                } while (0)
1621
1622        CAP32_TO_CAP16(SPEED_100M);
1623        CAP32_TO_CAP16(SPEED_1G);
1624        CAP32_TO_CAP16(SPEED_10G);
1625        CAP32_TO_CAP16(SPEED_25G);
1626        CAP32_TO_CAP16(SPEED_40G);
1627        CAP32_TO_CAP16(SPEED_100G);
1628        CAP32_TO_CAP16(FC_RX);
1629        CAP32_TO_CAP16(FC_TX);
1630        CAP32_TO_CAP16(802_3_PAUSE);
1631        CAP32_TO_CAP16(802_3_ASM_DIR);
1632        CAP32_TO_CAP16(ANEG);
1633        CAP32_TO_CAP16(FORCE_PAUSE);
1634        CAP32_TO_CAP16(MDIAUTO);
1635        CAP32_TO_CAP16(MDISTRAIGHT);
1636        CAP32_TO_CAP16(FEC_RS);
1637        CAP32_TO_CAP16(FEC_BASER_RS);
1638
1639        #undef CAP32_TO_CAP16
1640
1641        return caps16;
1642}
1643
1644/**
1645 *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
1646 *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
1647 *
1648 *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
1649 *      32-bit Port Capabilities value.
1650 */
1651fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
1652{
1653        fw_port_cap32_t linkattr = 0;
1654
1655        /* The format of the Link Status in the old
1656         * 16-bit Port Information message isn't the same as the
1657         * 16-bit Port Capabilities bitfield used everywhere else.
1658         */
1659        if (lstatus & FW_PORT_CMD_RXPAUSE_F)
1660                linkattr |= FW_PORT_CAP32_FC_RX;
1661        if (lstatus & FW_PORT_CMD_TXPAUSE_F)
1662                linkattr |= FW_PORT_CAP32_FC_TX;
1663        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
1664                linkattr |= FW_PORT_CAP32_SPEED_100M;
1665        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
1666                linkattr |= FW_PORT_CAP32_SPEED_1G;
1667        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
1668                linkattr |= FW_PORT_CAP32_SPEED_10G;
1669        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
1670                linkattr |= FW_PORT_CAP32_SPEED_25G;
1671        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
1672                linkattr |= FW_PORT_CAP32_SPEED_40G;
1673        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
1674                linkattr |= FW_PORT_CAP32_SPEED_100G;
1675
1676        return linkattr;
1677}
1678
1679/**
1680 *      csio_init_link_config - initialize a link's SW state
1681 *      @lc: pointer to structure holding the link state
1682 *      @pcaps: link Port Capabilities
1683 *      @acaps: link current Advertised Port Capabilities
1684 *
1685 *      Initializes the SW state maintained for each link, including the link's
1686 *      capabilities and default speed/flow-control/autonegotiation settings.
1687 */
1688static void csio_init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
1689                                  fw_port_cap32_t acaps)
1690{
1691        lc->pcaps = pcaps;
1692        lc->def_acaps = acaps;
1693        lc->lpacaps = 0;
1694        lc->speed_caps = 0;
1695        lc->speed = 0;
1696        lc->requested_fc = PAUSE_RX | PAUSE_TX;
1697        lc->fc = lc->requested_fc;
1698
1699        /*
1700         * For Forward Error Control, we default to whatever the Firmware
1701         * tells us the Link is currently advertising.
1702         */
1703        lc->requested_fec = FEC_AUTO;
1704        lc->fec = fwcap_to_cc_fec(lc->def_acaps);
1705
1706        /* If the Port is capable of Auto-Negtotiation, initialize it as
1707         * "enabled" and copy over all of the Physical Port Capabilities
1708         * to the Advertised Port Capabilities.  Otherwise mark it as
1709         * Auto-Negotiate disabled and select the highest supported speed
1710         * for the link.  Note parallel structure in t4_link_l1cfg_core()
1711         * and t4_handle_get_port_info().
1712         */
1713        if (lc->pcaps & FW_PORT_CAP32_ANEG) {
1714                lc->acaps = lc->pcaps & ADVERT_MASK;
1715                lc->autoneg = AUTONEG_ENABLE;
1716                lc->requested_fc |= PAUSE_AUTONEG;
1717        } else {
1718                lc->acaps = 0;
1719                lc->autoneg = AUTONEG_DISABLE;
1720        }
1721}
1722
1723static void csio_link_l1cfg(struct link_config *lc, uint16_t fw_caps,
1724                            uint32_t *rcaps)
1725{
1726        unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
1727        fw_port_cap32_t fw_fc, cc_fec, fw_fec, lrcap;
1728
1729        lc->link_ok = 0;
1730
1731        /*
1732         * Convert driver coding of Pause Frame Flow Control settings into the
1733         * Firmware's API.
1734         */
1735        fw_fc = cc_to_fwcap_pause(lc->requested_fc);
1736
1737        /*
1738         * Convert Common Code Forward Error Control settings into the
1739         * Firmware's API.  If the current Requested FEC has "Automatic"
1740         * (IEEE 802.3) specified, then we use whatever the Firmware
1741         * sent us as part of it's IEEE 802.3-based interpratation of
1742         * the Transceiver Module EPROM FEC parameters.  Otherwise we
1743         * use whatever is in the current Requested FEC settings.
1744         */
1745        if (lc->requested_fec & FEC_AUTO)
1746                cc_fec = fwcap_to_cc_fec(lc->def_acaps);
1747        else
1748                cc_fec = lc->requested_fec;
1749        fw_fec = cc_to_fwcap_fec(cc_fec);
1750
1751        /* Figure out what our Requested Port Capabilities are going to be.
1752         * Note parallel structure in t4_handle_get_port_info() and
1753         * init_link_config().
1754         */
1755        if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
1756                lrcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
1757                lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
1758                lc->fec = cc_fec;
1759        } else if (lc->autoneg == AUTONEG_DISABLE) {
1760                lrcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
1761                lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
1762                lc->fec = cc_fec;
1763        } else {
1764                lrcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
1765        }
1766
1767        *rcaps = lrcap;
1768}
1769
1770/*
1771 * csio_enable_ports - Bring up all available ports.
1772 * @hw: HW module.
1773 *
1774 */
1775static int
1776csio_enable_ports(struct csio_hw *hw)
1777{
1778        struct csio_mb  *mbp;
1779        u16 fw_caps = FW_CAPS_UNKNOWN;
1780        enum fw_retval retval;
1781        uint8_t portid;
1782        fw_port_cap32_t pcaps, acaps, rcaps;
1783        int i;
1784
1785        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1786        if (!mbp) {
1787                CSIO_INC_STATS(hw, n_err_nomem);
1788                return -ENOMEM;
1789        }
1790
1791        for (i = 0; i < hw->num_pports; i++) {
1792                portid = hw->pport[i].portid;
1793
1794                if (fw_caps == FW_CAPS_UNKNOWN) {
1795                        u32 param, val;
1796
1797                        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
1798                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
1799                        val = 1;
1800
1801                        csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO,
1802                                       hw->pfn, 0, 1, &param, &val, true,
1803                                       NULL);
1804
1805                        if (csio_mb_issue(hw, mbp)) {
1806                                csio_err(hw, "failed to issue FW_PARAMS_CMD(r) port:%d\n",
1807                                         portid);
1808                                mempool_free(mbp, hw->mb_mempool);
1809                                return -EINVAL;
1810                        }
1811
1812                        csio_mb_process_read_params_rsp(hw, mbp, &retval,
1813                                                        0, NULL);
1814                        fw_caps = retval ? FW_CAPS16 : FW_CAPS32;
1815                }
1816
1817                /* Read PORT information */
1818                csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid,
1819                             false, 0, fw_caps, NULL);
1820
1821                if (csio_mb_issue(hw, mbp)) {
1822                        csio_err(hw, "failed to issue FW_PORT_CMD(r) port:%d\n",
1823                                 portid);
1824                        mempool_free(mbp, hw->mb_mempool);
1825                        return -EINVAL;
1826                }
1827
1828                csio_mb_process_read_port_rsp(hw, mbp, &retval, fw_caps,
1829                                              &pcaps, &acaps);
1830                if (retval != FW_SUCCESS) {
1831                        csio_err(hw, "FW_PORT_CMD(r) port:%d failed: 0x%x\n",
1832                                 portid, retval);
1833                        mempool_free(mbp, hw->mb_mempool);
1834                        return -EINVAL;
1835                }
1836
1837                csio_init_link_config(&hw->pport[i].link_cfg, pcaps, acaps);
1838
1839                csio_link_l1cfg(&hw->pport[i].link_cfg, fw_caps, &rcaps);
1840
1841                /* Write back PORT information */
1842                csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid,
1843                             true, rcaps, fw_caps, NULL);
1844
1845                if (csio_mb_issue(hw, mbp)) {
1846                        csio_err(hw, "failed to issue FW_PORT_CMD(w) port:%d\n",
1847                                 portid);
1848                        mempool_free(mbp, hw->mb_mempool);
1849                        return -EINVAL;
1850                }
1851
1852                retval = csio_mb_fw_retval(mbp);
1853                if (retval != FW_SUCCESS) {
1854                        csio_err(hw, "FW_PORT_CMD(w) port:%d failed :0x%x\n",
1855                                 portid, retval);
1856                        mempool_free(mbp, hw->mb_mempool);
1857                        return -EINVAL;
1858                }
1859
1860        } /* For all ports */
1861
1862        mempool_free(mbp, hw->mb_mempool);
1863
1864        return 0;
1865}
1866
1867/*
1868 * csio_get_fcoe_resinfo - Read fcoe fw resource info.
1869 * @hw: HW module
1870 * Issued with lock held.
1871 */
1872static int
1873csio_get_fcoe_resinfo(struct csio_hw *hw)
1874{
1875        struct csio_fcoe_res_info *res_info = &hw->fres_info;
1876        struct fw_fcoe_res_info_cmd *rsp;
1877        struct csio_mb  *mbp;
1878        enum fw_retval retval;
1879
1880        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1881        if (!mbp) {
1882                CSIO_INC_STATS(hw, n_err_nomem);
1883                return -ENOMEM;
1884        }
1885
1886        /* Get FCoE FW resource information */
1887        csio_fcoe_read_res_info_init_mb(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL);
1888
1889        if (csio_mb_issue(hw, mbp)) {
1890                csio_err(hw, "failed to issue FW_FCOE_RES_INFO_CMD\n");
1891                mempool_free(mbp, hw->mb_mempool);
1892                return -EINVAL;
1893        }
1894
1895        rsp = (struct fw_fcoe_res_info_cmd *)(mbp->mb);
1896        retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16));
1897        if (retval != FW_SUCCESS) {
1898                csio_err(hw, "FW_FCOE_RES_INFO_CMD failed with ret x%x\n",
1899                         retval);
1900                mempool_free(mbp, hw->mb_mempool);
1901                return -EINVAL;
1902        }
1903
1904        res_info->e_d_tov = ntohs(rsp->e_d_tov);
1905        res_info->r_a_tov_seq = ntohs(rsp->r_a_tov_seq);
1906        res_info->r_a_tov_els = ntohs(rsp->r_a_tov_els);
1907        res_info->r_r_tov = ntohs(rsp->r_r_tov);
1908        res_info->max_xchgs = ntohl(rsp->max_xchgs);
1909        res_info->max_ssns = ntohl(rsp->max_ssns);
1910        res_info->used_xchgs = ntohl(rsp->used_xchgs);
1911        res_info->used_ssns = ntohl(rsp->used_ssns);
1912        res_info->max_fcfs = ntohl(rsp->max_fcfs);
1913        res_info->max_vnps = ntohl(rsp->max_vnps);
1914        res_info->used_fcfs = ntohl(rsp->used_fcfs);
1915        res_info->used_vnps = ntohl(rsp->used_vnps);
1916
1917        csio_dbg(hw, "max ssns:%d max xchgs:%d\n", res_info->max_ssns,
1918                                                  res_info->max_xchgs);
1919        mempool_free(mbp, hw->mb_mempool);
1920
1921        return 0;
1922}
1923
1924static int
1925csio_hw_check_fwconfig(struct csio_hw *hw, u32 *param)
1926{
1927        struct csio_mb  *mbp;
1928        enum fw_retval retval;
1929        u32 _param[1];
1930
1931        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1932        if (!mbp) {
1933                CSIO_INC_STATS(hw, n_err_nomem);
1934                return -ENOMEM;
1935        }
1936
1937        /*
1938         * Find out whether we're dealing with a version of
1939         * the firmware which has configuration file support.
1940         */
1941        _param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
1942                     FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
1943
1944        csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0,
1945                       ARRAY_SIZE(_param), _param, NULL, false, NULL);
1946        if (csio_mb_issue(hw, mbp)) {
1947                csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n");
1948                mempool_free(mbp, hw->mb_mempool);
1949                return -EINVAL;
1950        }
1951
1952        csio_mb_process_read_params_rsp(hw, mbp, &retval,
1953                        ARRAY_SIZE(_param), _param);
1954        if (retval != FW_SUCCESS) {
1955                csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n",
1956                                retval);
1957                mempool_free(mbp, hw->mb_mempool);
1958                return -EINVAL;
1959        }
1960
1961        mempool_free(mbp, hw->mb_mempool);
1962        *param = _param[0];
1963
1964        return 0;
1965}
1966
1967static int
1968csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path)
1969{
1970        int ret = 0;
1971        const struct firmware *cf;
1972        struct pci_dev *pci_dev = hw->pdev;
1973        struct device *dev = &pci_dev->dev;
1974        unsigned int mtype = 0, maddr = 0;
1975        uint32_t *cfg_data;
1976        int value_to_add = 0;
1977        const char *fw_cfg_file;
1978
1979        if (csio_is_t5(pci_dev->device & CSIO_HW_CHIP_MASK))
1980                fw_cfg_file = FW_CFG_NAME_T5;
1981        else
1982                fw_cfg_file = FW_CFG_NAME_T6;
1983
1984        if (request_firmware(&cf, fw_cfg_file, dev) < 0) {
1985                csio_err(hw, "could not find config file %s, err: %d\n",
1986                         fw_cfg_file, ret);
1987                return -ENOENT;
1988        }
1989
1990        if (cf->size%4 != 0)
1991                value_to_add = 4 - (cf->size % 4);
1992
1993        cfg_data = kzalloc(cf->size+value_to_add, GFP_KERNEL);
1994        if (cfg_data == NULL) {
1995                ret = -ENOMEM;
1996                goto leave;
1997        }
1998
1999        memcpy((void *)cfg_data, (const void *)cf->data, cf->size);
2000        if (csio_hw_check_fwconfig(hw, fw_cfg_param) != 0) {
2001                ret = -EINVAL;
2002                goto leave;
2003        }
2004
2005        mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
2006        maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
2007
2008        ret = csio_memory_write(hw, mtype, maddr,
2009                                cf->size + value_to_add, cfg_data);
2010
2011        if ((ret == 0) && (value_to_add != 0)) {
2012                union {
2013                        u32 word;
2014                        char buf[4];
2015                } last;
2016                size_t size = cf->size & ~0x3;
2017                int i;
2018
2019                last.word = cfg_data[size >> 2];
2020                for (i = value_to_add; i < 4; i++)
2021                        last.buf[i] = 0;
2022                ret = csio_memory_write(hw, mtype, maddr + size, 4, &last.word);
2023        }
2024        if (ret == 0) {
2025                csio_info(hw, "config file upgraded to %s\n", fw_cfg_file);
2026                snprintf(path, 64, "%s%s", "/lib/firmware/", fw_cfg_file);
2027        }
2028
2029leave:
2030        kfree(cfg_data);
2031        release_firmware(cf);
2032        return ret;
2033}
2034
2035/*
2036 * HW initialization: contact FW, obtain config, perform basic init.
2037 *
2038 * If the firmware we're dealing with has Configuration File support, then
2039 * we use that to perform all configuration -- either using the configuration
2040 * file stored in flash on the adapter or using a filesystem-local file
2041 * if available.
2042 *
2043 * If we don't have configuration file support in the firmware, then we'll
2044 * have to set things up the old fashioned way with hard-coded register
2045 * writes and firmware commands ...
2046 */
2047
2048/*
2049 * Attempt to initialize the HW via a Firmware Configuration File.
2050 */
2051static int
2052csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param)
2053{
2054        struct csio_mb  *mbp = NULL;
2055        struct fw_caps_config_cmd *caps_cmd;
2056        unsigned int mtype, maddr;
2057        int rv = -EINVAL;
2058        uint32_t finiver = 0, finicsum = 0, cfcsum = 0;
2059        char path[64];
2060        char *config_name = NULL;
2061
2062        /*
2063         * Reset device if necessary
2064         */
2065        if (reset) {
2066                rv = csio_do_reset(hw, true);
2067                if (rv != 0)
2068                        goto bye;
2069        }
2070
2071        /*
2072         * If we have a configuration file in host ,
2073         * then use that.  Otherwise, use the configuration file stored
2074         * in the HW flash ...
2075         */
2076        spin_unlock_irq(&hw->lock);
2077        rv = csio_hw_flash_config(hw, fw_cfg_param, path);
2078        spin_lock_irq(&hw->lock);
2079        if (rv != 0) {
2080                /*
2081                 * config file was not found. Use default
2082                 * config file from flash.
2083                 */
2084                config_name = "On FLASH";
2085                mtype = FW_MEMTYPE_CF_FLASH;
2086                maddr = hw->chip_ops->chip_flash_cfg_addr(hw);
2087        } else {
2088                config_name = path;
2089                mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
2090                maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
2091        }
2092
2093        mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
2094        if (!mbp) {
2095                CSIO_INC_STATS(hw, n_err_nomem);
2096                return -ENOMEM;
2097        }
2098        /*
2099         * Tell the firmware to process the indicated Configuration File.
2100         * If there are no errors and the caller has provided return value
2101         * pointers for the [fini] section version, checksum and computed
2102         * checksum, pass those back to the caller.
2103         */
2104        caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb);
2105        CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
2106        caps_cmd->op_to_write =
2107                htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
2108                      FW_CMD_REQUEST_F |
2109                      FW_CMD_READ_F);
2110        caps_cmd->cfvalid_to_len16 =
2111                htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
2112                      FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
2113                      FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
2114                      FW_LEN16(*caps_cmd));
2115
2116        if (csio_mb_issue(hw, mbp)) {
2117                rv = -EINVAL;
2118                goto bye;
2119        }
2120
2121        rv = csio_mb_fw_retval(mbp);
2122         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
2123          * Configuration File in FLASH), our last gasp effort is to use the
2124          * Firmware Configuration File which is embedded in the
2125          * firmware.  A very few early versions of the firmware didn't
2126          * have one embedded but we can ignore those.
2127          */
2128        if (rv == ENOENT) {
2129                CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
2130                caps_cmd->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
2131                                              FW_CMD_REQUEST_F |
2132                                              FW_CMD_READ_F);
2133                caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
2134
2135                if (csio_mb_issue(hw, mbp)) {
2136                        rv = -EINVAL;
2137                        goto bye;
2138                }
2139
2140                rv = csio_mb_fw_retval(mbp);
2141                config_name = "Firmware Default";
2142        }
2143        if (rv != FW_SUCCESS)
2144                goto bye;
2145
2146        finiver = ntohl(caps_cmd->finiver);
2147        finicsum = ntohl(caps_cmd->finicsum);
2148        cfcsum = ntohl(caps_cmd->cfcsum);
2149
2150        /*
2151         * And now tell the firmware to use the configuration we just loaded.
2152         */
2153        caps_cmd->op_to_write =
2154                htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
2155                      FW_CMD_REQUEST_F |
2156                      FW_CMD_WRITE_F);
2157        caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
2158
2159        if (csio_mb_issue(hw, mbp)) {
2160                rv = -EINVAL;
2161                goto bye;
2162        }
2163
2164        rv = csio_mb_fw_retval(mbp);
2165        if (rv != FW_SUCCESS) {
2166                csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv);
2167                goto bye;
2168        }
2169
2170        if (finicsum != cfcsum) {
2171                csio_warn(hw,
2172                      "Config File checksum mismatch: csum=%#x, computed=%#x\n",
2173                      finicsum, cfcsum);
2174        }
2175
2176        /* Validate device capabilities */
2177        rv = csio_hw_validate_caps(hw, mbp);
2178        if (rv != 0)
2179                goto bye;
2180
2181        mempool_free(mbp, hw->mb_mempool);
2182        mbp = NULL;
2183
2184        /*
2185         * Note that we're operating with parameters
2186         * not supplied by the driver, rather than from hard-wired
2187         * initialization constants buried in the driver.
2188         */
2189        hw->flags |= CSIO_HWF_USING_SOFT_PARAMS;
2190
2191        /* device parameters */
2192        rv = csio_get_device_params(hw);
2193        if (rv != 0)
2194                goto bye;
2195
2196        /* Configure SGE */
2197        csio_wr_sge_init(hw);
2198
2199        /*
2200         * And finally tell the firmware to initialize itself using the
2201         * parameters from the Configuration File.
2202         */
2203        /* Post event to notify completion of configuration */
2204        csio_post_event(&hw->sm, CSIO_HWE_INIT);
2205
2206        csio_info(hw, "Successfully configure using Firmware "
2207                  "Configuration File %s, version %#x, computed checksum %#x\n",
2208                  config_name, finiver, cfcsum);
2209        return 0;
2210
2211        /*
2212         * Something bad happened.  Return the error ...
2213         */
2214bye:
2215        if (mbp)
2216                mempool_free(mbp, hw->mb_mempool);
2217        hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS;
2218        csio_warn(hw, "Configuration file error %d\n", rv);
2219        return rv;
2220}
2221
2222/* Is the given firmware API compatible with the one the driver was compiled
2223 * with?
2224 */
2225static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2226{
2227
2228        /* short circuit if it's the exact same firmware version */
2229        if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2230                return 1;
2231
2232#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2233        if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2234            SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
2235                return 1;
2236#undef SAME_INTF
2237
2238        return 0;
2239}
2240
2241/* The firmware in the filesystem is usable, but should it be installed?
2242 * This routine explains itself in detail if it indicates the filesystem
2243 * firmware should be installed.
2244 */
2245static int csio_should_install_fs_fw(struct csio_hw *hw, int card_fw_usable,
2246                                int k, int c)
2247{
2248        const char *reason;
2249
2250        if (!card_fw_usable) {
2251                reason = "incompatible or unusable";
2252                goto install;
2253        }
2254
2255        if (k > c) {
2256                reason = "older than the version supported with this driver";
2257                goto install;
2258        }
2259
2260        return 0;
2261
2262install:
2263        csio_err(hw, "firmware on card (%u.%u.%u.%u) is %s, "
2264                "installing firmware %u.%u.%u.%u on card.\n",
2265                FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
2266                FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
2267                FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
2268                FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
2269
2270        return 1;
2271}
2272
2273static struct fw_info fw_info_array[] = {
2274        {
2275                .chip = CHELSIO_T5,
2276                .fs_name = FW_CFG_NAME_T5,
2277                .fw_mod_name = FW_FNAME_T5,
2278                .fw_hdr = {
2279                        .chip = FW_HDR_CHIP_T5,
2280                        .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
2281                        .intfver_nic = FW_INTFVER(T5, NIC),
2282                        .intfver_vnic = FW_INTFVER(T5, VNIC),
2283                        .intfver_ri = FW_INTFVER(T5, RI),
2284                        .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2285                        .intfver_fcoe = FW_INTFVER(T5, FCOE),
2286                },
2287        }, {
2288                .chip = CHELSIO_T6,
2289                .fs_name = FW_CFG_NAME_T6,
2290                .fw_mod_name = FW_FNAME_T6,
2291                .fw_hdr = {
2292                        .chip = FW_HDR_CHIP_T6,
2293                        .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
2294                        .intfver_nic = FW_INTFVER(T6, NIC),
2295                        .intfver_vnic = FW_INTFVER(T6, VNIC),
2296                        .intfver_ri = FW_INTFVER(T6, RI),
2297                        .intfver_iscsi = FW_INTFVER(T6, ISCSI),
2298                        .intfver_fcoe = FW_INTFVER(T6, FCOE),
2299                },
2300        }
2301};
2302
2303static struct fw_info *find_fw_info(int chip)
2304{
2305        int i;
2306
2307        for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
2308                if (fw_info_array[i].chip == chip)
2309                        return &fw_info_array[i];
2310        }
2311        return NULL;
2312}
2313
2314static int csio_hw_prep_fw(struct csio_hw *hw, struct fw_info *fw_info,
2315               const u8 *fw_data, unsigned int fw_size,
2316               struct fw_hdr *card_fw, enum csio_dev_state state,
2317               int *reset)
2318{
2319        int ret, card_fw_usable, fs_fw_usable;
2320        const struct fw_hdr *fs_fw;
2321        const struct fw_hdr *drv_fw;
2322
2323        drv_fw = &fw_info->fw_hdr;
2324
2325        /* Read the header of the firmware on the card */
2326        ret = csio_hw_read_flash(hw, FLASH_FW_START,
2327                            sizeof(*card_fw) / sizeof(uint32_t),
2328                            (uint32_t *)card_fw, 1);
2329        if (ret == 0) {
2330                card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
2331        } else {
2332                csio_err(hw,
2333                        "Unable to read card's firmware header: %d\n", ret);
2334                card_fw_usable = 0;
2335        }
2336
2337        if (fw_data != NULL) {
2338                fs_fw = (const void *)fw_data;
2339                fs_fw_usable = fw_compatible(drv_fw, fs_fw);
2340        } else {
2341                fs_fw = NULL;
2342                fs_fw_usable = 0;
2343        }
2344
2345        if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2346            (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
2347                /* Common case: the firmware on the card is an exact match and
2348                 * the filesystem one is an exact match too, or the filesystem
2349                 * one is absent/incompatible.
2350                 */
2351        } else if (fs_fw_usable && state == CSIO_DEV_STATE_UNINIT &&
2352                   csio_should_install_fs_fw(hw, card_fw_usable,
2353                                        be32_to_cpu(fs_fw->fw_ver),
2354                                        be32_to_cpu(card_fw->fw_ver))) {
2355                ret = csio_hw_fw_upgrade(hw, hw->pfn, fw_data,
2356                                     fw_size, 0);
2357                if (ret != 0) {
2358                        csio_err(hw,
2359                                "failed to install firmware: %d\n", ret);
2360                        goto bye;
2361                }
2362
2363                /* Installed successfully, update the cached header too. */
2364                memcpy(card_fw, fs_fw, sizeof(*card_fw));
2365                card_fw_usable = 1;
2366                *reset = 0;     /* already reset as part of load_fw */
2367        }
2368
2369        if (!card_fw_usable) {
2370                uint32_t d, c, k;
2371
2372                d = be32_to_cpu(drv_fw->fw_ver);
2373                c = be32_to_cpu(card_fw->fw_ver);
2374                k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
2375
2376                csio_err(hw, "Cannot find a usable firmware: "
2377                        "chip state %d, "
2378                        "driver compiled with %d.%d.%d.%d, "
2379                        "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
2380                        state,
2381                        FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
2382                        FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
2383                        FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
2384                        FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
2385                        FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
2386                        FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
2387                ret = EINVAL;
2388                goto bye;
2389        }
2390
2391        /* We're using whatever's on the card and it's known to be good. */
2392        hw->fwrev = be32_to_cpu(card_fw->fw_ver);
2393        hw->tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
2394
2395bye:
2396        return ret;
2397}
2398
2399/*
2400 * Returns -EINVAL if attempts to flash the firmware failed,
2401 * -ENOMEM if memory allocation failed else returns 0,
2402 * if flashing was not attempted because the card had the
2403 * latest firmware ECANCELED is returned
2404 */
2405static int
2406csio_hw_flash_fw(struct csio_hw *hw, int *reset)
2407{
2408        int ret = -ECANCELED;
2409        const struct firmware *fw;
2410        struct fw_info *fw_info;
2411        struct fw_hdr *card_fw;
2412        struct pci_dev *pci_dev = hw->pdev;
2413        struct device *dev = &pci_dev->dev ;
2414        const u8 *fw_data = NULL;
2415        unsigned int fw_size = 0;
2416        const char *fw_bin_file;
2417
2418        /* This is the firmware whose headers the driver was compiled
2419         * against
2420         */
2421        fw_info = find_fw_info(CHELSIO_CHIP_VERSION(hw->chip_id));
2422        if (fw_info == NULL) {
2423                csio_err(hw,
2424                        "unable to get firmware info for chip %d.\n",
2425                        CHELSIO_CHIP_VERSION(hw->chip_id));
2426                return -EINVAL;
2427        }
2428
2429        /* allocate memory to read the header of the firmware on the
2430         * card
2431         */
2432        card_fw = kmalloc(sizeof(*card_fw), GFP_KERNEL);
2433        if (!card_fw)
2434                return -ENOMEM;
2435
2436        if (csio_is_t5(pci_dev->device & CSIO_HW_CHIP_MASK))
2437                fw_bin_file = FW_FNAME_T5;
2438        else
2439                fw_bin_file = FW_FNAME_T6;
2440
2441        if (request_firmware(&fw, fw_bin_file, dev) < 0) {
2442                csio_err(hw, "could not find firmware image %s, err: %d\n",
2443                         fw_bin_file, ret);
2444        } else {
2445                fw_data = fw->data;
2446                fw_size = fw->size;
2447        }
2448
2449        /* upgrade FW logic */
2450        ret = csio_hw_prep_fw(hw, fw_info, fw_data, fw_size, card_fw,
2451                         hw->fw_state, reset);
2452
2453        /* Cleaning up */
2454        if (fw != NULL)
2455                release_firmware(fw);
2456        kfree(card_fw);
2457        return ret;
2458}
2459
2460static int csio_hw_check_fwver(struct csio_hw *hw)
2461{
2462        if (csio_is_t6(hw->pdev->device & CSIO_HW_CHIP_MASK) &&
2463            (hw->fwrev < CSIO_MIN_T6_FW)) {
2464                csio_hw_print_fw_version(hw, "T6 unsupported fw");
2465                return -1;
2466        }
2467
2468        return 0;
2469}
2470
2471/*
2472 * csio_hw_configure - Configure HW
2473 * @hw - HW module
2474 *
2475 */
2476static void
2477csio_hw_configure(struct csio_hw *hw)
2478{
2479        int reset = 1;
2480        int rv;
2481        u32 param[1];
2482
2483        rv = csio_hw_dev_ready(hw);
2484        if (rv != 0) {
2485                CSIO_INC_STATS(hw, n_err_fatal);
2486                csio_post_event(&hw->sm, CSIO_HWE_FATAL);
2487                goto out;
2488        }
2489
2490        /* HW version */
2491        hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A);
2492
2493        /* Needed for FW download */
2494        rv = csio_hw_get_flash_params(hw);
2495        if (rv != 0) {
2496                csio_err(hw, "Failed to get serial flash params rv:%d\n", rv);
2497                csio_post_event(&hw->sm, CSIO_HWE_FATAL);
2498                goto out;
2499        }
2500
2501        /* Set PCIe completion timeout to 4 seconds */
2502        if (pci_is_pcie(hw->pdev))
2503                pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2,
2504                                PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
2505
2506        hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR);
2507
2508        rv = csio_hw_get_fw_version(hw, &hw->fwrev);
2509        if (rv != 0)
2510                goto out;
2511
2512        csio_hw_print_fw_version(hw, "Firmware revision");
2513
2514        rv = csio_do_hello(hw, &hw->fw_state);
2515        if (rv != 0) {
2516                CSIO_INC_STATS(hw, n_err_fatal);
2517                csio_post_event(&hw->sm, CSIO_HWE_FATAL);
2518                goto out;
2519        }
2520
2521        /* Read vpd */
2522        rv = csio_hw_get_vpd_params(hw, &hw->vpd);
2523        if (rv != 0)
2524                goto out;
2525
2526        csio_hw_get_fw_version(hw, &hw->fwrev);
2527        csio_hw_get_tp_version(hw, &hw->tp_vers);
2528        if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) {
2529
2530                        /* Do firmware update */
2531                spin_unlock_irq(&hw->lock);
2532                rv = csio_hw_flash_fw(hw, &reset);
2533                spin_lock_irq(&hw->lock);
2534
2535                if (rv != 0)
2536                        goto out;
2537
2538                rv = csio_hw_check_fwver(hw);
2539                if (rv < 0)
2540                        goto out;
2541
2542                /* If the firmware doesn't support Configuration Files,
2543                 * return an error.
2544                 */
2545                rv = csio_hw_check_fwconfig(hw, param);
2546                if (rv != 0) {
2547                        csio_info(hw, "Firmware doesn't support "
2548                                  "Firmware Configuration files\n");
2549                        goto out;
2550                }
2551
2552                /* The firmware provides us with a memory buffer where we can
2553                 * load a Configuration File from the host if we want to
2554                 * override the Configuration File in flash.
2555                 */
2556                rv = csio_hw_use_fwconfig(hw, reset, param);
2557                if (rv == -ENOENT) {
2558                        csio_info(hw, "Could not initialize "
2559                                  "adapter, error%d\n", rv);
2560                        goto out;
2561                }
2562                if (rv != 0) {
2563                        csio_info(hw, "Could not initialize "
2564                                  "adapter, error%d\n", rv);
2565                        goto out;
2566                }
2567
2568        } else {
2569                rv = csio_hw_check_fwver(hw);
2570                if (rv < 0)
2571                        goto out;
2572
2573                if (hw->fw_state == CSIO_DEV_STATE_INIT) {
2574
2575                        hw->flags |= CSIO_HWF_USING_SOFT_PARAMS;
2576
2577                        /* device parameters */
2578                        rv = csio_get_device_params(hw);
2579                        if (rv != 0)
2580                                goto out;
2581
2582                        /* Get device capabilities */
2583                        rv = csio_config_device_caps(hw);
2584                        if (rv != 0)
2585                                goto out;
2586
2587                        /* Configure SGE */
2588                        csio_wr_sge_init(hw);
2589
2590                        /* Post event to notify completion of configuration */
2591                        csio_post_event(&hw->sm, CSIO_HWE_INIT);
2592                        goto out;
2593                }
2594        } /* if not master */
2595
2596out:
2597        return;
2598}
2599
2600/*
2601 * csio_hw_initialize - Initialize HW
2602 * @hw - HW module
2603 *
2604 */
2605static void
2606csio_hw_initialize(struct csio_hw *hw)
2607{
2608        struct csio_mb  *mbp;
2609        enum fw_retval retval;
2610        int rv;
2611        int i;
2612
2613        if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) {
2614                mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
2615                if (!mbp)
2616                        goto out;
2617
2618                csio_mb_initialize(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL);
2619
2620                if (csio_mb_issue(hw, mbp)) {
2621                        csio_err(hw, "Issue of FW_INITIALIZE_CMD failed!\n");
2622                        goto free_and_out;
2623                }
2624
2625                retval = csio_mb_fw_retval(mbp);
2626                if (retval != FW_SUCCESS) {
2627                        csio_err(hw, "FW_INITIALIZE_CMD returned 0x%x!\n",
2628                                 retval);
2629                        goto free_and_out;
2630                }
2631
2632                mempool_free(mbp, hw->mb_mempool);
2633        }
2634
2635        rv = csio_get_fcoe_resinfo(hw);
2636        if (rv != 0) {
2637                csio_err(hw, "Failed to read fcoe resource info: %d\n", rv);
2638                goto out;
2639        }
2640
2641        spin_unlock_irq(&hw->lock);
2642        rv = csio_config_queues(hw);
2643        spin_lock_irq(&hw->lock);
2644
2645        if (rv != 0) {
2646                csio_err(hw, "Config of queues failed!: %d\n", rv);
2647                goto out;
2648        }
2649
2650        for (i = 0; i < hw->num_pports; i++)
2651                hw->pport[i].mod_type = FW_PORT_MOD_TYPE_NA;
2652
2653        if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) {
2654                rv = csio_enable_ports(hw);
2655                if (rv != 0) {
2656                        csio_err(hw, "Failed to enable ports: %d\n", rv);
2657                        goto out;
2658                }
2659        }
2660
2661        csio_post_event(&hw->sm, CSIO_HWE_INIT_DONE);
2662        return;
2663
2664free_and_out:
2665        mempool_free(mbp, hw->mb_mempool);
2666out:
2667        return;
2668}
2669
2670#define PF_INTR_MASK (PFSW_F | PFCIM_F)
2671
2672/*
2673 * csio_hw_intr_enable - Enable HW interrupts
2674 * @hw: Pointer to HW module.
2675 *
2676 * Enable interrupts in HW registers.
2677 */
2678static void
2679csio_hw_intr_enable(struct csio_hw *hw)
2680{
2681        uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw));
2682        u32 pf = 0;
2683        uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A);
2684
2685        if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK))
2686                pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2687        else
2688                pf = T6_SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2689
2690        /*
2691         * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up
2692         * by FW, so do nothing for INTX.
2693         */
2694        if (hw->intr_mode == CSIO_IM_MSIX)
2695                csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2696                                   AIVEC_V(AIVEC_M), vec);
2697        else if (hw->intr_mode == CSIO_IM_MSI)
2698                csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2699                                   AIVEC_V(AIVEC_M), 0);
2700
2701        csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A));
2702
2703        /* Turn on MB interrupts - this will internally flush PIO as well */
2704        csio_mb_intr_enable(hw);
2705
2706        /* These are common registers - only a master can modify them */
2707        if (csio_is_hw_master(hw)) {
2708                /*
2709                 * Disable the Serial FLASH interrupt, if enabled!
2710                 */
2711                pl &= (~SF_F);
2712                csio_wr_reg32(hw, pl, PL_INT_ENABLE_A);
2713
2714                csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F |
2715                              EGRESS_SIZE_ERR_F | ERR_INVALID_CIDX_INC_F |
2716                              ERR_CPL_OPCODE_0_F | ERR_DROPPED_DB_F |
2717                              ERR_DATA_CPL_ON_HIGH_QID1_F |
2718                              ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
2719                              ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
2720                              ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
2721                              ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F,
2722                              SGE_INT_ENABLE3_A);
2723                csio_set_reg_field(hw, PL_INT_MAP0_A, 0, 1 << pf);
2724        }
2725
2726        hw->flags |= CSIO_HWF_HW_INTR_ENABLED;
2727
2728}
2729
2730/*
2731 * csio_hw_intr_disable - Disable HW interrupts
2732 * @hw: Pointer to HW module.
2733 *
2734 * Turn off Mailbox and PCI_PF_CFG interrupts.
2735 */
2736void
2737csio_hw_intr_disable(struct csio_hw *hw)
2738{
2739        u32 pf = 0;
2740
2741        if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK))
2742                pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2743        else
2744                pf = T6_SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2745
2746        if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED))
2747                return;
2748
2749        hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED;
2750
2751        csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A));
2752        if (csio_is_hw_master(hw))
2753                csio_set_reg_field(hw, PL_INT_MAP0_A, 1 << pf, 0);
2754
2755        /* Turn off MB interrupts */
2756        csio_mb_intr_disable(hw);
2757
2758}
2759
2760void
2761csio_hw_fatal_err(struct csio_hw *hw)
2762{
2763        csio_set_reg_field(hw, SGE_CONTROL_A, GLOBALENABLE_F, 0);
2764        csio_hw_intr_disable(hw);
2765
2766        /* Do not reset HW, we may need FW state for debugging */
2767        csio_fatal(hw, "HW Fatal error encountered!\n");
2768}
2769
2770/*****************************************************************************/
2771/* START: HW SM                                                              */
2772/*****************************************************************************/
2773/*
2774 * csio_hws_uninit - Uninit state
2775 * @hw - HW module
2776 * @evt - Event
2777 *
2778 */
2779static void
2780csio_hws_uninit(struct csio_hw *hw, enum csio_hw_ev evt)
2781{
2782        hw->prev_evt = hw->cur_evt;
2783        hw->cur_evt = evt;
2784        CSIO_INC_STATS(hw, n_evt_sm[evt]);
2785
2786        switch (evt) {
2787        case CSIO_HWE_CFG:
2788                csio_set_state(&hw->sm, csio_hws_configuring);
2789                csio_hw_configure(hw);
2790                break;
2791
2792        default:
2793                CSIO_INC_STATS(hw, n_evt_unexp);
2794                break;
2795        }
2796}
2797
2798/*
2799 * csio_hws_configuring - Configuring state
2800 * @hw - HW module
2801 * @evt - Event
2802 *
2803 */
2804static void
2805csio_hws_configuring(struct csio_hw *hw, enum csio_hw_ev evt)
2806{
2807        hw->prev_evt = hw->cur_evt;
2808        hw->cur_evt = evt;
2809        CSIO_INC_STATS(hw, n_evt_sm[evt]);
2810
2811        switch (evt) {
2812        case CSIO_HWE_INIT:
2813                csio_set_state(&hw->sm, csio_hws_initializing);
2814                csio_hw_initialize(hw);
2815                break;
2816
2817        case CSIO_HWE_INIT_DONE:
2818                csio_set_state(&hw->sm, csio_hws_ready);
2819                /* Fan out event to all lnode SMs */
2820                csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY);
2821                break;
2822
2823        case CSIO_HWE_FATAL:
2824                csio_set_state(&hw->sm, csio_hws_uninit);
2825                break;
2826
2827        case CSIO_HWE_PCI_REMOVE:
2828                csio_do_bye(hw);
2829                break;
2830        default:
2831                CSIO_INC_STATS(hw, n_evt_unexp);
2832                break;
2833        }
2834}
2835
2836/*
2837 * csio_hws_initializing - Initialiazing state
2838 * @hw - HW module
2839 * @evt - Event
2840 *
2841 */
2842static void
2843csio_hws_initializing(struct csio_hw *hw, enum csio_hw_ev evt)
2844{
2845        hw->prev_evt = hw->cur_evt;
2846        hw->cur_evt = evt;
2847        CSIO_INC_STATS(hw, n_evt_sm[evt]);
2848
2849        switch (evt) {
2850        case CSIO_HWE_INIT_DONE:
2851                csio_set_state(&hw->sm, csio_hws_ready);
2852
2853                /* Fan out event to all lnode SMs */
2854                csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY);
2855
2856                /* Enable interrupts */
2857                csio_hw_intr_enable(hw);
2858                break;
2859
2860        case CSIO_HWE_FATAL:
2861                csio_set_state(&hw->sm, csio_hws_uninit);
2862                break;
2863
2864        case CSIO_HWE_PCI_REMOVE:
2865                csio_do_bye(hw);
2866                break;
2867
2868        default:
2869                CSIO_INC_STATS(hw, n_evt_unexp);
2870                break;
2871        }
2872}
2873
2874/*
2875 * csio_hws_ready - Ready state
2876 * @hw - HW module
2877 * @evt - Event
2878 *
2879 */
2880static void
2881csio_hws_ready(struct csio_hw *hw, enum csio_hw_ev evt)
2882{
2883        /* Remember the event */
2884        hw->evtflag = evt;
2885
2886        hw->prev_evt = hw->cur_evt;
2887        hw->cur_evt = evt;
2888        CSIO_INC_STATS(hw, n_evt_sm[evt]);
2889
2890        switch (evt) {
2891        case CSIO_HWE_HBA_RESET:
2892        case CSIO_HWE_FW_DLOAD:
2893        case CSIO_HWE_SUSPEND:
2894        case CSIO_HWE_PCI_REMOVE:
2895        case CSIO_HWE_PCIERR_DETECTED:
2896                csio_set_state(&hw->sm, csio_hws_quiescing);
2897                /* cleanup all outstanding cmds */
2898                if (evt == CSIO_HWE_HBA_RESET ||
2899                    evt == CSIO_HWE_PCIERR_DETECTED)
2900                        csio_scsim_cleanup_io(csio_hw_to_scsim(hw), false);
2901                else
2902                        csio_scsim_cleanup_io(csio_hw_to_scsim(hw), true);
2903
2904                csio_hw_intr_disable(hw);
2905                csio_hw_mbm_cleanup(hw);
2906                csio_evtq_stop(hw);
2907                csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWSTOP);
2908                csio_evtq_flush(hw);
2909                csio_mgmtm_cleanup(csio_hw_to_mgmtm(hw));
2910                csio_post_event(&hw->sm, CSIO_HWE_QUIESCED);
2911                break;
2912
2913        case CSIO_HWE_FATAL:
2914                csio_set_state(&hw->sm, csio_hws_uninit);
2915                break;
2916
2917        default:
2918                CSIO_INC_STATS(hw, n_evt_unexp);
2919                break;
2920        }
2921}
2922
2923/*
2924 * csio_hws_quiescing - Quiescing state
2925 * @hw - HW module
2926 * @evt - Event
2927 *
2928 */
2929static void
2930csio_hws_quiescing(struct csio_hw *hw, enum csio_hw_ev evt)
2931{
2932        hw->prev_evt = hw->cur_evt;
2933        hw->cur_evt = evt;
2934        CSIO_INC_STATS(hw, n_evt_sm[evt]);
2935
2936        switch (evt) {
2937        case CSIO_HWE_QUIESCED:
2938                switch (hw->evtflag) {
2939                case CSIO_HWE_FW_DLOAD:
2940                        csio_set_state(&hw->sm, csio_hws_resetting);
2941                        /* Download firmware */
2942                        /* Fall through */
2943
2944                case CSIO_HWE_HBA_RESET:
2945                        csio_set_state(&hw->sm, csio_hws_resetting);
2946                        /* Start reset of the HBA */
2947                        csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWRESET);
2948                        csio_wr_destroy_queues(hw, false);
2949                        csio_do_reset(hw, false);
2950                        csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET_DONE);
2951                        break;
2952
2953                case CSIO_HWE_PCI_REMOVE:
2954                        csio_set_state(&hw->sm, csio_hws_removing);
2955                        csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREMOVE);
2956                        csio_wr_destroy_queues(hw, true);
2957                        /* Now send the bye command */
2958                        csio_do_bye(hw);
2959                        break;
2960
2961                case CSIO_HWE_SUSPEND:
2962                        csio_set_state(&hw->sm, csio_hws_quiesced);
2963                        break;
2964
2965                case CSIO_HWE_PCIERR_DETECTED:
2966                        csio_set_state(&hw->sm, csio_hws_pcierr);
2967                        csio_wr_destroy_queues(hw, false);
2968                        break;
2969
2970                default:
2971                        CSIO_INC_STATS(hw, n_evt_unexp);
2972                        break;
2973
2974                }
2975                break;
2976
2977        default:
2978                CSIO_INC_STATS(hw, n_evt_unexp);
2979                break;
2980        }
2981}
2982
2983/*
2984 * csio_hws_quiesced - Quiesced state
2985 * @hw - HW module
2986 * @evt - Event
2987 *
2988 */
2989static void
2990csio_hws_quiesced(struct csio_hw *hw, enum csio_hw_ev evt)
2991{
2992        hw->prev_evt = hw->cur_evt;
2993        hw->cur_evt = evt;
2994        CSIO_INC_STATS(hw, n_evt_sm[evt]);
2995
2996        switch (evt) {
2997        case CSIO_HWE_RESUME:
2998                csio_set_state(&hw->sm, csio_hws_configuring);
2999                csio_hw_configure(hw);
3000                break;
3001
3002        default:
3003                CSIO_INC_STATS(hw, n_evt_unexp);
3004                break;
3005        }
3006}
3007
3008/*
3009 * csio_hws_resetting - HW Resetting state
3010 * @hw - HW module
3011 * @evt - Event
3012 *
3013 */
3014static void
3015csio_hws_resetting(struct csio_hw *hw, enum csio_hw_ev evt)
3016{
3017        hw->prev_evt = hw->cur_evt;
3018        hw->cur_evt = evt;
3019        CSIO_INC_STATS(hw, n_evt_sm[evt]);
3020
3021        switch (evt) {
3022        case CSIO_HWE_HBA_RESET_DONE:
3023                csio_evtq_start(hw);
3024                csio_set_state(&hw->sm, csio_hws_configuring);
3025                csio_hw_configure(hw);
3026                break;
3027
3028        default:
3029                CSIO_INC_STATS(hw, n_evt_unexp);
3030                break;
3031        }
3032}
3033
3034/*
3035 * csio_hws_removing - PCI Hotplug removing state
3036 * @hw - HW module
3037 * @evt - Event
3038 *
3039 */
3040static void
3041csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt)
3042{
3043        hw->prev_evt = hw->cur_evt;
3044        hw->cur_evt = evt;
3045        CSIO_INC_STATS(hw, n_evt_sm[evt]);
3046
3047        switch (evt) {
3048        case CSIO_HWE_HBA_RESET:
3049                if (!csio_is_hw_master(hw))
3050                        break;
3051                /*
3052                 * The BYE should have alerady been issued, so we cant
3053                 * use the mailbox interface. Hence we use the PL_RST
3054                 * register directly.
3055                 */
3056                csio_err(hw, "Resetting HW and waiting 2 seconds...\n");
3057                csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
3058                mdelay(2000);
3059                break;
3060
3061        /* Should never receive any new events */
3062        default:
3063                CSIO_INC_STATS(hw, n_evt_unexp);
3064                break;
3065
3066        }
3067}
3068
3069/*
3070 * csio_hws_pcierr - PCI Error state
3071 * @hw - HW module
3072 * @evt - Event
3073 *
3074 */
3075static void
3076csio_hws_pcierr(struct csio_hw *hw, enum csio_hw_ev evt)
3077{
3078        hw->prev_evt = hw->cur_evt;
3079        hw->cur_evt = evt;
3080        CSIO_INC_STATS(hw, n_evt_sm[evt]);
3081
3082        switch (evt) {
3083        case CSIO_HWE_PCIERR_SLOT_RESET:
3084                csio_evtq_start(hw);
3085                csio_set_state(&hw->sm, csio_hws_configuring);
3086                csio_hw_configure(hw);
3087                break;
3088
3089        default:
3090                CSIO_INC_STATS(hw, n_evt_unexp);
3091                break;
3092        }
3093}
3094
3095/*****************************************************************************/
3096/* END: HW SM                                                                */
3097/*****************************************************************************/
3098
3099/*
3100 *      csio_handle_intr_status - table driven interrupt handler
3101 *      @hw: HW instance
3102 *      @reg: the interrupt status register to process
3103 *      @acts: table of interrupt actions
3104 *
3105 *      A table driven interrupt handler that applies a set of masks to an
3106 *      interrupt status word and performs the corresponding actions if the
3107 *      interrupts described by the mask have occured.  The actions include
3108 *      optionally emitting a warning or alert message. The table is terminated
3109 *      by an entry specifying mask 0.  Returns the number of fatal interrupt
3110 *      conditions.
3111 */
3112int
3113csio_handle_intr_status(struct csio_hw *hw, unsigned int reg,
3114                                 const struct intr_info *acts)
3115{
3116        int fatal = 0;
3117        unsigned int mask = 0;
3118        unsigned int status = csio_rd_reg32(hw, reg);
3119
3120        for ( ; acts->mask; ++acts) {
3121                if (!(status & acts->mask))
3122                        continue;
3123                if (acts->fatal) {
3124                        fatal++;
3125                        csio_fatal(hw, "Fatal %s (0x%x)\n",
3126                                    acts->msg, status & acts->mask);
3127                } else if (acts->msg)
3128                        csio_info(hw, "%s (0x%x)\n",
3129                                    acts->msg, status & acts->mask);
3130                mask |= acts->mask;
3131        }
3132        status &= mask;
3133        if (status)                           /* clear processed interrupts */
3134                csio_wr_reg32(hw, status, reg);
3135        return fatal;
3136}
3137
3138/*
3139 * TP interrupt handler.
3140 */
3141static void csio_tp_intr_handler(struct csio_hw *hw)
3142{
3143        static struct intr_info tp_intr_info[] = {
3144                { 0x3fffffff, "TP parity error", -1, 1 },
3145                { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3146                { 0, NULL, 0, 0 }
3147        };
3148
3149        if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info))
3150                csio_hw_fatal_err(hw);
3151}
3152
3153/*
3154 * SGE interrupt handler.
3155 */
3156static void csio_sge_intr_handler(struct csio_hw *hw)
3157{
3158        uint64_t v;
3159
3160        static struct intr_info sge_intr_info[] = {
3161                { ERR_CPL_EXCEED_IQE_SIZE_F,
3162                  "SGE received CPL exceeding IQE size", -1, 1 },
3163                { ERR_INVALID_CIDX_INC_F,
3164                  "SGE GTS CIDX increment too large", -1, 0 },
3165                { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3166                { ERR_DROPPED_DB_F, "SGE doorbell dropped", -1, 0 },
3167                { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3168                  "SGE IQID > 1023 received CPL for FL", -1, 0 },
3169                { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3170                  0 },
3171                { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3172                  0 },
3173                { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3174                  0 },
3175                { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3176                  0 },
3177                { ERR_ING_CTXT_PRIO_F,
3178                  "SGE too many priority ingress contexts", -1, 0 },
3179                { ERR_EGR_CTXT_PRIO_F,
3180                  "SGE too many priority egress contexts", -1, 0 },
3181                { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3182                { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3183                { 0, NULL, 0, 0 }
3184        };
3185
3186        v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) |
3187            ((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2_A) << 32);
3188        if (v) {
3189                csio_fatal(hw, "SGE parity error (%#llx)\n",
3190                            (unsigned long long)v);
3191                csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF),
3192                                                SGE_INT_CAUSE1_A);
3193                csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A);
3194        }
3195
3196        v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info);
3197
3198        if (csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info) ||
3199            v != 0)
3200                csio_hw_fatal_err(hw);
3201}
3202
3203#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3204                      OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3205#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3206                      IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3207
3208/*
3209 * CIM interrupt handler.
3210 */
3211static void csio_cim_intr_handler(struct csio_hw *hw)
3212{
3213        static struct intr_info cim_intr_info[] = {
3214                { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3215                { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3216                { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3217                { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3218                { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3219                { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3220                { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3221                { 0, NULL, 0, 0 }
3222        };
3223        static struct intr_info cim_upintr_info[] = {
3224                { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3225                { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3226                { ILLWRINT_F, "CIM illegal write", -1, 1 },
3227                { ILLRDINT_F, "CIM illegal read", -1, 1 },
3228                { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3229                { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3230                { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3231                { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3232                { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3233                { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3234                { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3235                { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3236                { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3237                { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3238                { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3239                { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3240                { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3241                { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3242                { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3243                { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3244                { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3245                { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3246                { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3247                { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3248                { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3249                { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3250                { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3251                { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3252                { 0, NULL, 0, 0 }
3253        };
3254
3255        int fat;
3256
3257        fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE_A,
3258                                      cim_intr_info) +
3259              csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE_A,
3260                                      cim_upintr_info);
3261        if (fat)
3262                csio_hw_fatal_err(hw);
3263}
3264
3265/*
3266 * ULP RX interrupt handler.
3267 */
3268static void csio_ulprx_intr_handler(struct csio_hw *hw)
3269{
3270        static struct intr_info ulprx_intr_info[] = {
3271                { 0x1800000, "ULPRX context error", -1, 1 },
3272                { 0x7fffff, "ULPRX parity error", -1, 1 },
3273                { 0, NULL, 0, 0 }
3274        };
3275
3276        if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3277                csio_hw_fatal_err(hw);
3278}
3279
3280/*
3281 * ULP TX interrupt handler.
3282 */
3283static void csio_ulptx_intr_handler(struct csio_hw *hw)
3284{
3285        static struct intr_info ulptx_intr_info[] = {
3286                { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
3287                  0 },
3288                { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
3289                  0 },
3290                { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
3291                  0 },
3292                { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
3293                  0 },
3294                { 0xfffffff, "ULPTX parity error", -1, 1 },
3295                { 0, NULL, 0, 0 }
3296        };
3297
3298        if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
3299                csio_hw_fatal_err(hw);
3300}
3301
3302/*
3303 * PM TX interrupt handler.
3304 */
3305static void csio_pmtx_intr_handler(struct csio_hw *hw)
3306{
3307        static struct intr_info pmtx_intr_info[] = {
3308                { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
3309                { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
3310                { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
3311                { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
3312                { 0xffffff0, "PMTX framing error", -1, 1 },
3313                { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
3314                { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1,
3315                  1 },
3316                { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
3317                { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
3318                { 0, NULL, 0, 0 }
3319        };
3320
3321        if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info))
3322                csio_hw_fatal_err(hw);
3323}
3324
3325/*
3326 * PM RX interrupt handler.
3327 */
3328static void csio_pmrx_intr_handler(struct csio_hw *hw)
3329{
3330        static struct intr_info pmrx_intr_info[] = {
3331                { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
3332                { 0x3ffff0, "PMRX framing error", -1, 1 },
3333                { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
3334                { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1,
3335                  1 },
3336                { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
3337                { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
3338                { 0, NULL, 0, 0 }
3339        };
3340
3341        if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info))
3342                csio_hw_fatal_err(hw);
3343}
3344
3345/*
3346 * CPL switch interrupt handler.
3347 */
3348static void csio_cplsw_intr_handler(struct csio_hw *hw)
3349{
3350        static struct intr_info cplsw_intr_info[] = {
3351                { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
3352                { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
3353                { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
3354                { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
3355                { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
3356                { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
3357                { 0, NULL, 0, 0 }
3358        };
3359
3360        if (csio_handle_intr_status(hw, CPL_INTR_CAUSE_A, cplsw_intr_info))
3361                csio_hw_fatal_err(hw);
3362}
3363
3364/*
3365 * LE interrupt handler.
3366 */
3367static void csio_le_intr_handler(struct csio_hw *hw)
3368{
3369        enum chip_type chip = CHELSIO_CHIP_VERSION(hw->chip_id);
3370
3371        static struct intr_info le_intr_info[] = {
3372                { LIPMISS_F, "LE LIP miss", -1, 0 },
3373                { LIP0_F, "LE 0 LIP error", -1, 0 },
3374                { PARITYERR_F, "LE parity error", -1, 1 },
3375                { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
3376                { REQQPARERR_F, "LE request queue parity error", -1, 1 },
3377                { 0, NULL, 0, 0 }
3378        };
3379
3380        static struct intr_info t6_le_intr_info[] = {
3381                { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
3382                { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
3383                { TCAMINTPERR_F, "LE parity error", -1, 1 },
3384                { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
3385                { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
3386                { 0, NULL, 0, 0 }
3387        };
3388
3389        if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE_A,
3390                                    (chip == CHELSIO_T5) ?
3391                                    le_intr_info : t6_le_intr_info))
3392                csio_hw_fatal_err(hw);
3393}
3394
3395/*
3396 * MPS interrupt handler.
3397 */
3398static void csio_mps_intr_handler(struct csio_hw *hw)
3399{
3400        static struct intr_info mps_rx_intr_info[] = {
3401                { 0xffffff, "MPS Rx parity error", -1, 1 },
3402                { 0, NULL, 0, 0 }
3403        };
3404        static struct intr_info mps_tx_intr_info[] = {
3405                { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
3406                { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
3407                { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
3408                  -1, 1 },
3409                { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
3410                  -1, 1 },
3411                { BUBBLE_F, "MPS Tx underflow", -1, 1 },
3412                { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
3413                { FRMERR_F, "MPS Tx framing error", -1, 1 },
3414                { 0, NULL, 0, 0 }
3415        };
3416        static struct intr_info mps_trc_intr_info[] = {
3417                { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
3418                { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
3419                  -1, 1 },
3420                { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
3421                { 0, NULL, 0, 0 }
3422        };
3423        static struct intr_info mps_stat_sram_intr_info[] = {
3424                { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
3425                { 0, NULL, 0, 0 }
3426        };
3427        static struct intr_info mps_stat_tx_intr_info[] = {
3428                { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
3429                { 0, NULL, 0, 0 }
3430        };
3431        static struct intr_info mps_stat_rx_intr_info[] = {
3432                { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
3433                { 0, NULL, 0, 0 }
3434        };
3435        static struct intr_info mps_cls_intr_info[] = {
3436                { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
3437                { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
3438                { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
3439                { 0, NULL, 0, 0 }
3440        };
3441
3442        int fat;
3443
3444        fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A,
3445                                      mps_rx_intr_info) +
3446              csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A,
3447                                      mps_tx_intr_info) +
3448              csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A,
3449                                      mps_trc_intr_info) +
3450              csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
3451                                      mps_stat_sram_intr_info) +
3452              csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
3453                                      mps_stat_tx_intr_info) +
3454              csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
3455                                      mps_stat_rx_intr_info) +
3456              csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A,
3457                                      mps_cls_intr_info);
3458
3459        csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A);
3460        csio_rd_reg32(hw, MPS_INT_CAUSE_A);                    /* flush */
3461        if (fat)
3462                csio_hw_fatal_err(hw);
3463}
3464
3465#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
3466                      ECC_UE_INT_CAUSE_F)
3467
3468/*
3469 * EDC/MC interrupt handler.
3470 */
3471static void csio_mem_intr_handler(struct csio_hw *hw, int idx)
3472{
3473        static const char name[3][5] = { "EDC0", "EDC1", "MC" };
3474
3475        unsigned int addr, cnt_addr, v;
3476
3477        if (idx <= MEM_EDC1) {
3478                addr = EDC_REG(EDC_INT_CAUSE_A, idx);
3479                cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
3480        } else {
3481                addr = MC_INT_CAUSE_A;
3482                cnt_addr = MC_ECC_STATUS_A;
3483        }
3484
3485        v = csio_rd_reg32(hw, addr) & MEM_INT_MASK;
3486        if (v & PERR_INT_CAUSE_F)
3487                csio_fatal(hw, "%s FIFO parity error\n", name[idx]);
3488        if (v & ECC_CE_INT_CAUSE_F) {
3489                uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr));
3490
3491                csio_wr_reg32(hw, ECC_CECNT_V(ECC_CECNT_M), cnt_addr);
3492                csio_warn(hw, "%u %s correctable ECC data error%s\n",
3493                            cnt, name[idx], cnt > 1 ? "s" : "");
3494        }
3495        if (v & ECC_UE_INT_CAUSE_F)
3496                csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]);
3497
3498        csio_wr_reg32(hw, v, addr);
3499        if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
3500                csio_hw_fatal_err(hw);
3501}
3502
3503/*
3504 * MA interrupt handler.
3505 */
3506static void csio_ma_intr_handler(struct csio_hw *hw)
3507{
3508        uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A);
3509
3510        if (status & MEM_PERR_INT_CAUSE_F)
3511                csio_fatal(hw, "MA parity error, parity status %#x\n",
3512                            csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS_A));
3513        if (status & MEM_WRAP_INT_CAUSE_F) {
3514                v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A);
3515                csio_fatal(hw,
3516                   "MA address wrap-around error by client %u to address %#x\n",
3517                   MEM_WRAP_CLIENT_NUM_G(v), MEM_WRAP_ADDRESS_G(v) << 4);
3518        }
3519        csio_wr_reg32(hw, status, MA_INT_CAUSE_A);
3520        csio_hw_fatal_err(hw);
3521}
3522
3523/*
3524 * SMB interrupt handler.
3525 */
3526static void csio_smb_intr_handler(struct csio_hw *hw)
3527{
3528        static struct intr_info smb_intr_info[] = {
3529                { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
3530                { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
3531                { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
3532                { 0, NULL, 0, 0 }
3533        };
3534
3535        if (csio_handle_intr_status(hw, SMB_INT_CAUSE_A, smb_intr_info))
3536                csio_hw_fatal_err(hw);
3537}
3538
3539/*
3540 * NC-SI interrupt handler.
3541 */
3542static void csio_ncsi_intr_handler(struct csio_hw *hw)
3543{
3544        static struct intr_info ncsi_intr_info[] = {
3545                { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
3546                { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
3547                { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
3548                { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
3549                { 0, NULL, 0, 0 }
3550        };
3551
3552        if (csio_handle_intr_status(hw, NCSI_INT_CAUSE_A, ncsi_intr_info))
3553                csio_hw_fatal_err(hw);
3554}
3555
3556/*
3557 * XGMAC interrupt handler.
3558 */
3559static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
3560{
3561        uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
3562
3563        v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
3564        if (!v)
3565                return;
3566
3567        if (v & TXFIFO_PRTY_ERR_F)
3568                csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port);
3569        if (v & RXFIFO_PRTY_ERR_F)
3570                csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port);
3571        csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
3572        csio_hw_fatal_err(hw);
3573}
3574
3575/*
3576 * PL interrupt handler.
3577 */
3578static void csio_pl_intr_handler(struct csio_hw *hw)
3579{
3580        static struct intr_info pl_intr_info[] = {
3581                { FATALPERR_F, "T4 fatal parity error", -1, 1 },
3582                { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
3583                { 0, NULL, 0, 0 }
3584        };
3585
3586        if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE_A, pl_intr_info))
3587                csio_hw_fatal_err(hw);
3588}
3589
3590/*
3591 *      csio_hw_slow_intr_handler - control path interrupt handler
3592 *      @hw: HW module
3593 *
3594 *      Interrupt handler for non-data global interrupt events, e.g., errors.
3595 *      The designation 'slow' is because it involves register reads, while
3596 *      data interrupts typically don't involve any MMIOs.
3597 */
3598int
3599csio_hw_slow_intr_handler(struct csio_hw *hw)
3600{
3601        uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A);
3602
3603        if (!(cause & CSIO_GLBL_INTR_MASK)) {
3604                CSIO_INC_STATS(hw, n_plint_unexp);
3605                return 0;
3606        }
3607
3608        csio_dbg(hw, "Slow interrupt! cause: 0x%x\n", cause);
3609
3610        CSIO_INC_STATS(hw, n_plint_cnt);
3611
3612        if (cause & CIM_F)
3613                csio_cim_intr_handler(hw);
3614
3615        if (cause & MPS_F)
3616                csio_mps_intr_handler(hw);
3617
3618        if (cause & NCSI_F)
3619                csio_ncsi_intr_handler(hw);
3620
3621        if (cause & PL_F)
3622                csio_pl_intr_handler(hw);
3623
3624        if (cause & SMB_F)
3625                csio_smb_intr_handler(hw);
3626
3627        if (cause & XGMAC0_F)
3628                csio_xgmac_intr_handler(hw, 0);
3629
3630        if (cause & XGMAC1_F)
3631                csio_xgmac_intr_handler(hw, 1);
3632
3633        if (cause & XGMAC_KR0_F)
3634                csio_xgmac_intr_handler(hw, 2);
3635
3636        if (cause & XGMAC_KR1_F)
3637                csio_xgmac_intr_handler(hw, 3);
3638
3639        if (cause & PCIE_F)
3640                hw->chip_ops->chip_pcie_intr_handler(hw);
3641
3642        if (cause & MC_F)
3643                csio_mem_intr_handler(hw, MEM_MC);
3644
3645        if (cause & EDC0_F)
3646                csio_mem_intr_handler(hw, MEM_EDC0);
3647
3648        if (cause & EDC1_F)
3649                csio_mem_intr_handler(hw, MEM_EDC1);
3650
3651        if (cause & LE_F)
3652                csio_le_intr_handler(hw);
3653
3654        if (cause & TP_F)
3655                csio_tp_intr_handler(hw);
3656
3657        if (cause & MA_F)
3658                csio_ma_intr_handler(hw);
3659
3660        if (cause & PM_TX_F)
3661                csio_pmtx_intr_handler(hw);
3662
3663        if (cause & PM_RX_F)
3664                csio_pmrx_intr_handler(hw);
3665
3666        if (cause & ULP_RX_F)
3667                csio_ulprx_intr_handler(hw);
3668
3669        if (cause & CPL_SWITCH_F)
3670                csio_cplsw_intr_handler(hw);
3671
3672        if (cause & SGE_F)
3673                csio_sge_intr_handler(hw);
3674
3675        if (cause & ULP_TX_F)
3676                csio_ulptx_intr_handler(hw);
3677
3678        /* Clear the interrupts just processed for which we are the master. */
3679        csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE_A);
3680        csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */
3681
3682        return 1;
3683}
3684
3685/*****************************************************************************
3686 * HW <--> mailbox interfacing routines.
3687 ****************************************************************************/
3688/*
3689 * csio_mberr_worker - Worker thread (dpc) for mailbox/error completions
3690 *
3691 * @data: Private data pointer.
3692 *
3693 * Called from worker thread context.
3694 */
3695static void
3696csio_mberr_worker(void *data)
3697{
3698        struct csio_hw *hw = (struct csio_hw *)data;
3699        struct csio_mbm *mbm = &hw->mbm;
3700        LIST_HEAD(cbfn_q);
3701        struct csio_mb *mbp_next;
3702        int rv;
3703
3704        del_timer_sync(&mbm->timer);
3705
3706        spin_lock_irq(&hw->lock);
3707        if (list_empty(&mbm->cbfn_q)) {
3708                spin_unlock_irq(&hw->lock);
3709                return;
3710        }
3711
3712        list_splice_tail_init(&mbm->cbfn_q, &cbfn_q);
3713        mbm->stats.n_cbfnq = 0;
3714
3715        /* Try to start waiting mailboxes */
3716        if (!list_empty(&mbm->req_q)) {
3717                mbp_next = list_first_entry(&mbm->req_q, struct csio_mb, list);
3718                list_del_init(&mbp_next->list);
3719
3720                rv = csio_mb_issue(hw, mbp_next);
3721                if (rv != 0)
3722                        list_add_tail(&mbp_next->list, &mbm->req_q);
3723                else
3724                        CSIO_DEC_STATS(mbm, n_activeq);
3725        }
3726        spin_unlock_irq(&hw->lock);
3727
3728        /* Now callback completions */
3729        csio_mb_completions(hw, &cbfn_q);
3730}
3731
3732/*
3733 * csio_hw_mb_timer - Top-level Mailbox timeout handler.
3734 *
3735 * @data: private data pointer
3736 *
3737 **/
3738static void
3739csio_hw_mb_timer(struct timer_list *t)
3740{
3741        struct csio_mbm *mbm = from_timer(mbm, t, timer);
3742        struct csio_hw *hw = mbm->hw;
3743        struct csio_mb *mbp = NULL;
3744
3745        spin_lock_irq(&hw->lock);
3746        mbp = csio_mb_tmo_handler(hw);
3747        spin_unlock_irq(&hw->lock);
3748
3749        /* Call back the function for the timed-out Mailbox */
3750        if (mbp)
3751                mbp->mb_cbfn(hw, mbp);
3752
3753}
3754
3755/*
3756 * csio_hw_mbm_cleanup - Cleanup Mailbox module.
3757 * @hw: HW module
3758 *
3759 * Called with lock held, should exit with lock held.
3760 * Cancels outstanding mailboxes (waiting, in-flight) and gathers them
3761 * into a local queue. Drops lock and calls the completions. Holds
3762 * lock and returns.
3763 */
3764static void
3765csio_hw_mbm_cleanup(struct csio_hw *hw)
3766{
3767        LIST_HEAD(cbfn_q);
3768
3769        csio_mb_cancel_all(hw, &cbfn_q);
3770
3771        spin_unlock_irq(&hw->lock);
3772        csio_mb_completions(hw, &cbfn_q);
3773        spin_lock_irq(&hw->lock);
3774}
3775
3776/*****************************************************************************
3777 * Event handling
3778 ****************************************************************************/
3779int
3780csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type, void *evt_msg,
3781                        uint16_t len)
3782{
3783        struct csio_evt_msg *evt_entry = NULL;
3784
3785        if (type >= CSIO_EVT_MAX)
3786                return -EINVAL;
3787
3788        if (len > CSIO_EVT_MSG_SIZE)
3789                return -EINVAL;
3790
3791        if (hw->flags & CSIO_HWF_FWEVT_STOP)
3792                return -EINVAL;
3793
3794        if (list_empty(&hw->evt_free_q)) {
3795                csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n",
3796                         type, len);
3797                return -ENOMEM;
3798        }
3799
3800        evt_entry = list_first_entry(&hw->evt_free_q,
3801                                     struct csio_evt_msg, list);
3802        list_del_init(&evt_entry->list);
3803
3804        /* copy event msg and queue the event */
3805        evt_entry->type = type;
3806        memcpy((void *)evt_entry->data, evt_msg, len);
3807        list_add_tail(&evt_entry->list, &hw->evt_active_q);
3808
3809        CSIO_DEC_STATS(hw, n_evt_freeq);
3810        CSIO_INC_STATS(hw, n_evt_activeq);
3811
3812        return 0;
3813}
3814
3815static int
3816csio_enqueue_evt_lock(struct csio_hw *hw, enum csio_evt type, void *evt_msg,
3817                        uint16_t len, bool msg_sg)
3818{
3819        struct csio_evt_msg *evt_entry = NULL;
3820        struct csio_fl_dma_buf *fl_sg;
3821        uint32_t off = 0;
3822        unsigned long flags;
3823        int n, ret = 0;
3824
3825        if (type >= CSIO_EVT_MAX)
3826                return -EINVAL;
3827
3828        if (len > CSIO_EVT_MSG_SIZE)
3829                return -EINVAL;
3830
3831        spin_lock_irqsave(&hw->lock, flags);
3832        if (hw->flags & CSIO_HWF_FWEVT_STOP) {
3833                ret = -EINVAL;
3834                goto out;
3835        }
3836
3837        if (list_empty(&hw->evt_free_q)) {
3838                csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n",
3839                         type, len);
3840                ret = -ENOMEM;
3841                goto out;
3842        }
3843
3844        evt_entry = list_first_entry(&hw->evt_free_q,
3845                                     struct csio_evt_msg, list);
3846        list_del_init(&evt_entry->list);
3847
3848        /* copy event msg and queue the event */
3849        evt_entry->type = type;
3850
3851        /* If Payload in SG list*/
3852        if (msg_sg) {
3853                fl_sg = (struct csio_fl_dma_buf *) evt_msg;
3854                for (n = 0; (n < CSIO_MAX_FLBUF_PER_IQWR && off < len); n++) {
3855                        memcpy((void *)((uintptr_t)evt_entry->data + off),
3856                                fl_sg->flbufs[n].vaddr,
3857                                fl_sg->flbufs[n].len);
3858                        off += fl_sg->flbufs[n].len;
3859                }
3860        } else
3861                memcpy((void *)evt_entry->data, evt_msg, len);
3862
3863        list_add_tail(&evt_entry->list, &hw->evt_active_q);
3864        CSIO_DEC_STATS(hw, n_evt_freeq);
3865        CSIO_INC_STATS(hw, n_evt_activeq);
3866out:
3867        spin_unlock_irqrestore(&hw->lock, flags);
3868        return ret;
3869}
3870
3871static void
3872csio_free_evt(struct csio_hw *hw, struct csio_evt_msg *evt_entry)
3873{
3874        if (evt_entry) {
3875                spin_lock_irq(&hw->lock);
3876                list_del_init(&evt_entry->list);
3877                list_add_tail(&evt_entry->list, &hw->evt_free_q);
3878                CSIO_DEC_STATS(hw, n_evt_activeq);
3879                CSIO_INC_STATS(hw, n_evt_freeq);
3880                spin_unlock_irq(&hw->lock);
3881        }
3882}
3883
3884void
3885csio_evtq_flush(struct csio_hw *hw)
3886{
3887        uint32_t count;
3888        count = 30;
3889        while (hw->flags & CSIO_HWF_FWEVT_PENDING && count--) {
3890                spin_unlock_irq(&hw->lock);
3891                msleep(2000);
3892                spin_lock_irq(&hw->lock);
3893        }
3894
3895        CSIO_DB_ASSERT(!(hw->flags & CSIO_HWF_FWEVT_PENDING));
3896}
3897
3898static void
3899csio_evtq_stop(struct csio_hw *hw)
3900{
3901        hw->flags |= CSIO_HWF_FWEVT_STOP;
3902}
3903
3904static void
3905csio_evtq_start(struct csio_hw *hw)
3906{
3907        hw->flags &= ~CSIO_HWF_FWEVT_STOP;
3908}
3909
3910static void
3911csio_evtq_cleanup(struct csio_hw *hw)
3912{
3913        struct list_head *evt_entry, *next_entry;
3914
3915        /* Release outstanding events from activeq to freeq*/
3916        if (!list_empty(&hw->evt_active_q))
3917                list_splice_tail_init(&hw->evt_active_q, &hw->evt_free_q);
3918
3919        hw->stats.n_evt_activeq = 0;
3920        hw->flags &= ~CSIO_HWF_FWEVT_PENDING;
3921
3922        /* Freeup event entry */
3923        list_for_each_safe(evt_entry, next_entry, &hw->evt_free_q) {
3924                kfree(evt_entry);
3925                CSIO_DEC_STATS(hw, n_evt_freeq);
3926        }
3927
3928        hw->stats.n_evt_freeq = 0;
3929}
3930
3931
3932static void
3933csio_process_fwevtq_entry(struct csio_hw *hw, void *wr, uint32_t len,
3934                          struct csio_fl_dma_buf *flb, void *priv)
3935{
3936        __u8 op;
3937        void *msg = NULL;
3938        uint32_t msg_len = 0;
3939        bool msg_sg = 0;
3940
3941        op = ((struct rss_header *) wr)->opcode;
3942        if (op == CPL_FW6_PLD) {
3943                CSIO_INC_STATS(hw, n_cpl_fw6_pld);
3944                if (!flb || !flb->totlen) {
3945                        CSIO_INC_STATS(hw, n_cpl_unexp);
3946                        return;
3947                }
3948
3949                msg = (void *) flb;
3950                msg_len = flb->totlen;
3951                msg_sg = 1;
3952        } else if (op == CPL_FW6_MSG || op == CPL_FW4_MSG) {
3953
3954                CSIO_INC_STATS(hw, n_cpl_fw6_msg);
3955                /* skip RSS header */
3956                msg = (void *)((uintptr_t)wr + sizeof(__be64));
3957                msg_len = (op == CPL_FW6_MSG) ? sizeof(struct cpl_fw6_msg) :
3958                           sizeof(struct cpl_fw4_msg);
3959        } else {
3960                csio_warn(hw, "unexpected CPL %#x on FW event queue\n", op);
3961                CSIO_INC_STATS(hw, n_cpl_unexp);
3962                return;
3963        }
3964
3965        /*
3966         * Enqueue event to EventQ. Events processing happens
3967         * in Event worker thread context
3968         */
3969        if (csio_enqueue_evt_lock(hw, CSIO_EVT_FW, msg,
3970                                  (uint16_t)msg_len, msg_sg))
3971                CSIO_INC_STATS(hw, n_evt_drop);
3972}
3973
3974void
3975csio_evtq_worker(struct work_struct *work)
3976{
3977        struct csio_hw *hw = container_of(work, struct csio_hw, evtq_work);
3978        struct list_head *evt_entry, *next_entry;
3979        LIST_HEAD(evt_q);
3980        struct csio_evt_msg     *evt_msg;
3981        struct cpl_fw6_msg *msg;
3982        struct csio_rnode *rn;
3983        int rv = 0;
3984        uint8_t evtq_stop = 0;
3985
3986        csio_dbg(hw, "event worker thread active evts#%d\n",
3987                 hw->stats.n_evt_activeq);
3988
3989        spin_lock_irq(&hw->lock);
3990        while (!list_empty(&hw->evt_active_q)) {
3991                list_splice_tail_init(&hw->evt_active_q, &evt_q);
3992                spin_unlock_irq(&hw->lock);
3993
3994                list_for_each_safe(evt_entry, next_entry, &evt_q) {
3995                        evt_msg = (struct csio_evt_msg *) evt_entry;
3996
3997                        /* Drop events if queue is STOPPED */
3998                        spin_lock_irq(&hw->lock);
3999                        if (hw->flags & CSIO_HWF_FWEVT_STOP)
4000                                evtq_stop = 1;
4001                        spin_unlock_irq(&hw->lock);
4002                        if (evtq_stop) {
4003                                CSIO_INC_STATS(hw, n_evt_drop);
4004                                goto free_evt;
4005                        }
4006
4007                        switch (evt_msg->type) {
4008                        case CSIO_EVT_FW:
4009                                msg = (struct cpl_fw6_msg *)(evt_msg->data);
4010
4011                                if ((msg->opcode == CPL_FW6_MSG ||
4012                                     msg->opcode == CPL_FW4_MSG) &&
4013                                    !msg->type) {
4014                                        rv = csio_mb_fwevt_handler(hw,
4015                                                                msg->data);
4016                                        if (!rv)
4017                                                break;
4018                                        /* Handle any remaining fw events */
4019                                        csio_fcoe_fwevt_handler(hw,
4020                                                        msg->opcode, msg->data);
4021                                } else if (msg->opcode == CPL_FW6_PLD) {
4022
4023                                        csio_fcoe_fwevt_handler(hw,
4024                                                        msg->opcode, msg->data);
4025                                } else {
4026                                        csio_warn(hw,
4027                                             "Unhandled FW msg op %x type %x\n",
4028                                                  msg->opcode, msg->type);
4029                                        CSIO_INC_STATS(hw, n_evt_drop);
4030                                }
4031                                break;
4032
4033                        case CSIO_EVT_MBX:
4034                                csio_mberr_worker(hw);
4035                                break;
4036
4037                        case CSIO_EVT_DEV_LOSS:
4038                                memcpy(&rn, evt_msg->data, sizeof(rn));
4039                                csio_rnode_devloss_handler(rn);
4040                                break;
4041
4042                        default:
4043                                csio_warn(hw, "Unhandled event %x on evtq\n",
4044                                          evt_msg->type);
4045                                CSIO_INC_STATS(hw, n_evt_unexp);
4046                                break;
4047                        }
4048free_evt:
4049                        csio_free_evt(hw, evt_msg);
4050                }
4051
4052                spin_lock_irq(&hw->lock);
4053        }
4054        hw->flags &= ~CSIO_HWF_FWEVT_PENDING;
4055        spin_unlock_irq(&hw->lock);
4056}
4057
4058int
4059csio_fwevtq_handler(struct csio_hw *hw)
4060{
4061        int rv;
4062
4063        if (csio_q_iqid(hw, hw->fwevt_iq_idx) == CSIO_MAX_QID) {
4064                CSIO_INC_STATS(hw, n_int_stray);
4065                return -EINVAL;
4066        }
4067
4068        rv = csio_wr_process_iq_idx(hw, hw->fwevt_iq_idx,
4069                           csio_process_fwevtq_entry, NULL);
4070        return rv;
4071}
4072
4073/****************************************************************************
4074 * Entry points
4075 ****************************************************************************/
4076
4077/* Management module */
4078/*
4079 * csio_mgmt_req_lookup - Lookup the given IO req exist in Active Q.
4080 * mgmt - mgmt module
4081 * @io_req - io request
4082 *
4083 * Return - 0:if given IO Req exists in active Q.
4084 *          -EINVAL  :if lookup fails.
4085 */
4086int
4087csio_mgmt_req_lookup(struct csio_mgmtm *mgmtm, struct csio_ioreq *io_req)
4088{
4089        struct list_head *tmp;
4090
4091        /* Lookup ioreq in the ACTIVEQ */
4092        list_for_each(tmp, &mgmtm->active_q) {
4093                if (io_req == (struct csio_ioreq *)tmp)
4094                        return 0;
4095        }
4096        return -EINVAL;
4097}
4098
4099#define ECM_MIN_TMO     1000    /* Minimum timeout value for req */
4100
4101/*
4102 * csio_mgmts_tmo_handler - MGMT IO Timeout handler.
4103 * @data - Event data.
4104 *
4105 * Return - none.
4106 */
4107static void
4108csio_mgmt_tmo_handler(struct timer_list *t)
4109{
4110        struct csio_mgmtm *mgmtm = from_timer(mgmtm, t, mgmt_timer);
4111        struct list_head *tmp;
4112        struct csio_ioreq *io_req;
4113
4114        csio_dbg(mgmtm->hw, "Mgmt timer invoked!\n");
4115
4116        spin_lock_irq(&mgmtm->hw->lock);
4117
4118        list_for_each(tmp, &mgmtm->active_q) {
4119                io_req = (struct csio_ioreq *) tmp;
4120                io_req->tmo -= min_t(uint32_t, io_req->tmo, ECM_MIN_TMO);
4121
4122                if (!io_req->tmo) {
4123                        /* Dequeue the request from retry Q. */
4124                        tmp = csio_list_prev(tmp);
4125                        list_del_init(&io_req->sm.sm_list);
4126                        if (io_req->io_cbfn) {
4127                                /* io_req will be freed by completion handler */
4128                                io_req->wr_status = -ETIMEDOUT;
4129                                io_req->io_cbfn(mgmtm->hw, io_req);
4130                        } else {
4131                                CSIO_DB_ASSERT(0);
4132                        }
4133                }
4134        }
4135
4136        /* If retry queue is not empty, re-arm timer */
4137        if (!list_empty(&mgmtm->active_q))
4138                mod_timer(&mgmtm->mgmt_timer,
4139                          jiffies + msecs_to_jiffies(ECM_MIN_TMO));
4140        spin_unlock_irq(&mgmtm->hw->lock);
4141}
4142
4143static void
4144csio_mgmtm_cleanup(struct csio_mgmtm *mgmtm)
4145{
4146        struct csio_hw *hw = mgmtm->hw;
4147        struct csio_ioreq *io_req;
4148        struct list_head *tmp;
4149        uint32_t count;
4150
4151        count = 30;
4152        /* Wait for all outstanding req to complete gracefully */
4153        while ((!list_empty(&mgmtm->active_q)) && count--) {
4154                spin_unlock_irq(&hw->lock);
4155                msleep(2000);
4156                spin_lock_irq(&hw->lock);
4157        }
4158
4159        /* release outstanding req from ACTIVEQ */
4160        list_for_each(tmp, &mgmtm->active_q) {
4161                io_req = (struct csio_ioreq *) tmp;
4162                tmp = csio_list_prev(tmp);
4163                list_del_init(&io_req->sm.sm_list);
4164                mgmtm->stats.n_active--;
4165                if (io_req->io_cbfn) {
4166                        /* io_req will be freed by completion handler */
4167                        io_req->wr_status = -ETIMEDOUT;
4168                        io_req->io_cbfn(mgmtm->hw, io_req);
4169                }
4170        }
4171}
4172
4173/*
4174 * csio_mgmt_init - Mgmt module init entry point
4175 * @mgmtsm - mgmt module
4176 * @hw   - HW module
4177 *
4178 * Initialize mgmt timer, resource wait queue, active queue,
4179 * completion q. Allocate Egress and Ingress
4180 * WR queues and save off the queue index returned by the WR
4181 * module for future use. Allocate and save off mgmt reqs in the
4182 * mgmt_req_freelist for future use. Make sure their SM is initialized
4183 * to uninit state.
4184 * Returns: 0 - on success
4185 *          -ENOMEM   - on error.
4186 */
4187static int
4188csio_mgmtm_init(struct csio_mgmtm *mgmtm, struct csio_hw *hw)
4189{
4190        timer_setup(&mgmtm->mgmt_timer, csio_mgmt_tmo_handler, 0);
4191
4192        INIT_LIST_HEAD(&mgmtm->active_q);
4193        INIT_LIST_HEAD(&mgmtm->cbfn_q);
4194
4195        mgmtm->hw = hw;
4196        /*mgmtm->iq_idx = hw->fwevt_iq_idx;*/
4197
4198        return 0;
4199}
4200
4201/*
4202 * csio_mgmtm_exit - MGMT module exit entry point
4203 * @mgmtsm - mgmt module
4204 *
4205 * This function called during MGMT module uninit.
4206 * Stop timers, free ioreqs allocated.
4207 * Returns: None
4208 *
4209 */
4210static void
4211csio_mgmtm_exit(struct csio_mgmtm *mgmtm)
4212{
4213        del_timer_sync(&mgmtm->mgmt_timer);
4214}
4215
4216
4217/**
4218 * csio_hw_start - Kicks off the HW State machine
4219 * @hw:         Pointer to HW module.
4220 *
4221 * It is assumed that the initialization is a synchronous operation.
4222 * So when we return afer posting the event, the HW SM should be in
4223 * the ready state, if there were no errors during init.
4224 */
4225int
4226csio_hw_start(struct csio_hw *hw)
4227{
4228        spin_lock_irq(&hw->lock);
4229        csio_post_event(&hw->sm, CSIO_HWE_CFG);
4230        spin_unlock_irq(&hw->lock);
4231
4232        if (csio_is_hw_ready(hw))
4233                return 0;
4234        else if (csio_match_state(hw, csio_hws_uninit))
4235                return -EINVAL;
4236        else
4237                return -ENODEV;
4238}
4239
4240int
4241csio_hw_stop(struct csio_hw *hw)
4242{
4243        csio_post_event(&hw->sm, CSIO_HWE_PCI_REMOVE);
4244
4245        if (csio_is_hw_removing(hw))
4246                return 0;
4247        else
4248                return -EINVAL;
4249}
4250
4251/* Max reset retries */
4252#define CSIO_MAX_RESET_RETRIES  3
4253
4254/**
4255 * csio_hw_reset - Reset the hardware
4256 * @hw:         HW module.
4257 *
4258 * Caller should hold lock across this function.
4259 */
4260int
4261csio_hw_reset(struct csio_hw *hw)
4262{
4263        if (!csio_is_hw_master(hw))
4264                return -EPERM;
4265
4266        if (hw->rst_retries >= CSIO_MAX_RESET_RETRIES) {
4267                csio_dbg(hw, "Max hw reset attempts reached..");
4268                return -EINVAL;
4269        }
4270
4271        hw->rst_retries++;
4272        csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET);
4273
4274        if (csio_is_hw_ready(hw)) {
4275                hw->rst_retries = 0;
4276                hw->stats.n_reset_start = jiffies_to_msecs(jiffies);
4277                return 0;
4278        } else
4279                return -EINVAL;
4280}
4281
4282/*
4283 * csio_hw_get_device_id - Caches the Adapter's vendor & device id.
4284 * @hw: HW module.
4285 */
4286static void
4287csio_hw_get_device_id(struct csio_hw *hw)
4288{
4289        /* Is the adapter device id cached already ?*/
4290        if (csio_is_dev_id_cached(hw))
4291                return;
4292
4293        /* Get the PCI vendor & device id */
4294        pci_read_config_word(hw->pdev, PCI_VENDOR_ID,
4295                             &hw->params.pci.vendor_id);
4296        pci_read_config_word(hw->pdev, PCI_DEVICE_ID,
4297                             &hw->params.pci.device_id);
4298
4299        csio_dev_id_cached(hw);
4300        hw->chip_id = (hw->params.pci.device_id & CSIO_HW_CHIP_MASK);
4301
4302} /* csio_hw_get_device_id */
4303
4304/*
4305 * csio_hw_set_description - Set the model, description of the hw.
4306 * @hw: HW module.
4307 * @ven_id: PCI Vendor ID
4308 * @dev_id: PCI Device ID
4309 */
4310static void
4311csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id)
4312{
4313        uint32_t adap_type, prot_type;
4314
4315        if (ven_id == CSIO_VENDOR_ID) {
4316                prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK);
4317                adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK);
4318
4319                if (prot_type == CSIO_T5_FCOE_ASIC) {
4320                        memcpy(hw->hw_ver,
4321                               csio_t5_fcoe_adapters[adap_type].model_no, 16);
4322                        memcpy(hw->model_desc,
4323                               csio_t5_fcoe_adapters[adap_type].description,
4324                               32);
4325                } else {
4326                        char tempName[32] = "Chelsio FCoE Controller";
4327                        memcpy(hw->model_desc, tempName, 32);
4328                }
4329        }
4330} /* csio_hw_set_description */
4331
4332/**
4333 * csio_hw_init - Initialize HW module.
4334 * @hw:         Pointer to HW module.
4335 *
4336 * Initialize the members of the HW module.
4337 */
4338int
4339csio_hw_init(struct csio_hw *hw)
4340{
4341        int rv = -EINVAL;
4342        uint32_t i;
4343        uint16_t ven_id, dev_id;
4344        struct csio_evt_msg     *evt_entry;
4345
4346        INIT_LIST_HEAD(&hw->sm.sm_list);
4347        csio_init_state(&hw->sm, csio_hws_uninit);
4348        spin_lock_init(&hw->lock);
4349        INIT_LIST_HEAD(&hw->sln_head);
4350
4351        /* Get the PCI vendor & device id */
4352        csio_hw_get_device_id(hw);
4353
4354        strcpy(hw->name, CSIO_HW_NAME);
4355
4356        /* Initialize the HW chip ops T5 specific ops */
4357        hw->chip_ops = &t5_ops;
4358
4359        /* Set the model & its description */
4360
4361        ven_id = hw->params.pci.vendor_id;
4362        dev_id = hw->params.pci.device_id;
4363
4364        csio_hw_set_description(hw, ven_id, dev_id);
4365
4366        /* Initialize default log level */
4367        hw->params.log_level = (uint32_t) csio_dbg_level;
4368
4369        csio_set_fwevt_intr_idx(hw, -1);
4370        csio_set_nondata_intr_idx(hw, -1);
4371
4372        /* Init all the modules: Mailbox, WorkRequest and Transport */
4373        if (csio_mbm_init(csio_hw_to_mbm(hw), hw, csio_hw_mb_timer))
4374                goto err;
4375
4376        rv = csio_wrm_init(csio_hw_to_wrm(hw), hw);
4377        if (rv)
4378                goto err_mbm_exit;
4379
4380        rv = csio_scsim_init(csio_hw_to_scsim(hw), hw);
4381        if (rv)
4382                goto err_wrm_exit;
4383
4384        rv = csio_mgmtm_init(csio_hw_to_mgmtm(hw), hw);
4385        if (rv)
4386                goto err_scsim_exit;
4387        /* Pre-allocate evtq and initialize them */
4388        INIT_LIST_HEAD(&hw->evt_active_q);
4389        INIT_LIST_HEAD(&hw->evt_free_q);
4390        for (i = 0; i < csio_evtq_sz; i++) {
4391
4392                evt_entry = kzalloc(sizeof(struct csio_evt_msg), GFP_KERNEL);
4393                if (!evt_entry) {
4394                        rv = -ENOMEM;
4395                        csio_err(hw, "Failed to initialize eventq");
4396                        goto err_evtq_cleanup;
4397                }
4398
4399                list_add_tail(&evt_entry->list, &hw->evt_free_q);
4400                CSIO_INC_STATS(hw, n_evt_freeq);
4401        }
4402
4403        hw->dev_num = dev_num;
4404        dev_num++;
4405
4406        return 0;
4407
4408err_evtq_cleanup:
4409        csio_evtq_cleanup(hw);
4410        csio_mgmtm_exit(csio_hw_to_mgmtm(hw));
4411err_scsim_exit:
4412        csio_scsim_exit(csio_hw_to_scsim(hw));
4413err_wrm_exit:
4414        csio_wrm_exit(csio_hw_to_wrm(hw), hw);
4415err_mbm_exit:
4416        csio_mbm_exit(csio_hw_to_mbm(hw));
4417err:
4418        return rv;
4419}
4420
4421/**
4422 * csio_hw_exit - Un-initialize HW module.
4423 * @hw:         Pointer to HW module.
4424 *
4425 */
4426void
4427csio_hw_exit(struct csio_hw *hw)
4428{
4429        csio_evtq_cleanup(hw);
4430        csio_mgmtm_exit(csio_hw_to_mgmtm(hw));
4431        csio_scsim_exit(csio_hw_to_scsim(hw));
4432        csio_wrm_exit(csio_hw_to_wrm(hw), hw);
4433        csio_mbm_exit(csio_hw_to_mbm(hw));
4434}
4435