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7#include "hisi_sas.h"
8#define DRV_NAME "hisi_sas_v2_hw"
9
10
11#define DLVRY_QUEUE_ENABLE 0x0
12#define IOST_BASE_ADDR_LO 0x8
13#define IOST_BASE_ADDR_HI 0xc
14#define ITCT_BASE_ADDR_LO 0x10
15#define ITCT_BASE_ADDR_HI 0x14
16#define IO_BROKEN_MSG_ADDR_LO 0x18
17#define IO_BROKEN_MSG_ADDR_HI 0x1c
18#define PHY_CONTEXT 0x20
19#define PHY_STATE 0x24
20#define PHY_PORT_NUM_MA 0x28
21#define PORT_STATE 0x2c
22#define PORT_STATE_PHY8_PORT_NUM_OFF 16
23#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
24#define PORT_STATE_PHY8_CONN_RATE_OFF 20
25#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
26#define PHY_CONN_RATE 0x30
27#define HGC_TRANS_TASK_CNT_LIMIT 0x38
28#define AXI_AHB_CLK_CFG 0x3c
29#define ITCT_CLR 0x44
30#define ITCT_CLR_EN_OFF 16
31#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
32#define ITCT_DEV_OFF 0
33#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
34#define AXI_USER1 0x48
35#define AXI_USER2 0x4c
36#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
37#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
38#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
39#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
40#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
41#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
42#define HGC_GET_ITV_TIME 0x90
43#define DEVICE_MSG_WORK_MODE 0x94
44#define OPENA_WT_CONTI_TIME 0x9c
45#define I_T_NEXUS_LOSS_TIME 0xa0
46#define MAX_CON_TIME_LIMIT_TIME 0xa4
47#define BUS_INACTIVE_LIMIT_TIME 0xa8
48#define REJECT_TO_OPEN_LIMIT_TIME 0xac
49#define CFG_AGING_TIME 0xbc
50#define HGC_DFX_CFG2 0xc0
51#define HGC_IOMB_PROC1_STATUS 0x104
52#define CFG_1US_TIMER_TRSH 0xcc
53#define HGC_LM_DFX_STATUS2 0x128
54#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
55#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
56 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
57#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
58#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
59 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
60#define HGC_CQE_ECC_ADDR 0x13c
61#define HGC_CQE_ECC_1B_ADDR_OFF 0
62#define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
63#define HGC_CQE_ECC_MB_ADDR_OFF 8
64#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
65#define HGC_IOST_ECC_ADDR 0x140
66#define HGC_IOST_ECC_1B_ADDR_OFF 0
67#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
68#define HGC_IOST_ECC_MB_ADDR_OFF 16
69#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
70#define HGC_DQE_ECC_ADDR 0x144
71#define HGC_DQE_ECC_1B_ADDR_OFF 0
72#define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
73#define HGC_DQE_ECC_MB_ADDR_OFF 16
74#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
75#define HGC_INVLD_DQE_INFO 0x148
76#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
77#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
78#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
79#define HGC_ITCT_ECC_ADDR 0x150
80#define HGC_ITCT_ECC_1B_ADDR_OFF 0
81#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
82 HGC_ITCT_ECC_1B_ADDR_OFF)
83#define HGC_ITCT_ECC_MB_ADDR_OFF 16
84#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
85 HGC_ITCT_ECC_MB_ADDR_OFF)
86#define HGC_AXI_FIFO_ERR_INFO 0x154
87#define AXI_ERR_INFO_OFF 0
88#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
89#define FIFO_ERR_INFO_OFF 8
90#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
91#define INT_COAL_EN 0x19c
92#define OQ_INT_COAL_TIME 0x1a0
93#define OQ_INT_COAL_CNT 0x1a4
94#define ENT_INT_COAL_TIME 0x1a8
95#define ENT_INT_COAL_CNT 0x1ac
96#define OQ_INT_SRC 0x1b0
97#define OQ_INT_SRC_MSK 0x1b4
98#define ENT_INT_SRC1 0x1b8
99#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
100#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
101#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
102#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
103#define ENT_INT_SRC2 0x1bc
104#define ENT_INT_SRC3 0x1c0
105#define ENT_INT_SRC3_WP_DEPTH_OFF 8
106#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
107#define ENT_INT_SRC3_RP_DEPTH_OFF 10
108#define ENT_INT_SRC3_AXI_OFF 11
109#define ENT_INT_SRC3_FIFO_OFF 12
110#define ENT_INT_SRC3_LM_OFF 14
111#define ENT_INT_SRC3_ITC_INT_OFF 15
112#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
113#define ENT_INT_SRC3_ABT_OFF 16
114#define ENT_INT_SRC_MSK1 0x1c4
115#define ENT_INT_SRC_MSK2 0x1c8
116#define ENT_INT_SRC_MSK3 0x1cc
117#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
118#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
119#define SAS_ECC_INTR 0x1e8
120#define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
121#define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
122#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
123#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
124#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
125#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
126#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
127#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
128#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
129#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
130#define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
131#define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
132#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
133#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
134#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
135#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
136#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
137#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
138#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
139#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
140#define SAS_ECC_INTR_MSK 0x1ec
141#define HGC_ERR_STAT_EN 0x238
142#define CQE_SEND_CNT 0x248
143#define DLVRY_Q_0_BASE_ADDR_LO 0x260
144#define DLVRY_Q_0_BASE_ADDR_HI 0x264
145#define DLVRY_Q_0_DEPTH 0x268
146#define DLVRY_Q_0_WR_PTR 0x26c
147#define DLVRY_Q_0_RD_PTR 0x270
148#define HYPER_STREAM_ID_EN_CFG 0xc80
149#define OQ0_INT_SRC_MSK 0xc90
150#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
151#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
152#define COMPL_Q_0_DEPTH 0x4e8
153#define COMPL_Q_0_WR_PTR 0x4ec
154#define COMPL_Q_0_RD_PTR 0x4f0
155#define HGC_RXM_DFX_STATUS14 0xae8
156#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
157#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
158 HGC_RXM_DFX_STATUS14_MEM0_OFF)
159#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
160#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
161 HGC_RXM_DFX_STATUS14_MEM1_OFF)
162#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
163#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
164 HGC_RXM_DFX_STATUS14_MEM2_OFF)
165#define HGC_RXM_DFX_STATUS15 0xaec
166#define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
167#define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS15_MEM3_OFF)
169
170#define PORT_BASE (0x2000)
171
172#define PHY_CFG (PORT_BASE + 0x0)
173#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
174#define PHY_CFG_ENA_OFF 0
175#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
176#define PHY_CFG_DC_OPT_OFF 2
177#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
178#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
179#define PROG_PHY_LINK_RATE_MAX_OFF 0
180#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
181#define PHY_CTRL (PORT_BASE + 0x14)
182#define PHY_CTRL_RESET_OFF 0
183#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
184#define SAS_PHY_CTRL (PORT_BASE + 0x20)
185#define SL_CFG (PORT_BASE + 0x84)
186#define PHY_PCN (PORT_BASE + 0x44)
187#define SL_TOUT_CFG (PORT_BASE + 0x8c)
188#define SL_CONTROL (PORT_BASE + 0x94)
189#define SL_CONTROL_NOTIFY_EN_OFF 0
190#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
191#define SL_CONTROL_CTA_OFF 17
192#define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
193#define RX_PRIMS_STATUS (PORT_BASE + 0x98)
194#define RX_BCAST_CHG_OFF 1
195#define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
196#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
197#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
198#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
199#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
200#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
201#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
202#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
203#define TXID_AUTO (PORT_BASE + 0xb8)
204#define TXID_AUTO_CT3_OFF 1
205#define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
206#define TXID_AUTO_CTB_OFF 11
207#define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
208#define TX_HARDRST_OFF 2
209#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
210#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
211#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
212#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
213#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
214#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
215#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
216#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
217#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
218#define CON_CONTROL (PORT_BASE + 0x118)
219#define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
220#define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
221 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
222#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
223#define CHL_INT0 (PORT_BASE + 0x1b4)
224#define CHL_INT0_HOTPLUG_TOUT_OFF 0
225#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
226#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
227#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
228#define CHL_INT0_SL_PHY_ENABLE_OFF 2
229#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
230#define CHL_INT0_NOT_RDY_OFF 4
231#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
232#define CHL_INT0_PHY_RDY_OFF 5
233#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
234#define CHL_INT1 (PORT_BASE + 0x1b8)
235#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
236#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
237#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
238#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
239#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
240#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
241#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
242#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
243#define CHL_INT2 (PORT_BASE + 0x1bc)
244#define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
245#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
246#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
247#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
248#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
249#define DMA_TX_DFX0 (PORT_BASE + 0x200)
250#define DMA_TX_DFX1 (PORT_BASE + 0x204)
251#define DMA_TX_DFX1_IPTT_OFF 0
252#define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
253#define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
254#define PORT_DFX0 (PORT_BASE + 0x258)
255#define LINK_DFX2 (PORT_BASE + 0X264)
256#define LINK_DFX2_RCVR_HOLD_STS_OFF 9
257#define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
258#define LINK_DFX2_SEND_HOLD_STS_OFF 10
259#define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
260#define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
261#define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
262#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
263#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
264#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
265#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
266#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
267#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
268#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
269#define DMA_TX_STATUS_BUSY_OFF 0
270#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
271#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
272#define DMA_RX_STATUS_BUSY_OFF 0
273#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
274
275#define AXI_CFG (0x5100)
276#define AM_CFG_MAX_TRANS (0x5010)
277#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
278
279#define AXI_MASTER_CFG_BASE (0x5000)
280#define AM_CTRL_GLOBAL (0x0)
281#define AM_CURR_TRANS_RETURN (0x150)
282
283
284
285
286#define CMD_HDR_ABORT_FLAG_OFF 0
287#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
288#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
289#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
290#define CMD_HDR_RESP_REPORT_OFF 5
291#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
292#define CMD_HDR_TLR_CTRL_OFF 6
293#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
294#define CMD_HDR_PHY_ID_OFF 8
295#define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF)
296#define CMD_HDR_FORCE_PHY_OFF 17
297#define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF)
298#define CMD_HDR_PORT_OFF 18
299#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
300#define CMD_HDR_PRIORITY_OFF 27
301#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
302#define CMD_HDR_CMD_OFF 29
303#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
304
305#define CMD_HDR_DIR_OFF 5
306#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
307#define CMD_HDR_RESET_OFF 7
308#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
309#define CMD_HDR_VDTL_OFF 10
310#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
311#define CMD_HDR_FRAME_TYPE_OFF 11
312#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
313#define CMD_HDR_DEV_ID_OFF 16
314#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
315
316#define CMD_HDR_CFL_OFF 0
317#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
318#define CMD_HDR_NCQ_TAG_OFF 10
319#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
320#define CMD_HDR_MRFL_OFF 15
321#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
322#define CMD_HDR_SG_MOD_OFF 24
323#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
324#define CMD_HDR_FIRST_BURST_OFF 26
325#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
326
327#define CMD_HDR_IPTT_OFF 0
328#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
329
330#define CMD_HDR_DIF_SGL_LEN_OFF 0
331#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
332#define CMD_HDR_DATA_SGL_LEN_OFF 16
333#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
334#define CMD_HDR_ABORT_IPTT_OFF 16
335#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
336
337
338
339#define CMPLT_HDR_ERR_PHASE_OFF 2
340#define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
341#define CMPLT_HDR_RSPNS_XFRD_OFF 10
342#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
343#define CMPLT_HDR_ERX_OFF 12
344#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
345#define CMPLT_HDR_ABORT_STAT_OFF 13
346#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
347
348#define STAT_IO_NOT_VALID 0x1
349#define STAT_IO_NO_DEVICE 0x2
350#define STAT_IO_COMPLETE 0x3
351#define STAT_IO_ABORTED 0x4
352
353#define CMPLT_HDR_IPTT_OFF 0
354#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
355#define CMPLT_HDR_DEV_ID_OFF 16
356#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
357
358
359
360#define ITCT_HDR_DEV_TYPE_OFF 0
361#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
362#define ITCT_HDR_VALID_OFF 2
363#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
364#define ITCT_HDR_MCR_OFF 5
365#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
366#define ITCT_HDR_VLN_OFF 9
367#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
368#define ITCT_HDR_SMP_TIMEOUT_OFF 16
369#define ITCT_HDR_SMP_TIMEOUT_8US 1
370#define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
371 250)
372#define ITCT_HDR_AWT_CONTINUE_OFF 25
373#define ITCT_HDR_PORT_ID_OFF 28
374#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
375
376#define ITCT_HDR_INLT_OFF 0
377#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
378#define ITCT_HDR_BITLT_OFF 16
379#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
380#define ITCT_HDR_MCTLT_OFF 32
381#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
382#define ITCT_HDR_RTOLT_OFF 48
383#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
384
385#define HISI_SAS_FATAL_INT_NR 2
386
387struct hisi_sas_complete_v2_hdr {
388 __le32 dw0;
389 __le32 dw1;
390 __le32 act;
391 __le32 dw3;
392};
393
394struct hisi_sas_err_record_v2 {
395
396 __le32 trans_tx_fail_type;
397
398
399 __le32 trans_rx_fail_type;
400
401
402 __le16 dma_tx_err_type;
403 __le16 sipc_rx_err_type;
404
405
406 __le32 dma_rx_err_type;
407};
408
409struct signal_attenuation_s {
410 u32 de_emphasis;
411 u32 preshoot;
412 u32 boost;
413};
414
415struct sig_atten_lu_s {
416 const struct signal_attenuation_s *att;
417 u32 sas_phy_ctrl;
418};
419
420static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
421 {
422 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
423 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
424 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
425 .msg = "hgc_dqe_ecc1b_intr",
426 .reg = HGC_DQE_ECC_ADDR,
427 },
428 {
429 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
430 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
431 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
432 .msg = "hgc_iost_ecc1b_intr",
433 .reg = HGC_IOST_ECC_ADDR,
434 },
435 {
436 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
437 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
438 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
439 .msg = "hgc_itct_ecc1b_intr",
440 .reg = HGC_ITCT_ECC_ADDR,
441 },
442 {
443 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
444 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
445 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
446 .msg = "hgc_iostl_ecc1b_intr",
447 .reg = HGC_LM_DFX_STATUS2,
448 },
449 {
450 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
451 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
452 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
453 .msg = "hgc_itctl_ecc1b_intr",
454 .reg = HGC_LM_DFX_STATUS2,
455 },
456 {
457 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
458 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
459 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
460 .msg = "hgc_cqe_ecc1b_intr",
461 .reg = HGC_CQE_ECC_ADDR,
462 },
463 {
464 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
465 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
466 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
467 .msg = "rxm_mem0_ecc1b_intr",
468 .reg = HGC_RXM_DFX_STATUS14,
469 },
470 {
471 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
472 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
473 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
474 .msg = "rxm_mem1_ecc1b_intr",
475 .reg = HGC_RXM_DFX_STATUS14,
476 },
477 {
478 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
479 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
480 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
481 .msg = "rxm_mem2_ecc1b_intr",
482 .reg = HGC_RXM_DFX_STATUS14,
483 },
484 {
485 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
486 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
487 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
488 .msg = "rxm_mem3_ecc1b_intr",
489 .reg = HGC_RXM_DFX_STATUS15,
490 },
491};
492
493static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
494 {
495 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
496 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
497 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
498 .msg = "hgc_dqe_eccbad_intr",
499 .reg = HGC_DQE_ECC_ADDR,
500 },
501 {
502 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
503 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
504 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
505 .msg = "hgc_iost_eccbad_intr",
506 .reg = HGC_IOST_ECC_ADDR,
507 },
508 {
509 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
510 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
511 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
512 .msg = "hgc_itct_eccbad_intr",
513 .reg = HGC_ITCT_ECC_ADDR,
514 },
515 {
516 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
517 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
518 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
519 .msg = "hgc_iostl_eccbad_intr",
520 .reg = HGC_LM_DFX_STATUS2,
521 },
522 {
523 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
524 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
525 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
526 .msg = "hgc_itctl_eccbad_intr",
527 .reg = HGC_LM_DFX_STATUS2,
528 },
529 {
530 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
531 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
532 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
533 .msg = "hgc_cqe_eccbad_intr",
534 .reg = HGC_CQE_ECC_ADDR,
535 },
536 {
537 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
538 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
539 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
540 .msg = "rxm_mem0_eccbad_intr",
541 .reg = HGC_RXM_DFX_STATUS14,
542 },
543 {
544 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
545 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
546 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
547 .msg = "rxm_mem1_eccbad_intr",
548 .reg = HGC_RXM_DFX_STATUS14,
549 },
550 {
551 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
552 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
553 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
554 .msg = "rxm_mem2_eccbad_intr",
555 .reg = HGC_RXM_DFX_STATUS14,
556 },
557 {
558 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
559 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
560 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
561 .msg = "rxm_mem3_eccbad_intr",
562 .reg = HGC_RXM_DFX_STATUS15,
563 },
564};
565
566enum {
567 HISI_SAS_PHY_PHY_UPDOWN,
568 HISI_SAS_PHY_CHNL_INT,
569 HISI_SAS_PHY_INT_NR
570};
571
572enum {
573 TRANS_TX_FAIL_BASE = 0x0,
574 TRANS_RX_FAIL_BASE = 0x20,
575 DMA_TX_ERR_BASE = 0x40,
576 SIPC_RX_ERR_BASE = 0x50,
577 DMA_RX_ERR_BASE = 0x60,
578
579
580 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE,
581 TRANS_TX_ERR_PHY_NOT_ENABLE,
582 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
583 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
584 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
585 RESERVED0,
586 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
587 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
588 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
589 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
590 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
591 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
592 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
593 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
594 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
595 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
596 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
597 TRANS_TX_ERR_FRAME_TXED,
598 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
599 TRANS_TX_ERR_WITH_BREAK_REQUEST,
600 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
601 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
602 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
603 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
604 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
605 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
606 TRANS_TX_ERR_WITH_NAK_RECEVIED,
607 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
608
609 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
610
611 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
612 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
613
614 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
615
616
617 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE,
618 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
619 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
620
621 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
622 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
623 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
624
625 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
626 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
627 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
628 TRANS_RX_ERR_WITH_BREAK_REQUEST,
629 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
630 RESERVED1,
631 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
632 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
633 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
634 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
635 TRANS_RX_ERR_WITH_DATA_LEN0,
636 TRANS_RX_ERR_WITH_BAD_HASH,
637
638 TRANS_RX_XRDY_WLEN_ZERO_ERR,
639
640 TRANS_RX_SSP_FRM_LEN_ERR,
641
642 RESERVED2,
643 RESERVED3,
644 RESERVED4,
645 RESERVED5,
646 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
647 TRANS_RX_SMP_FRM_LEN_ERR,
648 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
649 RESERVED6,
650 RESERVED7,
651 RESERVED8,
652 RESERVED9,
653 TRANS_RX_R_ERR,
654
655
656 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE,
657 DMA_TX_DIF_APP_ERR,
658 DMA_TX_DIF_RPP_ERR,
659 DMA_TX_DATA_SGL_OVERFLOW,
660 DMA_TX_DIF_SGL_OVERFLOW,
661 DMA_TX_UNEXP_XFER_ERR,
662 DMA_TX_UNEXP_RETRANS_ERR,
663 DMA_TX_XFER_LEN_OVERFLOW,
664 DMA_TX_XFER_OFFSET_ERR,
665 DMA_TX_RAM_ECC_ERR,
666 DMA_TX_DIF_LEN_ALIGN_ERR,
667 DMA_TX_MAX_ERR_CODE,
668
669
670 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE,
671 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
672 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
673 SIPC_RX_WRSETUP_LEN_ODD_ERR,
674 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
675 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
676 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
677 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
678 SIPC_RX_SATA_UNEXP_FIS_ERR,
679 SIPC_RX_WRSETUP_ESTATUS_ERR,
680 SIPC_RX_DATA_UNDERFLOW_ERR,
681 SIPC_RX_MAX_ERR_CODE,
682
683
684 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE,
685 DMA_RX_DIF_APP_ERR,
686 DMA_RX_DIF_RPP_ERR,
687 DMA_RX_DATA_SGL_OVERFLOW,
688 DMA_RX_DIF_SGL_OVERFLOW,
689 DMA_RX_DATA_LEN_OVERFLOW,
690 DMA_RX_DATA_LEN_UNDERFLOW,
691 DMA_RX_DATA_OFFSET_ERR,
692 RESERVED10,
693 DMA_RX_SATA_FRAME_TYPE_ERR,
694 DMA_RX_RESP_BUF_OVERFLOW,
695 DMA_RX_UNEXP_RETRANS_RESP_ERR,
696 DMA_RX_UNEXP_NORM_RESP_ERR,
697 DMA_RX_UNEXP_RDFRAME_ERR,
698 DMA_RX_PIO_DATA_LEN_ERR,
699 DMA_RX_RDSETUP_STATUS_ERR,
700 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
701 DMA_RX_RDSETUP_STATUS_BSY_ERR,
702 DMA_RX_RDSETUP_LEN_ODD_ERR,
703 DMA_RX_RDSETUP_LEN_ZERO_ERR,
704 DMA_RX_RDSETUP_LEN_OVER_ERR,
705 DMA_RX_RDSETUP_OFFSET_ERR,
706 DMA_RX_RDSETUP_ACTIVE_ERR,
707 DMA_RX_RDSETUP_ESTATUS_ERR,
708 DMA_RX_RAM_ECC_ERR,
709 DMA_RX_UNKNOWN_FRM_ERR,
710 DMA_RX_MAX_ERR_CODE,
711};
712
713#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
714#define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
715
716#define DIR_NO_DATA 0
717#define DIR_TO_INI 1
718#define DIR_TO_DEVICE 2
719#define DIR_RESERVED 3
720
721#define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
722 err_phase == 0x4 || err_phase == 0x8 ||\
723 err_phase == 0x6 || err_phase == 0xa)
724#define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
725 err_phase == 0x20 || err_phase == 0x40)
726
727static void link_timeout_disable_link(struct timer_list *t);
728
729static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
730{
731 void __iomem *regs = hisi_hba->regs + off;
732
733 return readl(regs);
734}
735
736static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
737{
738 void __iomem *regs = hisi_hba->regs + off;
739
740 return readl_relaxed(regs);
741}
742
743static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
744{
745 void __iomem *regs = hisi_hba->regs + off;
746
747 writel(val, regs);
748}
749
750static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
751 u32 off, u32 val)
752{
753 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
754
755 writel(val, regs);
756}
757
758static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
759 int phy_no, u32 off)
760{
761 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
762
763 return readl(regs);
764}
765
766
767static int
768slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba,
769 struct domain_device *device)
770{
771 int sata_dev = dev_is_sata(device);
772 void *bitmap = hisi_hba->slot_index_tags;
773 struct hisi_sas_device *sas_dev = device->lldd_dev;
774 int sata_idx = sas_dev->sata_idx;
775 int start, end;
776 unsigned long flags;
777
778 if (!sata_dev) {
779
780
781
782
783
784 start = 1;
785 end = hisi_hba->slot_index_count;
786 } else {
787 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
788 return -EINVAL;
789
790
791
792
793
794
795
796 start = 64 * (sata_idx + 1);
797 end = 64 * (sata_idx + 2);
798 }
799
800 spin_lock_irqsave(&hisi_hba->lock, flags);
801 while (1) {
802 start = find_next_zero_bit(bitmap,
803 hisi_hba->slot_index_count, start);
804 if (start >= end) {
805 spin_unlock_irqrestore(&hisi_hba->lock, flags);
806 return -SAS_QUEUE_FULL;
807 }
808
809
810
811 if (sata_dev ^ (start & 1))
812 break;
813 start++;
814 }
815
816 set_bit(start, bitmap);
817 spin_unlock_irqrestore(&hisi_hba->lock, flags);
818 return start;
819}
820
821static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
822{
823 unsigned int index;
824 struct device *dev = hisi_hba->dev;
825 void *bitmap = hisi_hba->sata_dev_bitmap;
826
827 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
828 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
829 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
830 return false;
831 }
832
833 set_bit(index, bitmap);
834 *idx = index;
835 return true;
836}
837
838
839static struct
840hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
841{
842 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
843 struct hisi_sas_device *sas_dev = NULL;
844 int i, sata_dev = dev_is_sata(device);
845 int sata_idx = -1;
846 unsigned long flags;
847
848 spin_lock_irqsave(&hisi_hba->lock, flags);
849
850 if (sata_dev)
851 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
852 goto out;
853
854 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
855
856
857
858 if (sata_dev && (i & 1))
859 continue;
860 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
861 int queue = i % hisi_hba->queue_count;
862 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
863
864 hisi_hba->devices[i].device_id = i;
865 sas_dev = &hisi_hba->devices[i];
866 sas_dev->dev_status = HISI_SAS_DEV_INIT;
867 sas_dev->dev_type = device->dev_type;
868 sas_dev->hisi_hba = hisi_hba;
869 sas_dev->sas_device = device;
870 sas_dev->sata_idx = sata_idx;
871 sas_dev->dq = dq;
872 spin_lock_init(&sas_dev->lock);
873 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
874 break;
875 }
876 }
877
878out:
879 spin_unlock_irqrestore(&hisi_hba->lock, flags);
880
881 return sas_dev;
882}
883
884static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
885{
886 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
887
888 cfg &= ~PHY_CFG_DC_OPT_MSK;
889 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
890 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
891}
892
893static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
894{
895 struct sas_identify_frame identify_frame;
896 u32 *identify_buffer;
897
898 memset(&identify_frame, 0, sizeof(identify_frame));
899 identify_frame.dev_type = SAS_END_DEVICE;
900 identify_frame.frame_type = 0;
901 identify_frame._un1 = 1;
902 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
903 identify_frame.target_bits = SAS_PROTOCOL_NONE;
904 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
905 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
906 identify_frame.phy_id = phy_no;
907 identify_buffer = (u32 *)(&identify_frame);
908
909 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
910 __swab32(identify_buffer[0]));
911 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
912 __swab32(identify_buffer[1]));
913 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
914 __swab32(identify_buffer[2]));
915 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
916 __swab32(identify_buffer[3]));
917 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
918 __swab32(identify_buffer[4]));
919 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
920 __swab32(identify_buffer[5]));
921}
922
923static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
924 struct hisi_sas_device *sas_dev)
925{
926 struct domain_device *device = sas_dev->sas_device;
927 struct device *dev = hisi_hba->dev;
928 u64 qw0, device_id = sas_dev->device_id;
929 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
930 struct domain_device *parent_dev = device->parent;
931 struct asd_sas_port *sas_port = device->port;
932 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
933 u64 sas_addr;
934
935 memset(itct, 0, sizeof(*itct));
936
937
938 qw0 = 0;
939 switch (sas_dev->dev_type) {
940 case SAS_END_DEVICE:
941 case SAS_EDGE_EXPANDER_DEVICE:
942 case SAS_FANOUT_EXPANDER_DEVICE:
943 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
944 break;
945 case SAS_SATA_DEV:
946 case SAS_SATA_PENDING:
947 if (parent_dev && dev_is_expander(parent_dev->dev_type))
948 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
949 else
950 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
951 break;
952 default:
953 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
954 sas_dev->dev_type);
955 }
956
957 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
958 (device->linkrate << ITCT_HDR_MCR_OFF) |
959 (1 << ITCT_HDR_VLN_OFF) |
960 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
961 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
962 (port->id << ITCT_HDR_PORT_ID_OFF));
963 itct->qw0 = cpu_to_le64(qw0);
964
965
966 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
967 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
968
969
970 if (!dev_is_sata(device))
971 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
972 (0x1ULL << ITCT_HDR_BITLT_OFF) |
973 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
974 (0x1ULL << ITCT_HDR_RTOLT_OFF));
975}
976
977static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
978 struct hisi_sas_device *sas_dev)
979{
980 DECLARE_COMPLETION_ONSTACK(completion);
981 u64 dev_id = sas_dev->device_id;
982 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
983 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
984 int i;
985
986 sas_dev->completion = &completion;
987
988
989 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
990 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
991 ENT_INT_SRC3_ITC_INT_MSK);
992
993 for (i = 0; i < 2; i++) {
994 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
995 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
996 wait_for_completion(sas_dev->completion);
997
998 memset(itct, 0, sizeof(struct hisi_sas_itct));
999 }
1000}
1001
1002static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
1003{
1004 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
1005
1006
1007 if (dev_is_sata(sas_dev->sas_device))
1008 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1009}
1010
1011static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1012{
1013 int i, reset_val;
1014 u32 val;
1015 unsigned long end_time;
1016 struct device *dev = hisi_hba->dev;
1017
1018
1019 if (hisi_hba->n_phy == 9)
1020 reset_val = 0x1fffff;
1021 else
1022 reset_val = 0x7ffff;
1023
1024 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1025
1026
1027 for (i = 0; i < hisi_hba->n_phy; i++) {
1028 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1029
1030 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1031 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1032 }
1033 udelay(50);
1034
1035
1036 for (i = 0; i < hisi_hba->n_phy; i++) {
1037 u32 dma_tx_status, dma_rx_status;
1038
1039 end_time = jiffies + msecs_to_jiffies(1000);
1040
1041 while (1) {
1042 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1043 DMA_TX_STATUS);
1044 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1045 DMA_RX_STATUS);
1046
1047 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1048 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1049 break;
1050
1051 msleep(20);
1052 if (time_after(jiffies, end_time))
1053 return -EIO;
1054 }
1055 }
1056
1057
1058 end_time = jiffies + msecs_to_jiffies(1000);
1059 while (1) {
1060 u32 axi_status =
1061 hisi_sas_read32(hisi_hba, AXI_CFG);
1062
1063 if (axi_status == 0)
1064 break;
1065
1066 msleep(20);
1067 if (time_after(jiffies, end_time))
1068 return -EIO;
1069 }
1070
1071 if (ACPI_HANDLE(dev)) {
1072 acpi_status s;
1073
1074 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1075 if (ACPI_FAILURE(s)) {
1076 dev_err(dev, "Reset failed\n");
1077 return -EIO;
1078 }
1079 } else if (hisi_hba->ctrl) {
1080
1081 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1082 reset_val);
1083 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1084 reset_val);
1085 msleep(1);
1086 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1087 if (reset_val != (val & reset_val)) {
1088 dev_err(dev, "SAS reset fail.\n");
1089 return -EIO;
1090 }
1091
1092
1093 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1094 reset_val);
1095 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1096 reset_val);
1097 msleep(1);
1098 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1099 &val);
1100 if (val & reset_val) {
1101 dev_err(dev, "SAS de-reset fail.\n");
1102 return -EIO;
1103 }
1104 } else {
1105 dev_err(dev, "no reset method\n");
1106 return -EINVAL;
1107 }
1108
1109 return 0;
1110}
1111
1112
1113static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1114{
1115 u32 cfg;
1116 int phy_no;
1117
1118 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1119 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1120 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1121 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1122 continue;
1123
1124 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1125 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1126 }
1127}
1128
1129static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1130{
1131 int phy_no;
1132 u32 dma_tx_dfx1;
1133
1134 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1135 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1136 continue;
1137
1138 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1139 DMA_TX_DFX1);
1140 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1141 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1142 phy_no, CON_CONTROL);
1143
1144 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1145 hisi_sas_phy_write32(hisi_hba, phy_no,
1146 CON_CONTROL, cfg);
1147 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1148 }
1149 }
1150}
1151
1152static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1153static const struct sig_atten_lu_s sig_atten_lu[] = {
1154 { &x6000, 0x3016a68 },
1155};
1156
1157static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1158{
1159 struct device *dev = hisi_hba->dev;
1160 u32 sas_phy_ctrl = 0x30b9908;
1161 u32 signal[3];
1162 int i;
1163
1164
1165
1166
1167 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1168 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1169 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1170 0x2020);
1171 }
1172
1173 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1174 (u32)((1ULL << hisi_hba->queue_count) - 1));
1175 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1176 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1177 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1178 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1179 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1180 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1181 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1182 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1183 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1184 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1185 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1186 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1187 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1188 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1189 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1190 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1191 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1192 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1193 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1194 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1195 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1196 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1197 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1198 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1199 for (i = 0; i < hisi_hba->queue_count; i++)
1200 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1201
1202 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1203 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1204
1205
1206 if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1207 signal, ARRAY_SIZE(signal))) {
1208 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1209 const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1210 const struct signal_attenuation_s *att = lookup->att;
1211
1212 if ((signal[0] == att->de_emphasis) &&
1213 (signal[1] == att->preshoot) &&
1214 (signal[2] == att->boost)) {
1215 sas_phy_ctrl = lookup->sas_phy_ctrl;
1216 break;
1217 }
1218 }
1219
1220 if (i == ARRAY_SIZE(sig_atten_lu))
1221 dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1222 }
1223
1224 for (i = 0; i < hisi_hba->n_phy; i++) {
1225 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1226 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1227 u32 prog_phy_link_rate = 0x800;
1228
1229 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1230 SAS_LINK_RATE_1_5_GBPS)) {
1231 prog_phy_link_rate = 0x855;
1232 } else {
1233 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1234
1235 prog_phy_link_rate =
1236 hisi_sas_get_prog_phy_linkrate_mask(max) |
1237 0x800;
1238 }
1239 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1240 prog_phy_link_rate);
1241 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1242 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1243 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1244 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1245 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1246 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1247 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1248 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1249 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1250 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1251 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1252 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1253 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1254 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1255 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1256 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1257 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1258 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1259 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1260 if (hisi_hba->refclk_frequency_mhz == 66)
1261 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1262
1263 }
1264
1265 for (i = 0; i < hisi_hba->queue_count; i++) {
1266
1267 hisi_sas_write32(hisi_hba,
1268 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1269 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1270
1271 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1272 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1273
1274 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1275 HISI_SAS_QUEUE_SLOTS);
1276
1277
1278 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1279 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1280
1281 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1282 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1283
1284 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1285 HISI_SAS_QUEUE_SLOTS);
1286 }
1287
1288
1289 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1290 lower_32_bits(hisi_hba->itct_dma));
1291
1292 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1293 upper_32_bits(hisi_hba->itct_dma));
1294
1295
1296 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1297 lower_32_bits(hisi_hba->iost_dma));
1298
1299 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1300 upper_32_bits(hisi_hba->iost_dma));
1301
1302
1303 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1304 lower_32_bits(hisi_hba->breakpoint_dma));
1305
1306 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1307 upper_32_bits(hisi_hba->breakpoint_dma));
1308
1309
1310 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1311 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1312
1313 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1314 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1315
1316
1317 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1318 lower_32_bits(hisi_hba->initial_fis_dma));
1319
1320 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1321 upper_32_bits(hisi_hba->initial_fis_dma));
1322}
1323
1324static void link_timeout_enable_link(struct timer_list *t)
1325{
1326 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1327 int i, reg_val;
1328
1329 for (i = 0; i < hisi_hba->n_phy; i++) {
1330 if (hisi_hba->reject_stp_links_msk & BIT(i))
1331 continue;
1332
1333 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1334 if (!(reg_val & BIT(0))) {
1335 hisi_sas_phy_write32(hisi_hba, i,
1336 CON_CONTROL, 0x7);
1337 break;
1338 }
1339 }
1340
1341 hisi_hba->timer.function = link_timeout_disable_link;
1342 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1343}
1344
1345static void link_timeout_disable_link(struct timer_list *t)
1346{
1347 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1348 int i, reg_val;
1349
1350 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1351 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1352 if (hisi_hba->reject_stp_links_msk & BIT(i))
1353 continue;
1354
1355 if (reg_val & BIT(i)) {
1356 hisi_sas_phy_write32(hisi_hba, i,
1357 CON_CONTROL, 0x6);
1358 break;
1359 }
1360 }
1361
1362 hisi_hba->timer.function = link_timeout_enable_link;
1363 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1364}
1365
1366static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1367{
1368 hisi_hba->timer.function = link_timeout_disable_link;
1369 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1370 add_timer(&hisi_hba->timer);
1371}
1372
1373static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1374{
1375 struct device *dev = hisi_hba->dev;
1376 int rc;
1377
1378 rc = reset_hw_v2_hw(hisi_hba);
1379 if (rc) {
1380 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1381 return rc;
1382 }
1383
1384 msleep(100);
1385 init_reg_v2_hw(hisi_hba);
1386
1387 return 0;
1388}
1389
1390static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1391{
1392 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1393
1394 cfg |= PHY_CFG_ENA_MSK;
1395 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1396}
1397
1398static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1399{
1400 u32 context;
1401
1402 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1403 if (context & (1 << phy_no))
1404 return true;
1405
1406 return false;
1407}
1408
1409static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1410{
1411 u32 dfx_val;
1412
1413 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1414
1415 if (dfx_val & BIT(16))
1416 return false;
1417
1418 return true;
1419}
1420
1421static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1422{
1423 int i, max_loop = 1000;
1424 struct device *dev = hisi_hba->dev;
1425 u32 status, axi_status, dfx_val, dfx_tx_val;
1426
1427 for (i = 0; i < max_loop; i++) {
1428 status = hisi_sas_read32_relaxed(hisi_hba,
1429 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1430
1431 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1432 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1433 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1434 phy_no, DMA_TX_FIFO_DFX0);
1435
1436 if ((status == 0x3) && (axi_status == 0x0) &&
1437 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1438 return true;
1439 udelay(10);
1440 }
1441 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1442 phy_no, status, axi_status,
1443 dfx_val, dfx_tx_val);
1444 return false;
1445}
1446
1447static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1448{
1449 int i, max_loop = 1000;
1450 struct device *dev = hisi_hba->dev;
1451 u32 status, tx_dfx0;
1452
1453 for (i = 0; i < max_loop; i++) {
1454 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1455 status = (status & 0x3fc0) >> 6;
1456
1457 if (status != 0x1)
1458 return true;
1459
1460 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1461 if ((tx_dfx0 & 0x1ff) == 0x2)
1462 return true;
1463 udelay(10);
1464 }
1465 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1466 phy_no, status, tx_dfx0);
1467 return false;
1468}
1469
1470static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1471{
1472 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1473 return true;
1474
1475 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1476 return false;
1477
1478 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1479 return false;
1480
1481 return true;
1482}
1483
1484
1485static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1486{
1487 u32 cfg, axi_val, dfx0_val, txid_auto;
1488 struct device *dev = hisi_hba->dev;
1489
1490
1491 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1492 AM_CTRL_GLOBAL);
1493 axi_val |= 0x1;
1494 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1495 AM_CTRL_GLOBAL, axi_val);
1496
1497 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1498 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1499 goto do_disable;
1500
1501
1502 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1503 return;
1504 }
1505
1506 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1507 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1508 if (dfx0_val != 0x4)
1509 goto do_disable;
1510
1511 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1512 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1513 phy_no);
1514 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1515 TXID_AUTO);
1516 txid_auto |= TXID_AUTO_CTB_MSK;
1517 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1518 txid_auto);
1519 }
1520
1521do_disable:
1522 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1523 cfg &= ~PHY_CFG_ENA_MSK;
1524 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1525
1526
1527 axi_val &= ~0x1;
1528 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1529 AM_CTRL_GLOBAL, axi_val);
1530}
1531
1532static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1533{
1534 config_id_frame_v2_hw(hisi_hba, phy_no);
1535 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1536 enable_phy_v2_hw(hisi_hba, phy_no);
1537}
1538
1539static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1540{
1541 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1542 u32 txid_auto;
1543
1544 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1545 if (phy->identify.device_type == SAS_END_DEVICE) {
1546 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1547 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1548 txid_auto | TX_HARDRST_MSK);
1549 }
1550 msleep(100);
1551 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1552}
1553
1554static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1555{
1556 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1557 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1558 struct sas_phy *sphy = sas_phy->phy;
1559 u32 err4_reg_val, err6_reg_val;
1560
1561
1562 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1563
1564
1565 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1566
1567 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1568 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1569 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1570 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1571}
1572
1573static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1574{
1575 int i;
1576
1577 for (i = 0; i < hisi_hba->n_phy; i++) {
1578 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1579 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1580
1581 if (!sas_phy->phy->enabled)
1582 continue;
1583
1584 hisi_sas_phy_enable(hisi_hba, i, 1);
1585 }
1586}
1587
1588static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1589{
1590 u32 sl_control;
1591
1592 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1593 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1594 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1595 msleep(1);
1596 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1597 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1598 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1599}
1600
1601static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1602{
1603 return SAS_LINK_RATE_12_0_GBPS;
1604}
1605
1606static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1607 struct sas_phy_linkrates *r)
1608{
1609 enum sas_linkrate max = r->maximum_linkrate;
1610 u32 prog_phy_link_rate = 0x800;
1611
1612 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1613 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1614 prog_phy_link_rate);
1615}
1616
1617static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1618{
1619 int i, bitmap = 0;
1620 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1621 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1622
1623 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1624 if (phy_state & 1 << i)
1625 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1626 bitmap |= 1 << i;
1627
1628 if (hisi_hba->n_phy == 9) {
1629 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1630
1631 if (phy_state & 1 << 8)
1632 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1633 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1634 bitmap |= 1 << 9;
1635 }
1636
1637 return bitmap;
1638}
1639
1640
1641
1642
1643
1644static int
1645get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1646{
1647 struct device *dev = hisi_hba->dev;
1648 int queue = dq->id;
1649 u32 r, w;
1650
1651 w = dq->wr_point;
1652 r = hisi_sas_read32_relaxed(hisi_hba,
1653 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1654 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1655 dev_warn(dev, "full queue=%d r=%d w=%d\n",
1656 queue, r, w);
1657 return -EAGAIN;
1658 }
1659
1660 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1661
1662 return w;
1663}
1664
1665
1666static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1667{
1668 struct hisi_hba *hisi_hba = dq->hisi_hba;
1669 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1670 int dlvry_queue = dq->id;
1671 int wp;
1672
1673 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1674 if (!s->ready)
1675 break;
1676 s2 = s;
1677 list_del(&s->delivery);
1678 }
1679
1680 if (!s2)
1681 return;
1682
1683
1684
1685
1686 smp_rmb();
1687 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1688
1689 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1690}
1691
1692static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1693 struct hisi_sas_slot *slot,
1694 struct hisi_sas_cmd_hdr *hdr,
1695 struct scatterlist *scatter,
1696 int n_elem)
1697{
1698 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1699 struct scatterlist *sg;
1700 int i;
1701
1702 for_each_sg(scatter, sg, n_elem, i) {
1703 struct hisi_sas_sge *entry = &sge_page->sge[i];
1704
1705 entry->addr = cpu_to_le64(sg_dma_address(sg));
1706 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1707 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1708 entry->data_off = 0;
1709 }
1710
1711 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1712
1713 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1714}
1715
1716static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1717 struct hisi_sas_slot *slot)
1718{
1719 struct sas_task *task = slot->task;
1720 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1721 struct domain_device *device = task->dev;
1722 struct hisi_sas_port *port = slot->port;
1723 struct scatterlist *sg_req;
1724 struct hisi_sas_device *sas_dev = device->lldd_dev;
1725 dma_addr_t req_dma_addr;
1726 unsigned int req_len;
1727
1728
1729 sg_req = &task->smp_task.smp_req;
1730 req_dma_addr = sg_dma_address(sg_req);
1731 req_len = sg_dma_len(&task->smp_task.smp_req);
1732
1733
1734
1735 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1736 (1 << CMD_HDR_PRIORITY_OFF) |
1737 (2 << CMD_HDR_CMD_OFF));
1738
1739
1740 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1741 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1742 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1743
1744
1745 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1746 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1747 CMD_HDR_MRFL_OFF));
1748
1749 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1750
1751 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1752 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1753}
1754
1755static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1756 struct hisi_sas_slot *slot)
1757{
1758 struct sas_task *task = slot->task;
1759 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1760 struct domain_device *device = task->dev;
1761 struct hisi_sas_device *sas_dev = device->lldd_dev;
1762 struct hisi_sas_port *port = slot->port;
1763 struct sas_ssp_task *ssp_task = &task->ssp_task;
1764 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1765 struct hisi_sas_tmf_task *tmf = slot->tmf;
1766 int has_data = 0, priority = !!tmf;
1767 u8 *buf_cmd;
1768 u32 dw1 = 0, dw2 = 0;
1769
1770 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1771 (2 << CMD_HDR_TLR_CTRL_OFF) |
1772 (port->id << CMD_HDR_PORT_OFF) |
1773 (priority << CMD_HDR_PRIORITY_OFF) |
1774 (1 << CMD_HDR_CMD_OFF));
1775
1776 dw1 = 1 << CMD_HDR_VDTL_OFF;
1777 if (tmf) {
1778 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1779 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1780 } else {
1781 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1782 switch (scsi_cmnd->sc_data_direction) {
1783 case DMA_TO_DEVICE:
1784 has_data = 1;
1785 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1786 break;
1787 case DMA_FROM_DEVICE:
1788 has_data = 1;
1789 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1790 break;
1791 default:
1792 dw1 &= ~CMD_HDR_DIR_MSK;
1793 }
1794 }
1795
1796
1797 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1798 hdr->dw1 = cpu_to_le32(dw1);
1799
1800 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1801 + 3) / 4) << CMD_HDR_CFL_OFF) |
1802 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1803 (2 << CMD_HDR_SG_MOD_OFF);
1804 hdr->dw2 = cpu_to_le32(dw2);
1805
1806 hdr->transfer_tags = cpu_to_le32(slot->idx);
1807
1808 if (has_data)
1809 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1810 slot->n_elem);
1811
1812 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1813 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1814 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1815
1816 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1817 sizeof(struct ssp_frame_hdr);
1818
1819 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1820 if (!tmf) {
1821 buf_cmd[9] = task->ssp_task.task_attr |
1822 (task->ssp_task.task_prio << 3);
1823 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1824 task->ssp_task.cmd->cmd_len);
1825 } else {
1826 buf_cmd[10] = tmf->tmf;
1827 switch (tmf->tmf) {
1828 case TMF_ABORT_TASK:
1829 case TMF_QUERY_TASK:
1830 buf_cmd[12] =
1831 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1832 buf_cmd[13] =
1833 tmf->tag_of_task_to_be_managed & 0xff;
1834 break;
1835 default:
1836 break;
1837 }
1838 }
1839}
1840
1841#define TRANS_TX_ERR 0
1842#define TRANS_RX_ERR 1
1843#define DMA_TX_ERR 2
1844#define SIPC_RX_ERR 3
1845#define DMA_RX_ERR 4
1846
1847#define DMA_TX_ERR_OFF 0
1848#define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1849#define SIPC_RX_ERR_OFF 16
1850#define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1851
1852static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1853{
1854 static const u8 trans_tx_err_code_prio[] = {
1855 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1856 TRANS_TX_ERR_PHY_NOT_ENABLE,
1857 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1858 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1859 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1860 RESERVED0,
1861 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1862 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1863 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1864 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1865 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1866 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1867 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1868 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1869 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1870 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1871 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1872 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1873 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1874 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1875 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1876 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1877 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1878 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1879 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1880 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1881 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1882 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1883 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1884 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1885 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1886 };
1887 int index, i;
1888
1889 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1890 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1891 if (err_msk & (1 << index))
1892 return trans_tx_err_code_prio[i];
1893 }
1894 return -1;
1895}
1896
1897static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1898{
1899 static const u8 trans_rx_err_code_prio[] = {
1900 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1901 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1902 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1903 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1904 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1905 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1906 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1907 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1908 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1909 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1910 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1911 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1912 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1913 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1914 RESERVED1,
1915 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1916 TRANS_RX_ERR_WITH_DATA_LEN0,
1917 TRANS_RX_ERR_WITH_BAD_HASH,
1918 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1919 TRANS_RX_SSP_FRM_LEN_ERR,
1920 RESERVED2,
1921 RESERVED3,
1922 RESERVED4,
1923 RESERVED5,
1924 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1925 TRANS_RX_SMP_FRM_LEN_ERR,
1926 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1927 RESERVED6,
1928 RESERVED7,
1929 RESERVED8,
1930 RESERVED9,
1931 TRANS_RX_R_ERR,
1932 };
1933 int index, i;
1934
1935 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1936 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1937 if (err_msk & (1 << index))
1938 return trans_rx_err_code_prio[i];
1939 }
1940 return -1;
1941}
1942
1943static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1944{
1945 static const u8 dma_tx_err_code_prio[] = {
1946 DMA_TX_UNEXP_XFER_ERR,
1947 DMA_TX_UNEXP_RETRANS_ERR,
1948 DMA_TX_XFER_LEN_OVERFLOW,
1949 DMA_TX_XFER_OFFSET_ERR,
1950 DMA_TX_RAM_ECC_ERR,
1951 DMA_TX_DIF_LEN_ALIGN_ERR,
1952 DMA_TX_DIF_CRC_ERR,
1953 DMA_TX_DIF_APP_ERR,
1954 DMA_TX_DIF_RPP_ERR,
1955 DMA_TX_DATA_SGL_OVERFLOW,
1956 DMA_TX_DIF_SGL_OVERFLOW,
1957 };
1958 int index, i;
1959
1960 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1961 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1962 err_msk = err_msk & DMA_TX_ERR_MSK;
1963 if (err_msk & (1 << index))
1964 return dma_tx_err_code_prio[i];
1965 }
1966 return -1;
1967}
1968
1969static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1970{
1971 static const u8 sipc_rx_err_code_prio[] = {
1972 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1973 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1974 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1975 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1976 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1977 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1978 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1979 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1980 SIPC_RX_SATA_UNEXP_FIS_ERR,
1981 SIPC_RX_WRSETUP_ESTATUS_ERR,
1982 SIPC_RX_DATA_UNDERFLOW_ERR,
1983 };
1984 int index, i;
1985
1986 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1987 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1988 err_msk = err_msk & SIPC_RX_ERR_MSK;
1989 if (err_msk & (1 << (index + 0x10)))
1990 return sipc_rx_err_code_prio[i];
1991 }
1992 return -1;
1993}
1994
1995static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1996{
1997 static const u8 dma_rx_err_code_prio[] = {
1998 DMA_RX_UNKNOWN_FRM_ERR,
1999 DMA_RX_DATA_LEN_OVERFLOW,
2000 DMA_RX_DATA_LEN_UNDERFLOW,
2001 DMA_RX_DATA_OFFSET_ERR,
2002 RESERVED10,
2003 DMA_RX_SATA_FRAME_TYPE_ERR,
2004 DMA_RX_RESP_BUF_OVERFLOW,
2005 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2006 DMA_RX_UNEXP_NORM_RESP_ERR,
2007 DMA_RX_UNEXP_RDFRAME_ERR,
2008 DMA_RX_PIO_DATA_LEN_ERR,
2009 DMA_RX_RDSETUP_STATUS_ERR,
2010 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2011 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2012 DMA_RX_RDSETUP_LEN_ODD_ERR,
2013 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2014 DMA_RX_RDSETUP_LEN_OVER_ERR,
2015 DMA_RX_RDSETUP_OFFSET_ERR,
2016 DMA_RX_RDSETUP_ACTIVE_ERR,
2017 DMA_RX_RDSETUP_ESTATUS_ERR,
2018 DMA_RX_RAM_ECC_ERR,
2019 DMA_RX_DIF_CRC_ERR,
2020 DMA_RX_DIF_APP_ERR,
2021 DMA_RX_DIF_RPP_ERR,
2022 DMA_RX_DATA_SGL_OVERFLOW,
2023 DMA_RX_DIF_SGL_OVERFLOW,
2024 };
2025 int index, i;
2026
2027 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2028 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2029 if (err_msk & (1 << index))
2030 return dma_rx_err_code_prio[i];
2031 }
2032 return -1;
2033}
2034
2035
2036static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2037 struct sas_task *task,
2038 struct hisi_sas_slot *slot,
2039 int err_phase)
2040{
2041 struct task_status_struct *ts = &task->task_status;
2042 struct hisi_sas_err_record_v2 *err_record =
2043 hisi_sas_status_buf_addr_mem(slot);
2044 u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type);
2045 u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type);
2046 u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type);
2047 u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type);
2048 u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type);
2049 int error = -1;
2050
2051 if (err_phase == 1) {
2052
2053 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2054 if (error == -1)
2055 error = parse_trans_tx_err_code_v2_hw(
2056 trans_tx_fail_type);
2057 } else if (err_phase == 2) {
2058
2059 error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type);
2060 if (error == -1) {
2061 error = parse_dma_rx_err_code_v2_hw(
2062 dma_rx_err_type);
2063 if (error == -1)
2064 error = parse_sipc_rx_err_code_v2_hw(
2065 sipc_rx_err_type);
2066 }
2067 }
2068
2069 switch (task->task_proto) {
2070 case SAS_PROTOCOL_SSP:
2071 {
2072 switch (error) {
2073 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2074 {
2075 ts->stat = SAS_OPEN_REJECT;
2076 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2077 break;
2078 }
2079 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2080 {
2081 ts->stat = SAS_OPEN_REJECT;
2082 ts->open_rej_reason = SAS_OREJ_EPROTO;
2083 break;
2084 }
2085 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2086 {
2087 ts->stat = SAS_OPEN_REJECT;
2088 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2089 break;
2090 }
2091 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2092 {
2093 ts->stat = SAS_OPEN_REJECT;
2094 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2095 break;
2096 }
2097 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2098 {
2099 ts->stat = SAS_OPEN_REJECT;
2100 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2101 break;
2102 }
2103 case DMA_RX_UNEXP_NORM_RESP_ERR:
2104 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2105 case DMA_RX_RESP_BUF_OVERFLOW:
2106 {
2107 ts->stat = SAS_OPEN_REJECT;
2108 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2109 break;
2110 }
2111 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2112 {
2113
2114 ts->stat = SAS_DEV_NO_RESPONSE;
2115 break;
2116 }
2117 case DMA_RX_DATA_LEN_OVERFLOW:
2118 {
2119 ts->stat = SAS_DATA_OVERRUN;
2120 ts->residual = 0;
2121 break;
2122 }
2123 case DMA_RX_DATA_LEN_UNDERFLOW:
2124 {
2125 ts->residual = trans_tx_fail_type;
2126 ts->stat = SAS_DATA_UNDERRUN;
2127 break;
2128 }
2129 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2130 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2131 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2132 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2133 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2134 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2135 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2136 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2137 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2138 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2139 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2140 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2141 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2142 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2143 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2144 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2145 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2146 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2147 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2148 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2149 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2150 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2151 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2152 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2153 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2154 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2155 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2156 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2157 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2158 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2159 case TRANS_TX_ERR_FRAME_TXED:
2160 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2161 case TRANS_RX_ERR_WITH_DATA_LEN0:
2162 case TRANS_RX_ERR_WITH_BAD_HASH:
2163 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2164 case TRANS_RX_SSP_FRM_LEN_ERR:
2165 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2166 case DMA_TX_DATA_SGL_OVERFLOW:
2167 case DMA_TX_UNEXP_XFER_ERR:
2168 case DMA_TX_UNEXP_RETRANS_ERR:
2169 case DMA_TX_XFER_LEN_OVERFLOW:
2170 case DMA_TX_XFER_OFFSET_ERR:
2171 case SIPC_RX_DATA_UNDERFLOW_ERR:
2172 case DMA_RX_DATA_SGL_OVERFLOW:
2173 case DMA_RX_DATA_OFFSET_ERR:
2174 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2175 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2176 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2177 case DMA_RX_SATA_FRAME_TYPE_ERR:
2178 case DMA_RX_UNKNOWN_FRM_ERR:
2179 {
2180
2181 ts->stat = SAS_QUEUE_FULL;
2182 slot->abort = 1;
2183 break;
2184 }
2185 default:
2186 break;
2187 }
2188 }
2189 break;
2190 case SAS_PROTOCOL_SMP:
2191 ts->stat = SAM_STAT_CHECK_CONDITION;
2192 break;
2193
2194 case SAS_PROTOCOL_SATA:
2195 case SAS_PROTOCOL_STP:
2196 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2197 {
2198 switch (error) {
2199 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2200 {
2201 ts->stat = SAS_OPEN_REJECT;
2202 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2203 break;
2204 }
2205 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2206 {
2207 ts->resp = SAS_TASK_UNDELIVERED;
2208 ts->stat = SAS_DEV_NO_RESPONSE;
2209 break;
2210 }
2211 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2212 {
2213 ts->stat = SAS_OPEN_REJECT;
2214 ts->open_rej_reason = SAS_OREJ_EPROTO;
2215 break;
2216 }
2217 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2218 {
2219 ts->stat = SAS_OPEN_REJECT;
2220 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2221 break;
2222 }
2223 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2224 {
2225 ts->stat = SAS_OPEN_REJECT;
2226 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2227 break;
2228 }
2229 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2230 {
2231 ts->stat = SAS_OPEN_REJECT;
2232 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2233 break;
2234 }
2235 case DMA_RX_RESP_BUF_OVERFLOW:
2236 case DMA_RX_UNEXP_NORM_RESP_ERR:
2237 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2238 {
2239 ts->stat = SAS_OPEN_REJECT;
2240 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2241 break;
2242 }
2243 case DMA_RX_DATA_LEN_OVERFLOW:
2244 {
2245 ts->stat = SAS_DATA_OVERRUN;
2246 ts->residual = 0;
2247 break;
2248 }
2249 case DMA_RX_DATA_LEN_UNDERFLOW:
2250 {
2251 ts->residual = trans_tx_fail_type;
2252 ts->stat = SAS_DATA_UNDERRUN;
2253 break;
2254 }
2255 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2256 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2257 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2258 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2259 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2260 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2261 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2262 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2263 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2264 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2265 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2266 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2267 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2268 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2269 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2270 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2271 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2272 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2273 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2274 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2275 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2276 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2277 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2278 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2279 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2280 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2281 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2282 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2283 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2284 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2285 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2286 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2287 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2288 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2289 case TRANS_RX_ERR_WITH_DATA_LEN0:
2290 case TRANS_RX_ERR_WITH_BAD_HASH:
2291 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2292 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2293 case DMA_TX_DATA_SGL_OVERFLOW:
2294 case DMA_TX_UNEXP_XFER_ERR:
2295 case DMA_TX_UNEXP_RETRANS_ERR:
2296 case DMA_TX_XFER_LEN_OVERFLOW:
2297 case DMA_TX_XFER_OFFSET_ERR:
2298 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2299 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2300 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2301 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2302 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2303 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2304 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2305 case DMA_RX_DATA_SGL_OVERFLOW:
2306 case DMA_RX_DATA_OFFSET_ERR:
2307 case DMA_RX_SATA_FRAME_TYPE_ERR:
2308 case DMA_RX_UNEXP_RDFRAME_ERR:
2309 case DMA_RX_PIO_DATA_LEN_ERR:
2310 case DMA_RX_RDSETUP_STATUS_ERR:
2311 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2312 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2313 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2314 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2315 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2316 case DMA_RX_RDSETUP_OFFSET_ERR:
2317 case DMA_RX_RDSETUP_ACTIVE_ERR:
2318 case DMA_RX_RDSETUP_ESTATUS_ERR:
2319 case DMA_RX_UNKNOWN_FRM_ERR:
2320 case TRANS_RX_SSP_FRM_LEN_ERR:
2321 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2322 {
2323 slot->abort = 1;
2324 ts->stat = SAS_PHY_DOWN;
2325 break;
2326 }
2327 default:
2328 {
2329 ts->stat = SAS_PROTO_RESPONSE;
2330 break;
2331 }
2332 }
2333 hisi_sas_sata_done(task, slot);
2334 }
2335 break;
2336 default:
2337 break;
2338 }
2339}
2340
2341static int
2342slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2343{
2344 struct sas_task *task = slot->task;
2345 struct hisi_sas_device *sas_dev;
2346 struct device *dev = hisi_hba->dev;
2347 struct task_status_struct *ts;
2348 struct domain_device *device;
2349 struct sas_ha_struct *ha;
2350 enum exec_status sts;
2351 struct hisi_sas_complete_v2_hdr *complete_queue =
2352 hisi_hba->complete_hdr[slot->cmplt_queue];
2353 struct hisi_sas_complete_v2_hdr *complete_hdr =
2354 &complete_queue[slot->cmplt_queue_slot];
2355 unsigned long flags;
2356 bool is_internal = slot->is_internal;
2357 u32 dw0;
2358
2359 if (unlikely(!task || !task->lldd_task || !task->dev))
2360 return -EINVAL;
2361
2362 ts = &task->task_status;
2363 device = task->dev;
2364 ha = device->port->ha;
2365 sas_dev = device->lldd_dev;
2366
2367 spin_lock_irqsave(&task->task_state_lock, flags);
2368 task->task_state_flags &=
2369 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2370 spin_unlock_irqrestore(&task->task_state_lock, flags);
2371
2372 memset(ts, 0, sizeof(*ts));
2373 ts->resp = SAS_TASK_COMPLETE;
2374
2375 if (unlikely(!sas_dev)) {
2376 dev_dbg(dev, "slot complete: port has no device\n");
2377 ts->stat = SAS_PHY_DOWN;
2378 goto out;
2379 }
2380
2381
2382 dw0 = le32_to_cpu(complete_hdr->dw0);
2383 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >>
2384 CMPLT_HDR_ABORT_STAT_OFF) {
2385 case STAT_IO_ABORTED:
2386
2387 ts->stat = SAS_ABORTED_TASK;
2388 goto out;
2389 case STAT_IO_COMPLETE:
2390
2391 ts->stat = TMF_RESP_FUNC_SUCC;
2392 del_timer(&slot->internal_abort_timer);
2393 goto out;
2394 case STAT_IO_NO_DEVICE:
2395 ts->stat = TMF_RESP_FUNC_COMPLETE;
2396 del_timer(&slot->internal_abort_timer);
2397 goto out;
2398 case STAT_IO_NOT_VALID:
2399
2400
2401
2402 ts->stat = TMF_RESP_FUNC_FAILED;
2403 del_timer(&slot->internal_abort_timer);
2404 goto out;
2405 default:
2406 break;
2407 }
2408
2409 if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2410 u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2411 >> CMPLT_HDR_ERR_PHASE_OFF;
2412 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2413
2414
2415 if (ERR_ON_TX_PHASE(err_phase))
2416 slot_err_v2_hw(hisi_hba, task, slot, 1);
2417 else if (ERR_ON_RX_PHASE(err_phase))
2418 slot_err_v2_hw(hisi_hba, task, slot, 2);
2419
2420 if (ts->stat != SAS_DATA_UNDERRUN)
2421 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2422 slot->idx, task, sas_dev->device_id,
2423 complete_hdr->dw0, complete_hdr->dw1,
2424 complete_hdr->act, complete_hdr->dw3,
2425 error_info[0], error_info[1],
2426 error_info[2], error_info[3]);
2427
2428 if (unlikely(slot->abort))
2429 return ts->stat;
2430 goto out;
2431 }
2432
2433 switch (task->task_proto) {
2434 case SAS_PROTOCOL_SSP:
2435 {
2436 struct hisi_sas_status_buffer *status_buffer =
2437 hisi_sas_status_buf_addr_mem(slot);
2438 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2439 &status_buffer->iu[0];
2440
2441 sas_ssp_task_response(dev, task, iu);
2442 break;
2443 }
2444 case SAS_PROTOCOL_SMP:
2445 {
2446 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2447 void *to;
2448
2449 ts->stat = SAM_STAT_GOOD;
2450 to = kmap_atomic(sg_page(sg_resp));
2451
2452 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2453 DMA_FROM_DEVICE);
2454 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2455 DMA_TO_DEVICE);
2456 memcpy(to + sg_resp->offset,
2457 hisi_sas_status_buf_addr_mem(slot) +
2458 sizeof(struct hisi_sas_err_record),
2459 sg_dma_len(sg_resp));
2460 kunmap_atomic(to);
2461 break;
2462 }
2463 case SAS_PROTOCOL_SATA:
2464 case SAS_PROTOCOL_STP:
2465 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2466 {
2467 ts->stat = SAM_STAT_GOOD;
2468 hisi_sas_sata_done(task, slot);
2469 break;
2470 }
2471 default:
2472 ts->stat = SAM_STAT_CHECK_CONDITION;
2473 break;
2474 }
2475
2476 if (!slot->port->port_attached) {
2477 dev_warn(dev, "slot complete: port %d has removed\n",
2478 slot->port->sas_port.id);
2479 ts->stat = SAS_PHY_DOWN;
2480 }
2481
2482out:
2483 sts = ts->stat;
2484 spin_lock_irqsave(&task->task_state_lock, flags);
2485 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2486 spin_unlock_irqrestore(&task->task_state_lock, flags);
2487 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2488 return SAS_ABORTED_TASK;
2489 }
2490 task->task_state_flags |= SAS_TASK_STATE_DONE;
2491 spin_unlock_irqrestore(&task->task_state_lock, flags);
2492 hisi_sas_slot_task_free(hisi_hba, task, slot);
2493
2494 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2495 spin_lock_irqsave(&device->done_lock, flags);
2496 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2497 spin_unlock_irqrestore(&device->done_lock, flags);
2498 dev_info(dev, "slot complete: task(%p) ignored\n",
2499 task);
2500 return sts;
2501 }
2502 spin_unlock_irqrestore(&device->done_lock, flags);
2503 }
2504
2505 if (task->task_done)
2506 task->task_done(task);
2507
2508 return sts;
2509}
2510
2511static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2512 struct hisi_sas_slot *slot)
2513{
2514 struct sas_task *task = slot->task;
2515 struct domain_device *device = task->dev;
2516 struct domain_device *parent_dev = device->parent;
2517 struct hisi_sas_device *sas_dev = device->lldd_dev;
2518 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2519 struct asd_sas_port *sas_port = device->port;
2520 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2521 struct hisi_sas_tmf_task *tmf = slot->tmf;
2522 u8 *buf_cmd;
2523 int has_data = 0, hdr_tag = 0;
2524 u32 dw0, dw1 = 0, dw2 = 0;
2525
2526
2527
2528 dw0 = port->id << CMD_HDR_PORT_OFF;
2529 if (parent_dev && dev_is_expander(parent_dev->dev_type))
2530 dw0 |= 3 << CMD_HDR_CMD_OFF;
2531 else
2532 dw0 |= 4 << CMD_HDR_CMD_OFF;
2533
2534 if (tmf && tmf->force_phy) {
2535 dw0 |= CMD_HDR_FORCE_PHY_MSK;
2536 dw0 |= (1 << tmf->phy_id) << CMD_HDR_PHY_ID_OFF;
2537 }
2538
2539 hdr->dw0 = cpu_to_le32(dw0);
2540
2541
2542 switch (task->data_dir) {
2543 case DMA_TO_DEVICE:
2544 has_data = 1;
2545 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2546 break;
2547 case DMA_FROM_DEVICE:
2548 has_data = 1;
2549 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2550 break;
2551 default:
2552 dw1 &= ~CMD_HDR_DIR_MSK;
2553 }
2554
2555 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2556 (task->ata_task.fis.control & ATA_SRST))
2557 dw1 |= 1 << CMD_HDR_RESET_OFF;
2558
2559 dw1 |= (hisi_sas_get_ata_protocol(
2560 &task->ata_task.fis, task->data_dir))
2561 << CMD_HDR_FRAME_TYPE_OFF;
2562 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2563 hdr->dw1 = cpu_to_le32(dw1);
2564
2565
2566 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2567 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2568 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2569 }
2570
2571 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2572 2 << CMD_HDR_SG_MOD_OFF;
2573 hdr->dw2 = cpu_to_le32(dw2);
2574
2575
2576 hdr->transfer_tags = cpu_to_le32(slot->idx);
2577
2578 if (has_data)
2579 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2580 slot->n_elem);
2581
2582 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2583 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2584 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2585
2586 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2587
2588 if (likely(!task->ata_task.device_control_reg_update))
2589 task->ata_task.fis.flags |= 0x80;
2590
2591 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2592}
2593
2594static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2595{
2596 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2597 struct hisi_sas_port *port = slot->port;
2598 struct asd_sas_port *asd_sas_port;
2599 struct asd_sas_phy *sas_phy;
2600
2601 if (!port)
2602 return;
2603
2604 asd_sas_port = &port->sas_port;
2605
2606
2607 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2608 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2609 struct hisi_hba *hisi_hba = phy->hisi_hba;
2610 int phy_no = sas_phy->id;
2611 u32 link_dfx2;
2612
2613 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2614 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2615 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2616 u32 txid_auto;
2617
2618 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2619 TXID_AUTO);
2620 txid_auto |= TXID_AUTO_CTB_MSK;
2621 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2622 txid_auto);
2623 return;
2624 }
2625 }
2626}
2627
2628static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2629 struct hisi_sas_slot *slot,
2630 int device_id, int abort_flag, int tag_to_abort)
2631{
2632 struct sas_task *task = slot->task;
2633 struct domain_device *dev = task->dev;
2634 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2635 struct hisi_sas_port *port = slot->port;
2636 struct timer_list *timer = &slot->internal_abort_timer;
2637
2638
2639 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2640
2641 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2642
2643
2644 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) |
2645 (port->id << CMD_HDR_PORT_OFF) |
2646 (dev_is_sata(dev) <<
2647 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2648 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2649
2650
2651 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2652
2653
2654 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2655 hdr->transfer_tags = cpu_to_le32(slot->idx);
2656}
2657
2658static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2659{
2660 int i, res = IRQ_HANDLED;
2661 u32 port_id, link_rate;
2662 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2663 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2664 struct device *dev = hisi_hba->dev;
2665 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2666 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2667 unsigned long flags;
2668
2669 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2670
2671 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2672 goto end;
2673
2674 del_timer(&phy->timer);
2675
2676 if (phy_no == 8) {
2677 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2678
2679 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2680 PORT_STATE_PHY8_PORT_NUM_OFF;
2681 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2682 PORT_STATE_PHY8_CONN_RATE_OFF;
2683 } else {
2684 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2685 port_id = (port_id >> (4 * phy_no)) & 0xf;
2686 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2687 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2688 }
2689
2690 if (port_id == 0xf) {
2691 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2692 res = IRQ_NONE;
2693 goto end;
2694 }
2695
2696 for (i = 0; i < 6; i++) {
2697 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2698 RX_IDAF_DWORD0 + (i * 4));
2699 frame_rcvd[i] = __swab32(idaf);
2700 }
2701
2702 sas_phy->linkrate = link_rate;
2703 sas_phy->oob_mode = SAS_OOB_MODE;
2704 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2705 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2706 phy->port_id = port_id;
2707 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2708 phy->phy_type |= PORT_TYPE_SAS;
2709 phy->phy_attached = 1;
2710 phy->identify.device_type = id->dev_type;
2711 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2712 if (phy->identify.device_type == SAS_END_DEVICE)
2713 phy->identify.target_port_protocols =
2714 SAS_PROTOCOL_SSP;
2715 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2716 phy->identify.target_port_protocols =
2717 SAS_PROTOCOL_SMP;
2718 if (!timer_pending(&hisi_hba->timer))
2719 set_link_timer_quirk(hisi_hba);
2720 }
2721 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2722 spin_lock_irqsave(&phy->lock, flags);
2723 if (phy->reset_completion) {
2724 phy->in_reset = 0;
2725 complete(phy->reset_completion);
2726 }
2727 spin_unlock_irqrestore(&phy->lock, flags);
2728
2729end:
2730 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2731 CHL_INT0_SL_PHY_ENABLE_MSK);
2732 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2733
2734 return res;
2735}
2736
2737static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2738{
2739 u32 port_state;
2740
2741 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2742 if (port_state & 0x1ff)
2743 return true;
2744
2745 return false;
2746}
2747
2748static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2749{
2750 u32 phy_state, sl_ctrl, txid_auto;
2751 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2752 struct hisi_sas_port *port = phy->port;
2753 struct device *dev = hisi_hba->dev;
2754
2755 del_timer(&phy->timer);
2756 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2757
2758 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2759 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2760 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2761
2762 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2763 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2764 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2765 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2766 if (!check_any_wideports_v2_hw(hisi_hba) &&
2767 timer_pending(&hisi_hba->timer))
2768 del_timer(&hisi_hba->timer);
2769
2770 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2771 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2772 txid_auto | TXID_AUTO_CT3_MSK);
2773
2774 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2775 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2776
2777 return IRQ_HANDLED;
2778}
2779
2780static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2781{
2782 struct hisi_hba *hisi_hba = p;
2783 u32 irq_msk;
2784 int phy_no = 0;
2785 irqreturn_t res = IRQ_NONE;
2786
2787 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2788 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2789 while (irq_msk) {
2790 if (irq_msk & 1) {
2791 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2792 CHL_INT0);
2793
2794 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2795 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2796
2797 case CHL_INT0_SL_PHY_ENABLE_MSK:
2798
2799 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2800 IRQ_HANDLED)
2801 res = IRQ_HANDLED;
2802 break;
2803
2804 case CHL_INT0_NOT_RDY_MSK:
2805
2806 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2807 IRQ_HANDLED)
2808 res = IRQ_HANDLED;
2809 break;
2810
2811 case (CHL_INT0_NOT_RDY_MSK |
2812 CHL_INT0_SL_PHY_ENABLE_MSK):
2813 reg_value = hisi_sas_read32(hisi_hba,
2814 PHY_STATE);
2815 if (reg_value & BIT(phy_no)) {
2816
2817 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2818 IRQ_HANDLED)
2819 res = IRQ_HANDLED;
2820 } else {
2821
2822 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2823 IRQ_HANDLED)
2824 res = IRQ_HANDLED;
2825 }
2826 break;
2827
2828 default:
2829 break;
2830 }
2831
2832 }
2833 irq_msk >>= 1;
2834 phy_no++;
2835 }
2836
2837 return res;
2838}
2839
2840static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2841{
2842 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2843 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2844 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2845 u32 bcast_status;
2846
2847 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2848 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2849 if ((bcast_status & RX_BCAST_CHG_MSK) &&
2850 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2851 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2852 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2853 CHL_INT0_SL_RX_BCST_ACK_MSK);
2854 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2855}
2856
2857static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2858 {
2859 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2860 .msg = "dmac_tx_ecc_bad_err",
2861 },
2862 {
2863 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2864 .msg = "dmac_rx_ecc_bad_err",
2865 },
2866 {
2867 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2868 .msg = "dma_tx_axi_wr_err",
2869 },
2870 {
2871 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2872 .msg = "dma_tx_axi_rd_err",
2873 },
2874 {
2875 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2876 .msg = "dma_rx_axi_wr_err",
2877 },
2878 {
2879 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2880 .msg = "dma_rx_axi_rd_err",
2881 },
2882};
2883
2884static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2885{
2886 struct hisi_hba *hisi_hba = p;
2887 struct device *dev = hisi_hba->dev;
2888 u32 ent_msk, ent_tmp, irq_msk;
2889 int phy_no = 0;
2890
2891 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2892 ent_tmp = ent_msk;
2893 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2894 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2895
2896 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2897 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2898
2899 while (irq_msk) {
2900 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2901 CHL_INT0);
2902 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2903 CHL_INT1);
2904 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2905 CHL_INT2);
2906
2907 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2908 int i;
2909
2910 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2911 const struct hisi_sas_hw_error *error =
2912 &port_ecc_axi_error[i];
2913
2914 if (!(irq_value1 & error->irq_msk))
2915 continue;
2916
2917 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2918 error->msg, phy_no, irq_value1);
2919 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2920 }
2921
2922 hisi_sas_phy_write32(hisi_hba, phy_no,
2923 CHL_INT1, irq_value1);
2924 }
2925
2926 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2927 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2928
2929 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2930 dev_warn(dev, "phy%d identify timeout\n",
2931 phy_no);
2932 hisi_sas_notify_phy_event(phy,
2933 HISI_PHYE_LINK_RESET);
2934 }
2935
2936 hisi_sas_phy_write32(hisi_hba, phy_no,
2937 CHL_INT2, irq_value2);
2938 }
2939
2940 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2941 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2942 phy_bcast_v2_hw(phy_no, hisi_hba);
2943
2944 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
2945 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
2946
2947 hisi_sas_phy_write32(hisi_hba, phy_no,
2948 CHL_INT0, irq_value0
2949 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2950 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2951 & (~CHL_INT0_NOT_RDY_MSK));
2952 }
2953 irq_msk &= ~(1 << phy_no);
2954 phy_no++;
2955 }
2956
2957 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2958
2959 return IRQ_HANDLED;
2960}
2961
2962static void
2963one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2964{
2965 struct device *dev = hisi_hba->dev;
2966 const struct hisi_sas_hw_error *ecc_error;
2967 u32 val;
2968 int i;
2969
2970 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2971 ecc_error = &one_bit_ecc_errors[i];
2972 if (irq_value & ecc_error->irq_msk) {
2973 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2974 val &= ecc_error->msk;
2975 val >>= ecc_error->shift;
2976 dev_warn(dev, "%s found: mem addr is 0x%08X\n",
2977 ecc_error->msg, val);
2978 }
2979 }
2980}
2981
2982static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2983 u32 irq_value)
2984{
2985 struct device *dev = hisi_hba->dev;
2986 const struct hisi_sas_hw_error *ecc_error;
2987 u32 val;
2988 int i;
2989
2990 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2991 ecc_error = &multi_bit_ecc_errors[i];
2992 if (irq_value & ecc_error->irq_msk) {
2993 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2994 val &= ecc_error->msk;
2995 val >>= ecc_error->shift;
2996 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
2997 ecc_error->msg, irq_value, val);
2998 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2999 }
3000 }
3001
3002 return;
3003}
3004
3005static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
3006{
3007 struct hisi_hba *hisi_hba = p;
3008 u32 irq_value, irq_msk;
3009
3010 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
3011 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
3012
3013 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3014 if (irq_value) {
3015 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3016 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3017 }
3018
3019 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3020 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3021
3022 return IRQ_HANDLED;
3023}
3024
3025static const struct hisi_sas_hw_error axi_error[] = {
3026 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3027 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3028 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3029 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3030 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3031 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3032 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3033 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3034 {}
3035};
3036
3037static const struct hisi_sas_hw_error fifo_error[] = {
3038 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3039 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3040 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3041 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3042 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3043 {}
3044};
3045
3046static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3047 {
3048 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3049 .msg = "write pointer and depth",
3050 },
3051 {
3052 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3053 .msg = "iptt no match slot",
3054 },
3055 {
3056 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3057 .msg = "read pointer and depth",
3058 },
3059 {
3060 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3061 .reg = HGC_AXI_FIFO_ERR_INFO,
3062 .sub = axi_error,
3063 },
3064 {
3065 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3066 .reg = HGC_AXI_FIFO_ERR_INFO,
3067 .sub = fifo_error,
3068 },
3069 {
3070 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3071 .msg = "LM add/fetch list",
3072 },
3073 {
3074 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3075 .msg = "SAS_HGC_ABT fetch LM list",
3076 },
3077};
3078
3079static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3080{
3081 struct hisi_hba *hisi_hba = p;
3082 u32 irq_value, irq_msk, err_value;
3083 struct device *dev = hisi_hba->dev;
3084 const struct hisi_sas_hw_error *axi_error;
3085 int i;
3086
3087 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3088 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3089
3090 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3091
3092 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3093 axi_error = &fatal_axi_errors[i];
3094 if (!(irq_value & axi_error->irq_msk))
3095 continue;
3096
3097 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3098 1 << axi_error->shift);
3099 if (axi_error->sub) {
3100 const struct hisi_sas_hw_error *sub = axi_error->sub;
3101
3102 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3103 for (; sub->msk || sub->msg; sub++) {
3104 if (!(err_value & sub->msk))
3105 continue;
3106 dev_err(dev, "%s (0x%x) found!\n",
3107 sub->msg, irq_value);
3108 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3109 }
3110 } else {
3111 dev_err(dev, "%s (0x%x) found!\n",
3112 axi_error->msg, irq_value);
3113 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3114 }
3115 }
3116
3117 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3118 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3119 u32 dev_id = reg_val & ITCT_DEV_MSK;
3120 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3121
3122 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3123 dev_dbg(dev, "clear ITCT ok\n");
3124 complete(sas_dev->completion);
3125 }
3126
3127 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3128 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3129
3130 return IRQ_HANDLED;
3131}
3132
3133static void cq_tasklet_v2_hw(unsigned long val)
3134{
3135 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3136 struct hisi_hba *hisi_hba = cq->hisi_hba;
3137 struct hisi_sas_slot *slot;
3138 struct hisi_sas_itct *itct;
3139 struct hisi_sas_complete_v2_hdr *complete_queue;
3140 u32 rd_point = cq->rd_point, wr_point, dev_id;
3141 int queue = cq->id;
3142
3143 if (unlikely(hisi_hba->reject_stp_links_msk))
3144 phys_try_accept_stp_links_v2_hw(hisi_hba);
3145
3146 complete_queue = hisi_hba->complete_hdr[queue];
3147
3148 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3149 (0x14 * queue));
3150
3151 while (rd_point != wr_point) {
3152 struct hisi_sas_complete_v2_hdr *complete_hdr;
3153 int iptt;
3154
3155 complete_hdr = &complete_queue[rd_point];
3156
3157
3158 if (complete_hdr->act) {
3159 u32 act_tmp = le32_to_cpu(complete_hdr->act);
3160 int ncq_tag_count = ffs(act_tmp);
3161 u32 dw1 = le32_to_cpu(complete_hdr->dw1);
3162
3163 dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3164 CMPLT_HDR_DEV_ID_OFF;
3165 itct = &hisi_hba->itct[dev_id];
3166
3167
3168 while (ncq_tag_count) {
3169 __le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag;
3170 u64 ncq_tag;
3171
3172 ncq_tag_count--;
3173 __ncq_tag = _ncq_tag[ncq_tag_count / 5];
3174 ncq_tag = le64_to_cpu(__ncq_tag);
3175 iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) &
3176 0xfff;
3177
3178 slot = &hisi_hba->slot_info[iptt];
3179 slot->cmplt_queue_slot = rd_point;
3180 slot->cmplt_queue = queue;
3181 slot_complete_v2_hw(hisi_hba, slot);
3182
3183 act_tmp &= ~(1 << ncq_tag_count);
3184 ncq_tag_count = ffs(act_tmp);
3185 }
3186 } else {
3187 u32 dw1 = le32_to_cpu(complete_hdr->dw1);
3188
3189 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
3190 slot = &hisi_hba->slot_info[iptt];
3191 slot->cmplt_queue_slot = rd_point;
3192 slot->cmplt_queue = queue;
3193 slot_complete_v2_hw(hisi_hba, slot);
3194 }
3195
3196 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3197 rd_point = 0;
3198 }
3199
3200
3201 cq->rd_point = rd_point;
3202 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3203}
3204
3205static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3206{
3207 struct hisi_sas_cq *cq = p;
3208 struct hisi_hba *hisi_hba = cq->hisi_hba;
3209 int queue = cq->id;
3210
3211 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3212
3213 tasklet_schedule(&cq->tasklet);
3214
3215 return IRQ_HANDLED;
3216}
3217
3218static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3219{
3220 struct hisi_sas_phy *phy = p;
3221 struct hisi_hba *hisi_hba = phy->hisi_hba;
3222 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3223 struct device *dev = hisi_hba->dev;
3224 struct hisi_sas_initial_fis *initial_fis;
3225 struct dev_to_host_fis *fis;
3226 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3227 irqreturn_t res = IRQ_HANDLED;
3228 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3229 unsigned long flags;
3230 int phy_no, offset;
3231
3232 del_timer(&phy->timer);
3233
3234 phy_no = sas_phy->id;
3235 initial_fis = &hisi_hba->initial_fis[phy_no];
3236 fis = &initial_fis->fis;
3237
3238 offset = 4 * (phy_no / 4);
3239 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3240 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3241 ent_msk | 1 << ((phy_no % 4) * 8));
3242
3243 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3244 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3245 (phy_no % 4)));
3246 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3247 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3248 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3249 res = IRQ_NONE;
3250 goto end;
3251 }
3252
3253
3254 if (fis->status & ATA_ERR) {
3255 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3256 fis->status);
3257 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
3258 res = IRQ_NONE;
3259 goto end;
3260 }
3261
3262 if (unlikely(phy_no == 8)) {
3263 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3264
3265 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3266 PORT_STATE_PHY8_PORT_NUM_OFF;
3267 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3268 PORT_STATE_PHY8_CONN_RATE_OFF;
3269 } else {
3270 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3271 port_id = (port_id >> (4 * phy_no)) & 0xf;
3272 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3273 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3274 }
3275
3276 if (port_id == 0xf) {
3277 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3278 res = IRQ_NONE;
3279 goto end;
3280 }
3281
3282 sas_phy->linkrate = link_rate;
3283 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3284 HARD_PHY_LINKRATE);
3285 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3286 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3287
3288 sas_phy->oob_mode = SATA_OOB_MODE;
3289
3290 attached_sas_addr[0] = 0x50;
3291 attached_sas_addr[6] = hisi_hba->shost->host_no;
3292 attached_sas_addr[7] = phy_no;
3293 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3294 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3295 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3296 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3297 phy->port_id = port_id;
3298 phy->phy_type |= PORT_TYPE_SATA;
3299 phy->phy_attached = 1;
3300 phy->identify.device_type = SAS_SATA_DEV;
3301 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3302 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3303 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3304
3305 spin_lock_irqsave(&phy->lock, flags);
3306 if (phy->reset_completion) {
3307 phy->in_reset = 0;
3308 complete(phy->reset_completion);
3309 }
3310 spin_unlock_irqrestore(&phy->lock, flags);
3311end:
3312 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3313 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3314
3315 return res;
3316}
3317
3318static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3319 int_phy_updown_v2_hw,
3320 int_chnl_int_v2_hw,
3321};
3322
3323static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3324 fatal_ecc_int_v2_hw,
3325 fatal_axi_int_v2_hw
3326};
3327
3328
3329
3330
3331
3332static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3333{
3334 struct platform_device *pdev = hisi_hba->platform_dev;
3335 struct device *dev = &pdev->dev;
3336 int irq, rc, irq_map[128];
3337 int i, phy_no, fatal_no, queue_no, k;
3338
3339 for (i = 0; i < 128; i++)
3340 irq_map[i] = platform_get_irq(pdev, i);
3341
3342 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3343 irq = irq_map[i + 1];
3344 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3345 DRV_NAME " phy", hisi_hba);
3346 if (rc) {
3347 dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
3348 irq, rc);
3349 rc = -ENOENT;
3350 goto free_phy_int_irqs;
3351 }
3352 }
3353
3354 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3355 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3356
3357 irq = irq_map[phy_no + 72];
3358 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3359 DRV_NAME " sata", phy);
3360 if (rc) {
3361 dev_err(dev, "irq init: could not request sata interrupt %d, rc=%d\n",
3362 irq, rc);
3363 rc = -ENOENT;
3364 goto free_sata_int_irqs;
3365 }
3366 }
3367
3368 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3369 irq = irq_map[fatal_no + 81];
3370 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3371 DRV_NAME " fatal", hisi_hba);
3372 if (rc) {
3373 dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
3374 irq, rc);
3375 rc = -ENOENT;
3376 goto free_fatal_int_irqs;
3377 }
3378 }
3379
3380 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3381 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3382 struct tasklet_struct *t = &cq->tasklet;
3383
3384 irq = irq_map[queue_no + 96];
3385 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3386 DRV_NAME " cq", cq);
3387 if (rc) {
3388 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
3389 irq, rc);
3390 rc = -ENOENT;
3391 goto free_cq_int_irqs;
3392 }
3393 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3394 }
3395
3396 hisi_hba->cq_nvecs = hisi_hba->queue_count;
3397
3398 return 0;
3399
3400free_cq_int_irqs:
3401 for (k = 0; k < queue_no; k++) {
3402 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3403
3404 free_irq(irq_map[k + 96], cq);
3405 tasklet_kill(&cq->tasklet);
3406 }
3407free_fatal_int_irqs:
3408 for (k = 0; k < fatal_no; k++)
3409 free_irq(irq_map[k + 81], hisi_hba);
3410free_sata_int_irqs:
3411 for (k = 0; k < phy_no; k++) {
3412 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3413
3414 free_irq(irq_map[k + 72], phy);
3415 }
3416free_phy_int_irqs:
3417 for (k = 0; k < i; k++)
3418 free_irq(irq_map[k + 1], hisi_hba);
3419 return rc;
3420}
3421
3422static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3423{
3424 int rc;
3425
3426 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3427
3428 rc = hw_init_v2_hw(hisi_hba);
3429 if (rc)
3430 return rc;
3431
3432 rc = interrupt_init_v2_hw(hisi_hba);
3433 if (rc)
3434 return rc;
3435
3436 return 0;
3437}
3438
3439static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3440{
3441 struct platform_device *pdev = hisi_hba->platform_dev;
3442 int i;
3443
3444 for (i = 0; i < hisi_hba->queue_count; i++)
3445 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3446
3447 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3448 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3449 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3450 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3451
3452 for (i = 0; i < hisi_hba->n_phy; i++) {
3453 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3454 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3455 }
3456
3457 for (i = 0; i < 128; i++)
3458 synchronize_irq(platform_get_irq(pdev, i));
3459}
3460
3461
3462static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3463{
3464 return hisi_sas_read32(hisi_hba, PHY_STATE);
3465}
3466
3467static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3468{
3469 struct device *dev = hisi_hba->dev;
3470 int rc, cnt;
3471
3472 interrupt_disable_v2_hw(hisi_hba);
3473 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3474 hisi_sas_kill_tasklets(hisi_hba);
3475
3476 hisi_sas_stop_phys(hisi_hba);
3477
3478 mdelay(10);
3479
3480 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3481
3482
3483 cnt = 0;
3484 while (1) {
3485 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3486 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3487
3488 if (status == 0x3)
3489 break;
3490
3491 udelay(10);
3492 if (cnt++ > 10) {
3493 dev_err(dev, "wait axi bus state to idle timeout!\n");
3494 return -1;
3495 }
3496 }
3497
3498 hisi_sas_init_mem(hisi_hba);
3499
3500 rc = hw_init_v2_hw(hisi_hba);
3501 if (rc)
3502 return rc;
3503
3504 phys_reject_stp_links_v2_hw(hisi_hba);
3505
3506 return 0;
3507}
3508
3509static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3510 u8 reg_index, u8 reg_count, u8 *write_data)
3511{
3512 struct device *dev = hisi_hba->dev;
3513 int phy_no, count;
3514
3515 if (!hisi_hba->sgpio_regs)
3516 return -EOPNOTSUPP;
3517
3518 switch (reg_type) {
3519 case SAS_GPIO_REG_TX:
3520 count = reg_count * 4;
3521 count = min(count, hisi_hba->n_phy);
3522
3523 for (phy_no = 0; phy_no < count; phy_no++) {
3524
3525
3526
3527
3528
3529
3530 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3531 reg_index * 4 + phy_no;
3532 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3533
3534 writeb(write_data[data_idx], reg_addr);
3535 }
3536
3537 break;
3538 default:
3539 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3540 reg_type);
3541 return -EINVAL;
3542 }
3543
3544 return 0;
3545}
3546
3547static int wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
3548 int delay_ms, int timeout_ms)
3549{
3550 struct device *dev = hisi_hba->dev;
3551 int entries, entries_old = 0, time;
3552
3553 for (time = 0; time < timeout_ms; time += delay_ms) {
3554 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
3555 if (entries == entries_old)
3556 break;
3557
3558 entries_old = entries;
3559 msleep(delay_ms);
3560 }
3561
3562 if (time >= timeout_ms)
3563 return -ETIMEDOUT;
3564
3565 dev_dbg(dev, "wait commands complete %dms\n", time);
3566
3567 return 0;
3568}
3569
3570static struct device_attribute *host_attrs_v2_hw[] = {
3571 &dev_attr_phy_event_threshold,
3572 NULL
3573};
3574
3575static struct scsi_host_template sht_v2_hw = {
3576 .name = DRV_NAME,
3577 .module = THIS_MODULE,
3578 .queuecommand = sas_queuecommand,
3579 .target_alloc = sas_target_alloc,
3580 .slave_configure = hisi_sas_slave_configure,
3581 .scan_finished = hisi_sas_scan_finished,
3582 .scan_start = hisi_sas_scan_start,
3583 .change_queue_depth = sas_change_queue_depth,
3584 .bios_param = sas_bios_param,
3585 .this_id = -1,
3586 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3587 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3588 .eh_device_reset_handler = sas_eh_device_reset_handler,
3589 .eh_target_reset_handler = sas_eh_target_reset_handler,
3590 .target_destroy = sas_target_destroy,
3591 .ioctl = sas_ioctl,
3592 .shost_attrs = host_attrs_v2_hw,
3593 .host_reset = hisi_sas_host_reset,
3594};
3595
3596static const struct hisi_sas_hw hisi_sas_v2_hw = {
3597 .hw_init = hisi_sas_v2_init,
3598 .setup_itct = setup_itct_v2_hw,
3599 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3600 .alloc_dev = alloc_dev_quirk_v2_hw,
3601 .sl_notify_ssp = sl_notify_ssp_v2_hw,
3602 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3603 .clear_itct = clear_itct_v2_hw,
3604 .free_device = free_device_v2_hw,
3605 .prep_smp = prep_smp_v2_hw,
3606 .prep_ssp = prep_ssp_v2_hw,
3607 .prep_stp = prep_ata_v2_hw,
3608 .prep_abort = prep_abort_v2_hw,
3609 .get_free_slot = get_free_slot_v2_hw,
3610 .start_delivery = start_delivery_v2_hw,
3611 .slot_complete = slot_complete_v2_hw,
3612 .phys_init = phys_init_v2_hw,
3613 .phy_start = start_phy_v2_hw,
3614 .phy_disable = disable_phy_v2_hw,
3615 .phy_hard_reset = phy_hard_reset_v2_hw,
3616 .get_events = phy_get_events_v2_hw,
3617 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3618 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3619 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3620 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3621 .soft_reset = soft_reset_v2_hw,
3622 .get_phys_state = get_phys_state_v2_hw,
3623 .write_gpio = write_gpio_v2_hw,
3624 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
3625 .sht = &sht_v2_hw,
3626};
3627
3628static int hisi_sas_v2_probe(struct platform_device *pdev)
3629{
3630
3631
3632
3633
3634 int ret = platform_get_irq(pdev, 0);
3635
3636 if (ret < 0) {
3637 if (ret != -EPROBE_DEFER)
3638 dev_err(&pdev->dev, "cannot obtain irq\n");
3639 return ret;
3640 }
3641
3642 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3643}
3644
3645static int hisi_sas_v2_remove(struct platform_device *pdev)
3646{
3647 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3648 struct hisi_hba *hisi_hba = sha->lldd_ha;
3649
3650 hisi_sas_kill_tasklets(hisi_hba);
3651
3652 return hisi_sas_remove(pdev);
3653}
3654
3655static const struct of_device_id sas_v2_of_match[] = {
3656 { .compatible = "hisilicon,hip06-sas-v2",},
3657 { .compatible = "hisilicon,hip07-sas-v2",},
3658 {},
3659};
3660MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3661
3662static const struct acpi_device_id sas_v2_acpi_match[] = {
3663 { "HISI0162", 0 },
3664 { }
3665};
3666
3667MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3668
3669static struct platform_driver hisi_sas_v2_driver = {
3670 .probe = hisi_sas_v2_probe,
3671 .remove = hisi_sas_v2_remove,
3672 .driver = {
3673 .name = DRV_NAME,
3674 .of_match_table = sas_v2_of_match,
3675 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3676 },
3677};
3678
3679module_platform_driver(hisi_sas_v2_driver);
3680
3681MODULE_LICENSE("GPL");
3682MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3683MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3684MODULE_ALIAS("platform:" DRV_NAME);
3685