linux/drivers/scsi/lpfc/lpfc_hw.h
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   1/*******************************************************************
   2 * This file is part of the Emulex Linux Device Driver for         *
   3 * Fibre Channel Host Bus Adapters.                                *
   4 * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term *
   5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.     *
   6 * Copyright (C) 2004-2016 Emulex.  All rights reserved.           *
   7 * EMULEX and SLI are trademarks of Emulex.                        *
   8 * www.broadcom.com                                                *
   9 *                                                                 *
  10 * This program is free software; you can redistribute it and/or   *
  11 * modify it under the terms of version 2 of the GNU General       *
  12 * Public License as published by the Free Software Foundation.    *
  13 * This program is distributed in the hope that it will be useful. *
  14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  18 * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  19 * more details, a copy of which can be found in the file COPYING  *
  20 * included with this package.                                     *
  21 *******************************************************************/
  22
  23#define FDMI_DID        0xfffffaU
  24#define NameServer_DID  0xfffffcU
  25#define SCR_DID         0xfffffdU
  26#define Fabric_DID      0xfffffeU
  27#define Bcast_DID       0xffffffU
  28#define Mask_DID        0xffffffU
  29#define CT_DID_MASK     0xffff00U
  30#define Fabric_DID_MASK 0xfff000U
  31#define WELL_KNOWN_DID_MASK 0xfffff0U
  32
  33#define PT2PT_LocalID   1
  34#define PT2PT_RemoteID  2
  35
  36#define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  37#define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  38#define FF_DEF_RATOV            10      /* Default RA_TOV (10s) */
  39#define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  40
  41#define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  42                                           0 */
  43
  44#define FCELSSIZE             1024      /* maximum ELS transfer size */
  45
  46#define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  47#define LPFC_EXTRA_RING          1      /* ring 1 for other protocols */
  48#define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  49
  50#define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  51#define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  52#define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
  53#define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
  54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  56#define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  57#define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  58#define SLI2_IOCB_CMD_R3_ENTRIES      0
  59#define SLI2_IOCB_RSP_R3_ENTRIES      0
  60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  62
  63#define SLI2_IOCB_CMD_SIZE      32
  64#define SLI2_IOCB_RSP_SIZE      32
  65#define SLI3_IOCB_CMD_SIZE      128
  66#define SLI3_IOCB_RSP_SIZE      64
  67
  68#define LPFC_UNREG_ALL_RPIS_VPORT       0xffff
  69#define LPFC_UNREG_ALL_DFLT_RPIS        0xffffffff
  70
  71/* vendor ID used in SCSI netlink calls */
  72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
  73
  74#define FW_REV_STR_SIZE 32
  75/* Common Transport structures and definitions */
  76
  77union CtRevisionId {
  78        /* Structure is in Big Endian format */
  79        struct {
  80                uint32_t Revision:8;
  81                uint32_t InId:24;
  82        } bits;
  83        uint32_t word;
  84};
  85
  86union CtCommandResponse {
  87        /* Structure is in Big Endian format */
  88        struct {
  89                uint32_t CmdRsp:16;
  90                uint32_t Size:16;
  91        } bits;
  92        uint32_t word;
  93};
  94
  95/* FC4 Feature bits for RFF_ID */
  96#define FC4_FEATURE_TARGET      0x1
  97#define FC4_FEATURE_INIT        0x2
  98#define FC4_FEATURE_NVME_DISC   0x4
  99
 100struct lpfc_sli_ct_request {
 101        /* Structure is in Big Endian format */
 102        union CtRevisionId RevisionId;
 103        uint8_t FsType;
 104        uint8_t FsSubType;
 105        uint8_t Options;
 106        uint8_t Rsrvd1;
 107        union CtCommandResponse CommandResponse;
 108        uint8_t Rsrvd2;
 109        uint8_t ReasonCode;
 110        uint8_t Explanation;
 111        uint8_t VendorUnique;
 112#define LPFC_CT_PREAMBLE        20      /* Size of CTReq + 4 up to here */
 113
 114        union {
 115                uint32_t PortID;
 116                struct gid {
 117                        uint8_t PortType;       /* for GID_PT requests */
 118#define GID_PT_N_PORT   1
 119                        uint8_t DomainScope;
 120                        uint8_t AreaScope;
 121                        uint8_t Fc4Type;        /* for GID_FT requests */
 122                } gid;
 123                struct gid_ff {
 124                        uint8_t Flags;
 125                        uint8_t DomainScope;
 126                        uint8_t AreaScope;
 127                        uint8_t rsvd1;
 128                        uint8_t rsvd2;
 129                        uint8_t rsvd3;
 130                        uint8_t Fc4FBits;
 131                        uint8_t Fc4Type;
 132                } gid_ff;
 133                struct rft {
 134                        uint32_t PortId;        /* For RFT_ID requests */
 135
 136#ifdef __BIG_ENDIAN_BITFIELD
 137                        uint32_t rsvd0:16;
 138                        uint32_t rsvd1:7;
 139                        uint32_t fcpReg:1;      /* Type 8 */
 140                        uint32_t rsvd2:2;
 141                        uint32_t ipReg:1;       /* Type 5 */
 142                        uint32_t rsvd3:5;
 143#else   /*  __LITTLE_ENDIAN_BITFIELD */
 144                        uint32_t rsvd0:16;
 145                        uint32_t fcpReg:1;      /* Type 8 */
 146                        uint32_t rsvd1:7;
 147                        uint32_t rsvd3:5;
 148                        uint32_t ipReg:1;       /* Type 5 */
 149                        uint32_t rsvd2:2;
 150#endif
 151
 152                        uint32_t rsvd[7];
 153                } rft;
 154                struct rnn {
 155                        uint32_t PortId;        /* For RNN_ID requests */
 156                        uint8_t wwnn[8];
 157                } rnn;
 158                struct rsnn {   /* For RSNN_ID requests */
 159                        uint8_t wwnn[8];
 160                        uint8_t len;
 161                        uint8_t symbname[255];
 162                } rsnn;
 163                struct da_id { /* For DA_ID requests */
 164                        uint32_t port_id;
 165                } da_id;
 166                struct rspn {   /* For RSPN_ID requests */
 167                        uint32_t PortId;
 168                        uint8_t len;
 169                        uint8_t symbname[255];
 170                } rspn;
 171                struct gff {
 172                        uint32_t PortId;
 173                } gff;
 174                struct gff_acc {
 175                        uint8_t fbits[128];
 176                } gff_acc;
 177                struct gft {
 178                        uint32_t PortId;
 179                } gft;
 180                struct gft_acc {
 181                        uint32_t fc4_types[8];
 182                } gft_acc;
 183#define FCP_TYPE_FEATURE_OFFSET 7
 184                struct rff {
 185                        uint32_t PortId;
 186                        uint8_t reserved[2];
 187                        uint8_t fbits;
 188                        uint8_t type_code;     /* type=8 for FCP */
 189                } rff;
 190        } un;
 191};
 192
 193#define LPFC_MAX_CT_SIZE        (60 * 4096)
 194
 195#define  SLI_CT_REVISION        1
 196#define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 197                           sizeof(struct gid))
 198#define  GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
 199                           sizeof(struct gid_ff))
 200#define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 201                           sizeof(struct gff))
 202#define  GFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 203                           sizeof(struct gft))
 204#define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 205                           sizeof(struct rft))
 206#define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 207                           sizeof(struct rff))
 208#define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 209                           sizeof(struct rnn))
 210#define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 211                           sizeof(struct rsnn))
 212#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
 213                          sizeof(struct da_id))
 214#define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 215                           sizeof(struct rspn))
 216
 217/*
 218 * FsType Definitions
 219 */
 220
 221#define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 222#define  SLI_CT_TIME_SERVICE              0xFB
 223#define  SLI_CT_DIRECTORY_SERVICE         0xFC
 224#define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 225
 226/*
 227 * Directory Service Subtypes
 228 */
 229
 230#define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 231
 232/*
 233 * Response Codes
 234 */
 235
 236#define  SLI_CT_RESPONSE_FS_RJT           0x8001
 237#define  SLI_CT_RESPONSE_FS_ACC           0x8002
 238
 239/*
 240 * Reason Codes
 241 */
 242
 243#define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 244#define  SLI_CT_INVALID_COMMAND           0x01
 245#define  SLI_CT_INVALID_VERSION           0x02
 246#define  SLI_CT_LOGICAL_ERROR             0x03
 247#define  SLI_CT_INVALID_IU_SIZE           0x04
 248#define  SLI_CT_LOGICAL_BUSY              0x05
 249#define  SLI_CT_PROTOCOL_ERROR            0x07
 250#define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 251#define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 252#define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 253#define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 254#define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 255#define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 256#define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 257#define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 258#define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 259#define  SLI_CT_VENDOR_UNIQUE             0xff
 260
 261/*
 262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 263 */
 264
 265#define  SLI_CT_NO_PORT_ID                0x01
 266#define  SLI_CT_NO_PORT_NAME              0x02
 267#define  SLI_CT_NO_NODE_NAME              0x03
 268#define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 269#define  SLI_CT_NO_IP_ADDRESS             0x05
 270#define  SLI_CT_NO_IPA                    0x06
 271#define  SLI_CT_NO_FC4_TYPES              0x07
 272#define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 273#define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 274#define  SLI_CT_NO_PORT_TYPE              0x0A
 275#define  SLI_CT_ACCESS_DENIED             0x10
 276#define  SLI_CT_INVALID_PORT_ID           0x11
 277#define  SLI_CT_DATABASE_EMPTY            0x12
 278
 279/*
 280 * Name Server Command Codes
 281 */
 282
 283#define  SLI_CTNS_GA_NXT      0x0100
 284#define  SLI_CTNS_GPN_ID      0x0112
 285#define  SLI_CTNS_GNN_ID      0x0113
 286#define  SLI_CTNS_GCS_ID      0x0114
 287#define  SLI_CTNS_GFT_ID      0x0117
 288#define  SLI_CTNS_GSPN_ID     0x0118
 289#define  SLI_CTNS_GPT_ID      0x011A
 290#define  SLI_CTNS_GFF_ID      0x011F
 291#define  SLI_CTNS_GID_PN      0x0121
 292#define  SLI_CTNS_GID_NN      0x0131
 293#define  SLI_CTNS_GIP_NN      0x0135
 294#define  SLI_CTNS_GIPA_NN     0x0136
 295#define  SLI_CTNS_GSNN_NN     0x0139
 296#define  SLI_CTNS_GNN_IP      0x0153
 297#define  SLI_CTNS_GIPA_IP     0x0156
 298#define  SLI_CTNS_GID_FT      0x0171
 299#define  SLI_CTNS_GID_FF      0x01F1
 300#define  SLI_CTNS_GID_PT      0x01A1
 301#define  SLI_CTNS_RPN_ID      0x0212
 302#define  SLI_CTNS_RNN_ID      0x0213
 303#define  SLI_CTNS_RCS_ID      0x0214
 304#define  SLI_CTNS_RFT_ID      0x0217
 305#define  SLI_CTNS_RSPN_ID     0x0218
 306#define  SLI_CTNS_RPT_ID      0x021A
 307#define  SLI_CTNS_RFF_ID      0x021F
 308#define  SLI_CTNS_RIP_NN      0x0235
 309#define  SLI_CTNS_RIPA_NN     0x0236
 310#define  SLI_CTNS_RSNN_NN     0x0239
 311#define  SLI_CTNS_DA_ID       0x0300
 312
 313/*
 314 * Port Types
 315 */
 316
 317#define SLI_CTPT_N_PORT         0x01
 318#define SLI_CTPT_NL_PORT        0x02
 319#define SLI_CTPT_FNL_PORT       0x03
 320#define SLI_CTPT_IP             0x04
 321#define SLI_CTPT_FCP            0x08
 322#define SLI_CTPT_NVME           0x28
 323#define SLI_CTPT_NX_PORT        0x7F
 324#define SLI_CTPT_F_PORT         0x81
 325#define SLI_CTPT_FL_PORT        0x82
 326#define SLI_CTPT_E_PORT         0x84
 327
 328#define SLI_CT_LAST_ENTRY     0x80000000
 329
 330/* Fibre Channel Service Parameter definitions */
 331
 332#define FC_PH_4_0   6           /* FC-PH version 4.0 */
 333#define FC_PH_4_1   7           /* FC-PH version 4.1 */
 334#define FC_PH_4_2   8           /* FC-PH version 4.2 */
 335#define FC_PH_4_3   9           /* FC-PH version 4.3 */
 336
 337#define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 338#define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 339#define FC_PH3   0x20           /* FC-PH-3 version */
 340
 341#define FF_FRAME_SIZE     2048
 342
 343struct lpfc_name {
 344        union {
 345                struct {
 346#ifdef __BIG_ENDIAN_BITFIELD
 347                        uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 348                        uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 349                                                   8:11 of IEEE ext */
 350#else   /*  __LITTLE_ENDIAN_BITFIELD */
 351                        uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 352                                                   8:11 of IEEE ext */
 353                        uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 354#endif
 355
 356#define NAME_IEEE           0x1 /* IEEE name - nameType */
 357#define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 358#define NAME_FC_TYPE        0x3 /* FC native name type */
 359#define NAME_IP_TYPE        0x4 /* IP address */
 360#define NAME_CCITT_TYPE     0xC
 361#define NAME_CCITT_GR_TYPE  0xE
 362                        uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 363                                                   extended Lsb */
 364                        uint8_t IEEE[6];        /* FC IEEE address */
 365                } s;
 366                uint8_t wwn[8];
 367                uint64_t name;
 368        } u;
 369};
 370
 371struct csp {
 372        uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 373        uint8_t fcphLow;
 374        uint8_t bbCreditMsb;
 375        uint8_t bbCreditLsb;    /* FC Word 0, byte 3 */
 376
 377/*
 378 * Word 1 Bit 31 in common service parameter is overloaded.
 379 * Word 1 Bit 31 in FLOGI request is multiple NPort request
 380 * Word 1 Bit 31 in FLOGI response is clean address bit
 381 */
 382#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
 383/*
 384 * Word 1 Bit 30 in common service parameter is overloaded.
 385 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
 386 * Word 1 Bit 30 in PLOGI request is random offset
 387 */
 388#define virtual_fabric_support randomOffset /* Word 1, bit 30 */
 389/*
 390 * Word 1 Bit 29 in common service parameter is overloaded.
 391 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
 392 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
 393 */
 394#define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
 395#ifdef __BIG_ENDIAN_BITFIELD
 396        uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 397        uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 398        uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 399        uint16_t fPort:1;       /* FC Word 1, bit 28 */
 400        uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 401        uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 402        uint16_t multicast:1;   /* FC Word 1, bit 25 */
 403        uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 404
 405        uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 406        uint16_t simplex:1;     /* FC Word 1, bit 22 */
 407        uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 408        uint16_t dhd:1;         /* FC Word 1, bit 18 */
 409        uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 410        uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 411#else   /*  __LITTLE_ENDIAN_BITFIELD */
 412        uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 413        uint16_t multicast:1;   /* FC Word 1, bit 25 */
 414        uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 415        uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 416        uint16_t fPort:1;       /* FC Word 1, bit 28 */
 417        uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 418        uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 419        uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 420
 421        uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 422        uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 423        uint16_t dhd:1;         /* FC Word 1, bit 18 */
 424        uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 425        uint16_t simplex:1;     /* FC Word 1, bit 22 */
 426        uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 427#endif
 428
 429        uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 430        uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 431        union {
 432                struct {
 433                        uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 434
 435                        uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 436                        uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 437
 438                        uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 439                } nPort;
 440                uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 441        } w2;
 442
 443        uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 444};
 445
 446struct class_parms {
 447#ifdef __BIG_ENDIAN_BITFIELD
 448        uint8_t classValid:1;   /* FC Word 0, bit 31 */
 449        uint8_t intermix:1;     /* FC Word 0, bit 30 */
 450        uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 451        uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 452        uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 453        uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 454#else   /*  __LITTLE_ENDIAN_BITFIELD */
 455        uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 456        uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 457        uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 458        uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 459        uint8_t intermix:1;     /* FC Word 0, bit 30 */
 460        uint8_t classValid:1;   /* FC Word 0, bit 31 */
 461
 462#endif
 463
 464        uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 465
 466#ifdef __BIG_ENDIAN_BITFIELD
 467        uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 468        uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 469        uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 470        uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 471        uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 472#else   /*  __LITTLE_ENDIAN_BITFIELD */
 473        uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 474        uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 475        uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 476        uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 477        uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 478#endif
 479
 480        uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 481
 482#ifdef __BIG_ENDIAN_BITFIELD
 483        uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 484        uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 485        uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 486        uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 487        uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 488        uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 489#else   /*  __LITTLE_ENDIAN_BITFIELD */
 490        uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 491        uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 492        uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 493        uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 494        uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 495        uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 496#endif
 497
 498        uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 499        uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 500        uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 501
 502        uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 503        uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 504        uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 505        uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 506
 507        uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 508        uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 509        uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 510        uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 511};
 512
 513#define FAPWWN_KEY_VENDOR       0x42524344 /*valid vendor version fawwpn key*/
 514
 515struct serv_parm {      /* Structure is in Big Endian format */
 516        struct csp cmn;
 517        struct lpfc_name portName;
 518        struct lpfc_name nodeName;
 519        struct class_parms cls1;
 520        struct class_parms cls2;
 521        struct class_parms cls3;
 522        struct class_parms cls4;
 523        union {
 524                uint8_t vendorVersion[16];
 525                struct {
 526                        uint32_t vid;
 527#define LPFC_VV_EMLX_ID 0x454d4c58      /* EMLX */
 528                        uint32_t flags;
 529#define LPFC_VV_SUPPRESS_RSP    1
 530                } vv;
 531        } un;
 532};
 533
 534/*
 535 * Virtual Fabric Tagging Header
 536 */
 537struct fc_vft_header {
 538         uint32_t word0;
 539#define fc_vft_hdr_r_ctl_SHIFT          24
 540#define fc_vft_hdr_r_ctl_MASK           0xFF
 541#define fc_vft_hdr_r_ctl_WORD           word0
 542#define fc_vft_hdr_ver_SHIFT            22
 543#define fc_vft_hdr_ver_MASK             0x3
 544#define fc_vft_hdr_ver_WORD             word0
 545#define fc_vft_hdr_type_SHIFT           18
 546#define fc_vft_hdr_type_MASK            0xF
 547#define fc_vft_hdr_type_WORD            word0
 548#define fc_vft_hdr_e_SHIFT              16
 549#define fc_vft_hdr_e_MASK               0x1
 550#define fc_vft_hdr_e_WORD               word0
 551#define fc_vft_hdr_priority_SHIFT       13
 552#define fc_vft_hdr_priority_MASK        0x7
 553#define fc_vft_hdr_priority_WORD        word0
 554#define fc_vft_hdr_vf_id_SHIFT          1
 555#define fc_vft_hdr_vf_id_MASK           0xFFF
 556#define fc_vft_hdr_vf_id_WORD           word0
 557        uint32_t word1;
 558#define fc_vft_hdr_hopct_SHIFT          24
 559#define fc_vft_hdr_hopct_MASK           0xFF
 560#define fc_vft_hdr_hopct_WORD           word1
 561};
 562
 563#include <uapi/scsi/fc/fc_els.h>
 564
 565/*
 566 *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 567 */
 568#ifdef __BIG_ENDIAN_BITFIELD
 569#define ELS_CMD_MASK      0xffff0000
 570#define ELS_RSP_MASK      0xff000000
 571#define ELS_CMD_LS_RJT    0x01000000
 572#define ELS_CMD_ACC       0x02000000
 573#define ELS_CMD_PLOGI     0x03000000
 574#define ELS_CMD_FLOGI     0x04000000
 575#define ELS_CMD_LOGO      0x05000000
 576#define ELS_CMD_ABTX      0x06000000
 577#define ELS_CMD_RCS       0x07000000
 578#define ELS_CMD_RES       0x08000000
 579#define ELS_CMD_RSS       0x09000000
 580#define ELS_CMD_RSI       0x0A000000
 581#define ELS_CMD_ESTS      0x0B000000
 582#define ELS_CMD_ESTC      0x0C000000
 583#define ELS_CMD_ADVC      0x0D000000
 584#define ELS_CMD_RTV       0x0E000000
 585#define ELS_CMD_RLS       0x0F000000
 586#define ELS_CMD_ECHO      0x10000000
 587#define ELS_CMD_TEST      0x11000000
 588#define ELS_CMD_RRQ       0x12000000
 589#define ELS_CMD_REC       0x13000000
 590#define ELS_CMD_RDP       0x18000000
 591#define ELS_CMD_PRLI      0x20100014
 592#define ELS_CMD_NVMEPRLI  0x20140018
 593#define ELS_CMD_PRLO      0x21100014
 594#define ELS_CMD_PRLO_ACC  0x02100014
 595#define ELS_CMD_PDISC     0x50000000
 596#define ELS_CMD_FDISC     0x51000000
 597#define ELS_CMD_ADISC     0x52000000
 598#define ELS_CMD_FARP      0x54000000
 599#define ELS_CMD_FARPR     0x55000000
 600#define ELS_CMD_RPS       0x56000000
 601#define ELS_CMD_RPL       0x57000000
 602#define ELS_CMD_FAN       0x60000000
 603#define ELS_CMD_RSCN      0x61040000
 604#define ELS_CMD_RSCN_XMT  0x61040008
 605#define ELS_CMD_SCR       0x62000000
 606#define ELS_CMD_RNID      0x78000000
 607#define ELS_CMD_LIRR      0x7A000000
 608#define ELS_CMD_LCB       0x81000000
 609#define ELS_CMD_FPIN      0x16000000
 610#else   /*  __LITTLE_ENDIAN_BITFIELD */
 611#define ELS_CMD_MASK      0xffff
 612#define ELS_RSP_MASK      0xff
 613#define ELS_CMD_LS_RJT    0x01
 614#define ELS_CMD_ACC       0x02
 615#define ELS_CMD_PLOGI     0x03
 616#define ELS_CMD_FLOGI     0x04
 617#define ELS_CMD_LOGO      0x05
 618#define ELS_CMD_ABTX      0x06
 619#define ELS_CMD_RCS       0x07
 620#define ELS_CMD_RES       0x08
 621#define ELS_CMD_RSS       0x09
 622#define ELS_CMD_RSI       0x0A
 623#define ELS_CMD_ESTS      0x0B
 624#define ELS_CMD_ESTC      0x0C
 625#define ELS_CMD_ADVC      0x0D
 626#define ELS_CMD_RTV       0x0E
 627#define ELS_CMD_RLS       0x0F
 628#define ELS_CMD_ECHO      0x10
 629#define ELS_CMD_TEST      0x11
 630#define ELS_CMD_RRQ       0x12
 631#define ELS_CMD_REC       0x13
 632#define ELS_CMD_RDP       0x18
 633#define ELS_CMD_PRLI      0x14001020
 634#define ELS_CMD_NVMEPRLI  0x18001420
 635#define ELS_CMD_PRLO      0x14001021
 636#define ELS_CMD_PRLO_ACC  0x14001002
 637#define ELS_CMD_PDISC     0x50
 638#define ELS_CMD_FDISC     0x51
 639#define ELS_CMD_ADISC     0x52
 640#define ELS_CMD_FARP      0x54
 641#define ELS_CMD_FARPR     0x55
 642#define ELS_CMD_RPS       0x56
 643#define ELS_CMD_RPL       0x57
 644#define ELS_CMD_FAN       0x60
 645#define ELS_CMD_RSCN      0x0461
 646#define ELS_CMD_RSCN_XMT  0x08000461
 647#define ELS_CMD_SCR       0x62
 648#define ELS_CMD_RNID      0x78
 649#define ELS_CMD_LIRR      0x7A
 650#define ELS_CMD_LCB       0x81
 651#define ELS_CMD_FPIN      ELS_FPIN
 652#endif
 653
 654/*
 655 *  LS_RJT Payload Definition
 656 */
 657
 658struct ls_rjt { /* Structure is in Big Endian format */
 659        union {
 660                uint32_t lsRjtError;
 661                struct {
 662                        uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 663
 664                        uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 665                        /* LS_RJT reason codes */
 666#define LSRJT_INVALID_CMD     0x01
 667#define LSRJT_LOGICAL_ERR     0x03
 668#define LSRJT_LOGICAL_BSY     0x05
 669#define LSRJT_PROTOCOL_ERR    0x07
 670#define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 671#define LSRJT_CMD_UNSUPPORTED 0x0B
 672#define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 673
 674                        uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 675                        /* LS_RJT reason explanation */
 676#define LSEXP_NOTHING_MORE      0x00
 677#define LSEXP_SPARM_OPTIONS     0x01
 678#define LSEXP_SPARM_ICTL        0x03
 679#define LSEXP_SPARM_RCTL        0x05
 680#define LSEXP_SPARM_RCV_SIZE    0x07
 681#define LSEXP_SPARM_CONCUR_SEQ  0x09
 682#define LSEXP_SPARM_CREDIT      0x0B
 683#define LSEXP_INVALID_PNAME     0x0D
 684#define LSEXP_INVALID_NNAME     0x0E
 685#define LSEXP_INVALID_CSP       0x0F
 686#define LSEXP_INVALID_ASSOC_HDR 0x11
 687#define LSEXP_ASSOC_HDR_REQ     0x13
 688#define LSEXP_INVALID_O_SID     0x15
 689#define LSEXP_INVALID_OX_RX     0x17
 690#define LSEXP_CMD_IN_PROGRESS   0x19
 691#define LSEXP_PORT_LOGIN_REQ    0x1E
 692#define LSEXP_INVALID_NPORT_ID  0x1F
 693#define LSEXP_INVALID_SEQ_ID    0x21
 694#define LSEXP_INVALID_XCHG      0x23
 695#define LSEXP_INACTIVE_XCHG     0x25
 696#define LSEXP_RQ_REQUIRED       0x27
 697#define LSEXP_OUT_OF_RESOURCE   0x29
 698#define LSEXP_CANT_GIVE_DATA    0x2A
 699#define LSEXP_REQ_UNSUPPORTED   0x2C
 700                        uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 701                } b;
 702        } un;
 703};
 704
 705/*
 706 *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 707 */
 708
 709typedef struct _LOGO {          /* Structure is in Big Endian format */
 710        union {
 711                uint32_t nPortId32;     /* Access nPortId as a word */
 712                struct {
 713                        uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 714                        uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 715                        uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 716                        uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 717                } b;
 718        } un;
 719        struct lpfc_name portName;      /* N_port name field */
 720} LOGO;
 721
 722/*
 723 *  FCP Login (PRLI Request / ACC) Payload Definition
 724 */
 725
 726#define PRLX_PAGE_LEN   0x10
 727#define TPRLO_PAGE_LEN  0x14
 728
 729typedef struct _PRLI {          /* Structure is in Big Endian format */
 730        uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 731
 732#define PRLI_FCP_TYPE 0x08
 733#define PRLI_NVME_TYPE 0x28
 734        uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 735
 736#ifdef __BIG_ENDIAN_BITFIELD
 737        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 738        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 739        uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 740
 741        /*    ACC = imagePairEstablished */
 742        uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 743        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 744#else   /*  __LITTLE_ENDIAN_BITFIELD */
 745        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 746        uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 747        uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 748        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 749        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 750        /*    ACC = imagePairEstablished */
 751#endif
 752
 753#define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 754#define PRLI_NO_RESOURCES     0x2
 755#define PRLI_INIT_INCOMPLETE  0x3
 756#define PRLI_NO_SUCH_PA       0x4
 757#define PRLI_PREDEF_CONFIG    0x5
 758#define PRLI_PARTIAL_SUCCESS  0x6
 759#define PRLI_INVALID_PAGE_CNT 0x7
 760        uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 761
 762        uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 763
 764        uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 765
 766        uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 767        uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 768
 769#ifdef __BIG_ENDIAN_BITFIELD
 770        uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 771        uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 772        uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 773        uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 774        uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 775        uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 776        uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 777        uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 778        uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 779        uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 780        uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 781        uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 782        uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 783        uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 784        uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 785        uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 786#else   /*  __LITTLE_ENDIAN_BITFIELD */
 787        uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 788        uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 789        uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 790        uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 791        uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 792        uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 793        uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 794        uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 795        uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 796        uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 797        uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 798        uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 799        uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 800        uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 801        uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 802        uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 803#endif
 804} PRLI;
 805
 806/*
 807 *  FCP Logout (PRLO Request / ACC) Payload Definition
 808 */
 809
 810typedef struct _PRLO {          /* Structure is in Big Endian format */
 811        uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 812
 813#define PRLO_FCP_TYPE  0x08
 814        uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 815
 816#ifdef __BIG_ENDIAN_BITFIELD
 817        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 818        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 819        uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 820        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 821#else   /*  __LITTLE_ENDIAN_BITFIELD */
 822        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 823        uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 824        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 825        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 826#endif
 827
 828#define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 829#define PRLO_NO_SUCH_IMAGE    0x4
 830#define PRLO_INVALID_PAGE_CNT 0x7
 831
 832        uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 833
 834        uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 835
 836        uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 837
 838        uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 839} PRLO;
 840
 841typedef struct _ADISC {         /* Structure is in Big Endian format */
 842        uint32_t hardAL_PA;
 843        struct lpfc_name portName;
 844        struct lpfc_name nodeName;
 845        uint32_t DID;
 846} ADISC;
 847
 848typedef struct _FARP {          /* Structure is in Big Endian format */
 849        uint32_t Mflags:8;
 850        uint32_t Odid:24;
 851#define FARP_NO_ACTION          0       /* FARP information enclosed, no
 852                                           action */
 853#define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 854#define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 855#define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 856#define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 857                                           supported */
 858#define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 859                                           supported */
 860        uint32_t Rflags:8;
 861        uint32_t Rdid:24;
 862#define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 863#define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 864        struct lpfc_name OportName;
 865        struct lpfc_name OnodeName;
 866        struct lpfc_name RportName;
 867        struct lpfc_name RnodeName;
 868        uint8_t Oipaddr[16];
 869        uint8_t Ripaddr[16];
 870} FARP;
 871
 872typedef struct _FAN {           /* Structure is in Big Endian format */
 873        uint32_t Fdid;
 874        struct lpfc_name FportName;
 875        struct lpfc_name FnodeName;
 876} FAN;
 877
 878typedef struct _SCR {           /* Structure is in Big Endian format */
 879        uint8_t resvd1;
 880        uint8_t resvd2;
 881        uint8_t resvd3;
 882        uint8_t Function;
 883#define  SCR_FUNC_FABRIC     0x01
 884#define  SCR_FUNC_NPORT      0x02
 885#define  SCR_FUNC_FULL       0x03
 886#define  SCR_CLEAR           0xff
 887} SCR;
 888
 889typedef struct _RNID_TOP_DISC {
 890        struct lpfc_name portName;
 891        uint8_t resvd[8];
 892        uint32_t unitType;
 893#define RNID_HBA            0x7
 894#define RNID_HOST           0xa
 895#define RNID_DRIVER         0xd
 896        uint32_t physPort;
 897        uint32_t attachedNodes;
 898        uint16_t ipVersion;
 899#define RNID_IPV4           0x1
 900#define RNID_IPV6           0x2
 901        uint16_t UDPport;
 902        uint8_t ipAddr[16];
 903        uint16_t resvd1;
 904        uint16_t flags;
 905#define RNID_TD_SUPPORT     0x1
 906#define RNID_LP_VALID       0x2
 907} RNID_TOP_DISC;
 908
 909typedef struct _RNID {          /* Structure is in Big Endian format */
 910        uint8_t Format;
 911#define RNID_TOPOLOGY_DISC  0xdf
 912        uint8_t CommonLen;
 913        uint8_t resvd1;
 914        uint8_t SpecificLen;
 915        struct lpfc_name portName;
 916        struct lpfc_name nodeName;
 917        union {
 918                RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 919        } un;
 920} RNID;
 921
 922typedef struct  _RPS {          /* Structure is in Big Endian format */
 923        union {
 924                uint32_t portNum;
 925                struct lpfc_name portName;
 926        } un;
 927} RPS;
 928
 929typedef struct  _RPS_RSP {      /* Structure is in Big Endian format */
 930        uint16_t rsvd1;
 931        uint16_t portStatus;
 932        uint32_t linkFailureCnt;
 933        uint32_t lossSyncCnt;
 934        uint32_t lossSignalCnt;
 935        uint32_t primSeqErrCnt;
 936        uint32_t invalidXmitWord;
 937        uint32_t crcCnt;
 938} RPS_RSP;
 939
 940struct RLS {                    /* Structure is in Big Endian format */
 941        uint32_t rls;
 942#define rls_rsvd_SHIFT          24
 943#define rls_rsvd_MASK           0x000000ff
 944#define rls_rsvd_WORD           rls
 945#define rls_did_SHIFT           0
 946#define rls_did_MASK            0x00ffffff
 947#define rls_did_WORD            rls
 948};
 949
 950struct  RLS_RSP {               /* Structure is in Big Endian format */
 951        uint32_t linkFailureCnt;
 952        uint32_t lossSyncCnt;
 953        uint32_t lossSignalCnt;
 954        uint32_t primSeqErrCnt;
 955        uint32_t invalidXmitWord;
 956        uint32_t crcCnt;
 957};
 958
 959struct RRQ {                    /* Structure is in Big Endian format */
 960        uint32_t rrq;
 961#define rrq_rsvd_SHIFT          24
 962#define rrq_rsvd_MASK           0x000000ff
 963#define rrq_rsvd_WORD           rrq
 964#define rrq_did_SHIFT           0
 965#define rrq_did_MASK            0x00ffffff
 966#define rrq_did_WORD            rrq
 967        uint32_t rrq_exchg;
 968#define rrq_oxid_SHIFT          16
 969#define rrq_oxid_MASK           0xffff
 970#define rrq_oxid_WORD           rrq_exchg
 971#define rrq_rxid_SHIFT          0
 972#define rrq_rxid_MASK           0xffff
 973#define rrq_rxid_WORD           rrq_exchg
 974};
 975
 976#define LPFC_MAX_VFN_PER_PFN    255 /* Maximum VFs allowed per ARI */
 977#define LPFC_DEF_VFN_PER_PFN    0   /* Default VFs due to platform limitation*/
 978
 979struct RTV_RSP {                /* Structure is in Big Endian format */
 980        uint32_t ratov;
 981        uint32_t edtov;
 982        uint32_t qtov;
 983#define qtov_rsvd0_SHIFT        28
 984#define qtov_rsvd0_MASK         0x0000000f
 985#define qtov_rsvd0_WORD         qtov            /* reserved */
 986#define qtov_edtovres_SHIFT     27
 987#define qtov_edtovres_MASK      0x00000001
 988#define qtov_edtovres_WORD      qtov            /* E_D_TOV Resolution */
 989#define qtov__rsvd1_SHIFT       19
 990#define qtov_rsvd1_MASK         0x0000003f
 991#define qtov_rsvd1_WORD         qtov            /* reserved */
 992#define qtov_rttov_SHIFT        18
 993#define qtov_rttov_MASK         0x00000001
 994#define qtov_rttov_WORD         qtov            /* R_T_TOV value */
 995#define qtov_rsvd2_SHIFT        0
 996#define qtov_rsvd2_MASK         0x0003ffff
 997#define qtov_rsvd2_WORD         qtov            /* reserved */
 998};
 999
1000

1001typedef struct  _RPL {          /* Structure is in Big Endian format */
1002        uint32_t maxsize;
1003        uint32_t index;
1004} RPL;
1005
1006typedef struct  _PORT_NUM_BLK {
1007        uint32_t portNum;
1008        uint32_t portID;
1009        struct lpfc_name portName;
1010} PORT_NUM_BLK;
1011
1012typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
1013        uint32_t listLen;
1014        uint32_t index;
1015        PORT_NUM_BLK port_num_blk;
1016} RPL_RSP;
1017
1018/* This is used for RSCN command */
1019typedef struct _D_ID {          /* Structure is in Big Endian format */
1020        union {
1021                uint32_t word;
1022                struct {
1023#ifdef __BIG_ENDIAN_BITFIELD
1024                        uint8_t resv;
1025                        uint8_t domain;
1026                        uint8_t area;
1027                        uint8_t id;
1028#else   /*  __LITTLE_ENDIAN_BITFIELD */
1029                        uint8_t id;
1030                        uint8_t area;
1031                        uint8_t domain;
1032                        uint8_t resv;
1033#endif
1034                } b;
1035        } un;
1036} D_ID;
1037
1038#define RSCN_ADDRESS_FORMAT_PORT        0x0
1039#define RSCN_ADDRESS_FORMAT_AREA        0x1
1040#define RSCN_ADDRESS_FORMAT_DOMAIN      0x2
1041#define RSCN_ADDRESS_FORMAT_FABRIC      0x3
1042#define RSCN_ADDRESS_FORMAT_MASK        0x3
1043
1044/*
1045 *  Structure to define all ELS Payload types
1046 */
1047
1048typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
1049        uint8_t elsCode;        /* FC Word 0, bit 24:31 */
1050        uint8_t elsByte1;
1051        uint8_t elsByte2;
1052        uint8_t elsByte3;
1053        union {
1054                struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
1055                struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
1056                LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
1057                PRLI prli;      /* Payload for PRLI/ACC */
1058                PRLO prlo;      /* Payload for PRLO/ACC */
1059                ADISC adisc;    /* Payload for ADISC/ACC */
1060                FARP farp;      /* Payload for FARP/ACC */
1061                FAN fan;        /* Payload for FAN */
1062                SCR scr;        /* Payload for SCR/ACC */
1063                RNID rnid;      /* Payload for RNID */
1064                uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
1065        } un;
1066} ELS_PKT;
1067
1068/*
1069 * Link Cable Beacon (LCB) ELS Frame
1070 */
1071
1072struct fc_lcb_request_frame {
1073        uint32_t      lcb_command;      /* ELS command opcode (0x81)     */
1074        uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1075#define LPFC_LCB_ON             0x1
1076#define LPFC_LCB_OFF            0x2
1077        uint8_t       reserved[2];
1078        uint8_t       capability;       /* LCB Payload Word 1, bit 0:7 */
1079        uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1080#define LPFC_LCB_GREEN          0x1
1081#define LPFC_LCB_AMBER          0x2
1082        uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1083#define LCB_CAPABILITY_DURATION 1
1084#define BEACON_VERSION_V1       1
1085#define BEACON_VERSION_V0       0
1086        uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1087};
1088
1089/*
1090 * Link Cable Beacon (LCB) ELS Response Frame
1091 */
1092struct fc_lcb_res_frame {
1093        uint32_t      lcb_ls_acc;       /* Acceptance of LCB request (0x02) */
1094        uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1095        uint8_t       reserved[2];
1096        uint8_t       capability;       /* LCB Payload Word 1, bit 0:7 */
1097        uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1098        uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1099        uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1100};
1101
1102/*
1103 * Read Diagnostic Parameters (RDP) ELS frame.
1104 */
1105#define SFF_PG0_IDENT_SFP              0x3
1106
1107#define SFP_FLAG_PT_OPTICAL            0x0
1108#define SFP_FLAG_PT_SWLASER            0x01
1109#define SFP_FLAG_PT_LWLASER_LC1310     0x02
1110#define SFP_FLAG_PT_LWLASER_LL1550     0x03
1111#define SFP_FLAG_PT_MASK               0x0F
1112#define SFP_FLAG_PT_SHIFT              0
1113
1114#define SFP_FLAG_IS_OPTICAL_PORT       0x01
1115#define SFP_FLAG_IS_OPTICAL_MASK       0x010
1116#define SFP_FLAG_IS_OPTICAL_SHIFT      4
1117
1118#define SFP_FLAG_IS_DESC_VALID         0x01
1119#define SFP_FLAG_IS_DESC_VALID_MASK    0x020
1120#define SFP_FLAG_IS_DESC_VALID_SHIFT   5
1121
1122#define SFP_FLAG_CT_UNKNOWN            0x0
1123#define SFP_FLAG_CT_SFP_PLUS           0x01
1124#define SFP_FLAG_CT_MASK               0x3C
1125#define SFP_FLAG_CT_SHIFT              6
1126
1127struct fc_rdp_port_name_info {
1128        uint8_t wwnn[8];
1129        uint8_t wwpn[8];
1130};
1131
1132
1133/*
1134 * Link Error Status Block Structure (FC-FS-3) for RDP
1135 * This similar to RPS ELS
1136 */
1137struct fc_link_status {
1138        uint32_t      link_failure_cnt;
1139        uint32_t      loss_of_synch_cnt;
1140        uint32_t      loss_of_signal_cnt;
1141        uint32_t      primitive_seq_proto_err;
1142        uint32_t      invalid_trans_word;
1143        uint32_t      invalid_crc_cnt;
1144
1145};
1146
1147#define RDP_PORT_NAMES_DESC_TAG  0x00010003
1148struct fc_rdp_port_name_desc {
1149        uint32_t        tag;     /* 0001 0003h */
1150        uint32_t        length;  /* set to size of payload struct */
1151        struct fc_rdp_port_name_info  port_names;
1152};
1153
1154
1155struct fc_rdp_fec_info {
1156        uint32_t CorrectedBlocks;
1157        uint32_t UncorrectableBlocks;
1158};
1159
1160#define RDP_FEC_DESC_TAG  0x00010005
1161struct fc_fec_rdp_desc {
1162        uint32_t tag;
1163        uint32_t length;
1164        struct fc_rdp_fec_info info;
1165};
1166
1167struct fc_rdp_link_error_status_payload_info {
1168        struct fc_link_status link_status; /* 24 bytes */
1169        uint32_t  port_type;             /* bits 31-30 only */
1170};
1171
1172#define RDP_LINK_ERROR_STATUS_DESC_TAG  0x00010002
1173struct fc_rdp_link_error_status_desc {
1174        uint32_t         tag;     /* 0001 0002h */
1175        uint32_t         length;  /* set to size of payload struct */
1176        struct fc_rdp_link_error_status_payload_info info;
1177};
1178
1179#define VN_PT_PHY_UNKNOWN      0x00
1180#define VN_PT_PHY_PF_PORT      0x01
1181#define VN_PT_PHY_ETH_MAC      0x10
1182#define VN_PT_PHY_SHIFT                30
1183
1184#define RDP_PS_1GB             0x8000
1185#define RDP_PS_2GB             0x4000
1186#define RDP_PS_4GB             0x2000
1187#define RDP_PS_10GB            0x1000
1188#define RDP_PS_8GB             0x0800
1189#define RDP_PS_16GB            0x0400
1190#define RDP_PS_32GB            0x0200
1191#define RDP_PS_64GB            0x0100
1192#define RDP_PS_128GB           0x0080
1193#define RDP_PS_256GB           0x0040
1194
1195#define RDP_CAP_USER_CONFIGURED 0x0002
1196#define RDP_CAP_UNKNOWN         0x0001
1197#define RDP_PS_UNKNOWN          0x0002
1198#define RDP_PS_NOT_ESTABLISHED  0x0001
1199
1200struct fc_rdp_port_speed {
1201        uint16_t   capabilities;
1202        uint16_t   speed;
1203};
1204
1205struct fc_rdp_port_speed_info {
1206        struct fc_rdp_port_speed   port_speed;
1207};
1208
1209#define RDP_PORT_SPEED_DESC_TAG  0x00010001
1210struct fc_rdp_port_speed_desc {
1211        uint32_t         tag;            /* 00010001h */
1212        uint32_t         length;         /* set to size of payload struct */
1213        struct fc_rdp_port_speed_info info;
1214};
1215
1216#define RDP_NPORT_ID_SIZE      4
1217#define RDP_N_PORT_DESC_TAG    0x00000003
1218struct fc_rdp_nport_desc {
1219        uint32_t         tag;          /* 0000 0003h, big endian */
1220        uint32_t         length;       /* size of RDP_N_PORT_ID struct */
1221        uint32_t         nport_id : 12;
1222        uint32_t         reserved : 8;
1223};
1224
1225
1226struct fc_rdp_link_service_info {
1227        uint32_t         els_req;    /* Request payload word 0 value.*/
1228};
1229
1230#define RDP_LINK_SERVICE_DESC_TAG  0x00000001
1231struct fc_rdp_link_service_desc {
1232        uint32_t         tag;     /* Descriptor tag  1 */
1233        uint32_t         length;  /* set to size of payload struct. */
1234        struct fc_rdp_link_service_info  payload;
1235                                  /* must be ELS req Word 0(0x18) */
1236};
1237
1238struct fc_rdp_sfp_info {
1239        uint16_t        temperature;
1240        uint16_t        vcc;
1241        uint16_t        tx_bias;
1242        uint16_t        tx_power;
1243        uint16_t        rx_power;
1244        uint16_t        flags;
1245};
1246
1247#define RDP_SFP_DESC_TAG  0x00010000
1248struct fc_rdp_sfp_desc {
1249        uint32_t         tag;
1250        uint32_t         length;  /* set to size of sfp_info struct */
1251        struct fc_rdp_sfp_info sfp_info;
1252};
1253
1254/* Buffer Credit Descriptor */
1255struct fc_rdp_bbc_info {
1256        uint32_t              port_bbc; /* FC_Port buffer-to-buffer credit */
1257        uint32_t              attached_port_bbc;
1258        uint32_t              rtt;      /* Round trip time */
1259};
1260#define RDP_BBC_DESC_TAG  0x00010006
1261struct fc_rdp_bbc_desc {
1262        uint32_t              tag;
1263        uint32_t              length;
1264        struct fc_rdp_bbc_info  bbc_info;
1265};
1266
1267/* Optical Element Type Transgression Flags */
1268#define RDP_OET_LOW_WARNING  0x1
1269#define RDP_OET_HIGH_WARNING 0x2
1270#define RDP_OET_LOW_ALARM    0x4
1271#define RDP_OET_HIGH_ALARM   0x8
1272
1273#define RDP_OED_TEMPERATURE  0x1
1274#define RDP_OED_VOLTAGE      0x2
1275#define RDP_OED_TXBIAS       0x3
1276#define RDP_OED_TXPOWER      0x4
1277#define RDP_OED_RXPOWER      0x5
1278
1279#define RDP_OED_TYPE_SHIFT   28
1280/* Optical Element Data descriptor */
1281struct fc_rdp_oed_info {
1282        uint16_t            hi_alarm;
1283        uint16_t            lo_alarm;
1284        uint16_t            hi_warning;
1285        uint16_t            lo_warning;
1286        uint32_t            function_flags;
1287};
1288#define RDP_OED_DESC_TAG  0x00010007
1289struct fc_rdp_oed_sfp_desc {
1290        uint32_t             tag;
1291        uint32_t             length;
1292        struct fc_rdp_oed_info oed_info;
1293};
1294
1295/* Optical Product Data descriptor */
1296struct fc_rdp_opd_sfp_info {
1297        uint8_t            vendor_name[16];
1298        uint8_t            model_number[16];
1299        uint8_t            serial_number[16];
1300        uint8_t            revision[4];
1301        uint8_t            date[8];
1302};
1303
1304#define RDP_OPD_DESC_TAG  0x00010008
1305struct fc_rdp_opd_sfp_desc {
1306        uint32_t             tag;
1307        uint32_t             length;
1308        struct fc_rdp_opd_sfp_info opd_info;
1309};
1310
1311struct fc_rdp_req_frame {
1312        uint32_t         rdp_command;           /* ELS command opcode (0x18)*/
1313        uint32_t         rdp_des_length;        /* RDP Payload Word 1 */
1314        struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1315};
1316
1317
1318struct fc_rdp_res_frame {
1319        uint32_t    reply_sequence;             /* FC word0 LS_ACC or LS_RJT */
1320        uint32_t   length;                      /* FC Word 1      */
1321        struct fc_rdp_link_service_desc link_service_desc;    /* Word 2 -4   */
1322        struct fc_rdp_sfp_desc sfp_desc;                      /* Word 5 -9   */
1323        struct fc_rdp_port_speed_desc portspeed_desc;         /* Word 10 -12 */
1324        struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1325        struct fc_rdp_port_name_desc diag_port_names_desc;    /* Word 22 -27 */
1326        struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1327        struct fc_fec_rdp_desc fec_desc;                      /* FC word 34-37*/
1328        struct fc_rdp_bbc_desc bbc_desc;                      /* FC Word 38-42*/
1329        struct fc_rdp_oed_sfp_desc oed_temp_desc;             /* FC Word 43-47*/
1330        struct fc_rdp_oed_sfp_desc oed_voltage_desc;          /* FC word 48-52*/
1331        struct fc_rdp_oed_sfp_desc oed_txbias_desc;           /* FC word 53-57*/
1332        struct fc_rdp_oed_sfp_desc oed_txpower_desc;          /* FC word 58-62*/
1333        struct fc_rdp_oed_sfp_desc oed_rxpower_desc;          /* FC word 63-67*/
1334        struct fc_rdp_opd_sfp_desc opd_desc;                  /* FC word 68-84*/
1335};
1336
1337
1338/******** FDMI ********/
1339
1340/* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1341#define  SLI_CT_FDMI_Subtypes     0x10  /* Management Service Subtype */
1342
1343/*
1344 * Registered Port List Format
1345 */
1346struct lpfc_fdmi_reg_port_list {
1347        uint32_t EntryCnt;
1348        uint32_t pe;            /* Variable-length array */
1349};
1350
1351
1352/* Definitions for HBA / Port attribute entries */
1353
1354struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1355        /* Structure is in Big Endian format */
1356        uint32_t AttrType:16;
1357        uint32_t AttrLen:16;
1358        uint32_t AttrValue;  /* Marks start of Value (ATTRIBUTE_ENTRY) */
1359};
1360
1361
1362/* Attribute Entry */
1363struct lpfc_fdmi_attr_entry {
1364        union {
1365                uint32_t AttrInt;
1366                uint8_t  AttrTypes[32];
1367                uint8_t  AttrString[256];
1368                struct lpfc_name AttrWWN;
1369        } un;
1370};
1371
1372#define LPFC_FDMI_MAX_AE_SIZE   sizeof(struct lpfc_fdmi_attr_entry)
1373
1374/*
1375 * HBA Attribute Block
1376 */
1377struct lpfc_fdmi_attr_block {
1378        uint32_t EntryCnt;              /* Number of HBA attribute entries */
1379        struct lpfc_fdmi_attr_entry Entry;      /* Variable-length array */
1380};
1381
1382/*
1383 * Port Entry
1384 */
1385struct lpfc_fdmi_port_entry {
1386        struct lpfc_name PortName;
1387};
1388
1389/*
1390 * HBA Identifier
1391 */
1392struct lpfc_fdmi_hba_ident {
1393        struct lpfc_name PortName;
1394};
1395
1396/*
1397 * Register HBA(RHBA)
1398 */
1399struct lpfc_fdmi_reg_hba {
1400        struct lpfc_fdmi_hba_ident hi;
1401        struct lpfc_fdmi_reg_port_list rpl;     /* variable-length array */
1402/* struct lpfc_fdmi_attr_block   ab; */
1403};
1404
1405/*
1406 * Register HBA Attributes (RHAT)
1407 */
1408struct lpfc_fdmi_reg_hbaattr {
1409        struct lpfc_name HBA_PortName;
1410        struct lpfc_fdmi_attr_block ab;
1411};
1412
1413/*
1414 * Register Port Attributes (RPA)
1415 */
1416struct lpfc_fdmi_reg_portattr {
1417        struct lpfc_name PortName;
1418        struct lpfc_fdmi_attr_block ab;
1419};
1420
1421/*
1422 * HBA MAnagement Operations Command Codes
1423 */
1424#define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
1425#define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
1426#define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
1427#define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
1428#define  SLI_MGMT_GPAS     0x120        /* Get Port Statistics */
1429#define  SLI_MGMT_RHBA     0x200        /* Register HBA */
1430#define  SLI_MGMT_RHAT     0x201        /* Register HBA attributes */
1431#define  SLI_MGMT_RPRT     0x210        /* Register Port */
1432#define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
1433#define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
1434#define  SLI_MGMT_DHAT     0x301        /* De-register HBA attributes */
1435#define  SLI_MGMT_DPRT     0x310        /* De-register Port */
1436#define  SLI_MGMT_DPA      0x311        /* De-register Port attributes */
1437
1438#define LPFC_FDMI_MAX_RETRY     3  /* Max retries for a FDMI command */
1439
1440/*
1441 * HBA Attribute Types
1442 */
1443#define  RHBA_NODENAME           0x1 /* 8 byte WWNN */
1444#define  RHBA_MANUFACTURER       0x2 /* 4 to 64 byte ASCII string */
1445#define  RHBA_SERIAL_NUMBER      0x3 /* 4 to 64 byte ASCII string */
1446#define  RHBA_MODEL              0x4 /* 4 to 256 byte ASCII string */
1447#define  RHBA_MODEL_DESCRIPTION  0x5 /* 4 to 256 byte ASCII string */
1448#define  RHBA_HARDWARE_VERSION   0x6 /* 4 to 256 byte ASCII string */
1449#define  RHBA_DRIVER_VERSION     0x7 /* 4 to 256 byte ASCII string */
1450#define  RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1451#define  RHBA_FIRMWARE_VERSION   0x9 /* 4 to 256 byte ASCII string */
1452#define  RHBA_OS_NAME_VERSION    0xa /* 4 to 256 byte ASCII string */
1453#define  RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1454#define  RHBA_SYM_NODENAME       0xc /* 4 to 256 byte ASCII string */
1455#define  RHBA_VENDOR_INFO        0xd  /* 32-bit unsigned int */
1456#define  RHBA_NUM_PORTS          0xe  /* 32-bit unsigned int */
1457#define  RHBA_FABRIC_WWNN        0xf  /* 8 byte WWNN */
1458#define  RHBA_BIOS_VERSION       0x10 /* 4 to 256 byte ASCII string */
1459#define  RHBA_BIOS_STATE         0x11 /* 32-bit unsigned int */
1460#define  RHBA_VENDOR_ID          0xe0 /* 8 byte ASCII string */
1461
1462/* Bit mask for all individual HBA attributes */
1463#define LPFC_FDMI_HBA_ATTR_wwnn                 0x00000001
1464#define LPFC_FDMI_HBA_ATTR_manufacturer         0x00000002
1465#define LPFC_FDMI_HBA_ATTR_sn                   0x00000004
1466#define LPFC_FDMI_HBA_ATTR_model                0x00000008
1467#define LPFC_FDMI_HBA_ATTR_description          0x00000010
1468#define LPFC_FDMI_HBA_ATTR_hdw_ver              0x00000020
1469#define LPFC_FDMI_HBA_ATTR_drvr_ver             0x00000040
1470#define LPFC_FDMI_HBA_ATTR_rom_ver              0x00000080
1471#define LPFC_FDMI_HBA_ATTR_fmw_ver              0x00000100
1472#define LPFC_FDMI_HBA_ATTR_os_ver               0x00000200
1473#define LPFC_FDMI_HBA_ATTR_ct_len               0x00000400
1474#define LPFC_FDMI_HBA_ATTR_symbolic_name        0x00000800
1475#define LPFC_FDMI_HBA_ATTR_vendor_info          0x00001000 /* Not used */
1476#define LPFC_FDMI_HBA_ATTR_num_ports            0x00002000
1477#define LPFC_FDMI_HBA_ATTR_fabric_wwnn          0x00004000
1478#define LPFC_FDMI_HBA_ATTR_bios_ver             0x00008000
1479#define LPFC_FDMI_HBA_ATTR_bios_state           0x00010000 /* Not used */
1480#define LPFC_FDMI_HBA_ATTR_vendor_id            0x00020000
1481
1482/* Bit mask for FDMI-1 defined HBA attributes */
1483#define LPFC_FDMI1_HBA_ATTR                     0x000007ff
1484
1485/* Bit mask for FDMI-2 defined HBA attributes */
1486/* Skip vendor_info and bios_state */
1487#define LPFC_FDMI2_HBA_ATTR                     0x0002efff
1488
1489/*
1490 * Port Attrubute Types
1491 */
1492#define  RPRT_SUPPORTED_FC4_TYPES     0x1 /* 32 byte binary array */
1493#define  RPRT_SUPPORTED_SPEED         0x2 /* 32-bit unsigned int */
1494#define  RPRT_PORT_SPEED              0x3 /* 32-bit unsigned int */
1495#define  RPRT_MAX_FRAME_SIZE          0x4 /* 32-bit unsigned int */
1496#define  RPRT_OS_DEVICE_NAME          0x5 /* 4 to 256 byte ASCII string */
1497#define  RPRT_HOST_NAME               0x6 /* 4 to 256 byte ASCII string */
1498#define  RPRT_NODENAME                0x7 /* 8 byte WWNN */
1499#define  RPRT_PORTNAME                0x8 /* 8 byte WWPN */
1500#define  RPRT_SYM_PORTNAME            0x9 /* 4 to 256 byte ASCII string */
1501#define  RPRT_PORT_TYPE               0xa /* 32-bit unsigned int */
1502#define  RPRT_SUPPORTED_CLASS         0xb /* 32-bit unsigned int */
1503#define  RPRT_FABRICNAME              0xc /* 8 byte Fabric WWPN */
1504#define  RPRT_ACTIVE_FC4_TYPES        0xd /* 32 byte binary array */
1505#define  RPRT_PORT_STATE              0x101 /* 32-bit unsigned int */
1506#define  RPRT_DISC_PORT               0x102 /* 32-bit unsigned int */
1507#define  RPRT_PORT_ID                 0x103 /* 32-bit unsigned int */
1508#define  RPRT_SMART_SERVICE           0xf100 /* 4 to 256 byte ASCII string */
1509#define  RPRT_SMART_GUID              0xf101 /* 8 byte WWNN + 8 byte WWPN */
1510#define  RPRT_SMART_VERSION           0xf102 /* 4 to 256 byte ASCII string */
1511#define  RPRT_SMART_MODEL             0xf103 /* 4 to 256 byte ASCII string */
1512#define  RPRT_SMART_PORT_INFO         0xf104 /* 32-bit unsigned int */
1513#define  RPRT_SMART_QOS               0xf105 /* 32-bit unsigned int */
1514#define  RPRT_SMART_SECURITY          0xf106 /* 32-bit unsigned int */
1515
1516/* Bit mask for all individual PORT attributes */
1517#define LPFC_FDMI_PORT_ATTR_fc4type             0x00000001
1518#define LPFC_FDMI_PORT_ATTR_support_speed       0x00000002
1519#define LPFC_FDMI_PORT_ATTR_speed               0x00000004
1520#define LPFC_FDMI_PORT_ATTR_max_frame           0x00000008
1521#define LPFC_FDMI_PORT_ATTR_os_devname          0x00000010
1522#define LPFC_FDMI_PORT_ATTR_host_name           0x00000020
1523#define LPFC_FDMI_PORT_ATTR_wwnn                0x00000040
1524#define LPFC_FDMI_PORT_ATTR_wwpn                0x00000080
1525#define LPFC_FDMI_PORT_ATTR_symbolic_name       0x00000100
1526#define LPFC_FDMI_PORT_ATTR_port_type           0x00000200
1527#define LPFC_FDMI_PORT_ATTR_class               0x00000400
1528#define LPFC_FDMI_PORT_ATTR_fabric_wwpn         0x00000800
1529#define LPFC_FDMI_PORT_ATTR_port_state          0x00001000
1530#define LPFC_FDMI_PORT_ATTR_active_fc4type      0x00002000
1531#define LPFC_FDMI_PORT_ATTR_num_disc            0x00004000
1532#define LPFC_FDMI_PORT_ATTR_nportid             0x00008000
1533#define LPFC_FDMI_SMART_ATTR_service            0x00010000 /* Vendor specific */
1534#define LPFC_FDMI_SMART_ATTR_guid               0x00020000 /* Vendor specific */
1535#define LPFC_FDMI_SMART_ATTR_version            0x00040000 /* Vendor specific */
1536#define LPFC_FDMI_SMART_ATTR_model              0x00080000 /* Vendor specific */
1537#define LPFC_FDMI_SMART_ATTR_port_info          0x00100000 /* Vendor specific */
1538#define LPFC_FDMI_SMART_ATTR_qos                0x00200000 /* Vendor specific */
1539#define LPFC_FDMI_SMART_ATTR_security           0x00400000 /* Vendor specific */
1540
1541/* Bit mask for FDMI-1 defined PORT attributes */
1542#define LPFC_FDMI1_PORT_ATTR                    0x0000003f
1543
1544/* Bit mask for FDMI-2 defined PORT attributes */
1545#define LPFC_FDMI2_PORT_ATTR                    0x0000ffff
1546
1547/* Bit mask for Smart SAN defined PORT attributes */
1548#define LPFC_FDMI2_SMART_ATTR                   0x007fffff
1549
1550/* Defines for PORT port state attribute */
1551#define LPFC_FDMI_PORTSTATE_UNKNOWN     1
1552#define LPFC_FDMI_PORTSTATE_ONLINE      2
1553
1554/* Defines for PORT port type attribute */
1555#define LPFC_FDMI_PORTTYPE_UNKNOWN      0
1556#define LPFC_FDMI_PORTTYPE_NPORT        1
1557#define LPFC_FDMI_PORTTYPE_NLPORT       2
1558
1559/*
1560 *  Begin HBA configuration parameters.
1561 *  The PCI configuration register BAR assignments are:
1562 *  BAR0, offset 0x10 - SLIM base memory address
1563 *  BAR1, offset 0x14 - SLIM base memory high address
1564 *  BAR2, offset 0x18 - REGISTER base memory address
1565 *  BAR3, offset 0x1c - REGISTER base memory high address
1566 *  BAR4, offset 0x20 - BIU I/O registers
1567 *  BAR5, offset 0x24 - REGISTER base io high address
1568 */
1569
1570/* Number of rings currently used and available. */
1571#define MAX_SLI3_CONFIGURED_RINGS     3
1572#define MAX_SLI3_RINGS                4
1573
1574/* IOCB / Mailbox is owned by FireFly */
1575#define OWN_CHIP        1
1576
1577/* IOCB / Mailbox is owned by Host */
1578#define OWN_HOST        0
1579
1580/* Number of 4-byte words in an IOCB. */
1581#define IOCB_WORD_SZ    8
1582
1583/* network headers for Dfctl field */
1584#define FC_NET_HDR      0x20
1585
1586/* Start FireFly Register definitions */
1587#define PCI_VENDOR_ID_EMULEX        0x10df
1588#define PCI_DEVICE_ID_FIREFLY       0x1ae5
1589#define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1590#define PCI_DEVICE_ID_BALIUS        0xe131
1591#define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1592#define PCI_DEVICE_ID_LANCER_FC     0xe200
1593#define PCI_DEVICE_ID_LANCER_FC_VF  0xe208
1594#define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1595#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1596#define PCI_DEVICE_ID_LANCER_G6_FC  0xe300
1597#define PCI_DEVICE_ID_LANCER_G7_FC  0xf400
1598#define PCI_DEVICE_ID_SAT_SMB       0xf011
1599#define PCI_DEVICE_ID_SAT_MID       0xf015
1600#define PCI_DEVICE_ID_RFLY          0xf095
1601#define PCI_DEVICE_ID_PFLY          0xf098
1602#define PCI_DEVICE_ID_LP101         0xf0a1
1603#define PCI_DEVICE_ID_TFLY          0xf0a5
1604#define PCI_DEVICE_ID_BSMB          0xf0d1
1605#define PCI_DEVICE_ID_BMID          0xf0d5
1606#define PCI_DEVICE_ID_ZSMB          0xf0e1
1607#define PCI_DEVICE_ID_ZMID          0xf0e5
1608#define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1609#define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1610#define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1611#define PCI_DEVICE_ID_SAT           0xf100
1612#define PCI_DEVICE_ID_SAT_SCSP      0xf111
1613#define PCI_DEVICE_ID_SAT_DCSP      0xf112
1614#define PCI_DEVICE_ID_FALCON        0xf180
1615#define PCI_DEVICE_ID_SUPERFLY      0xf700
1616#define PCI_DEVICE_ID_DRAGONFLY     0xf800
1617#define PCI_DEVICE_ID_CENTAUR       0xf900
1618#define PCI_DEVICE_ID_PEGASUS       0xf980
1619#define PCI_DEVICE_ID_THOR          0xfa00
1620#define PCI_DEVICE_ID_VIPER         0xfb00
1621#define PCI_DEVICE_ID_LP10000S      0xfc00
1622#define PCI_DEVICE_ID_LP11000S      0xfc10
1623#define PCI_DEVICE_ID_LPE11000S     0xfc20
1624#define PCI_DEVICE_ID_SAT_S         0xfc40
1625#define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1626#define PCI_DEVICE_ID_HELIOS        0xfd00
1627#define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1628#define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1629#define PCI_DEVICE_ID_ZEPHYR        0xfe00
1630#define PCI_DEVICE_ID_HORNET        0xfe05
1631#define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1632#define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1633#define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1634#define PCI_DEVICE_ID_TIGERSHARK    0x0704
1635#define PCI_DEVICE_ID_TOMCAT        0x0714
1636#define PCI_DEVICE_ID_SKYHAWK       0x0724
1637#define PCI_DEVICE_ID_SKYHAWK_VF    0x072c
1638
1639#define JEDEC_ID_ADDRESS            0x0080001c
1640#define FIREFLY_JEDEC_ID            0x1ACC
1641#define SUPERFLY_JEDEC_ID           0x0020
1642#define DRAGONFLY_JEDEC_ID          0x0021
1643#define DRAGONFLY_V2_JEDEC_ID       0x0025
1644#define CENTAUR_2G_JEDEC_ID         0x0026
1645#define CENTAUR_1G_JEDEC_ID         0x0028
1646#define PEGASUS_ORION_JEDEC_ID      0x0036
1647#define PEGASUS_JEDEC_ID            0x0038
1648#define THOR_JEDEC_ID               0x0012
1649#define HELIOS_JEDEC_ID             0x0364
1650#define ZEPHYR_JEDEC_ID             0x0577
1651#define VIPER_JEDEC_ID              0x4838
1652#define SATURN_JEDEC_ID             0x1004
1653#define HORNET_JDEC_ID              0x2057706D
1654
1655#define JEDEC_ID_MASK               0x0FFFF000
1656#define JEDEC_ID_SHIFT              12
1657#define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1658
1659typedef struct {                /* FireFly BIU registers */
1660        uint32_t hostAtt;       /* See definitions for Host Attention
1661                                   register */
1662        uint32_t chipAtt;       /* See definitions for Chip Attention
1663                                   register */
1664        uint32_t hostStatus;    /* See definitions for Host Status register */
1665        uint32_t hostControl;   /* See definitions for Host Control register */
1666        uint32_t buiConfig;     /* See definitions for BIU configuration
1667                                   register */
1668} FF_REGS;
1669
1670/* IO Register size in bytes */
1671#define FF_REG_AREA_SIZE       256
1672
1673/* Host Attention Register */
1674
1675#define HA_REG_OFFSET  0        /* Byte offset from register base address */
1676
1677#define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1678#define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1679#define HA_R0ATT       0x00000008       /* Bit  3 */
1680#define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1681#define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1682#define HA_R1ATT       0x00000080       /* Bit  7 */
1683#define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1684#define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1685#define HA_R2ATT       0x00000800       /* Bit 11 */
1686#define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1687#define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1688#define HA_R3ATT       0x00008000       /* Bit 15 */
1689#define HA_LATT        0x20000000       /* Bit 29 */
1690#define HA_MBATT       0x40000000       /* Bit 30 */
1691#define HA_ERATT       0x80000000       /* Bit 31 */
1692
1693#define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1694#define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1695#define HA_RXATT       0x00000008       /* Bit  3 */
1696#define HA_RXMASK      0x0000000f
1697
1698#define HA_R0_CLR_MSK   (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1699#define HA_R1_CLR_MSK   (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1700#define HA_R2_CLR_MSK   (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1701#define HA_R3_CLR_MSK   (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1702
1703#define HA_R0_POS       3
1704#define HA_R1_POS       7
1705#define HA_R2_POS       11
1706#define HA_R3_POS       15
1707#define HA_LE_POS       29
1708#define HA_MB_POS       30
1709#define HA_ER_POS       31
1710/* Chip Attention Register */
1711
1712#define CA_REG_OFFSET  4        /* Byte offset from register base address */
1713
1714#define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1715#define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1716#define CA_R0ATT       0x00000008       /* Bit  3 */
1717#define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1718#define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1719#define CA_R1ATT       0x00000080       /* Bit  7 */
1720#define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1721#define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1722#define CA_R2ATT       0x00000800       /* Bit 11 */
1723#define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1724#define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1725#define CA_R3ATT       0x00008000       /* Bit 15 */
1726#define CA_MBATT       0x40000000       /* Bit 30 */
1727
1728/* Host Status Register */
1729
1730#define HS_REG_OFFSET  8        /* Byte offset from register base address */
1731
1732#define HS_MBRDY       0x00400000       /* Bit 22 */
1733#define HS_FFRDY       0x00800000       /* Bit 23 */
1734#define HS_FFER8       0x01000000       /* Bit 24 */
1735#define HS_FFER7       0x02000000       /* Bit 25 */
1736#define HS_FFER6       0x04000000       /* Bit 26 */
1737#define HS_FFER5       0x08000000       /* Bit 27 */
1738#define HS_FFER4       0x10000000       /* Bit 28 */
1739#define HS_FFER3       0x20000000       /* Bit 29 */
1740#define HS_FFER2       0x40000000       /* Bit 30 */
1741#define HS_FFER1       0x80000000       /* Bit 31 */
1742#define HS_CRIT_TEMP   0x00000100       /* Bit 8  */
1743#define HS_FFERM       0xFF000100       /* Mask for error bits 31:24 and 8 */
1744#define UNPLUG_ERR     0x00000001       /* Indicate pci hot unplug */
1745/* Host Control Register */
1746
1747#define HC_REG_OFFSET  12       /* Byte offset from register base address */
1748
1749#define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1750#define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1751#define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1752#define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1753#define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1754#define HC_INITHBI     0x02000000       /* Bit 25 */
1755#define HC_INITMB      0x04000000       /* Bit 26 */
1756#define HC_INITFF      0x08000000       /* Bit 27 */
1757#define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1758#define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1759
1760/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1761#define MSIX_DFLT_ID    0
1762#define MSIX_RNG0_ID    0
1763#define MSIX_RNG1_ID    1
1764#define MSIX_RNG2_ID    2
1765#define MSIX_RNG3_ID    3
1766
1767#define MSIX_LINK_ID    4
1768#define MSIX_MBOX_ID    5
1769
1770#define MSIX_SPARE0_ID  6
1771#define MSIX_SPARE1_ID  7
1772
1773/* Mailbox Commands */
1774#define MBX_SHUTDOWN        0x00        /* terminate testing */
1775#define MBX_LOAD_SM         0x01
1776#define MBX_READ_NV         0x02
1777#define MBX_WRITE_NV        0x03
1778#define MBX_RUN_BIU_DIAG    0x04
1779#define MBX_INIT_LINK       0x05
1780#define MBX_DOWN_LINK       0x06
1781#define MBX_CONFIG_LINK     0x07
1782#define MBX_CONFIG_RING     0x09
1783#define MBX_RESET_RING      0x0A
1784#define MBX_READ_CONFIG     0x0B
1785#define MBX_READ_RCONFIG    0x0C
1786#define MBX_READ_SPARM      0x0D
1787#define MBX_READ_STATUS     0x0E
1788#define MBX_READ_RPI        0x0F
1789#define MBX_READ_XRI        0x10
1790#define MBX_READ_REV        0x11
1791#define MBX_READ_LNK_STAT   0x12
1792#define MBX_REG_LOGIN       0x13
1793#define MBX_UNREG_LOGIN     0x14
1794#define MBX_CLEAR_LA        0x16
1795#define MBX_DUMP_MEMORY     0x17
1796#define MBX_DUMP_CONTEXT    0x18
1797#define MBX_RUN_DIAGS       0x19
1798#define MBX_RESTART         0x1A
1799#define MBX_UPDATE_CFG      0x1B
1800#define MBX_DOWN_LOAD       0x1C
1801#define MBX_DEL_LD_ENTRY    0x1D
1802#define MBX_RUN_PROGRAM     0x1E
1803#define MBX_SET_MASK        0x20
1804#define MBX_SET_VARIABLE    0x21
1805#define MBX_UNREG_D_ID      0x23
1806#define MBX_KILL_BOARD      0x24
1807#define MBX_CONFIG_FARP     0x25
1808#define MBX_BEACON          0x2A
1809#define MBX_CONFIG_MSI      0x30
1810#define MBX_HEARTBEAT       0x31
1811#define MBX_WRITE_VPARMS    0x32
1812#define MBX_ASYNCEVT_ENABLE 0x33
1813#define MBX_READ_EVENT_LOG_STATUS 0x37
1814#define MBX_READ_EVENT_LOG  0x38
1815#define MBX_WRITE_EVENT_LOG 0x39
1816
1817#define MBX_PORT_CAPABILITIES 0x3B
1818#define MBX_PORT_IOV_CONTROL 0x3C
1819
1820#define MBX_CONFIG_HBQ      0x7C
1821#define MBX_LOAD_AREA       0x81
1822#define MBX_RUN_BIU_DIAG64  0x84
1823#define MBX_CONFIG_PORT     0x88
1824#define MBX_READ_SPARM64    0x8D
1825#define MBX_READ_RPI64      0x8F
1826#define MBX_REG_LOGIN64     0x93
1827#define MBX_READ_TOPOLOGY   0x95
1828#define MBX_REG_VPI         0x96
1829#define MBX_UNREG_VPI       0x97
1830
1831#define MBX_WRITE_WWN       0x98
1832#define MBX_SET_DEBUG       0x99
1833#define MBX_LOAD_EXP_ROM    0x9C
1834#define MBX_SLI4_CONFIG     0x9B
1835#define MBX_SLI4_REQ_FTRS   0x9D
1836#define MBX_MAX_CMDS        0x9E
1837#define MBX_RESUME_RPI      0x9E
1838#define MBX_SLI2_CMD_MASK   0x80
1839#define MBX_REG_VFI         0x9F
1840#define MBX_REG_FCFI        0xA0
1841#define MBX_UNREG_VFI       0xA1
1842#define MBX_UNREG_FCFI      0xA2
1843#define MBX_INIT_VFI        0xA3
1844#define MBX_INIT_VPI        0xA4
1845#define MBX_ACCESS_VDATA    0xA5
1846#define MBX_REG_FCFI_MRQ    0xAF
1847
1848#define MBX_AUTH_PORT       0xF8
1849#define MBX_SECURITY_MGMT   0xF9
1850
1851/* IOCB Commands */
1852
1853#define CMD_RCV_SEQUENCE_CX     0x01
1854#define CMD_XMIT_SEQUENCE_CR    0x02
1855#define CMD_XMIT_SEQUENCE_CX    0x03
1856#define CMD_XMIT_BCAST_CN       0x04
1857#define CMD_XMIT_BCAST_CX       0x05
1858#define CMD_QUE_RING_BUF_CN     0x06
1859#define CMD_QUE_XRI_BUF_CX      0x07
1860#define CMD_IOCB_CONTINUE_CN    0x08
1861#define CMD_RET_XRI_BUF_CX      0x09
1862#define CMD_ELS_REQUEST_CR      0x0A
1863#define CMD_ELS_REQUEST_CX      0x0B
1864#define CMD_RCV_ELS_REQ_CX      0x0D
1865#define CMD_ABORT_XRI_CN        0x0E
1866#define CMD_ABORT_XRI_CX        0x0F
1867#define CMD_CLOSE_XRI_CN        0x10
1868#define CMD_CLOSE_XRI_CX        0x11
1869#define CMD_CREATE_XRI_CR       0x12
1870#define CMD_CREATE_XRI_CX       0x13
1871#define CMD_GET_RPI_CN          0x14
1872#define CMD_XMIT_ELS_RSP_CX     0x15
1873#define CMD_GET_RPI_CR          0x16
1874#define CMD_XRI_ABORTED_CX      0x17
1875#define CMD_FCP_IWRITE_CR       0x18
1876#define CMD_FCP_IWRITE_CX       0x19
1877#define CMD_FCP_IREAD_CR        0x1A
1878#define CMD_FCP_IREAD_CX        0x1B
1879#define CMD_FCP_ICMND_CR        0x1C
1880#define CMD_FCP_ICMND_CX        0x1D
1881#define CMD_FCP_TSEND_CX        0x1F
1882#define CMD_FCP_TRECEIVE_CX     0x21
1883#define CMD_FCP_TRSP_CX         0x23
1884#define CMD_FCP_AUTO_TRSP_CX    0x29
1885
1886#define CMD_ADAPTER_MSG         0x20
1887#define CMD_ADAPTER_DUMP        0x22
1888
1889/*  SLI_2 IOCB Command Set */
1890
1891#define CMD_ASYNC_STATUS        0x7C
1892#define CMD_RCV_SEQUENCE64_CX   0x81
1893#define CMD_XMIT_SEQUENCE64_CR  0x82
1894#define CMD_XMIT_SEQUENCE64_CX  0x83
1895#define CMD_XMIT_BCAST64_CN     0x84
1896#define CMD_XMIT_BCAST64_CX     0x85
1897#define CMD_QUE_RING_BUF64_CN   0x86
1898#define CMD_QUE_XRI_BUF64_CX    0x87
1899#define CMD_IOCB_CONTINUE64_CN  0x88
1900#define CMD_RET_XRI_BUF64_CX    0x89
1901#define CMD_ELS_REQUEST64_CR    0x8A
1902#define CMD_ELS_REQUEST64_CX    0x8B
1903#define CMD_ABORT_MXRI64_CN     0x8C
1904#define CMD_RCV_ELS_REQ64_CX    0x8D
1905#define CMD_XMIT_ELS_RSP64_CX   0x95
1906#define CMD_XMIT_BLS_RSP64_CX   0x97
1907#define CMD_FCP_IWRITE64_CR     0x98
1908#define CMD_FCP_IWRITE64_CX     0x99
1909#define CMD_FCP_IREAD64_CR      0x9A
1910#define CMD_FCP_IREAD64_CX      0x9B
1911#define CMD_FCP_ICMND64_CR      0x9C
1912#define CMD_FCP_ICMND64_CX      0x9D
1913#define CMD_FCP_TSEND64_CX      0x9F
1914#define CMD_FCP_TRECEIVE64_CX   0xA1
1915#define CMD_FCP_TRSP64_CX       0xA3
1916
1917#define CMD_QUE_XRI64_CX        0xB3
1918#define CMD_IOCB_RCV_SEQ64_CX   0xB5
1919#define CMD_IOCB_RCV_ELS64_CX   0xB7
1920#define CMD_IOCB_RET_XRI64_CX   0xB9
1921#define CMD_IOCB_RCV_CONT64_CX  0xBB
1922
1923#define CMD_GEN_REQUEST64_CR    0xC2
1924#define CMD_GEN_REQUEST64_CX    0xC3
1925
1926/* Unhandled SLI-3 Commands */
1927#define CMD_IOCB_XMIT_MSEQ64_CR         0xB0
1928#define CMD_IOCB_XMIT_MSEQ64_CX         0xB1
1929#define CMD_IOCB_RCV_SEQ_LIST64_CX      0xC1
1930#define CMD_IOCB_RCV_ELS_LIST64_CX      0xCD
1931#define CMD_IOCB_CLOSE_EXTENDED_CN      0xB6
1932#define CMD_IOCB_ABORT_EXTENDED_CN      0xBA
1933#define CMD_IOCB_RET_HBQE64_CN          0xCA
1934#define CMD_IOCB_FCP_IBIDIR64_CR        0xAC
1935#define CMD_IOCB_FCP_IBIDIR64_CX        0xAD
1936#define CMD_IOCB_FCP_ITASKMGT64_CX      0xAF
1937#define CMD_IOCB_LOGENTRY_CN            0x94
1938#define CMD_IOCB_LOGENTRY_ASYNC_CN      0x96
1939
1940/* Data Security SLI Commands */
1941#define DSSCMD_IWRITE64_CR              0xF8
1942#define DSSCMD_IWRITE64_CX              0xF9
1943#define DSSCMD_IREAD64_CR               0xFA
1944#define DSSCMD_IREAD64_CX               0xFB
1945
1946#define CMD_MAX_IOCB_CMD        0xFB
1947#define CMD_IOCB_MASK           0xff
1948
1949#define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
1950                                           iocb */
1951#define LPFC_MAX_ADPTMSG         32     /* max msg data */
1952/*
1953 *  Define Status
1954 */
1955#define MBX_SUCCESS                 0
1956#define MBXERR_NUM_RINGS            1
1957#define MBXERR_NUM_IOCBS            2
1958#define MBXERR_IOCBS_EXCEEDED       3
1959#define MBXERR_BAD_RING_NUMBER      4
1960#define MBXERR_MASK_ENTRIES_RANGE   5
1961#define MBXERR_MASKS_EXCEEDED       6
1962#define MBXERR_BAD_PROFILE          7
1963#define MBXERR_BAD_DEF_CLASS        8
1964#define MBXERR_BAD_MAX_RESPONDER    9
1965#define MBXERR_BAD_MAX_ORIGINATOR   10
1966#define MBXERR_RPI_REGISTERED       11
1967#define MBXERR_RPI_FULL             12
1968#define MBXERR_NO_RESOURCES         13
1969#define MBXERR_BAD_RCV_LENGTH       14
1970#define MBXERR_DMA_ERROR            15
1971#define MBXERR_ERROR                16
1972#define MBXERR_LINK_DOWN            0x33
1973#define MBXERR_SEC_NO_PERMISSION    0xF02
1974#define MBX_NOT_FINISHED            255
1975
1976#define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1977#define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1978
1979#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1980
1981/*
1982 * return code Fail
1983 */
1984#define FAILURE 1
1985
1986/*
1987 *    Begin Structure Definitions for Mailbox Commands
1988 */
1989
1990typedef struct {
1991#ifdef __BIG_ENDIAN_BITFIELD
1992        uint8_t tval;
1993        uint8_t tmask;
1994        uint8_t rval;
1995        uint8_t rmask;
1996#else   /*  __LITTLE_ENDIAN_BITFIELD */
1997        uint8_t rmask;
1998        uint8_t rval;
1999        uint8_t tmask;
2000        uint8_t tval;

2001#endif
2002} RR_REG;
2003
2004struct ulp_bde {
2005        uint32_t bdeAddress;
2006#ifdef __BIG_ENDIAN_BITFIELD
2007        uint32_t bdeReserved:4;
2008        uint32_t bdeAddrHigh:4;
2009        uint32_t bdeSize:24;
2010#else   /*  __LITTLE_ENDIAN_BITFIELD */
2011        uint32_t bdeSize:24;
2012        uint32_t bdeAddrHigh:4;
2013        uint32_t bdeReserved:4;
2014#endif
2015};
2016
2017typedef struct ULP_BDL {        /* SLI-2 */
2018#ifdef __BIG_ENDIAN_BITFIELD
2019        uint32_t bdeFlags:8;    /* BDL Flags */
2020        uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
2021#else   /*  __LITTLE_ENDIAN_BITFIELD */
2022        uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
2023        uint32_t bdeFlags:8;    /* BDL Flags */
2024#endif
2025
2026        uint32_t addrLow;       /* Address 0:31 */
2027        uint32_t addrHigh;      /* Address 32:63 */
2028        uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
2029} ULP_BDL;
2030
2031/*
2032 * BlockGuard Definitions
2033 */
2034
2035enum lpfc_protgrp_type {
2036        LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
2037        LPFC_PG_TYPE_NO_DIF,      /* no DIF data pointed to by prot grp       */
2038        LPFC_PG_TYPE_EMBD_DIF,    /* DIF is embedded (inline) with data       */
2039        LPFC_PG_TYPE_DIF_BUF      /* DIF has its own scatter/gather list      */
2040};
2041
2042/* PDE Descriptors */
2043#define LPFC_PDE5_DESCRIPTOR            0x85
2044#define LPFC_PDE6_DESCRIPTOR            0x86
2045#define LPFC_PDE7_DESCRIPTOR            0x87
2046
2047/* BlockGuard Opcodes */
2048#define BG_OP_IN_NODIF_OUT_CRC          0x0
2049#define BG_OP_IN_CRC_OUT_NODIF          0x1
2050#define BG_OP_IN_NODIF_OUT_CSUM         0x2
2051#define BG_OP_IN_CSUM_OUT_NODIF         0x3
2052#define BG_OP_IN_CRC_OUT_CRC            0x4
2053#define BG_OP_IN_CSUM_OUT_CSUM          0x5
2054#define BG_OP_IN_CRC_OUT_CSUM           0x6
2055#define BG_OP_IN_CSUM_OUT_CRC           0x7
2056#define BG_OP_RAW_MODE                  0x8
2057
2058struct lpfc_pde5 {
2059        uint32_t word0;
2060#define pde5_type_SHIFT         24
2061#define pde5_type_MASK          0x000000ff
2062#define pde5_type_WORD          word0
2063#define pde5_rsvd0_SHIFT        0
2064#define pde5_rsvd0_MASK         0x00ffffff
2065#define pde5_rsvd0_WORD         word0
2066        uint32_t reftag;        /* Reference Tag Value                  */
2067        uint32_t reftagtr;      /* Reference Tag Translation Value      */
2068};
2069
2070struct lpfc_pde6 {
2071        uint32_t word0;
2072#define pde6_type_SHIFT         24
2073#define pde6_type_MASK          0x000000ff
2074#define pde6_type_WORD          word0
2075#define pde6_rsvd0_SHIFT        0
2076#define pde6_rsvd0_MASK         0x00ffffff
2077#define pde6_rsvd0_WORD         word0
2078        uint32_t word1;
2079#define pde6_rsvd1_SHIFT        26
2080#define pde6_rsvd1_MASK         0x0000003f
2081#define pde6_rsvd1_WORD         word1
2082#define pde6_na_SHIFT           25
2083#define pde6_na_MASK            0x00000001
2084#define pde6_na_WORD            word1
2085#define pde6_rsvd2_SHIFT        16
2086#define pde6_rsvd2_MASK         0x000001FF
2087#define pde6_rsvd2_WORD         word1
2088#define pde6_apptagtr_SHIFT     0
2089#define pde6_apptagtr_MASK      0x0000ffff
2090#define pde6_apptagtr_WORD      word1
2091        uint32_t word2;
2092#define pde6_optx_SHIFT         28
2093#define pde6_optx_MASK          0x0000000f
2094#define pde6_optx_WORD          word2
2095#define pde6_oprx_SHIFT         24
2096#define pde6_oprx_MASK          0x0000000f
2097#define pde6_oprx_WORD          word2
2098#define pde6_nr_SHIFT           23
2099#define pde6_nr_MASK            0x00000001
2100#define pde6_nr_WORD            word2
2101#define pde6_ce_SHIFT           22
2102#define pde6_ce_MASK            0x00000001
2103#define pde6_ce_WORD            word2
2104#define pde6_re_SHIFT           21
2105#define pde6_re_MASK            0x00000001
2106#define pde6_re_WORD            word2
2107#define pde6_ae_SHIFT           20
2108#define pde6_ae_MASK            0x00000001
2109#define pde6_ae_WORD            word2
2110#define pde6_ai_SHIFT           19
2111#define pde6_ai_MASK            0x00000001
2112#define pde6_ai_WORD            word2
2113#define pde6_bs_SHIFT           16
2114#define pde6_bs_MASK            0x00000007
2115#define pde6_bs_WORD            word2
2116#define pde6_apptagval_SHIFT    0
2117#define pde6_apptagval_MASK     0x0000ffff
2118#define pde6_apptagval_WORD     word2
2119};
2120
2121struct lpfc_pde7 {
2122        uint32_t word0;
2123#define pde7_type_SHIFT         24
2124#define pde7_type_MASK          0x000000ff
2125#define pde7_type_WORD          word0
2126#define pde7_rsvd0_SHIFT        0
2127#define pde7_rsvd0_MASK         0x00ffffff
2128#define pde7_rsvd0_WORD         word0
2129        uint32_t addrHigh;
2130        uint32_t addrLow;
2131};
2132
2133/* Structure for MB Command LOAD_SM and DOWN_LOAD */
2134
2135typedef struct {
2136#ifdef __BIG_ENDIAN_BITFIELD
2137        uint32_t rsvd2:25;
2138        uint32_t acknowledgment:1;
2139        uint32_t version:1;
2140        uint32_t erase_or_prog:1;
2141        uint32_t update_flash:1;
2142        uint32_t update_ram:1;
2143        uint32_t method:1;
2144        uint32_t load_cmplt:1;
2145#else   /*  __LITTLE_ENDIAN_BITFIELD */
2146        uint32_t load_cmplt:1;
2147        uint32_t method:1;
2148        uint32_t update_ram:1;
2149        uint32_t update_flash:1;
2150        uint32_t erase_or_prog:1;
2151        uint32_t version:1;
2152        uint32_t acknowledgment:1;
2153        uint32_t rsvd2:25;
2154#endif
2155
2156        uint32_t dl_to_adr_low;
2157        uint32_t dl_to_adr_high;
2158        uint32_t dl_len;
2159        union {
2160                uint32_t dl_from_mbx_offset;
2161                struct ulp_bde dl_from_bde;
2162                struct ulp_bde64 dl_from_bde64;
2163        } un;
2164
2165} LOAD_SM_VAR;
2166
2167/* Structure for MB Command READ_NVPARM (02) */
2168
2169typedef struct {
2170        uint32_t rsvd1[3];      /* Read as all one's */
2171        uint32_t rsvd2;         /* Read as all zero's */
2172        uint32_t portname[2];   /* N_PORT name */
2173        uint32_t nodename[2];   /* NODE name */
2174
2175#ifdef __BIG_ENDIAN_BITFIELD
2176        uint32_t pref_DID:24;
2177        uint32_t hardAL_PA:8;
2178#else   /*  __LITTLE_ENDIAN_BITFIELD */
2179        uint32_t hardAL_PA:8;
2180        uint32_t pref_DID:24;
2181#endif
2182
2183        uint32_t rsvd3[21];     /* Read as all one's */
2184} READ_NV_VAR;
2185
2186/* Structure for MB Command WRITE_NVPARMS (03) */
2187
2188typedef struct {
2189        uint32_t rsvd1[3];      /* Must be all one's */
2190        uint32_t rsvd2;         /* Must be all zero's */
2191        uint32_t portname[2];   /* N_PORT name */
2192        uint32_t nodename[2];   /* NODE name */
2193
2194#ifdef __BIG_ENDIAN_BITFIELD
2195        uint32_t pref_DID:24;
2196        uint32_t hardAL_PA:8;
2197#else   /*  __LITTLE_ENDIAN_BITFIELD */
2198        uint32_t hardAL_PA:8;
2199        uint32_t pref_DID:24;
2200#endif
2201
2202        uint32_t rsvd3[21];     /* Must be all one's */
2203} WRITE_NV_VAR;
2204
2205/* Structure for MB Command RUN_BIU_DIAG (04) */
2206/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2207
2208typedef struct {
2209        uint32_t rsvd1;
2210        union {
2211                struct {
2212                        struct ulp_bde xmit_bde;
2213                        struct ulp_bde rcv_bde;
2214                } s1;
2215                struct {
2216                        struct ulp_bde64 xmit_bde64;
2217                        struct ulp_bde64 rcv_bde64;
2218                } s2;
2219        } un;
2220} BIU_DIAG_VAR;
2221
2222/* Structure for MB command READ_EVENT_LOG (0x38) */
2223struct READ_EVENT_LOG_VAR {
2224        uint32_t word1;
2225#define lpfc_event_log_SHIFT    29
2226#define lpfc_event_log_MASK     0x00000001
2227#define lpfc_event_log_WORD     word1
2228#define USE_MAILBOX_RESPONSE    1
2229        uint32_t offset;
2230        struct ulp_bde64 rcv_bde64;
2231};
2232
2233/* Structure for MB Command INIT_LINK (05) */
2234
2235typedef struct {
2236#ifdef __BIG_ENDIAN_BITFIELD
2237        uint32_t rsvd1:24;
2238        uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2239#else   /*  __LITTLE_ENDIAN_BITFIELD */
2240        uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2241        uint32_t rsvd1:24;
2242#endif
2243
2244#ifdef __BIG_ENDIAN_BITFIELD
2245        uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
2246        uint8_t rsvd2;
2247        uint16_t link_flags;
2248#else   /*  __LITTLE_ENDIAN_BITFIELD */
2249        uint16_t link_flags;
2250        uint8_t rsvd2;
2251        uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
2252#endif
2253
2254#define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
2255#define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
2256#define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
2257#define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
2258#define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
2259#define FLAGS_UNREG_LOGIN_ALL        0x08 /* UNREG_LOGIN all on link down */
2260#define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
2261
2262#define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
2263#define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
2264#define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
2265
2266        uint32_t link_speed;
2267#define LINK_SPEED_AUTO 0x0     /* Auto selection */
2268#define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
2269#define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
2270#define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
2271#define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
2272#define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
2273#define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
2274#define LINK_SPEED_32G  0x14    /* 32 Gigabaud */
2275#define LINK_SPEED_64G  0x17    /* 64 Gigabaud */
2276#define LINK_SPEED_128G 0x1A    /* 128 Gigabaud */
2277#define LINK_SPEED_256G 0x1D    /* 256 Gigabaud */
2278
2279} INIT_LINK_VAR;
2280
2281/* Structure for MB Command DOWN_LINK (06) */
2282
2283typedef struct {
2284        uint32_t rsvd1;
2285} DOWN_LINK_VAR;
2286
2287/* Structure for MB Command CONFIG_LINK (07) */
2288
2289typedef struct {
2290#ifdef __BIG_ENDIAN_BITFIELD
2291        uint32_t cr:1;
2292        uint32_t ci:1;
2293        uint32_t cr_delay:6;
2294        uint32_t cr_count:8;
2295        uint32_t rsvd1:8;
2296        uint32_t MaxBBC:8;
2297#else   /*  __LITTLE_ENDIAN_BITFIELD */
2298        uint32_t MaxBBC:8;
2299        uint32_t rsvd1:8;
2300        uint32_t cr_count:8;
2301        uint32_t cr_delay:6;
2302        uint32_t ci:1;
2303        uint32_t cr:1;
2304#endif
2305
2306        uint32_t myId;
2307        uint32_t rsvd2;
2308        uint32_t edtov;
2309        uint32_t arbtov;
2310        uint32_t ratov;
2311        uint32_t rttov;
2312        uint32_t altov;
2313        uint32_t crtov;
2314
2315#ifdef __BIG_ENDIAN_BITFIELD
2316        uint32_t rsvd4:19;
2317        uint32_t cscn:1;
2318        uint32_t bbscn:4;
2319        uint32_t rsvd3:8;
2320#else   /*  __LITTLE_ENDIAN_BITFIELD */
2321        uint32_t rsvd3:8;
2322        uint32_t bbscn:4;
2323        uint32_t cscn:1;
2324        uint32_t rsvd4:19;
2325#endif
2326
2327#ifdef __BIG_ENDIAN_BITFIELD
2328        uint32_t rrq_enable:1;
2329        uint32_t rrq_immed:1;
2330        uint32_t rsvd5:29;
2331        uint32_t ack0_enable:1;
2332#else   /*  __LITTLE_ENDIAN_BITFIELD */
2333        uint32_t ack0_enable:1;
2334        uint32_t rsvd5:29;
2335        uint32_t rrq_immed:1;
2336        uint32_t rrq_enable:1;
2337#endif
2338} CONFIG_LINK;
2339
2340/* Structure for MB Command PART_SLIM (08)
2341 * will be removed since SLI1 is no longer supported!
2342 */
2343typedef struct {
2344#ifdef __BIG_ENDIAN_BITFIELD
2345        uint16_t offCiocb;
2346        uint16_t numCiocb;
2347        uint16_t offRiocb;
2348        uint16_t numRiocb;
2349#else   /*  __LITTLE_ENDIAN_BITFIELD */
2350        uint16_t numCiocb;
2351        uint16_t offCiocb;
2352        uint16_t numRiocb;
2353        uint16_t offRiocb;
2354#endif
2355} RING_DEF;
2356
2357typedef struct {
2358#ifdef __BIG_ENDIAN_BITFIELD
2359        uint32_t unused1:24;
2360        uint32_t numRing:8;
2361#else   /*  __LITTLE_ENDIAN_BITFIELD */
2362        uint32_t numRing:8;
2363        uint32_t unused1:24;
2364#endif
2365
2366        RING_DEF ringdef[4];
2367        uint32_t hbainit;
2368} PART_SLIM_VAR;
2369
2370/* Structure for MB Command CONFIG_RING (09) */
2371
2372typedef struct {
2373#ifdef __BIG_ENDIAN_BITFIELD
2374        uint32_t unused2:6;
2375        uint32_t recvSeq:1;
2376        uint32_t recvNotify:1;
2377        uint32_t numMask:8;
2378        uint32_t profile:8;
2379        uint32_t unused1:4;
2380        uint32_t ring:4;
2381#else   /*  __LITTLE_ENDIAN_BITFIELD */
2382        uint32_t ring:4;
2383        uint32_t unused1:4;
2384        uint32_t profile:8;
2385        uint32_t numMask:8;
2386        uint32_t recvNotify:1;
2387        uint32_t recvSeq:1;
2388        uint32_t unused2:6;
2389#endif
2390
2391#ifdef __BIG_ENDIAN_BITFIELD
2392        uint16_t maxRespXchg;
2393        uint16_t maxOrigXchg;
2394#else   /*  __LITTLE_ENDIAN_BITFIELD */
2395        uint16_t maxOrigXchg;
2396        uint16_t maxRespXchg;
2397#endif
2398
2399        RR_REG rrRegs[6];
2400} CONFIG_RING_VAR;
2401
2402/* Structure for MB Command RESET_RING (10) */
2403
2404typedef struct {
2405        uint32_t ring_no;
2406} RESET_RING_VAR;
2407
2408/* Structure for MB Command READ_CONFIG (11) */
2409
2410typedef struct {
2411#ifdef __BIG_ENDIAN_BITFIELD
2412        uint32_t cr:1;
2413        uint32_t ci:1;
2414        uint32_t cr_delay:6;
2415        uint32_t cr_count:8;
2416        uint32_t InitBBC:8;
2417        uint32_t MaxBBC:8;
2418#else   /*  __LITTLE_ENDIAN_BITFIELD */
2419        uint32_t MaxBBC:8;
2420        uint32_t InitBBC:8;
2421        uint32_t cr_count:8;
2422        uint32_t cr_delay:6;
2423        uint32_t ci:1;
2424        uint32_t cr:1;
2425#endif
2426
2427#ifdef __BIG_ENDIAN_BITFIELD
2428        uint32_t topology:8;
2429        uint32_t myDid:24;
2430#else   /*  __LITTLE_ENDIAN_BITFIELD */
2431        uint32_t myDid:24;
2432        uint32_t topology:8;
2433#endif
2434
2435        /* Defines for topology (defined previously) */
2436#ifdef __BIG_ENDIAN_BITFIELD
2437        uint32_t AR:1;
2438        uint32_t IR:1;
2439        uint32_t rsvd1:29;
2440        uint32_t ack0:1;
2441#else   /*  __LITTLE_ENDIAN_BITFIELD */
2442        uint32_t ack0:1;
2443        uint32_t rsvd1:29;
2444        uint32_t IR:1;
2445        uint32_t AR:1;
2446#endif
2447
2448        uint32_t edtov;
2449        uint32_t arbtov;
2450        uint32_t ratov;
2451        uint32_t rttov;
2452        uint32_t altov;
2453        uint32_t lmt;
2454#define LMT_RESERVED  0x000    /* Not used */
2455#define LMT_1Gb       0x004
2456#define LMT_2Gb       0x008
2457#define LMT_4Gb       0x040
2458#define LMT_8Gb       0x080
2459#define LMT_10Gb      0x100
2460#define LMT_16Gb      0x200
2461#define LMT_32Gb      0x400
2462#define LMT_64Gb      0x800
2463#define LMT_128Gb     0x1000
2464#define LMT_256Gb     0x2000
2465        uint32_t rsvd2;
2466        uint32_t rsvd3;
2467        uint32_t max_xri;
2468        uint32_t max_iocb;
2469        uint32_t max_rpi;
2470        uint32_t avail_xri;
2471        uint32_t avail_iocb;
2472        uint32_t avail_rpi;
2473        uint32_t max_vpi;
2474        uint32_t rsvd4;
2475        uint32_t rsvd5;
2476        uint32_t avail_vpi;
2477} READ_CONFIG_VAR;
2478
2479/* Structure for MB Command READ_RCONFIG (12) */
2480
2481typedef struct {
2482#ifdef __BIG_ENDIAN_BITFIELD
2483        uint32_t rsvd2:7;
2484        uint32_t recvNotify:1;
2485        uint32_t numMask:8;
2486        uint32_t profile:8;
2487        uint32_t rsvd1:4;
2488        uint32_t ring:4;
2489#else   /*  __LITTLE_ENDIAN_BITFIELD */
2490        uint32_t ring:4;
2491        uint32_t rsvd1:4;
2492        uint32_t profile:8;
2493        uint32_t numMask:8;
2494        uint32_t recvNotify:1;
2495        uint32_t rsvd2:7;
2496#endif
2497
2498#ifdef __BIG_ENDIAN_BITFIELD
2499        uint16_t maxResp;
2500        uint16_t maxOrig;
2501#else   /*  __LITTLE_ENDIAN_BITFIELD */
2502        uint16_t maxOrig;
2503        uint16_t maxResp;
2504#endif
2505
2506        RR_REG rrRegs[6];
2507
2508#ifdef __BIG_ENDIAN_BITFIELD
2509        uint16_t cmdRingOffset;
2510        uint16_t cmdEntryCnt;
2511        uint16_t rspRingOffset;
2512        uint16_t rspEntryCnt;
2513        uint16_t nextCmdOffset;
2514        uint16_t rsvd3;
2515        uint16_t nextRspOffset;
2516        uint16_t rsvd4;
2517#else   /*  __LITTLE_ENDIAN_BITFIELD */
2518        uint16_t cmdEntryCnt;
2519        uint16_t cmdRingOffset;
2520        uint16_t rspEntryCnt;
2521        uint16_t rspRingOffset;
2522        uint16_t rsvd3;
2523        uint16_t nextCmdOffset;
2524        uint16_t rsvd4;
2525        uint16_t nextRspOffset;
2526#endif
2527} READ_RCONF_VAR;
2528
2529/* Structure for MB Command READ_SPARM (13) */
2530/* Structure for MB Command READ_SPARM64 (0x8D) */
2531
2532typedef struct {
2533        uint32_t rsvd1;
2534        uint32_t rsvd2;
2535        union {
2536                struct ulp_bde sp; /* This BDE points to struct serv_parm
2537                                      structure */
2538                struct ulp_bde64 sp64;
2539        } un;
2540#ifdef __BIG_ENDIAN_BITFIELD
2541        uint16_t rsvd3;
2542        uint16_t vpi;
2543#else   /*  __LITTLE_ENDIAN_BITFIELD */
2544        uint16_t vpi;
2545        uint16_t rsvd3;
2546#endif
2547} READ_SPARM_VAR;
2548
2549/* Structure for MB Command READ_STATUS (14) */
2550
2551typedef struct {
2552#ifdef __BIG_ENDIAN_BITFIELD
2553        uint32_t rsvd1:31;
2554        uint32_t clrCounters:1;
2555        uint16_t activeXriCnt;
2556        uint16_t activeRpiCnt;
2557#else   /*  __LITTLE_ENDIAN_BITFIELD */
2558        uint32_t clrCounters:1;
2559        uint32_t rsvd1:31;
2560        uint16_t activeRpiCnt;
2561        uint16_t activeXriCnt;
2562#endif
2563
2564        uint32_t xmitByteCnt;
2565        uint32_t rcvByteCnt;
2566        uint32_t xmitFrameCnt;
2567        uint32_t rcvFrameCnt;
2568        uint32_t xmitSeqCnt;
2569        uint32_t rcvSeqCnt;
2570        uint32_t totalOrigExchanges;
2571        uint32_t totalRespExchanges;
2572        uint32_t rcvPbsyCnt;
2573        uint32_t rcvFbsyCnt;
2574} READ_STATUS_VAR;
2575
2576/* Structure for MB Command READ_RPI (15) */
2577/* Structure for MB Command READ_RPI64 (0x8F) */
2578
2579typedef struct {
2580#ifdef __BIG_ENDIAN_BITFIELD
2581        uint16_t nextRpi;
2582        uint16_t reqRpi;
2583        uint32_t rsvd2:8;
2584        uint32_t DID:24;
2585#else   /*  __LITTLE_ENDIAN_BITFIELD */
2586        uint16_t reqRpi;
2587        uint16_t nextRpi;
2588        uint32_t DID:24;
2589        uint32_t rsvd2:8;
2590#endif
2591
2592        union {
2593                struct ulp_bde sp;
2594                struct ulp_bde64 sp64;
2595        } un;
2596
2597} READ_RPI_VAR;
2598
2599/* Structure for MB Command READ_XRI (16) */
2600
2601typedef struct {
2602#ifdef __BIG_ENDIAN_BITFIELD
2603        uint16_t nextXri;
2604        uint16_t reqXri;
2605        uint16_t rsvd1;
2606        uint16_t rpi;
2607        uint32_t rsvd2:8;
2608        uint32_t DID:24;
2609        uint32_t rsvd3:8;
2610        uint32_t SID:24;
2611        uint32_t rsvd4;
2612        uint8_t seqId;
2613        uint8_t rsvd5;
2614        uint16_t seqCount;
2615        uint16_t oxId;
2616        uint16_t rxId;
2617        uint32_t rsvd6:30;
2618        uint32_t si:1;
2619        uint32_t exchOrig:1;
2620#else   /*  __LITTLE_ENDIAN_BITFIELD */
2621        uint16_t reqXri;
2622        uint16_t nextXri;
2623        uint16_t rpi;
2624        uint16_t rsvd1;
2625        uint32_t DID:24;
2626        uint32_t rsvd2:8;
2627        uint32_t SID:24;
2628        uint32_t rsvd3:8;
2629        uint32_t rsvd4;
2630        uint16_t seqCount;
2631        uint8_t rsvd5;
2632        uint8_t seqId;
2633        uint16_t rxId;
2634        uint16_t oxId;
2635        uint32_t exchOrig:1;
2636        uint32_t si:1;
2637        uint32_t rsvd6:30;
2638#endif
2639} READ_XRI_VAR;
2640
2641/* Structure for MB Command READ_REV (17) */
2642
2643typedef struct {
2644#ifdef __BIG_ENDIAN_BITFIELD
2645        uint32_t cv:1;
2646        uint32_t rr:1;
2647        uint32_t rsvd2:2;
2648        uint32_t v3req:1;
2649        uint32_t v3rsp:1;
2650        uint32_t rsvd1:25;
2651        uint32_t rv:1;
2652#else   /*  __LITTLE_ENDIAN_BITFIELD */
2653        uint32_t rv:1;
2654        uint32_t rsvd1:25;
2655        uint32_t v3rsp:1;
2656        uint32_t v3req:1;
2657        uint32_t rsvd2:2;
2658        uint32_t rr:1;
2659        uint32_t cv:1;
2660#endif
2661
2662        uint32_t biuRev;
2663        uint32_t smRev;
2664        union {
2665                uint32_t smFwRev;
2666                struct {
2667#ifdef __BIG_ENDIAN_BITFIELD
2668                        uint8_t ProgType;
2669                        uint8_t ProgId;
2670                        uint16_t ProgVer:4;
2671                        uint16_t ProgRev:4;
2672                        uint16_t ProgFixLvl:2;
2673                        uint16_t ProgDistType:2;
2674                        uint16_t DistCnt:4;
2675#else   /*  __LITTLE_ENDIAN_BITFIELD */
2676                        uint16_t DistCnt:4;
2677                        uint16_t ProgDistType:2;
2678                        uint16_t ProgFixLvl:2;
2679                        uint16_t ProgRev:4;
2680                        uint16_t ProgVer:4;
2681                        uint8_t ProgId;
2682                        uint8_t ProgType;
2683#endif
2684
2685                } b;
2686        } un;
2687        uint32_t endecRev;
2688#ifdef __BIG_ENDIAN_BITFIELD
2689        uint8_t feaLevelHigh;
2690        uint8_t feaLevelLow;
2691        uint8_t fcphHigh;
2692        uint8_t fcphLow;
2693#else   /*  __LITTLE_ENDIAN_BITFIELD */
2694        uint8_t fcphLow;
2695        uint8_t fcphHigh;
2696        uint8_t feaLevelLow;
2697        uint8_t feaLevelHigh;
2698#endif
2699
2700        uint32_t postKernRev;
2701        uint32_t opFwRev;
2702        uint8_t opFwName[16];
2703        uint32_t sli1FwRev;
2704        uint8_t sli1FwName[16];
2705        uint32_t sli2FwRev;
2706        uint8_t sli2FwName[16];
2707        uint32_t sli3Feat;
2708        uint32_t RandomData[6];
2709} READ_REV_VAR;
2710
2711/* Structure for MB Command READ_LINK_STAT (18) */
2712
2713typedef struct {
2714        uint32_t word0;
2715
2716#define lpfc_read_link_stat_rec_SHIFT   0
2717#define lpfc_read_link_stat_rec_MASK   0x1
2718#define lpfc_read_link_stat_rec_WORD   word0
2719
2720#define lpfc_read_link_stat_gec_SHIFT   1
2721#define lpfc_read_link_stat_gec_MASK   0x1
2722#define lpfc_read_link_stat_gec_WORD   word0
2723
2724#define lpfc_read_link_stat_w02oftow23of_SHIFT  2
2725#define lpfc_read_link_stat_w02oftow23of_MASK   0x3FFFFF
2726#define lpfc_read_link_stat_w02oftow23of_WORD   word0
2727
2728#define lpfc_read_link_stat_rsvd_SHIFT  24
2729#define lpfc_read_link_stat_rsvd_MASK   0x1F
2730#define lpfc_read_link_stat_rsvd_WORD   word0
2731
2732#define lpfc_read_link_stat_gec2_SHIFT  29
2733#define lpfc_read_link_stat_gec2_MASK   0x1
2734#define lpfc_read_link_stat_gec2_WORD   word0
2735
2736#define lpfc_read_link_stat_clrc_SHIFT  30
2737#define lpfc_read_link_stat_clrc_MASK   0x1
2738#define lpfc_read_link_stat_clrc_WORD   word0
2739
2740#define lpfc_read_link_stat_clof_SHIFT  31
2741#define lpfc_read_link_stat_clof_MASK   0x1
2742#define lpfc_read_link_stat_clof_WORD   word0
2743
2744        uint32_t linkFailureCnt;
2745        uint32_t lossSyncCnt;
2746        uint32_t lossSignalCnt;
2747        uint32_t primSeqErrCnt;
2748        uint32_t invalidXmitWord;
2749        uint32_t crcCnt;
2750        uint32_t primSeqTimeout;
2751        uint32_t elasticOverrun;
2752        uint32_t arbTimeout;
2753        uint32_t advRecBufCredit;
2754        uint32_t curRecBufCredit;
2755        uint32_t advTransBufCredit;
2756        uint32_t curTransBufCredit;
2757        uint32_t recEofCount;
2758        uint32_t recEofdtiCount;
2759        uint32_t recEofniCount;
2760        uint32_t recSofcount;
2761        uint32_t rsvd1;
2762        uint32_t rsvd2;
2763        uint32_t recDrpXriCount;
2764        uint32_t fecCorrBlkCount;
2765        uint32_t fecUncorrBlkCount;
2766} READ_LNK_VAR;
2767
2768/* Structure for MB Command REG_LOGIN (19) */
2769/* Structure for MB Command REG_LOGIN64 (0x93) */
2770
2771typedef struct {
2772#ifdef __BIG_ENDIAN_BITFIELD
2773        uint16_t rsvd1;
2774        uint16_t rpi;
2775        uint32_t rsvd2:8;
2776        uint32_t did:24;
2777#else   /*  __LITTLE_ENDIAN_BITFIELD */
2778        uint16_t rpi;
2779        uint16_t rsvd1;
2780        uint32_t did:24;
2781        uint32_t rsvd2:8;
2782#endif
2783
2784        union {
2785                struct ulp_bde sp;
2786                struct ulp_bde64 sp64;
2787        } un;
2788
2789#ifdef __BIG_ENDIAN_BITFIELD
2790        uint16_t rsvd6;
2791        uint16_t vpi;
2792#else /* __LITTLE_ENDIAN_BITFIELD */
2793        uint16_t vpi;
2794        uint16_t rsvd6;
2795#endif
2796
2797} REG_LOGIN_VAR;
2798
2799/* Word 30 contents for REG_LOGIN */
2800typedef union {
2801        struct {
2802#ifdef __BIG_ENDIAN_BITFIELD
2803                uint16_t rsvd1:12;
2804                uint16_t wd30_class:4;
2805                uint16_t xri;
2806#else   /*  __LITTLE_ENDIAN_BITFIELD */
2807                uint16_t xri;
2808                uint16_t wd30_class:4;
2809                uint16_t rsvd1:12;
2810#endif
2811        } f;
2812        uint32_t word;
2813} REG_WD30;
2814
2815/* Structure for MB Command UNREG_LOGIN (20) */
2816
2817typedef struct {
2818#ifdef __BIG_ENDIAN_BITFIELD
2819        uint16_t rsvd1;
2820        uint16_t rpi;
2821        uint32_t rsvd2;
2822        uint32_t rsvd3;
2823        uint32_t rsvd4;
2824        uint32_t rsvd5;
2825        uint16_t rsvd6;
2826        uint16_t vpi;
2827#else   /*  __LITTLE_ENDIAN_BITFIELD */
2828        uint16_t rpi;
2829        uint16_t rsvd1;
2830        uint32_t rsvd2;
2831        uint32_t rsvd3;
2832        uint32_t rsvd4;
2833        uint32_t rsvd5;
2834        uint16_t vpi;
2835        uint16_t rsvd6;
2836#endif
2837} UNREG_LOGIN_VAR;
2838
2839/* Structure for MB Command REG_VPI (0x96) */
2840typedef struct {
2841#ifdef __BIG_ENDIAN_BITFIELD
2842        uint32_t rsvd1;
2843        uint32_t rsvd2:7;
2844        uint32_t upd:1;
2845        uint32_t sid:24;
2846        uint32_t wwn[2];
2847        uint32_t rsvd5;
2848        uint16_t vfi;
2849        uint16_t vpi;
2850#else   /*  __LITTLE_ENDIAN */
2851        uint32_t rsvd1;
2852        uint32_t sid:24;
2853        uint32_t upd:1;
2854        uint32_t rsvd2:7;
2855        uint32_t wwn[2];
2856        uint32_t rsvd5;
2857        uint16_t vpi;
2858        uint16_t vfi;
2859#endif
2860} REG_VPI_VAR;
2861
2862/* Structure for MB Command UNREG_VPI (0x97) */
2863typedef struct {
2864        uint32_t rsvd1;
2865#ifdef __BIG_ENDIAN_BITFIELD
2866        uint16_t rsvd2;
2867        uint16_t sli4_vpi;
2868#else   /*  __LITTLE_ENDIAN */
2869        uint16_t sli4_vpi;
2870        uint16_t rsvd2;
2871#endif
2872        uint32_t rsvd3;
2873        uint32_t rsvd4;
2874        uint32_t rsvd5;
2875#ifdef __BIG_ENDIAN_BITFIELD
2876        uint16_t rsvd6;
2877        uint16_t vpi;
2878#else   /*  __LITTLE_ENDIAN */
2879        uint16_t vpi;
2880        uint16_t rsvd6;
2881#endif
2882} UNREG_VPI_VAR;
2883
2884/* Structure for MB Command UNREG_D_ID (0x23) */
2885
2886typedef struct {
2887        uint32_t did;
2888        uint32_t rsvd2;
2889        uint32_t rsvd3;
2890        uint32_t rsvd4;
2891        uint32_t rsvd5;
2892#ifdef __BIG_ENDIAN_BITFIELD
2893        uint16_t rsvd6;
2894        uint16_t vpi;
2895#else
2896        uint16_t vpi;
2897        uint16_t rsvd6;
2898#endif
2899} UNREG_D_ID_VAR;
2900
2901/* Structure for MB Command READ_TOPOLOGY (0x95) */
2902struct lpfc_mbx_read_top {
2903        uint32_t eventTag;      /* Event tag */
2904        uint32_t word2;
2905#define lpfc_mbx_read_top_fa_SHIFT              12
2906#define lpfc_mbx_read_top_fa_MASK               0x00000001
2907#define lpfc_mbx_read_top_fa_WORD               word2
2908#define lpfc_mbx_read_top_mm_SHIFT              11
2909#define lpfc_mbx_read_top_mm_MASK               0x00000001
2910#define lpfc_mbx_read_top_mm_WORD               word2
2911#define lpfc_mbx_read_top_pb_SHIFT              9
2912#define lpfc_mbx_read_top_pb_MASK               0X00000001
2913#define lpfc_mbx_read_top_pb_WORD               word2
2914#define lpfc_mbx_read_top_il_SHIFT              8
2915#define lpfc_mbx_read_top_il_MASK               0x00000001
2916#define lpfc_mbx_read_top_il_WORD               word2
2917#define lpfc_mbx_read_top_att_type_SHIFT        0
2918#define lpfc_mbx_read_top_att_type_MASK         0x000000FF
2919#define lpfc_mbx_read_top_att_type_WORD         word2
2920#define LPFC_ATT_RESERVED    0x00       /* Reserved - attType */
2921#define LPFC_ATT_LINK_UP     0x01       /* Link is up */
2922#define LPFC_ATT_LINK_DOWN   0x02       /* Link is down */
2923#define LPFC_ATT_UNEXP_WWPN  0x06       /* Link is down Unexpected WWWPN */
2924        uint32_t word3;
2925#define lpfc_mbx_read_top_alpa_granted_SHIFT    24
2926#define lpfc_mbx_read_top_alpa_granted_MASK     0x000000FF
2927#define lpfc_mbx_read_top_alpa_granted_WORD     word3
2928#define lpfc_mbx_read_top_lip_alps_SHIFT        16
2929#define lpfc_mbx_read_top_lip_alps_MASK         0x000000FF
2930#define lpfc_mbx_read_top_lip_alps_WORD         word3
2931#define lpfc_mbx_read_top_lip_type_SHIFT        8
2932#define lpfc_mbx_read_top_lip_type_MASK         0x000000FF
2933#define lpfc_mbx_read_top_lip_type_WORD         word3
2934#define lpfc_mbx_read_top_topology_SHIFT        0
2935#define lpfc_mbx_read_top_topology_MASK         0x000000FF
2936#define lpfc_mbx_read_top_topology_WORD         word3
2937#define LPFC_TOPOLOGY_PT_PT 0x01        /* Topology is pt-pt / pt-fabric */
2938#define LPFC_TOPOLOGY_LOOP  0x02        /* Topology is FC-AL */
2939#define LPFC_TOPOLOGY_MM    0x05        /* maint mode zephtr to menlo */
2940        /* store the LILP AL_PA position map into */
2941        struct ulp_bde64 lilpBde64;
2942#define LPFC_ALPA_MAP_SIZE      128
2943        uint32_t word7;
2944#define lpfc_mbx_read_top_ld_lu_SHIFT           31
2945#define lpfc_mbx_read_top_ld_lu_MASK            0x00000001
2946#define lpfc_mbx_read_top_ld_lu_WORD            word7
2947#define lpfc_mbx_read_top_ld_tf_SHIFT           30
2948#define lpfc_mbx_read_top_ld_tf_MASK            0x00000001
2949#define lpfc_mbx_read_top_ld_tf_WORD            word7
2950#define lpfc_mbx_read_top_ld_link_spd_SHIFT     8
2951#define lpfc_mbx_read_top_ld_link_spd_MASK      0x000000FF
2952#define lpfc_mbx_read_top_ld_link_spd_WORD      word7
2953#define lpfc_mbx_read_top_ld_nl_port_SHIFT      4
2954#define lpfc_mbx_read_top_ld_nl_port_MASK       0x0000000F
2955#define lpfc_mbx_read_top_ld_nl_port_WORD       word7
2956#define lpfc_mbx_read_top_ld_tx_SHIFT           2
2957#define lpfc_mbx_read_top_ld_tx_MASK            0x00000003
2958#define lpfc_mbx_read_top_ld_tx_WORD            word7
2959#define lpfc_mbx_read_top_ld_rx_SHIFT           0
2960#define lpfc_mbx_read_top_ld_rx_MASK            0x00000003
2961#define lpfc_mbx_read_top_ld_rx_WORD            word7
2962        uint32_t word8;
2963#define lpfc_mbx_read_top_lu_SHIFT              31
2964#define lpfc_mbx_read_top_lu_MASK               0x00000001
2965#define lpfc_mbx_read_top_lu_WORD               word8
2966#define lpfc_mbx_read_top_tf_SHIFT              30
2967#define lpfc_mbx_read_top_tf_MASK               0x00000001
2968#define lpfc_mbx_read_top_tf_WORD               word8
2969#define lpfc_mbx_read_top_link_spd_SHIFT        8
2970#define lpfc_mbx_read_top_link_spd_MASK         0x000000FF
2971#define lpfc_mbx_read_top_link_spd_WORD         word8
2972#define lpfc_mbx_read_top_nl_port_SHIFT         4
2973#define lpfc_mbx_read_top_nl_port_MASK          0x0000000F
2974#define lpfc_mbx_read_top_nl_port_WORD          word8
2975#define lpfc_mbx_read_top_tx_SHIFT              2
2976#define lpfc_mbx_read_top_tx_MASK               0x00000003
2977#define lpfc_mbx_read_top_tx_WORD               word8
2978#define lpfc_mbx_read_top_rx_SHIFT              0
2979#define lpfc_mbx_read_top_rx_MASK               0x00000003
2980#define lpfc_mbx_read_top_rx_WORD               word8
2981#define LPFC_LINK_SPEED_UNKNOWN 0x0
2982#define LPFC_LINK_SPEED_1GHZ    0x04
2983#define LPFC_LINK_SPEED_2GHZ    0x08
2984#define LPFC_LINK_SPEED_4GHZ    0x10
2985#define LPFC_LINK_SPEED_8GHZ    0x20
2986#define LPFC_LINK_SPEED_10GHZ   0x40
2987#define LPFC_LINK_SPEED_16GHZ   0x80
2988#define LPFC_LINK_SPEED_32GHZ   0x90
2989#define LPFC_LINK_SPEED_64GHZ   0xA0
2990#define LPFC_LINK_SPEED_128GHZ  0xB0
2991#define LPFC_LINK_SPEED_256GHZ  0xC0
2992};
2993
2994/* Structure for MB Command CLEAR_LA (22) */
2995
2996typedef struct {
2997        uint32_t eventTag;      /* Event tag */
2998        uint32_t rsvd1;
2999} CLEAR_LA_VAR;
3000

3001/* Structure for MB Command DUMP */
3002
3003typedef struct {
3004#ifdef __BIG_ENDIAN_BITFIELD
3005        uint32_t rsvd:25;
3006        uint32_t ra:1;
3007        uint32_t co:1;
3008        uint32_t cv:1;
3009        uint32_t type:4;
3010        uint32_t entry_index:16;
3011        uint32_t region_id:16;
3012#else   /*  __LITTLE_ENDIAN_BITFIELD */
3013        uint32_t type:4;
3014        uint32_t cv:1;
3015        uint32_t co:1;
3016        uint32_t ra:1;
3017        uint32_t rsvd:25;
3018        uint32_t region_id:16;
3019        uint32_t entry_index:16;
3020#endif
3021
3022        uint32_t sli4_length;
3023        uint32_t word_cnt;
3024        uint32_t resp_offset;
3025} DUMP_VAR;
3026
3027#define  DMP_MEM_REG             0x1
3028#define  DMP_NV_PARAMS           0x2
3029#define  DMP_LMSD                0x3 /* Link Module Serial Data */
3030#define  DMP_WELL_KNOWN          0x4
3031
3032#define  DMP_REGION_VPD          0xe
3033#define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
3034#define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
3035#define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
3036
3037#define  DMP_REGION_VPORT        0x16   /* VPort info region */
3038#define  DMP_VPORT_REGION_SIZE   0x200
3039#define  DMP_MBOX_OFFSET_WORD    0x5
3040
3041#define  DMP_REGION_23           0x17   /* fcoe param  and port state region */
3042#define  DMP_RGN23_SIZE          0x400
3043
3044#define  WAKE_UP_PARMS_REGION_ID    4
3045#define  WAKE_UP_PARMS_WORD_SIZE   15
3046
3047struct vport_rec {
3048        uint8_t wwpn[8];
3049        uint8_t wwnn[8];
3050};
3051
3052#define VPORT_INFO_SIG 0x32324752
3053#define VPORT_INFO_REV_MASK 0xff
3054#define VPORT_INFO_REV 0x1
3055#define MAX_STATIC_VPORT_COUNT 16
3056struct static_vport_info {
3057        uint32_t                signature;
3058        uint32_t                rev;
3059        struct vport_rec        vport_list[MAX_STATIC_VPORT_COUNT];
3060        uint32_t                resvd[66];
3061};
3062
3063/* Option rom version structure */
3064struct prog_id {
3065#ifdef __BIG_ENDIAN_BITFIELD
3066        uint8_t  type;
3067        uint8_t  id;
3068        uint32_t ver:4;  /* Major Version */
3069        uint32_t rev:4;  /* Revision */
3070        uint32_t lev:2;  /* Level */
3071        uint32_t dist:2; /* Dist Type */
3072        uint32_t num:4;  /* number after dist type */
3073#else /*  __LITTLE_ENDIAN_BITFIELD */
3074        uint32_t num:4;  /* number after dist type */
3075        uint32_t dist:2; /* Dist Type */
3076        uint32_t lev:2;  /* Level */
3077        uint32_t rev:4;  /* Revision */
3078        uint32_t ver:4;  /* Major Version */
3079        uint8_t  id;
3080        uint8_t  type;
3081#endif
3082};
3083
3084/* Structure for MB Command UPDATE_CFG (0x1B) */
3085
3086struct update_cfg_var {
3087#ifdef __BIG_ENDIAN_BITFIELD
3088        uint32_t rsvd2:16;
3089        uint32_t type:8;
3090        uint32_t rsvd:1;
3091        uint32_t ra:1;
3092        uint32_t co:1;
3093        uint32_t cv:1;
3094        uint32_t req:4;
3095        uint32_t entry_length:16;
3096        uint32_t region_id:16;
3097#else  /*  __LITTLE_ENDIAN_BITFIELD */
3098        uint32_t req:4;
3099        uint32_t cv:1;
3100        uint32_t co:1;
3101        uint32_t ra:1;
3102        uint32_t rsvd:1;
3103        uint32_t type:8;
3104        uint32_t rsvd2:16;
3105        uint32_t region_id:16;
3106        uint32_t entry_length:16;
3107#endif
3108
3109        uint32_t resp_info;
3110        uint32_t byte_cnt;
3111        uint32_t data_offset;
3112};
3113
3114struct hbq_mask {
3115#ifdef __BIG_ENDIAN_BITFIELD
3116        uint8_t tmatch;
3117        uint8_t tmask;
3118        uint8_t rctlmatch;
3119        uint8_t rctlmask;
3120#else   /*  __LITTLE_ENDIAN */
3121        uint8_t rctlmask;
3122        uint8_t rctlmatch;
3123        uint8_t tmask;
3124        uint8_t tmatch;
3125#endif
3126};
3127
3128
3129/* Structure for MB Command CONFIG_HBQ (7c) */
3130
3131struct config_hbq_var {
3132#ifdef __BIG_ENDIAN_BITFIELD
3133        uint32_t rsvd1      :7;
3134        uint32_t recvNotify :1;     /* Receive Notification */
3135        uint32_t numMask    :8;     /* # Mask Entries       */
3136        uint32_t profile    :8;     /* Selection Profile    */
3137        uint32_t rsvd2      :8;
3138#else   /*  __LITTLE_ENDIAN */
3139        uint32_t rsvd2      :8;
3140        uint32_t profile    :8;     /* Selection Profile    */
3141        uint32_t numMask    :8;     /* # Mask Entries       */
3142        uint32_t recvNotify :1;     /* Receive Notification */
3143        uint32_t rsvd1      :7;
3144#endif
3145
3146#ifdef __BIG_ENDIAN_BITFIELD
3147        uint32_t hbqId      :16;
3148        uint32_t rsvd3      :12;
3149        uint32_t ringMask   :4;
3150#else   /*  __LITTLE_ENDIAN */
3151        uint32_t ringMask   :4;
3152        uint32_t rsvd3      :12;
3153        uint32_t hbqId      :16;
3154#endif
3155
3156#ifdef __BIG_ENDIAN_BITFIELD
3157        uint32_t entry_count :16;
3158        uint32_t rsvd4        :8;
3159        uint32_t headerLen    :8;
3160#else   /*  __LITTLE_ENDIAN */
3161        uint32_t headerLen    :8;
3162        uint32_t rsvd4        :8;
3163        uint32_t entry_count :16;
3164#endif
3165
3166        uint32_t hbqaddrLow;
3167        uint32_t hbqaddrHigh;
3168
3169#ifdef __BIG_ENDIAN_BITFIELD
3170        uint32_t rsvd5      :31;
3171        uint32_t logEntry   :1;
3172#else   /*  __LITTLE_ENDIAN */
3173        uint32_t logEntry   :1;
3174        uint32_t rsvd5      :31;
3175#endif
3176
3177        uint32_t rsvd6;    /* w7 */
3178        uint32_t rsvd7;    /* w8 */
3179        uint32_t rsvd8;    /* w9 */
3180
3181        struct hbq_mask hbqMasks[6];
3182
3183
3184        union {
3185                uint32_t allprofiles[12];
3186
3187                struct {
3188                        #ifdef __BIG_ENDIAN_BITFIELD
3189                                uint32_t        seqlenoff       :16;
3190                                uint32_t        maxlen          :16;
3191                        #else   /*  __LITTLE_ENDIAN */
3192                                uint32_t        maxlen          :16;
3193                                uint32_t        seqlenoff       :16;
3194                        #endif
3195                        #ifdef __BIG_ENDIAN_BITFIELD
3196                                uint32_t        rsvd1           :28;
3197                                uint32_t        seqlenbcnt      :4;
3198                        #else   /*  __LITTLE_ENDIAN */
3199                                uint32_t        seqlenbcnt      :4;
3200                                uint32_t        rsvd1           :28;
3201                        #endif
3202                        uint32_t rsvd[10];
3203                } profile2;
3204
3205                struct {
3206                        #ifdef __BIG_ENDIAN_BITFIELD
3207                                uint32_t        seqlenoff       :16;
3208                                uint32_t        maxlen          :16;
3209                        #else   /*  __LITTLE_ENDIAN */
3210                                uint32_t        maxlen          :16;
3211                                uint32_t        seqlenoff       :16;
3212                        #endif
3213                        #ifdef __BIG_ENDIAN_BITFIELD
3214                                uint32_t        cmdcodeoff      :28;
3215                                uint32_t        rsvd1           :12;
3216                                uint32_t        seqlenbcnt      :4;
3217                        #else   /*  __LITTLE_ENDIAN */
3218                                uint32_t        seqlenbcnt      :4;
3219                                uint32_t        rsvd1           :12;
3220                                uint32_t        cmdcodeoff      :28;
3221                        #endif
3222                        uint32_t cmdmatch[8];
3223
3224                        uint32_t rsvd[2];
3225                } profile3;
3226
3227                struct {
3228                        #ifdef __BIG_ENDIAN_BITFIELD
3229                                uint32_t        seqlenoff       :16;
3230                                uint32_t        maxlen          :16;
3231                        #else   /*  __LITTLE_ENDIAN */
3232                                uint32_t        maxlen          :16;
3233                                uint32_t        seqlenoff       :16;
3234                        #endif
3235                        #ifdef __BIG_ENDIAN_BITFIELD
3236                                uint32_t        cmdcodeoff      :28;
3237                                uint32_t        rsvd1           :12;
3238                                uint32_t        seqlenbcnt      :4;
3239                        #else   /*  __LITTLE_ENDIAN */
3240                                uint32_t        seqlenbcnt      :4;
3241                                uint32_t        rsvd1           :12;
3242                                uint32_t        cmdcodeoff      :28;
3243                        #endif
3244                        uint32_t cmdmatch[8];
3245
3246                        uint32_t rsvd[2];
3247                } profile5;
3248
3249        } profiles;
3250
3251};
3252
3253
3254
3255/* Structure for MB Command CONFIG_PORT (0x88) */
3256typedef struct {
3257#ifdef __BIG_ENDIAN_BITFIELD
3258        uint32_t cBE       :  1;
3259        uint32_t cET       :  1;
3260        uint32_t cHpcb     :  1;
3261        uint32_t cMA       :  1;
3262        uint32_t sli_mode  :  4;
3263        uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3264                                        * config block */
3265#else   /*  __LITTLE_ENDIAN */
3266        uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3267                                        * config block */
3268        uint32_t sli_mode  :  4;
3269        uint32_t cMA       :  1;
3270        uint32_t cHpcb     :  1;
3271        uint32_t cET       :  1;
3272        uint32_t cBE       :  1;
3273#endif
3274
3275        uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
3276        uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
3277        uint32_t hbainit[5];
3278#ifdef __BIG_ENDIAN_BITFIELD
3279        uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
3280        uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3281#else   /*  __LITTLE_ENDIAN */
3282        uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3283        uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
3284#endif
3285
3286#ifdef __BIG_ENDIAN_BITFIELD
3287        uint32_t rsvd1     : 19;  /* Reserved                             */
3288        uint32_t cdss      :  1;  /* Configure Data Security SLI          */
3289        uint32_t casabt    :  1;  /* Configure async abts status notice   */
3290        uint32_t rsvd2     :  2;  /* Reserved                             */
3291        uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3292        uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3293        uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3294        uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3295        uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3296        uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3297        uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3298        uint32_t cmx       :  1;  /* Configure Max XRIs                   */
3299        uint32_t cmr       :  1;  /* Configure Max RPIs                   */
3300#else   /*  __LITTLE_ENDIAN */
3301        uint32_t cmr       :  1;  /* Configure Max RPIs                   */
3302        uint32_t cmx       :  1;  /* Configure Max XRIs                   */
3303        uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3304        uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3305        uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3306        uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3307        uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3308        uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3309        uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3310        uint32_t rsvd2     :  2;  /* Reserved                             */
3311        uint32_t casabt    :  1;  /* Configure async abts status notice   */
3312        uint32_t cdss      :  1;  /* Configure Data Security SLI          */
3313        uint32_t rsvd1     : 19;  /* Reserved                             */
3314#endif
3315#ifdef __BIG_ENDIAN_BITFIELD
3316        uint32_t rsvd3     : 19;  /* Reserved                             */
3317        uint32_t gdss      :  1;  /* Configure Data Security SLI          */
3318        uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3319        uint32_t rsvd4     :  2;  /* Reserved                             */
3320        uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3321        uint32_t gmv       :  1;  /* Grant Max VPIs                       */
3322        uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
3323        uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
3324        uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
3325        uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
3326        uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
3327        uint32_t gmx       :  1;  /* Grant Max XRIs                       */
3328        uint32_t gmr       :  1;  /* Grant Max RPIs                       */
3329#else   /*  __LITTLE_ENDIAN */
3330        uint32_t gmr       :  1;  /* Grant Max RPIs                       */
3331        uint32_t gmx       :  1;  /* Grant Max XRIs                       */
3332        uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
3333        uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
3334        uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
3335        uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
3336        uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
3337        uint32_t gmv       :  1;  /* Grant Max VPIs                       */
3338        uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3339        uint32_t rsvd4     :  2;  /* Reserved                             */
3340        uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3341        uint32_t gdss      :  1;  /* Configure Data Security SLI          */
3342        uint32_t rsvd3     : 19;  /* Reserved                             */
3343#endif
3344
3345#ifdef __BIG_ENDIAN_BITFIELD
3346        uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3347        uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3348#else   /*  __LITTLE_ENDIAN */
3349        uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3350        uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3351#endif
3352
3353#ifdef __BIG_ENDIAN_BITFIELD
3354        uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3355        uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3356#else   /*  __LITTLE_ENDIAN */
3357        uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3358        uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3359#endif
3360
3361        uint32_t rsvd6;           /* Reserved                             */
3362
3363#ifdef __BIG_ENDIAN_BITFIELD
3364        uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
3365        uint32_t fips_level : 4;   /* FIPS Level                           */
3366        uint32_t sec_err    : 9;   /* security crypto error                */
3367        uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3368#else   /*  __LITTLE_ENDIAN */
3369        uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3370        uint32_t sec_err    : 9;   /* security crypto error                */
3371        uint32_t fips_level : 4;   /* FIPS Level                           */
3372        uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
3373#endif
3374
3375} CONFIG_PORT_VAR;
3376
3377/* Structure for MB Command CONFIG_MSI (0x30) */
3378struct config_msi_var {
3379#ifdef __BIG_ENDIAN_BITFIELD
3380        uint32_t dfltMsgNum:8;  /* Default message number            */
3381        uint32_t rsvd1:11;      /* Reserved                          */
3382        uint32_t NID:5;         /* Number of secondary attention IDs */
3383        uint32_t rsvd2:5;       /* Reserved                          */
3384        uint32_t dfltPresent:1; /* Default message number present    */
3385        uint32_t addFlag:1;     /* Add association flag              */
3386        uint32_t reportFlag:1;  /* Report association flag           */
3387#else   /*  __LITTLE_ENDIAN_BITFIELD */
3388        uint32_t reportFlag:1;  /* Report association flag           */
3389        uint32_t addFlag:1;     /* Add association flag              */
3390        uint32_t dfltPresent:1; /* Default message number present    */
3391        uint32_t rsvd2:5;       /* Reserved                          */
3392        uint32_t NID:5;         /* Number of secondary attention IDs */
3393        uint32_t rsvd1:11;      /* Reserved                          */
3394        uint32_t dfltMsgNum:8;  /* Default message number            */
3395#endif
3396        uint32_t attentionConditions[2];
3397        uint8_t  attentionId[16];
3398        uint8_t  messageNumberByHA[64];
3399        uint8_t  messageNumberByID[16];
3400        uint32_t autoClearHA[2];
3401#ifdef __BIG_ENDIAN_BITFIELD
3402        uint32_t rsvd3:16;
3403        uint32_t autoClearID:16;
3404#else   /*  __LITTLE_ENDIAN_BITFIELD */
3405        uint32_t autoClearID:16;
3406        uint32_t rsvd3:16;
3407#endif
3408        uint32_t rsvd4;
3409};
3410
3411/* SLI-2 Port Control Block */
3412
3413/* SLIM POINTER */
3414#define SLIMOFF 0x30            /* WORD */
3415
3416typedef struct _SLI2_RDSC {
3417        uint32_t cmdEntries;
3418        uint32_t cmdAddrLow;
3419        uint32_t cmdAddrHigh;
3420
3421        uint32_t rspEntries;
3422        uint32_t rspAddrLow;
3423        uint32_t rspAddrHigh;
3424} SLI2_RDSC;
3425
3426typedef struct _PCB {
3427#ifdef __BIG_ENDIAN_BITFIELD
3428        uint32_t type:8;
3429#define TYPE_NATIVE_SLI2       0x01
3430        uint32_t feature:8;
3431#define FEATURE_INITIAL_SLI2   0x01
3432        uint32_t rsvd:12;
3433        uint32_t maxRing:4;
3434#else   /*  __LITTLE_ENDIAN_BITFIELD */
3435        uint32_t maxRing:4;
3436        uint32_t rsvd:12;
3437        uint32_t feature:8;
3438#define FEATURE_INITIAL_SLI2   0x01
3439        uint32_t type:8;
3440#define TYPE_NATIVE_SLI2       0x01
3441#endif
3442
3443        uint32_t mailBoxSize;
3444        uint32_t mbAddrLow;
3445        uint32_t mbAddrHigh;
3446
3447        uint32_t hgpAddrLow;
3448        uint32_t hgpAddrHigh;
3449
3450        uint32_t pgpAddrLow;
3451        uint32_t pgpAddrHigh;
3452        SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3453} PCB_t;
3454
3455/* NEW_FEATURE */
3456typedef struct {
3457#ifdef __BIG_ENDIAN_BITFIELD
3458        uint32_t rsvd0:27;
3459        uint32_t discardFarp:1;
3460        uint32_t IPEnable:1;
3461        uint32_t nodeName:1;
3462        uint32_t portName:1;
3463        uint32_t filterEnable:1;
3464#else   /*  __LITTLE_ENDIAN_BITFIELD */
3465        uint32_t filterEnable:1;
3466        uint32_t portName:1;
3467        uint32_t nodeName:1;
3468        uint32_t IPEnable:1;
3469        uint32_t discardFarp:1;
3470        uint32_t rsvd:27;
3471#endif
3472
3473        uint8_t portname[8];    /* Used to be struct lpfc_name */
3474        uint8_t nodename[8];
3475        uint32_t rsvd1;
3476        uint32_t rsvd2;
3477        uint32_t rsvd3;
3478        uint32_t IPAddress;
3479} CONFIG_FARP_VAR;
3480
3481/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3482
3483typedef struct {
3484#ifdef __BIG_ENDIAN_BITFIELD
3485        uint32_t rsvd:30;
3486        uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3487#else /*  __LITTLE_ENDIAN */
3488        uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3489        uint32_t rsvd:30;
3490#endif
3491} ASYNCEVT_ENABLE_VAR;
3492
3493/* Union of all Mailbox Command types */
3494#define MAILBOX_CMD_WSIZE       32
3495#define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3496/* ext_wsize times 4 bytes should not be greater than max xmit size */
3497#define MAILBOX_EXT_WSIZE       512
3498#define MAILBOX_EXT_SIZE        (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3499#define MAILBOX_HBA_EXT_OFFSET  0x100
3500/* max mbox xmit size is a page size for sysfs IO operations */
3501#define MAILBOX_SYSFS_MAX       4096
3502
3503typedef union {
3504        uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3505                                                    * feature/max ring number
3506                                                    */
3507        LOAD_SM_VAR varLdSM;            /* cmd =  1 (LOAD_SM)        */
3508        READ_NV_VAR varRDnvp;           /* cmd =  2 (READ_NVPARMS)   */
3509        WRITE_NV_VAR varWTnvp;          /* cmd =  3 (WRITE_NVPARMS)  */
3510        BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
3511        INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
3512        DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
3513        CONFIG_LINK varCfgLnk;          /* cmd =  7 (CONFIG_LINK)    */
3514        PART_SLIM_VAR varSlim;          /* cmd =  8 (PART_SLIM)      */
3515        CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
3516        RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
3517        READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
3518        READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
3519        READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
3520        READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
3521        READ_RPI_VAR varRdRPI;          /* cmd = 15 (READ_RPI(64))   */
3522        READ_XRI_VAR varRdXRI;          /* cmd = 16 (READ_XRI)       */
3523        READ_REV_VAR varRdRev;          /* cmd = 17 (READ_REV)       */
3524        READ_LNK_VAR varRdLnk;          /* cmd = 18 (READ_LNK_STAT)  */
3525        REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
3526        UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
3527        CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
3528        DUMP_VAR varDmp;                /* Warm Start DUMP mbx cmd   */
3529        UNREG_D_ID_VAR varUnregDID;     /* cmd = 0x23 (UNREG_D_ID)   */
3530        CONFIG_FARP_VAR varCfgFarp;     /* cmd = 0x25 (CONFIG_FARP)
3531                                         * NEW_FEATURE
3532                                         */
3533        struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3534        struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3535        CONFIG_PORT_VAR varCfgPort;     /* cmd = 0x88 (CONFIG_PORT)  */
3536        struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3537        REG_VPI_VAR varRegVpi;          /* cmd = 0x96 (REG_VPI) */
3538        UNREG_VPI_VAR varUnregVpi;      /* cmd = 0x97 (UNREG_VPI) */
3539        ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3540        struct READ_EVENT_LOG_VAR varRdEventLog;        /* cmd = 0x38
3541                                                         * (READ_EVENT_LOG)
3542                                                         */
3543        struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3544} MAILVARIANTS;
3545
3546/*
3547 * SLI-2 specific structures
3548 */
3549
3550struct lpfc_hgp {
3551        __le32 cmdPutInx;
3552        __le32 rspGetInx;
3553};
3554
3555struct lpfc_pgp {
3556        __le32 cmdGetInx;
3557        __le32 rspPutInx;
3558};
3559
3560struct sli2_desc {
3561        uint32_t unused1[16];
3562        struct lpfc_hgp host[MAX_SLI3_RINGS];
3563        struct lpfc_pgp port[MAX_SLI3_RINGS];
3564};
3565
3566struct sli3_desc {
3567        struct lpfc_hgp host[MAX_SLI3_RINGS];
3568        uint32_t reserved[8];
3569        uint32_t hbq_put[16];
3570};
3571
3572struct sli3_pgp {
3573        struct lpfc_pgp port[MAX_SLI3_RINGS];
3574        uint32_t hbq_get[16];
3575};
3576
3577union sli_var {
3578        struct sli2_desc        s2;
3579        struct sli3_desc        s3;
3580        struct sli3_pgp         s3_pgp;
3581};
3582
3583typedef struct {
3584#ifdef __BIG_ENDIAN_BITFIELD
3585        uint16_t mbxStatus;
3586        uint8_t mbxCommand;
3587        uint8_t mbxReserved:6;
3588        uint8_t mbxHc:1;
3589        uint8_t mbxOwner:1;     /* Low order bit first word */
3590#else   /*  __LITTLE_ENDIAN_BITFIELD */
3591        uint8_t mbxOwner:1;     /* Low order bit first word */
3592        uint8_t mbxHc:1;
3593        uint8_t mbxReserved:6;
3594        uint8_t mbxCommand;
3595        uint16_t mbxStatus;
3596#endif
3597
3598        MAILVARIANTS un;
3599        union sli_var us;
3600} MAILBOX_t;
3601
3602/*
3603 *    Begin Structure Definitions for IOCB Commands
3604 */
3605
3606typedef struct {
3607#ifdef __BIG_ENDIAN_BITFIELD
3608        uint8_t statAction;
3609        uint8_t statRsn;
3610        uint8_t statBaExp;
3611        uint8_t statLocalError;
3612#else   /*  __LITTLE_ENDIAN_BITFIELD */
3613        uint8_t statLocalError;
3614        uint8_t statBaExp;
3615        uint8_t statRsn;
3616        uint8_t statAction;
3617#endif
3618        /* statRsn  P/F_RJT reason codes */
3619#define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
3620#define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
3621#define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
3622#define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
3623#define RJT_UNSUP_CLASS    0x05 /* Class not supported */
3624#define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
3625#define RJT_UNSUP_TYPE     0x07 /* Type not supported */
3626#define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
3627#define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
3628#define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
3629#define RJT_BAD_OXID       0x0B /* OX_ID invalid */
3630#define RJT_BAD_RXID       0x0C /* RX_ID invalid */
3631#define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
3632#define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
3633#define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
3634#define RJT_BAD_PARM       0x10 /* Param. field invalid */
3635#define RJT_XCHG_ERR       0x11 /* Exchange error */
3636#define RJT_PROT_ERR       0x12 /* Protocol error */
3637#define RJT_BAD_LENGTH     0x13 /* Invalid Length */
3638#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3639#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3640#define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
3641#define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
3642#define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
3643#define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
3644#define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
3645
3646#define IOERR_SUCCESS                 0x00      /* statLocalError */
3647#define IOERR_MISSING_CONTINUE        0x01
3648#define IOERR_SEQUENCE_TIMEOUT        0x02
3649#define IOERR_INTERNAL_ERROR          0x03
3650#define IOERR_INVALID_RPI             0x04
3651#define IOERR_NO_XRI                  0x05
3652#define IOERR_ILLEGAL_COMMAND         0x06
3653#define IOERR_XCHG_DROPPED            0x07
3654#define IOERR_ILLEGAL_FIELD           0x08
3655#define IOERR_BAD_CONTINUE            0x09
3656#define IOERR_TOO_MANY_BUFFERS        0x0A
3657#define IOERR_RCV_BUFFER_WAITING      0x0B
3658#define IOERR_NO_CONNECTION           0x0C
3659#define IOERR_TX_DMA_FAILED           0x0D
3660#define IOERR_RX_DMA_FAILED           0x0E
3661#define IOERR_ILLEGAL_FRAME           0x0F
3662#define IOERR_EXTRA_DATA              0x10
3663#define IOERR_NO_RESOURCES            0x11
3664#define IOERR_RESERVED                0x12
3665#define IOERR_ILLEGAL_LENGTH          0x13
3666#define IOERR_UNSUPPORTED_FEATURE     0x14
3667#define IOERR_ABORT_IN_PROGRESS       0x15
3668#define IOERR_ABORT_REQUESTED         0x16
3669#define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3670#define IOERR_LOOP_OPEN_FAILURE       0x18
3671#define IOERR_RING_RESET              0x19
3672#define IOERR_LINK_DOWN               0x1A
3673#define IOERR_CORRUPTED_DATA          0x1B
3674#define IOERR_CORRUPTED_RPI           0x1C
3675#define IOERR_OUT_OF_ORDER_DATA       0x1D
3676#define IOERR_OUT_OF_ORDER_ACK        0x1E
3677#define IOERR_DUP_FRAME               0x1F
3678#define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
3679#define IOERR_BAD_HOST_ADDRESS        0x21
3680#define IOERR_RCV_HDRBUF_WAITING      0x22
3681#define IOERR_MISSING_HDR_BUFFER      0x23
3682#define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3683#define IOERR_ABORTMULT_REQUESTED     0x25
3684#define IOERR_BUFFER_SHORTAGE         0x28
3685#define IOERR_DEFAULT                 0x29
3686#define IOERR_CNT                     0x2A
3687#define IOERR_SLER_FAILURE            0x46
3688#define IOERR_SLER_CMD_RCV_FAILURE    0x47
3689#define IOERR_SLER_REC_RJT_ERR        0x48
3690#define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3691#define IOERR_SLER_SRR_RJT_ERR        0x4A
3692#define IOERR_SLER_RRQ_RJT_ERR        0x4C
3693#define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3694#define IOERR_SLER_ABTS_ERR           0x4E
3695#define IOERR_ELXSEC_KEY_UNWRAP_ERROR           0xF0
3696#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR   0xF1
3697#define IOERR_ELXSEC_CRYPTO_ERROR               0xF2
3698#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR       0xF3
3699#define IOERR_DRVR_MASK               0x100
3700#define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3701#define IOERR_SLI_BRESET              0x102
3702#define IOERR_SLI_ABORTED             0x103
3703#define IOERR_PARAM_MASK              0x1ff
3704} PARM_ERR;
3705
3706typedef union {
3707        struct {
3708#ifdef __BIG_ENDIAN_BITFIELD
3709                uint8_t Rctl;   /* R_CTL field */
3710                uint8_t Type;   /* TYPE field */
3711                uint8_t Dfctl;  /* DF_CTL field */
3712                uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3713#else   /*  __LITTLE_ENDIAN_BITFIELD */
3714                uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3715                uint8_t Dfctl;  /* DF_CTL field */
3716                uint8_t Type;   /* TYPE field */
3717                uint8_t Rctl;   /* R_CTL field */
3718#endif
3719
3720#define BC      0x02            /* Broadcast Received  - Fctl */
3721#define SI      0x04            /* Sequence Initiative */
3722#define LA      0x08            /* Ignore Link Attention state */
3723#define LS      0x80            /* Last Sequence */
3724        } hcsw;
3725        uint32_t reserved;
3726} WORD5;
3727
3728/* IOCB Command template for a generic response */
3729typedef struct {
3730        uint32_t reserved[4];
3731        PARM_ERR perr;
3732} GENERIC_RSP;
3733
3734/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3735typedef struct {
3736        struct ulp_bde xrsqbde[2];
3737        uint32_t xrsqRo;        /* Starting Relative Offset */
3738        WORD5 w5;               /* Header control/status word */
3739} XR_SEQ_FIELDS;
3740
3741/* IOCB Command template for ELS_REQUEST */
3742typedef struct {
3743        struct ulp_bde elsReq;
3744        struct ulp_bde elsRsp;
3745
3746#ifdef __BIG_ENDIAN_BITFIELD
3747        uint32_t word4Rsvd:7;
3748        uint32_t fl:1;
3749        uint32_t myID:24;
3750        uint32_t word5Rsvd:8;
3751        uint32_t remoteID:24;
3752#else   /*  __LITTLE_ENDIAN_BITFIELD */
3753        uint32_t myID:24;
3754        uint32_t fl:1;
3755        uint32_t word4Rsvd:7;
3756        uint32_t remoteID:24;
3757        uint32_t word5Rsvd:8;
3758#endif
3759} ELS_REQUEST;
3760
3761/* IOCB Command template for RCV_ELS_REQ */
3762typedef struct {
3763        struct ulp_bde elsReq[2];
3764        uint32_t parmRo;
3765
3766#ifdef __BIG_ENDIAN_BITFIELD
3767        uint32_t word5Rsvd:8;
3768        uint32_t remoteID:24;
3769#else   /*  __LITTLE_ENDIAN_BITFIELD */
3770        uint32_t remoteID:24;
3771        uint32_t word5Rsvd:8;
3772#endif
3773} RCV_ELS_REQ;
3774
3775/* IOCB Command template for ABORT / CLOSE_XRI */
3776typedef struct {
3777        uint32_t rsvd[3];
3778        uint32_t abortType;
3779#define ABORT_TYPE_ABTX  0x00000000
3780#define ABORT_TYPE_ABTS  0x00000001
3781        uint32_t parm;
3782#ifdef __BIG_ENDIAN_BITFIELD
3783        uint16_t abortContextTag; /* ulpContext from command to abort/close */
3784        uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3785#else   /*  __LITTLE_ENDIAN_BITFIELD */
3786        uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3787        uint16_t abortContextTag; /* ulpContext from command to abort/close */
3788#endif
3789} AC_XRI;
3790
3791/* IOCB Command template for ABORT_MXRI64 */
3792typedef struct {
3793        uint32_t rsvd[3];
3794        uint32_t abortType;
3795        uint32_t parm;
3796        uint32_t iotag32;
3797} A_MXRI64;
3798
3799/* IOCB Command template for GET_RPI */
3800typedef struct {
3801        uint32_t rsvd[4];
3802        uint32_t parmRo;
3803#ifdef __BIG_ENDIAN_BITFIELD
3804        uint32_t word5Rsvd:8;
3805        uint32_t remoteID:24;
3806#else   /*  __LITTLE_ENDIAN_BITFIELD */
3807        uint32_t remoteID:24;
3808        uint32_t word5Rsvd:8;
3809#endif
3810} GET_RPI;
3811
3812/* IOCB Command template for all FCP Initiator commands */
3813typedef struct {
3814        struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
3815        struct ulp_bde fcpi_rsp;        /* Rcv buffer */
3816        uint32_t fcpi_parm;
3817        uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
3818} FCPI_FIELDS;
3819
3820/* IOCB Command template for all FCP Target commands */
3821typedef struct {
3822        struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
3823        uint32_t fcpt_Offset;
3824        uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3825} FCPT_FIELDS;
3826
3827/* SLI-2 IOCB structure definitions */
3828
3829/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3830typedef struct {
3831        ULP_BDL bdl;
3832        uint32_t xrsqRo;        /* Starting Relative Offset */
3833        WORD5 w5;               /* Header control/status word */
3834} XMT_SEQ_FIELDS64;
3835
3836/* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3837#define xmit_els_remoteID xrsqRo
3838
3839/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3840typedef struct {
3841        struct ulp_bde64 rcvBde;
3842        uint32_t rsvd1;
3843        uint32_t xrsqRo;        /* Starting Relative Offset */
3844        WORD5 w5;               /* Header control/status word */
3845} RCV_SEQ_FIELDS64;
3846
3847/* IOCB Command template for ELS_REQUEST64 */
3848typedef struct {
3849        ULP_BDL bdl;
3850#ifdef __BIG_ENDIAN_BITFIELD
3851        uint32_t word4Rsvd:7;
3852        uint32_t fl:1;
3853        uint32_t myID:24;
3854        uint32_t word5Rsvd:8;
3855        uint32_t remoteID:24;
3856#else   /*  __LITTLE_ENDIAN_BITFIELD */
3857        uint32_t myID:24;
3858        uint32_t fl:1;
3859        uint32_t word4Rsvd:7;
3860        uint32_t remoteID:24;
3861        uint32_t word5Rsvd:8;
3862#endif
3863} ELS_REQUEST64;
3864
3865/* IOCB Command template for GEN_REQUEST64 */
3866typedef struct {
3867        ULP_BDL bdl;
3868        uint32_t xrsqRo;        /* Starting Relative Offset */
3869        WORD5 w5;               /* Header control/status word */
3870} GEN_REQUEST64;
3871
3872/* IOCB Command template for RCV_ELS_REQ64 */
3873typedef struct {
3874        struct ulp_bde64 elsReq;
3875        uint32_t rcvd1;
3876        uint32_t parmRo;
3877
3878#ifdef __BIG_ENDIAN_BITFIELD
3879        uint32_t word5Rsvd:8;
3880        uint32_t remoteID:24;
3881#else   /*  __LITTLE_ENDIAN_BITFIELD */
3882        uint32_t remoteID:24;
3883        uint32_t word5Rsvd:8;
3884#endif
3885} RCV_ELS_REQ64;
3886
3887/* IOCB Command template for RCV_SEQ64 */
3888struct rcv_seq64 {
3889        struct ulp_bde64 elsReq;
3890        uint32_t hbq_1;
3891        uint32_t parmRo;
3892#ifdef __BIG_ENDIAN_BITFIELD
3893        uint32_t rctl:8;
3894        uint32_t type:8;
3895        uint32_t dfctl:8;
3896        uint32_t ls:1;
3897        uint32_t fs:1;
3898        uint32_t rsvd2:3;
3899        uint32_t si:1;
3900        uint32_t bc:1;
3901        uint32_t rsvd3:1;
3902#else   /*  __LITTLE_ENDIAN_BITFIELD */
3903        uint32_t rsvd3:1;
3904        uint32_t bc:1;
3905        uint32_t si:1;
3906        uint32_t rsvd2:3;
3907        uint32_t fs:1;
3908        uint32_t ls:1;
3909        uint32_t dfctl:8;
3910        uint32_t type:8;
3911        uint32_t rctl:8;
3912#endif
3913};
3914
3915/* IOCB Command template for all 64 bit FCP Initiator commands */
3916typedef struct {
3917        ULP_BDL bdl;
3918        uint32_t fcpi_parm;
3919        uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
3920} FCPI_FIELDS64;
3921
3922/* IOCB Command template for all 64 bit FCP Target commands */
3923typedef struct {
3924        ULP_BDL bdl;
3925        uint32_t fcpt_Offset;
3926        uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3927} FCPT_FIELDS64;
3928
3929/* IOCB Command template for Async Status iocb commands */
3930typedef struct {
3931        uint32_t rsvd[4];
3932        uint32_t param;
3933#ifdef __BIG_ENDIAN_BITFIELD
3934        uint16_t evt_code;              /* High order bits word 5 */
3935        uint16_t sub_ctxt_tag;          /* Low  order bits word 5 */
3936#else   /*  __LITTLE_ENDIAN_BITFIELD */
3937        uint16_t sub_ctxt_tag;          /* High order bits word 5 */
3938        uint16_t evt_code;              /* Low  order bits word 5 */
3939#endif
3940} ASYNCSTAT_FIELDS;
3941#define ASYNC_TEMP_WARN         0x100
3942#define ASYNC_TEMP_SAFE         0x101
3943#define ASYNC_STATUS_CN         0x102
3944
3945/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3946   or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3947
3948struct rcv_sli3 {
3949#ifdef __BIG_ENDIAN_BITFIELD
3950        uint16_t ox_id;
3951        uint16_t seq_cnt;
3952
3953        uint16_t vpi;
3954        uint16_t word9Rsvd;
3955#else  /*  __LITTLE_ENDIAN */
3956        uint16_t seq_cnt;
3957        uint16_t ox_id;
3958
3959        uint16_t word9Rsvd;
3960        uint16_t vpi;
3961#endif
3962        uint32_t word10Rsvd;
3963        uint32_t acc_len;      /* accumulated length */
3964        struct ulp_bde64 bde2;
3965};
3966
3967/* Structure used for a single HBQ entry */
3968struct lpfc_hbq_entry {
3969        struct ulp_bde64 bde;
3970        uint32_t buffer_tag;
3971};
3972
3973/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3974typedef struct {
3975        struct lpfc_hbq_entry   buff;
3976        uint32_t                rsvd;
3977        uint32_t                rsvd1;
3978} QUE_XRI64_CX_FIELDS;
3979
3980struct que_xri64cx_ext_fields {
3981        uint32_t        iotag64_low;
3982        uint32_t        iotag64_high;
3983        uint32_t        ebde_count;
3984        uint32_t        rsvd;
3985        struct lpfc_hbq_entry   buff[5];
3986};
3987
3988struct sli3_bg_fields {
3989        uint32_t filler[6];     /* word 8-13 in IOCB */
3990        uint32_t bghm;          /* word 14 - BlockGuard High Water Mark */
3991/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3992#define BGS_BIDIR_BG_PROF_MASK          0xff000000
3993#define BGS_BIDIR_BG_PROF_SHIFT         24
3994#define BGS_BIDIR_ERR_COND_FLAGS_MASK   0x003f0000
3995#define BGS_BIDIR_ERR_COND_SHIFT        16
3996#define BGS_BG_PROFILE_MASK             0x0000ff00
3997#define BGS_BG_PROFILE_SHIFT            8
3998#define BGS_INVALID_PROF_MASK           0x00000020
3999#define BGS_INVALID_PROF_SHIFT          5
4000#define BGS_UNINIT_DIF_BLOCK_MASK       0x00000010

4001#define BGS_UNINIT_DIF_BLOCK_SHIFT      4
4002#define BGS_HI_WATER_MARK_PRESENT_MASK  0x00000008
4003#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
4004#define BGS_REFTAG_ERR_MASK             0x00000004
4005#define BGS_REFTAG_ERR_SHIFT            2
4006#define BGS_APPTAG_ERR_MASK             0x00000002
4007#define BGS_APPTAG_ERR_SHIFT            1
4008#define BGS_GUARD_ERR_MASK              0x00000001
4009#define BGS_GUARD_ERR_SHIFT             0
4010        uint32_t bgstat;        /* word 15 - BlockGuard Status */
4011};
4012
4013static inline uint32_t
4014lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4015{
4016        return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4017                                BGS_BIDIR_BG_PROF_SHIFT;
4018}
4019
4020static inline uint32_t
4021lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4022{
4023        return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4024                                BGS_BIDIR_ERR_COND_SHIFT;
4025}
4026
4027static inline uint32_t
4028lpfc_bgs_get_bg_prof(uint32_t bgstat)
4029{
4030        return (bgstat & BGS_BG_PROFILE_MASK) >>
4031                                BGS_BG_PROFILE_SHIFT;
4032}
4033
4034static inline uint32_t
4035lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4036{
4037        return (bgstat & BGS_INVALID_PROF_MASK) >>
4038                                BGS_INVALID_PROF_SHIFT;
4039}
4040
4041static inline uint32_t
4042lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4043{
4044        return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4045                                BGS_UNINIT_DIF_BLOCK_SHIFT;
4046}
4047
4048static inline uint32_t
4049lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4050{
4051        return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4052                                BGS_HI_WATER_MARK_PRESENT_SHIFT;
4053}
4054
4055static inline uint32_t
4056lpfc_bgs_get_reftag_err(uint32_t bgstat)
4057{
4058        return (bgstat & BGS_REFTAG_ERR_MASK) >>
4059                                BGS_REFTAG_ERR_SHIFT;
4060}
4061
4062static inline uint32_t
4063lpfc_bgs_get_apptag_err(uint32_t bgstat)
4064{
4065        return (bgstat & BGS_APPTAG_ERR_MASK) >>
4066                                BGS_APPTAG_ERR_SHIFT;
4067}
4068
4069static inline uint32_t
4070lpfc_bgs_get_guard_err(uint32_t bgstat)
4071{
4072        return (bgstat & BGS_GUARD_ERR_MASK) >>
4073                                BGS_GUARD_ERR_SHIFT;
4074}
4075
4076#define LPFC_EXT_DATA_BDE_COUNT 3
4077struct fcp_irw_ext {
4078        uint32_t        io_tag64_low;
4079        uint32_t        io_tag64_high;
4080#ifdef __BIG_ENDIAN_BITFIELD
4081        uint8_t         reserved1;
4082        uint8_t         reserved2;
4083        uint8_t         reserved3;
4084        uint8_t         ebde_count;
4085#else  /* __LITTLE_ENDIAN */
4086        uint8_t         ebde_count;
4087        uint8_t         reserved3;
4088        uint8_t         reserved2;
4089        uint8_t         reserved1;
4090#endif
4091        uint32_t        reserved4;
4092        struct ulp_bde64 rbde;          /* response bde */
4093        struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4094        uint8_t icd[32];                /* immediate command data (32 bytes) */
4095};
4096
4097typedef struct _IOCB {  /* IOCB structure */
4098        union {
4099                GENERIC_RSP grsp;       /* Generic response */
4100                XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
4101                struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4102                RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
4103                AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
4104                A_MXRI64 amxri; /* abort multiple xri command overlay */
4105                GET_RPI getrpi; /* GET_RPI template */
4106                FCPI_FIELDS fcpi;       /* FCP Initiator template */
4107                FCPT_FIELDS fcpt;       /* FCP target template */
4108
4109                /* SLI-2 structures */
4110
4111                struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
4112                                              * bde_64s */
4113                ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4114                GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4115                RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4116                XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
4117                FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
4118                FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
4119                ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4120                QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4121                struct rcv_seq64 rcvseq64;      /* RCV_SEQ64 and RCV_CONT64 */
4122                struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4123                uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
4124        } un;
4125        union {
4126                struct {
4127#ifdef __BIG_ENDIAN_BITFIELD
4128                        uint16_t ulpContext;    /* High order bits word 6 */
4129                        uint16_t ulpIoTag;      /* Low  order bits word 6 */
4130#else   /*  __LITTLE_ENDIAN_BITFIELD */
4131                        uint16_t ulpIoTag;      /* Low  order bits word 6 */
4132                        uint16_t ulpContext;    /* High order bits word 6 */
4133#endif
4134                } t1;
4135                struct {
4136#ifdef __BIG_ENDIAN_BITFIELD
4137                        uint16_t ulpContext;    /* High order bits word 6 */
4138                        uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
4139                        uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
4140#else   /*  __LITTLE_ENDIAN_BITFIELD */
4141                        uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
4142                        uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
4143                        uint16_t ulpContext;    /* High order bits word 6 */
4144#endif
4145                } t2;
4146        } un1;
4147#define ulpContext un1.t1.ulpContext
4148#define ulpIoTag   un1.t1.ulpIoTag
4149#define ulpIoTag0  un1.t2.ulpIoTag0
4150
4151#ifdef __BIG_ENDIAN_BITFIELD
4152        uint32_t ulpTimeout:8;
4153        uint32_t ulpXS:1;
4154        uint32_t ulpFCP2Rcvy:1;
4155        uint32_t ulpPU:2;
4156        uint32_t ulpIr:1;
4157        uint32_t ulpClass:3;
4158        uint32_t ulpCommand:8;
4159        uint32_t ulpStatus:4;
4160        uint32_t ulpBdeCount:2;
4161        uint32_t ulpLe:1;
4162        uint32_t ulpOwner:1;    /* Low order bit word 7 */
4163#else   /*  __LITTLE_ENDIAN_BITFIELD */
4164        uint32_t ulpOwner:1;    /* Low order bit word 7 */
4165        uint32_t ulpLe:1;
4166        uint32_t ulpBdeCount:2;
4167        uint32_t ulpStatus:4;
4168        uint32_t ulpCommand:8;
4169        uint32_t ulpClass:3;
4170        uint32_t ulpIr:1;
4171        uint32_t ulpPU:2;
4172        uint32_t ulpFCP2Rcvy:1;
4173        uint32_t ulpXS:1;
4174        uint32_t ulpTimeout:8;
4175#endif
4176
4177        union {
4178                struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4179
4180                /* words 8-31 used for que_xri_cx iocb */
4181                struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4182                struct fcp_irw_ext fcp_ext;
4183                uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4184
4185                /* words 8-15 for BlockGuard */
4186                struct sli3_bg_fields sli3_bg;
4187        } unsli3;
4188
4189#define ulpCt_h ulpXS
4190#define ulpCt_l ulpFCP2Rcvy
4191
4192#define IOCB_FCP           1    /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4193#define IOCB_IP            2    /* IOCB is used for IP ELS cmds */
4194#define PARM_UNUSED        0    /* PU field (Word 4) not used */
4195#define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
4196#define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
4197#define PARM_NPIV_DID      3
4198#define CLASS1             0    /* Class 1 */
4199#define CLASS2             1    /* Class 2 */
4200#define CLASS3             2    /* Class 3 */
4201#define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
4202
4203#define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
4204#define IOSTAT_FCP_RSP_ERROR   0x1
4205#define IOSTAT_REMOTE_STOP     0x2
4206#define IOSTAT_LOCAL_REJECT    0x3
4207#define IOSTAT_NPORT_RJT       0x4
4208#define IOSTAT_FABRIC_RJT      0x5
4209#define IOSTAT_NPORT_BSY       0x6
4210#define IOSTAT_FABRIC_BSY      0x7
4211#define IOSTAT_INTERMED_RSP    0x8
4212#define IOSTAT_LS_RJT          0x9
4213#define IOSTAT_BA_RJT          0xA
4214#define IOSTAT_RSVD1           0xB
4215#define IOSTAT_RSVD2           0xC
4216#define IOSTAT_RSVD3           0xD
4217#define IOSTAT_RSVD4           0xE
4218#define IOSTAT_NEED_BUFFER     0xF
4219#define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
4220#define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
4221#define IOSTAT_CNT             0x11
4222
4223} IOCB_t;
4224
4225
4226#define SLI1_SLIM_SIZE   (4 * 1024)
4227
4228/* Up to 498 IOCBs will fit into 16k
4229 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4230 */
4231#define SLI2_SLIM_SIZE   (64 * 1024)
4232
4233/* Maximum IOCBs that will fit in SLI2 slim */
4234#define MAX_SLI2_IOCB    498
4235#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4236                            (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4237                            sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4238
4239/* HBQ entries are 4 words each = 4k */
4240#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
4241                             lpfc_sli_hbq_count())
4242
4243struct lpfc_sli2_slim {
4244        MAILBOX_t mbx;
4245        uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
4246        PCB_t pcb;
4247        IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4248};
4249
4250/*
4251 * This function checks PCI device to allow special handling for LC HBAs.
4252 *
4253 * Parameters:
4254 * device : struct pci_dev 's device field
4255 *
4256 * return 1 => TRUE
4257 *        0 => FALSE
4258 */
4259static inline int
4260lpfc_is_LC_HBA(unsigned short device)
4261{
4262        if ((device == PCI_DEVICE_ID_TFLY) ||
4263            (device == PCI_DEVICE_ID_PFLY) ||
4264            (device == PCI_DEVICE_ID_LP101) ||
4265            (device == PCI_DEVICE_ID_BMID) ||
4266            (device == PCI_DEVICE_ID_BSMB) ||
4267            (device == PCI_DEVICE_ID_ZMID) ||
4268            (device == PCI_DEVICE_ID_ZSMB) ||
4269            (device == PCI_DEVICE_ID_SAT_MID) ||
4270            (device == PCI_DEVICE_ID_SAT_SMB) ||
4271            (device == PCI_DEVICE_ID_RFLY))
4272                return 1;
4273        else
4274                return 0;
4275}
4276
4277/*
4278 * Determine if an IOCB failed because of a link event or firmware reset.
4279 */
4280
4281static inline int
4282lpfc_error_lost_link(IOCB_t *iocbp)
4283{
4284        return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4285                (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4286                 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4287                 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4288}
4289
4290#define MENLO_TRANSPORT_TYPE 0xfe
4291#define MENLO_CONTEXT 0
4292#define MENLO_PU 3
4293#define MENLO_TIMEOUT 30
4294#define SETVAR_MLOMNT 0x103107
4295#define SETVAR_MLORST 0x103007
4296
4297#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
4298
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.