1/******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23/* Macros to deal with bit fields. Each bit field must have 3 #defines 24 * associated with it (_SHIFT, _MASK, and _WORD). 25 * EG. For a bit field that is in the 7th bit of the "field4" field of a 26 * structure and is 2 bits in size the following #defines must exist: 27 * struct temp { 28 * uint32_t field1; 29 * uint32_t field2; 30 * uint32_t field3; 31 * uint32_t field4; 32 * #define example_bit_field_SHIFT 7 33 * #define example_bit_field_MASK 0x03 34 * #define example_bit_field_WORD field4 35 * uint32_t field5; 36 * }; 37 * Then the macros below may be used to get or set the value of that field. 38 * EG. To get the value of the bit field from the above example: 39 * struct temp t1; 40 * value = bf_get(example_bit_field, &t1); 41 * And then to set that bit field: 42 * bf_set(example_bit_field, &t1, 2); 43 * Or clear that bit field: 44 * bf_set(example_bit_field, &t1, 0); 45 */ 46#define bf_get_be32(name, ptr) \ 47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48#define bf_get_le32(name, ptr) \ 49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50#define bf_get(name, ptr) \ 51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 52#define bf_set_le32(name, ptr, value) \ 53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 55 ~(name##_MASK << name##_SHIFT))))) 56#define bf_set(name, ptr, value) \ 57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 59 60struct dma_address { 61 uint32_t addr_lo; 62 uint32_t addr_hi; 63}; 64 65struct lpfc_sli_intf { 66 uint32_t word0; 67#define lpfc_sli_intf_valid_SHIFT 29 68#define lpfc_sli_intf_valid_MASK 0x00000007 69#define lpfc_sli_intf_valid_WORD word0 70#define LPFC_SLI_INTF_VALID 6 71#define lpfc_sli_intf_sli_hint2_SHIFT 24 72#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 73#define lpfc_sli_intf_sli_hint2_WORD word0 74#define LPFC_SLI_INTF_SLI_HINT2_NONE 0 75#define lpfc_sli_intf_sli_hint1_SHIFT 16 76#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 77#define lpfc_sli_intf_sli_hint1_WORD word0 78#define LPFC_SLI_INTF_SLI_HINT1_NONE 0 79#define LPFC_SLI_INTF_SLI_HINT1_1 1 80#define LPFC_SLI_INTF_SLI_HINT1_2 2 81#define lpfc_sli_intf_if_type_SHIFT 12 82#define lpfc_sli_intf_if_type_MASK 0x0000000F 83#define lpfc_sli_intf_if_type_WORD word0 84#define LPFC_SLI_INTF_IF_TYPE_0 0 85#define LPFC_SLI_INTF_IF_TYPE_1 1 86#define LPFC_SLI_INTF_IF_TYPE_2 2 87#define LPFC_SLI_INTF_IF_TYPE_6 6 88#define lpfc_sli_intf_sli_family_SHIFT 8 89#define lpfc_sli_intf_sli_family_MASK 0x0000000F 90#define lpfc_sli_intf_sli_family_WORD word0 91#define LPFC_SLI_INTF_FAMILY_BE2 0x0 92#define LPFC_SLI_INTF_FAMILY_BE3 0x1 93#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 94#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 95#define lpfc_sli_intf_slirev_SHIFT 4 96#define lpfc_sli_intf_slirev_MASK 0x0000000F 97#define lpfc_sli_intf_slirev_WORD word0 98#define LPFC_SLI_INTF_REV_SLI3 3 99#define LPFC_SLI_INTF_REV_SLI4 4 100#define lpfc_sli_intf_func_type_SHIFT 0 101#define lpfc_sli_intf_func_type_MASK 0x00000001 102#define lpfc_sli_intf_func_type_WORD word0 103#define LPFC_SLI_INTF_IF_TYPE_PHYS 0 104#define LPFC_SLI_INTF_IF_TYPE_VIRT 1 105}; 106 107#define LPFC_SLI4_MBX_EMBED true 108#define LPFC_SLI4_MBX_NEMBED false 109 110#define LPFC_SLI4_MB_WORD_COUNT 64 111#define LPFC_MAX_MQ_PAGE 8 112#define LPFC_MAX_WQ_PAGE_V0 4 113#define LPFC_MAX_WQ_PAGE 8 114#define LPFC_MAX_RQ_PAGE 8 115#define LPFC_MAX_CQ_PAGE 4 116#define LPFC_MAX_EQ_PAGE 8 117 118#define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 119#define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 120#define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 121 122/* Define SLI4 Alignment requirements. */ 123#define LPFC_ALIGN_16_BYTE 16 124#define LPFC_ALIGN_64_BYTE 64 125 126/* Define SLI4 specific definitions. */ 127#define LPFC_MQ_CQE_BYTE_OFFSET 256 128#define LPFC_MBX_CMD_HDR_LENGTH 16 129#define LPFC_MBX_ERROR_RANGE 0x4000 130#define LPFC_BMBX_BIT1_ADDR_HI 0x2 131#define LPFC_BMBX_BIT1_ADDR_LO 0 132#define LPFC_RPI_HDR_COUNT 64 133#define LPFC_HDR_TEMPLATE_SIZE 4096 134#define LPFC_RPI_ALLOC_ERROR 0xFFFF 135#define LPFC_FCF_RECORD_WD_CNT 132 136#define LPFC_ENTIRE_FCF_DATABASE 0 137#define LPFC_DFLT_FCF_INDEX 0 138 139/* Virtual function numbers */ 140#define LPFC_VF0 0 141#define LPFC_VF1 1 142#define LPFC_VF2 2 143#define LPFC_VF3 3 144#define LPFC_VF4 4 145#define LPFC_VF5 5 146#define LPFC_VF6 6 147#define LPFC_VF7 7 148#define LPFC_VF8 8 149#define LPFC_VF9 9 150#define LPFC_VF10 10 151#define LPFC_VF11 11 152#define LPFC_VF12 12 153#define LPFC_VF13 13 154#define LPFC_VF14 14 155#define LPFC_VF15 15 156#define LPFC_VF16 16 157#define LPFC_VF17 17 158#define LPFC_VF18 18 159#define LPFC_VF19 19 160#define LPFC_VF20 20 161#define LPFC_VF21 21 162#define LPFC_VF22 22 163#define LPFC_VF23 23 164#define LPFC_VF24 24 165#define LPFC_VF25 25 166#define LPFC_VF26 26 167#define LPFC_VF27 27 168#define LPFC_VF28 28 169#define LPFC_VF29 29 170#define LPFC_VF30 30 171#define LPFC_VF31 31 172 173/* PCI function numbers */ 174#define LPFC_PCI_FUNC0 0 175#define LPFC_PCI_FUNC1 1 176#define LPFC_PCI_FUNC2 2 177#define LPFC_PCI_FUNC3 3 178#define LPFC_PCI_FUNC4 4 179 180/* SLI4 interface type-2 PDEV_CTL register */ 181#define LPFC_CTL_PDEV_CTL_OFFSET 0x414 182#define LPFC_CTL_PDEV_CTL_DRST 0x00000001 183#define LPFC_CTL_PDEV_CTL_FRST 0x00000002 184#define LPFC_CTL_PDEV_CTL_DD 0x00000004 185#define LPFC_CTL_PDEV_CTL_LC 0x00000008 186#define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 187#define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 188#define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 189#define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 190 191#define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 192 193/* Active interrupt test count */ 194#define LPFC_ACT_INTR_CNT 4 195 196/* Algrithmns for scheduling FCP commands to WQs */ 197#define LPFC_FCP_SCHED_BY_HDWQ 0 198#define LPFC_FCP_SCHED_BY_CPU 1 199 200/* Algrithmns for NameServer Query after RSCN */ 201#define LPFC_NS_QUERY_GID_FT 0 202#define LPFC_NS_QUERY_GID_PT 1 203 204/* Delay Multiplier constant */ 205#define LPFC_DMULT_CONST 651042 206#define LPFC_DMULT_MAX 1023 207 208/* Configuration of Interrupts / sec for entire HBA port */ 209#define LPFC_MIN_IMAX 5000 210#define LPFC_MAX_IMAX 5000000 211#define LPFC_DEF_IMAX 0 212 213#define LPFC_IMAX_THRESHOLD 1000 214#define LPFC_MAX_AUTO_EQ_DELAY 120 215#define LPFC_EQ_DELAY_STEP 15 216#define LPFC_EQD_ISR_TRIGGER 20000 217/* 1s intervals */ 218#define LPFC_EQ_DELAY_MSECS 1000 219 220#define LPFC_MIN_CPU_MAP 0 221#define LPFC_MAX_CPU_MAP 1 222#define LPFC_HBA_CPU_MAP 1 223 224/* PORT_CAPABILITIES constants. */ 225#define LPFC_MAX_SUPPORTED_PAGES 8 226 227struct ulp_bde64 { 228 union ULP_BDE_TUS { 229 uint32_t w; 230 struct { 231#ifdef __BIG_ENDIAN_BITFIELD 232 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 233 VALUE !! */ 234 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 235#else /* __LITTLE_ENDIAN_BITFIELD */ 236 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 237 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 238 VALUE !! */ 239#endif 240#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 241#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 242#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 243#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 244#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 245#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 246#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 247 } f; 248 } tus; 249 uint32_t addrLow; 250 uint32_t addrHigh; 251}; 252 253/* Maximun size of immediate data that can fit into a 128 byte WQE */ 254#define LPFC_MAX_BDE_IMM_SIZE 64 255 256struct lpfc_sli4_flags { 257 uint32_t word0; 258#define lpfc_idx_rsrc_rdy_SHIFT 0 259#define lpfc_idx_rsrc_rdy_MASK 0x00000001 260#define lpfc_idx_rsrc_rdy_WORD word0 261#define LPFC_IDX_RSRC_RDY 1 262#define lpfc_rpi_rsrc_rdy_SHIFT 1 263#define lpfc_rpi_rsrc_rdy_MASK 0x00000001 264#define lpfc_rpi_rsrc_rdy_WORD word0 265#define LPFC_RPI_RSRC_RDY 1 266#define lpfc_vpi_rsrc_rdy_SHIFT 2 267#define lpfc_vpi_rsrc_rdy_MASK 0x00000001 268#define lpfc_vpi_rsrc_rdy_WORD word0 269#define LPFC_VPI_RSRC_RDY 1 270#define lpfc_vfi_rsrc_rdy_SHIFT 3 271#define lpfc_vfi_rsrc_rdy_MASK 0x00000001 272#define lpfc_vfi_rsrc_rdy_WORD word0 273#define LPFC_VFI_RSRC_RDY 1 274}; 275 276struct sli4_bls_rsp { 277 uint32_t word0_rsvd; /* Word0 must be reserved */ 278 uint32_t word1; 279#define lpfc_abts_orig_SHIFT 0 280#define lpfc_abts_orig_MASK 0x00000001 281#define lpfc_abts_orig_WORD word1 282#define LPFC_ABTS_UNSOL_RSP 1 283#define LPFC_ABTS_UNSOL_INT 0 284 uint32_t word2; 285#define lpfc_abts_rxid_SHIFT 0 286#define lpfc_abts_rxid_MASK 0x0000FFFF 287#define lpfc_abts_rxid_WORD word2 288#define lpfc_abts_oxid_SHIFT 16 289#define lpfc_abts_oxid_MASK 0x0000FFFF 290#define lpfc_abts_oxid_WORD word2 291 uint32_t word3; 292#define lpfc_vndr_code_SHIFT 0 293#define lpfc_vndr_code_MASK 0x000000FF 294#define lpfc_vndr_code_WORD word3 295#define lpfc_rsn_expln_SHIFT 8 296#define lpfc_rsn_expln_MASK 0x000000FF 297#define lpfc_rsn_expln_WORD word3 298#define lpfc_rsn_code_SHIFT 16 299#define lpfc_rsn_code_MASK 0x000000FF 300#define lpfc_rsn_code_WORD word3 301 302 uint32_t word4; 303 uint32_t word5_rsvd; /* Word5 must be reserved */ 304}; 305 306/* event queue entry structure */ 307struct lpfc_eqe { 308 uint32_t word0; 309#define lpfc_eqe_resource_id_SHIFT 16 310#define lpfc_eqe_resource_id_MASK 0x0000FFFF 311#define lpfc_eqe_resource_id_WORD word0 312#define lpfc_eqe_minor_code_SHIFT 4 313#define lpfc_eqe_minor_code_MASK 0x00000FFF 314#define lpfc_eqe_minor_code_WORD word0 315#define lpfc_eqe_major_code_SHIFT 1 316#define lpfc_eqe_major_code_MASK 0x00000007 317#define lpfc_eqe_major_code_WORD word0 318#define lpfc_eqe_valid_SHIFT 0 319#define lpfc_eqe_valid_MASK 0x00000001 320#define lpfc_eqe_valid_WORD word0 321}; 322 323/* completion queue entry structure (common fields for all cqe types) */ 324struct lpfc_cqe { 325 uint32_t reserved0; 326 uint32_t reserved1; 327 uint32_t reserved2; 328 uint32_t word3; 329#define lpfc_cqe_valid_SHIFT 31 330#define lpfc_cqe_valid_MASK 0x00000001 331#define lpfc_cqe_valid_WORD word3 332#define lpfc_cqe_code_SHIFT 16 333#define lpfc_cqe_code_MASK 0x000000FF 334#define lpfc_cqe_code_WORD word3 335}; 336 337/* Completion Queue Entry Status Codes */ 338#define CQE_STATUS_SUCCESS 0x0 339#define CQE_STATUS_FCP_RSP_FAILURE 0x1 340#define CQE_STATUS_REMOTE_STOP 0x2 341#define CQE_STATUS_LOCAL_REJECT 0x3 342#define CQE_STATUS_NPORT_RJT 0x4 343#define CQE_STATUS_FABRIC_RJT 0x5 344#define CQE_STATUS_NPORT_BSY 0x6 345#define CQE_STATUS_FABRIC_BSY 0x7 346#define CQE_STATUS_INTERMED_RSP 0x8 347#define CQE_STATUS_LS_RJT 0x9 348#define CQE_STATUS_CMD_REJECT 0xb 349#define CQE_STATUS_FCP_TGT_LENCHECK 0xc 350#define CQE_STATUS_NEED_BUFF_ENTRY 0xf 351#define CQE_STATUS_DI_ERROR 0x16 352 353/* Used when mapping CQE status to IOCB */ 354#define LPFC_IOCB_STATUS_MASK 0xf 355 356/* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 357#define CQE_HW_STATUS_NO_ERR 0x0 358#define CQE_HW_STATUS_UNDERRUN 0x1 359#define CQE_HW_STATUS_OVERRUN 0x2 360 361/* Completion Queue Entry Codes */ 362#define CQE_CODE_COMPL_WQE 0x1 363#define CQE_CODE_RELEASE_WQE 0x2 364#define CQE_CODE_RECEIVE 0x4 365#define CQE_CODE_XRI_ABORTED 0x5 366#define CQE_CODE_RECEIVE_V1 0x9 367#define CQE_CODE_NVME_ERSP 0xd 368 369/* 370 * Define mask value for xri_aborted and wcqe completed CQE extended status. 371 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 372 */ 373#define WCQE_PARAM_MASK 0x1FF 374 375/* completion queue entry for wqe completions */ 376struct lpfc_wcqe_complete { 377 uint32_t word0; 378#define lpfc_wcqe_c_request_tag_SHIFT 16 379#define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 380#define lpfc_wcqe_c_request_tag_WORD word0 381#define lpfc_wcqe_c_status_SHIFT 8 382#define lpfc_wcqe_c_status_MASK 0x000000FF 383#define lpfc_wcqe_c_status_WORD word0 384#define lpfc_wcqe_c_hw_status_SHIFT 0 385#define lpfc_wcqe_c_hw_status_MASK 0x000000FF 386#define lpfc_wcqe_c_hw_status_WORD word0 387#define lpfc_wcqe_c_ersp0_SHIFT 0 388#define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 389#define lpfc_wcqe_c_ersp0_WORD word0 390 uint32_t total_data_placed; 391 uint32_t parameter; 392#define lpfc_wcqe_c_bg_edir_SHIFT 5 393#define lpfc_wcqe_c_bg_edir_MASK 0x00000001 394#define lpfc_wcqe_c_bg_edir_WORD parameter 395#define lpfc_wcqe_c_bg_tdpv_SHIFT 3 396#define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 397#define lpfc_wcqe_c_bg_tdpv_WORD parameter 398#define lpfc_wcqe_c_bg_re_SHIFT 2 399#define lpfc_wcqe_c_bg_re_MASK 0x00000001 400#define lpfc_wcqe_c_bg_re_WORD parameter 401#define lpfc_wcqe_c_bg_ae_SHIFT 1 402#define lpfc_wcqe_c_bg_ae_MASK 0x00000001 403#define lpfc_wcqe_c_bg_ae_WORD parameter 404#define lpfc_wcqe_c_bg_ge_SHIFT 0 405#define lpfc_wcqe_c_bg_ge_MASK 0x00000001 406#define lpfc_wcqe_c_bg_ge_WORD parameter 407 uint32_t word3; 408#define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 409#define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 410#define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 411#define lpfc_wcqe_c_xb_SHIFT 28 412#define lpfc_wcqe_c_xb_MASK 0x00000001 413#define lpfc_wcqe_c_xb_WORD word3 414#define lpfc_wcqe_c_pv_SHIFT 27 415#define lpfc_wcqe_c_pv_MASK 0x00000001 416#define lpfc_wcqe_c_pv_WORD word3 417#define lpfc_wcqe_c_priority_SHIFT 24 418#define lpfc_wcqe_c_priority_MASK 0x00000007 419#define lpfc_wcqe_c_priority_WORD word3 420#define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 421#define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 422#define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 423#define lpfc_wcqe_c_sqhead_SHIFT 0 424#define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 425#define lpfc_wcqe_c_sqhead_WORD word3 426}; 427 428/* completion queue entry for wqe release */ 429struct lpfc_wcqe_release { 430 uint32_t reserved0; 431 uint32_t reserved1; 432 uint32_t word2; 433#define lpfc_wcqe_r_wq_id_SHIFT 16 434#define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 435#define lpfc_wcqe_r_wq_id_WORD word2 436#define lpfc_wcqe_r_wqe_index_SHIFT 0 437#define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 438#define lpfc_wcqe_r_wqe_index_WORD word2 439 uint32_t word3; 440#define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 441#define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 442#define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 443#define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 444#define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 445#define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 446}; 447 448struct sli4_wcqe_xri_aborted { 449 uint32_t word0; 450#define lpfc_wcqe_xa_status_SHIFT 8 451#define lpfc_wcqe_xa_status_MASK 0x000000FF 452#define lpfc_wcqe_xa_status_WORD word0 453 uint32_t parameter; 454 uint32_t word2; 455#define lpfc_wcqe_xa_remote_xid_SHIFT 16 456#define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 457#define lpfc_wcqe_xa_remote_xid_WORD word2 458#define lpfc_wcqe_xa_xri_SHIFT 0 459#define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 460#define lpfc_wcqe_xa_xri_WORD word2 461 uint32_t word3; 462#define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 463#define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 464#define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 465#define lpfc_wcqe_xa_ia_SHIFT 30 466#define lpfc_wcqe_xa_ia_MASK 0x00000001 467#define lpfc_wcqe_xa_ia_WORD word3 468#define CQE_XRI_ABORTED_IA_REMOTE 0 469#define CQE_XRI_ABORTED_IA_LOCAL 1 470#define lpfc_wcqe_xa_br_SHIFT 29 471#define lpfc_wcqe_xa_br_MASK 0x00000001 472#define lpfc_wcqe_xa_br_WORD word3 473#define CQE_XRI_ABORTED_BR_BA_ACC 0 474#define CQE_XRI_ABORTED_BR_BA_RJT 1 475#define lpfc_wcqe_xa_eo_SHIFT 28 476#define lpfc_wcqe_xa_eo_MASK 0x00000001 477#define lpfc_wcqe_xa_eo_WORD word3 478#define CQE_XRI_ABORTED_EO_REMOTE 0 479#define CQE_XRI_ABORTED_EO_LOCAL 1 480#define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 481#define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 482#define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 483}; 484 485/* completion queue entry structure for rqe completion */ 486struct lpfc_rcqe { 487 uint32_t word0; 488#define lpfc_rcqe_bindex_SHIFT 16 489#define lpfc_rcqe_bindex_MASK 0x0000FFF 490#define lpfc_rcqe_bindex_WORD word0 491#define lpfc_rcqe_status_SHIFT 8 492#define lpfc_rcqe_status_MASK 0x000000FF 493#define lpfc_rcqe_status_WORD word0 494#define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 495#define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 496#define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 497#define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 498 uint32_t word1; 499#define lpfc_rcqe_fcf_id_v1_SHIFT 0 500#define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 501#define lpfc_rcqe_fcf_id_v1_WORD word1 502 uint32_t word2; 503#define lpfc_rcqe_length_SHIFT 16 504#define lpfc_rcqe_length_MASK 0x0000FFFF 505#define lpfc_rcqe_length_WORD word2 506#define lpfc_rcqe_rq_id_SHIFT 6 507#define lpfc_rcqe_rq_id_MASK 0x000003FF 508#define lpfc_rcqe_rq_id_WORD word2 509#define lpfc_rcqe_fcf_id_SHIFT 0 510#define lpfc_rcqe_fcf_id_MASK 0x0000003F 511#define lpfc_rcqe_fcf_id_WORD word2 512#define lpfc_rcqe_rq_id_v1_SHIFT 0 513#define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 514#define lpfc_rcqe_rq_id_v1_WORD word2 515 uint32_t word3; 516#define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 517#define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 518#define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 519#define lpfc_rcqe_port_SHIFT 30 520#define lpfc_rcqe_port_MASK 0x00000001 521#define lpfc_rcqe_port_WORD word3 522#define lpfc_rcqe_hdr_length_SHIFT 24 523#define lpfc_rcqe_hdr_length_MASK 0x0000001F 524#define lpfc_rcqe_hdr_length_WORD word3 525#define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 526#define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 527#define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 528#define lpfc_rcqe_eof_SHIFT 8 529#define lpfc_rcqe_eof_MASK 0x000000FF 530#define lpfc_rcqe_eof_WORD word3 531#define FCOE_EOFn 0x41 532#define FCOE_EOFt 0x42 533#define FCOE_EOFni 0x49 534#define FCOE_EOFa 0x50 535#define lpfc_rcqe_sof_SHIFT 0 536#define lpfc_rcqe_sof_MASK 0x000000FF 537#define lpfc_rcqe_sof_WORD word3 538#define FCOE_SOFi2 0x2d 539#define FCOE_SOFi3 0x2e 540#define FCOE_SOFn2 0x35 541#define FCOE_SOFn3 0x36 542}; 543 544struct lpfc_rqe { 545 uint32_t address_hi; 546 uint32_t address_lo; 547}; 548 549/* buffer descriptors */ 550struct lpfc_bde4 { 551 uint32_t addr_hi; 552 uint32_t addr_lo; 553 uint32_t word2; 554#define lpfc_bde4_last_SHIFT 31 555#define lpfc_bde4_last_MASK 0x00000001 556#define lpfc_bde4_last_WORD word2 557#define lpfc_bde4_sge_offset_SHIFT 0 558#define lpfc_bde4_sge_offset_MASK 0x000003FF 559#define lpfc_bde4_sge_offset_WORD word2 560 uint32_t word3; 561#define lpfc_bde4_length_SHIFT 0 562#define lpfc_bde4_length_MASK 0x000000FF 563#define lpfc_bde4_length_WORD word3 564}; 565 566struct lpfc_register { 567 uint32_t word0; 568}; 569 570#define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 571#define LPFC_PORT_SEM_MASK 0xF000 572/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 573#define LPFC_UERR_STATUS_HI 0x00A4 574#define LPFC_UERR_STATUS_LO 0x00A0 575#define LPFC_UE_MASK_HI 0x00AC 576#define LPFC_UE_MASK_LO 0x00A8 577 578/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 579#define LPFC_SLI_INTF 0x0058 580#define LPFC_SLI_ASIC_VER 0x009C 581 582#define LPFC_CTL_PORT_SEM_OFFSET 0x400 583#define lpfc_port_smphr_perr_SHIFT 31 584#define lpfc_port_smphr_perr_MASK 0x1 585#define lpfc_port_smphr_perr_WORD word0 586#define lpfc_port_smphr_sfi_SHIFT 30 587#define lpfc_port_smphr_sfi_MASK 0x1 588#define lpfc_port_smphr_sfi_WORD word0 589#define lpfc_port_smphr_nip_SHIFT 29 590#define lpfc_port_smphr_nip_MASK 0x1 591#define lpfc_port_smphr_nip_WORD word0 592#define lpfc_port_smphr_ipc_SHIFT 28 593#define lpfc_port_smphr_ipc_MASK 0x1 594#define lpfc_port_smphr_ipc_WORD word0 595#define lpfc_port_smphr_scr1_SHIFT 27 596#define lpfc_port_smphr_scr1_MASK 0x1 597#define lpfc_port_smphr_scr1_WORD word0 598#define lpfc_port_smphr_scr2_SHIFT 26 599#define lpfc_port_smphr_scr2_MASK 0x1 600#define lpfc_port_smphr_scr2_WORD word0 601#define lpfc_port_smphr_host_scratch_SHIFT 16 602#define lpfc_port_smphr_host_scratch_MASK 0xFF 603#define lpfc_port_smphr_host_scratch_WORD word0 604#define lpfc_port_smphr_port_status_SHIFT 0 605#define lpfc_port_smphr_port_status_MASK 0xFFFF 606#define lpfc_port_smphr_port_status_WORD word0 607 608#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 609#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 610#define LPFC_POST_STAGE_HOST_RDY 0x0002 611#define LPFC_POST_STAGE_BE_RESET 0x0003 612#define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 613#define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 614#define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 615#define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 616#define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 617#define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 618#define LPFC_POST_STAGE_DDR_TEST_START 0x0400 619#define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 620#define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 621#define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 622#define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 623#define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 624#define LPFC_POST_STAGE_ARMFW_START 0x0800 625#define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 626#define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 627#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 628#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 629#define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 630#define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 631#define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 632#define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 633#define LPFC_POST_STAGE_PARSE_XML 0x0B04 634#define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 635#define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 636#define LPFC_POST_STAGE_RC_DONE 0x0B07 637#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 638#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 639#define LPFC_POST_STAGE_PORT_READY 0xC000 640#define LPFC_POST_STAGE_PORT_UE 0xF000 641 642#define LPFC_CTL_PORT_STA_OFFSET 0x404 643#define lpfc_sliport_status_err_SHIFT 31 644#define lpfc_sliport_status_err_MASK 0x1 645#define lpfc_sliport_status_err_WORD word0 646#define lpfc_sliport_status_end_SHIFT 30 647#define lpfc_sliport_status_end_MASK 0x1 648#define lpfc_sliport_status_end_WORD word0 649#define lpfc_sliport_status_oti_SHIFT 29 650#define lpfc_sliport_status_oti_MASK 0x1 651#define lpfc_sliport_status_oti_WORD word0 652#define lpfc_sliport_status_rn_SHIFT 24 653#define lpfc_sliport_status_rn_MASK 0x1 654#define lpfc_sliport_status_rn_WORD word0 655#define lpfc_sliport_status_rdy_SHIFT 23 656#define lpfc_sliport_status_rdy_MASK 0x1 657#define lpfc_sliport_status_rdy_WORD word0 658#define MAX_IF_TYPE_2_RESETS 6 659 660#define LPFC_CTL_PORT_CTL_OFFSET 0x408 661#define lpfc_sliport_ctrl_end_SHIFT 30 662#define lpfc_sliport_ctrl_end_MASK 0x1 663#define lpfc_sliport_ctrl_end_WORD word0 664#define LPFC_SLIPORT_LITTLE_ENDIAN 0 665#define LPFC_SLIPORT_BIG_ENDIAN 1 666#define lpfc_sliport_ctrl_ip_SHIFT 27 667#define lpfc_sliport_ctrl_ip_MASK 0x1 668#define lpfc_sliport_ctrl_ip_WORD word0 669#define LPFC_SLIPORT_INIT_PORT 1 670 671#define LPFC_CTL_PORT_ER1_OFFSET 0x40C 672#define LPFC_CTL_PORT_ER2_OFFSET 0x410 673 674#define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 675#define lpfc_sliport_eqdelay_delay_SHIFT 16 676#define lpfc_sliport_eqdelay_delay_MASK 0xffff 677#define lpfc_sliport_eqdelay_delay_WORD word0 678#define lpfc_sliport_eqdelay_id_SHIFT 0 679#define lpfc_sliport_eqdelay_id_MASK 0xfff 680#define lpfc_sliport_eqdelay_id_WORD word0 681#define LPFC_SEC_TO_USEC 1000000 682 683/* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 684 * reside in BAR 2. 685 */ 686#define LPFC_SLIPORT_IF0_SMPHR 0x00AC 687 688#define LPFC_IMR_MASK_ALL 0xFFFFFFFF 689#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 690 691#define LPFC_HST_ISR0 0x0C18 692#define LPFC_HST_ISR1 0x0C1C 693#define LPFC_HST_ISR2 0x0C20 694#define LPFC_HST_ISR3 0x0C24 695#define LPFC_HST_ISR4 0x0C28 696 697#define LPFC_HST_IMR0 0x0C48 698#define LPFC_HST_IMR1 0x0C4C 699#define LPFC_HST_IMR2 0x0C50 700#define LPFC_HST_IMR3 0x0C54 701#define LPFC_HST_IMR4 0x0C58 702 703#define LPFC_HST_ISCR0 0x0C78 704#define LPFC_HST_ISCR1 0x0C7C 705#define LPFC_HST_ISCR2 0x0C80 706#define LPFC_HST_ISCR3 0x0C84 707#define LPFC_HST_ISCR4 0x0C88 708 709#define LPFC_SLI4_INTR0 BIT0 710#define LPFC_SLI4_INTR1 BIT1 711#define LPFC_SLI4_INTR2 BIT2 712#define LPFC_SLI4_INTR3 BIT3 713#define LPFC_SLI4_INTR4 BIT4 714#define LPFC_SLI4_INTR5 BIT5 715#define LPFC_SLI4_INTR6 BIT6 716#define LPFC_SLI4_INTR7 BIT7 717#define LPFC_SLI4_INTR8 BIT8 718#define LPFC_SLI4_INTR9 BIT9 719#define LPFC_SLI4_INTR10 BIT10 720#define LPFC_SLI4_INTR11 BIT11 721#define LPFC_SLI4_INTR12 BIT12 722#define LPFC_SLI4_INTR13 BIT13 723#define LPFC_SLI4_INTR14 BIT14 724#define LPFC_SLI4_INTR15 BIT15 725#define LPFC_SLI4_INTR16 BIT16 726#define LPFC_SLI4_INTR17 BIT17 727#define LPFC_SLI4_INTR18 BIT18 728#define LPFC_SLI4_INTR19 BIT19 729#define LPFC_SLI4_INTR20 BIT20 730#define LPFC_SLI4_INTR21 BIT21 731#define LPFC_SLI4_INTR22 BIT22 732#define LPFC_SLI4_INTR23 BIT23 733#define LPFC_SLI4_INTR24 BIT24 734#define LPFC_SLI4_INTR25 BIT25 735#define LPFC_SLI4_INTR26 BIT26 736#define LPFC_SLI4_INTR27 BIT27 737#define LPFC_SLI4_INTR28 BIT28 738#define LPFC_SLI4_INTR29 BIT29 739#define LPFC_SLI4_INTR30 BIT30 740#define LPFC_SLI4_INTR31 BIT31 741 742/* 743 * The Doorbell registers defined here exist in different BAR 744 * register sets depending on the UCNA Port's reported if_type 745 * value. For UCNA ports running SLI4 and if_type 0, they reside in 746 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 747 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 748 * BAR2. The offsets and base address are different, so the driver 749 * has to compute the register addresses accordingly 750 */ 751#define LPFC_ULP0_RQ_DOORBELL 0x00A0 752#define LPFC_ULP1_RQ_DOORBELL 0x00C0 753#define LPFC_IF6_RQ_DOORBELL 0x0080 754#define lpfc_rq_db_list_fm_num_posted_SHIFT 24 755#define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 756#define lpfc_rq_db_list_fm_num_posted_WORD word0 757#define lpfc_rq_db_list_fm_index_SHIFT 16 758#define lpfc_rq_db_list_fm_index_MASK 0x00FF 759#define lpfc_rq_db_list_fm_index_WORD word0 760#define lpfc_rq_db_list_fm_id_SHIFT 0 761#define lpfc_rq_db_list_fm_id_MASK 0xFFFF 762#define lpfc_rq_db_list_fm_id_WORD word0 763#define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 764#define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 765#define lpfc_rq_db_ring_fm_num_posted_WORD word0 766#define lpfc_rq_db_ring_fm_id_SHIFT 0 767#define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 768#define lpfc_rq_db_ring_fm_id_WORD word0 769 770#define LPFC_ULP0_WQ_DOORBELL 0x0040 771#define LPFC_ULP1_WQ_DOORBELL 0x0060 772#define lpfc_wq_db_list_fm_num_posted_SHIFT 24 773#define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 774#define lpfc_wq_db_list_fm_num_posted_WORD word0 775#define lpfc_wq_db_list_fm_index_SHIFT 16 776#define lpfc_wq_db_list_fm_index_MASK 0x00FF 777#define lpfc_wq_db_list_fm_index_WORD word0 778#define lpfc_wq_db_list_fm_id_SHIFT 0 779#define lpfc_wq_db_list_fm_id_MASK 0xFFFF 780#define lpfc_wq_db_list_fm_id_WORD word0 781#define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 782#define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 783#define lpfc_wq_db_ring_fm_num_posted_WORD word0 784#define lpfc_wq_db_ring_fm_id_SHIFT 0 785#define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 786#define lpfc_wq_db_ring_fm_id_WORD word0 787 788#define LPFC_IF6_WQ_DOORBELL 0x0040 789#define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 790#define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 791#define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 792#define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 793#define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 794#define lpfc_if6_wq_db_list_fm_dpp_WORD word0 795#define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 796#define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 797#define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 798#define lpfc_if6_wq_db_list_fm_id_SHIFT 0 799#define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 800#define lpfc_if6_wq_db_list_fm_id_WORD word0 801 802#define LPFC_EQCQ_DOORBELL 0x0120 803#define lpfc_eqcq_doorbell_se_SHIFT 31 804#define lpfc_eqcq_doorbell_se_MASK 0x0001 805#define lpfc_eqcq_doorbell_se_WORD word0 806#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 807#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 808#define lpfc_eqcq_doorbell_arm_SHIFT 29 809#define lpfc_eqcq_doorbell_arm_MASK 0x0001 810#define lpfc_eqcq_doorbell_arm_WORD word0 811#define lpfc_eqcq_doorbell_num_released_SHIFT 16 812#define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 813#define lpfc_eqcq_doorbell_num_released_WORD word0 814#define lpfc_eqcq_doorbell_qt_SHIFT 10 815#define lpfc_eqcq_doorbell_qt_MASK 0x0001 816#define lpfc_eqcq_doorbell_qt_WORD word0 817#define LPFC_QUEUE_TYPE_COMPLETION 0 818#define LPFC_QUEUE_TYPE_EVENT 1 819#define lpfc_eqcq_doorbell_eqci_SHIFT 9 820#define lpfc_eqcq_doorbell_eqci_MASK 0x0001 821#define lpfc_eqcq_doorbell_eqci_WORD word0 822#define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 823#define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 824#define lpfc_eqcq_doorbell_cqid_lo_WORD word0 825#define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 826#define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 827#define lpfc_eqcq_doorbell_cqid_hi_WORD word0 828#define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 829#define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 830#define lpfc_eqcq_doorbell_eqid_lo_WORD word0 831#define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 832#define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 833#define lpfc_eqcq_doorbell_eqid_hi_WORD word0 834#define LPFC_CQID_HI_FIELD_SHIFT 10 835#define LPFC_EQID_HI_FIELD_SHIFT 9 836 837#define LPFC_IF6_CQ_DOORBELL 0x00C0 838#define lpfc_if6_cq_doorbell_se_SHIFT 31 839#define lpfc_if6_cq_doorbell_se_MASK 0x0001 840#define lpfc_if6_cq_doorbell_se_WORD word0 841#define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 842#define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 843#define lpfc_if6_cq_doorbell_arm_SHIFT 29 844#define lpfc_if6_cq_doorbell_arm_MASK 0x0001 845#define lpfc_if6_cq_doorbell_arm_WORD word0 846#define lpfc_if6_cq_doorbell_num_released_SHIFT 16 847#define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 848#define lpfc_if6_cq_doorbell_num_released_WORD word0 849#define lpfc_if6_cq_doorbell_cqid_SHIFT 0 850#define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 851#define lpfc_if6_cq_doorbell_cqid_WORD word0 852 853#define LPFC_IF6_EQ_DOORBELL 0x0120 854#define lpfc_if6_eq_doorbell_io_SHIFT 31 855#define lpfc_if6_eq_doorbell_io_MASK 0x0001 856#define lpfc_if6_eq_doorbell_io_WORD word0 857#define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 858#define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 859#define lpfc_if6_eq_doorbell_arm_SHIFT 29 860#define lpfc_if6_eq_doorbell_arm_MASK 0x0001 861#define lpfc_if6_eq_doorbell_arm_WORD word0 862#define lpfc_if6_eq_doorbell_num_released_SHIFT 16 863#define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 864#define lpfc_if6_eq_doorbell_num_released_WORD word0 865#define lpfc_if6_eq_doorbell_eqid_SHIFT 0 866#define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 867#define lpfc_if6_eq_doorbell_eqid_WORD word0 868 869#define LPFC_BMBX 0x0160 870#define lpfc_bmbx_addr_SHIFT 2 871#define lpfc_bmbx_addr_MASK 0x3FFFFFFF 872#define lpfc_bmbx_addr_WORD word0 873#define lpfc_bmbx_hi_SHIFT 1 874#define lpfc_bmbx_hi_MASK 0x0001 875#define lpfc_bmbx_hi_WORD word0 876#define lpfc_bmbx_rdy_SHIFT 0 877#define lpfc_bmbx_rdy_MASK 0x0001 878#define lpfc_bmbx_rdy_WORD word0 879 880#define LPFC_MQ_DOORBELL 0x0140 881#define LPFC_IF6_MQ_DOORBELL 0x0160 882#define lpfc_mq_doorbell_num_posted_SHIFT 16 883#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 884#define lpfc_mq_doorbell_num_posted_WORD word0 885#define lpfc_mq_doorbell_id_SHIFT 0 886#define lpfc_mq_doorbell_id_MASK 0xFFFF 887#define lpfc_mq_doorbell_id_WORD word0 888 889struct lpfc_sli4_cfg_mhdr { 890 uint32_t word1; 891#define lpfc_mbox_hdr_emb_SHIFT 0 892#define lpfc_mbox_hdr_emb_MASK 0x00000001 893#define lpfc_mbox_hdr_emb_WORD word1 894#define lpfc_mbox_hdr_sge_cnt_SHIFT 3 895#define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 896#define lpfc_mbox_hdr_sge_cnt_WORD word1 897 uint32_t payload_length; 898 uint32_t tag_lo; 899 uint32_t tag_hi; 900 uint32_t reserved5; 901}; 902 903union lpfc_sli4_cfg_shdr { 904 struct { 905 uint32_t word6; 906#define lpfc_mbox_hdr_opcode_SHIFT 0 907#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 908#define lpfc_mbox_hdr_opcode_WORD word6 909#define lpfc_mbox_hdr_subsystem_SHIFT 8 910#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 911#define lpfc_mbox_hdr_subsystem_WORD word6 912#define lpfc_mbox_hdr_port_number_SHIFT 16 913#define lpfc_mbox_hdr_port_number_MASK 0x000000FF 914#define lpfc_mbox_hdr_port_number_WORD word6 915#define lpfc_mbox_hdr_domain_SHIFT 24 916#define lpfc_mbox_hdr_domain_MASK 0x000000FF 917#define lpfc_mbox_hdr_domain_WORD word6 918 uint32_t timeout; 919 uint32_t request_length; 920 uint32_t word9; 921#define lpfc_mbox_hdr_version_SHIFT 0 922#define lpfc_mbox_hdr_version_MASK 0x000000FF 923#define lpfc_mbox_hdr_version_WORD word9 924#define lpfc_mbox_hdr_pf_num_SHIFT 16 925#define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 926#define lpfc_mbox_hdr_pf_num_WORD word9 927#define lpfc_mbox_hdr_vh_num_SHIFT 24 928#define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 929#define lpfc_mbox_hdr_vh_num_WORD word9 930#define LPFC_Q_CREATE_VERSION_2 2 931#define LPFC_Q_CREATE_VERSION_1 1 932#define LPFC_Q_CREATE_VERSION_0 0 933#define LPFC_OPCODE_VERSION_0 0 934#define LPFC_OPCODE_VERSION_1 1 935 } request; 936 struct { 937 uint32_t word6; 938#define lpfc_mbox_hdr_opcode_SHIFT 0 939#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 940#define lpfc_mbox_hdr_opcode_WORD word6 941#define lpfc_mbox_hdr_subsystem_SHIFT 8 942#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 943#define lpfc_mbox_hdr_subsystem_WORD word6 944#define lpfc_mbox_hdr_domain_SHIFT 24 945#define lpfc_mbox_hdr_domain_MASK 0x000000FF 946#define lpfc_mbox_hdr_domain_WORD word6 947 uint32_t word7; 948#define lpfc_mbox_hdr_status_SHIFT 0 949#define lpfc_mbox_hdr_status_MASK 0x000000FF 950#define lpfc_mbox_hdr_status_WORD word7 951#define lpfc_mbox_hdr_add_status_SHIFT 8 952#define lpfc_mbox_hdr_add_status_MASK 0x000000FF 953#define lpfc_mbox_hdr_add_status_WORD word7 954 uint32_t response_length; 955 uint32_t actual_response_length; 956 } response; 957}; 958 959/* Mailbox Header structures. 960 * struct mbox_header is defined for first generation SLI4_CFG mailbox 961 * calls deployed for BE-based ports. 962 * 963 * struct sli4_mbox_header is defined for second generation SLI4 964 * ports that don't deploy the SLI4_CFG mechanism. 965 */ 966struct mbox_header { 967 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 968 union lpfc_sli4_cfg_shdr cfg_shdr; 969}; 970 971#define LPFC_EXTENT_LOCAL 0 972#define LPFC_TIMEOUT_DEFAULT 0 973#define LPFC_EXTENT_VERSION_DEFAULT 0 974 975/* Subsystem Definitions */ 976#define LPFC_MBOX_SUBSYSTEM_NA 0x0 977#define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 978#define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 979#define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 980 981/* Device Specific Definitions */ 982 983/* The HOST ENDIAN defines are in Big Endian format. */ 984#define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 985#define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 986 987/* Common Opcodes */ 988#define LPFC_MBOX_OPCODE_NA 0x00 989#define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 990#define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 991#define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 992#define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 993#define LPFC_MBOX_OPCODE_NOP 0x21 994#define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 995#define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 996#define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 997#define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 998#define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 999#define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1000#define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
1001#define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1002#define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1003#define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1004#define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1005#define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1006#define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1007#define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1008#define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1009#define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1010#define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1011#define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1012#define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1013#define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1014#define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1015#define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1016#define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1017#define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1018#define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1019#define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1020#define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1021#define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1022#define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1023#define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1024#define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1025#define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1026#define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1027 1028/* FCoE Opcodes */ 1029#define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1030#define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1031#define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1032#define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1033#define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1034#define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1035#define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1036#define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1037#define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1038#define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1039#define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1040#define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1041#define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1042#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1043#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1044#define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1045 1046/* Low level Opcodes */ 1047#define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1048 1049/* Mailbox command structures */ 1050struct eq_context { 1051 uint32_t word0; 1052#define lpfc_eq_context_size_SHIFT 31 1053#define lpfc_eq_context_size_MASK 0x00000001 1054#define lpfc_eq_context_size_WORD word0 1055#define LPFC_EQE_SIZE_4 0x0 1056#define LPFC_EQE_SIZE_16 0x1 1057#define lpfc_eq_context_valid_SHIFT 29 1058#define lpfc_eq_context_valid_MASK 0x00000001 1059#define lpfc_eq_context_valid_WORD word0 1060#define lpfc_eq_context_autovalid_SHIFT 28 1061#define lpfc_eq_context_autovalid_MASK 0x00000001 1062#define lpfc_eq_context_autovalid_WORD word0 1063 uint32_t word1; 1064#define lpfc_eq_context_count_SHIFT 26 1065#define lpfc_eq_context_count_MASK 0x00000003 1066#define lpfc_eq_context_count_WORD word1 1067#define LPFC_EQ_CNT_256 0x0 1068#define LPFC_EQ_CNT_512 0x1 1069#define LPFC_EQ_CNT_1024 0x2 1070#define LPFC_EQ_CNT_2048 0x3 1071#define LPFC_EQ_CNT_4096 0x4 1072 uint32_t word2; 1073#define lpfc_eq_context_delay_multi_SHIFT 13 1074#define lpfc_eq_context_delay_multi_MASK 0x000003FF 1075#define lpfc_eq_context_delay_multi_WORD word2 1076 uint32_t reserved3; 1077}; 1078 1079struct eq_delay_info { 1080 uint32_t eq_id; 1081 uint32_t phase; 1082 uint32_t delay_multi; 1083}; 1084#define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1085 1086struct sgl_page_pairs { 1087 uint32_t sgl_pg0_addr_lo; 1088 uint32_t sgl_pg0_addr_hi; 1089 uint32_t sgl_pg1_addr_lo; 1090 uint32_t sgl_pg1_addr_hi; 1091}; 1092 1093struct lpfc_mbx_post_sgl_pages { 1094 struct mbox_header header; 1095 uint32_t word0; 1096#define lpfc_post_sgl_pages_xri_SHIFT 0 1097#define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1098#define lpfc_post_sgl_pages_xri_WORD word0 1099#define lpfc_post_sgl_pages_xricnt_SHIFT 16 1100#define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1101#define lpfc_post_sgl_pages_xricnt_WORD word0 1102 struct sgl_page_pairs sgl_pg_pairs[1]; 1103}; 1104 1105/* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1106struct lpfc_mbx_post_uembed_sgl_page1 { 1107 union lpfc_sli4_cfg_shdr cfg_shdr; 1108 uint32_t word0; 1109 struct sgl_page_pairs sgl_pg_pairs; 1110}; 1111 1112struct lpfc_mbx_sge { 1113 uint32_t pa_lo; 1114 uint32_t pa_hi; 1115 uint32_t length; 1116}; 1117 1118struct lpfc_mbx_nembed_cmd { 1119 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1120#define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1121 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1122}; 1123 1124struct lpfc_mbx_nembed_sge_virt { 1125 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1126}; 1127 1128struct lpfc_mbx_eq_create { 1129 struct mbox_header header; 1130 union { 1131 struct { 1132 uint32_t word0; 1133#define lpfc_mbx_eq_create_num_pages_SHIFT 0 1134#define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1135#define lpfc_mbx_eq_create_num_pages_WORD word0 1136 struct eq_context context; 1137 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1138 } request; 1139 struct { 1140 uint32_t word0; 1141#define lpfc_mbx_eq_create_q_id_SHIFT 0 1142#define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1143#define lpfc_mbx_eq_create_q_id_WORD word0 1144 } response; 1145 } u; 1146}; 1147 1148struct lpfc_mbx_modify_eq_delay { 1149 struct mbox_header header; 1150 union { 1151 struct { 1152 uint32_t num_eq; 1153 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1154 } request; 1155 struct { 1156 uint32_t word0; 1157 } response; 1158 } u; 1159}; 1160 1161struct lpfc_mbx_eq_destroy { 1162 struct mbox_header header; 1163 union { 1164 struct { 1165 uint32_t word0; 1166#define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1167#define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1168#define lpfc_mbx_eq_destroy_q_id_WORD word0 1169 } request; 1170 struct { 1171 uint32_t word0; 1172 } response; 1173 } u; 1174}; 1175 1176struct lpfc_mbx_nop { 1177 struct mbox_header header; 1178 uint32_t context[2]; 1179}; 1180 1181 1182 1183struct lpfc_mbx_set_ras_fwlog { 1184 struct mbox_header header; 1185 union { 1186 struct { 1187 uint32_t word4; 1188#define lpfc_fwlog_enable_SHIFT 0 1189#define lpfc_fwlog_enable_MASK 0x00000001 1190#define lpfc_fwlog_enable_WORD word4 1191#define lpfc_fwlog_loglvl_SHIFT 8 1192#define lpfc_fwlog_loglvl_MASK 0x0000000F 1193#define lpfc_fwlog_loglvl_WORD word4 1194#define lpfc_fwlog_ra_SHIFT 15 1195#define lpfc_fwlog_ra_WORD 0x00000008 1196#define lpfc_fwlog_buffcnt_SHIFT 16 1197#define lpfc_fwlog_buffcnt_MASK 0x000000FF 1198#define lpfc_fwlog_buffcnt_WORD word4 1199#define lpfc_fwlog_buffsz_SHIFT 24 1200#define lpfc_fwlog_buffsz_MASK 0x000000FF 1201#define lpfc_fwlog_buffsz_WORD word4 1202 uint32_t word5; 1203#define lpfc_fwlog_acqe_SHIFT 0 1204#define lpfc_fwlog_acqe_MASK 0x0000FFFF 1205#define lpfc_fwlog_acqe_WORD word5 1206#define lpfc_fwlog_cqid_SHIFT 16 1207#define lpfc_fwlog_cqid_MASK 0x0000FFFF 1208#define lpfc_fwlog_cqid_WORD word5 1209#define LPFC_MAX_FWLOG_PAGE 16 1210 struct dma_address lwpd; 1211 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1212 } request; 1213 struct { 1214 uint32_t word0; 1215 } response; 1216 } u; 1217}; 1218 1219 1220struct cq_context { 1221 uint32_t word0; 1222#define lpfc_cq_context_event_SHIFT 31 1223#define lpfc_cq_context_event_MASK 0x00000001 1224#define lpfc_cq_context_event_WORD word0 1225#define lpfc_cq_context_valid_SHIFT 29 1226#define lpfc_cq_context_valid_MASK 0x00000001 1227#define lpfc_cq_context_valid_WORD word0 1228#define lpfc_cq_context_count_SHIFT 27 1229#define lpfc_cq_context_count_MASK 0x00000003 1230#define lpfc_cq_context_count_WORD word0 1231#define LPFC_CQ_CNT_256 0x0 1232#define LPFC_CQ_CNT_512 0x1 1233#define LPFC_CQ_CNT_1024 0x2 1234#define LPFC_CQ_CNT_WORD7 0x3 1235#define lpfc_cq_context_autovalid_SHIFT 15 1236#define lpfc_cq_context_autovalid_MASK 0x00000001 1237#define lpfc_cq_context_autovalid_WORD word0 1238 uint32_t word1; 1239#define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1240#define lpfc_cq_eq_id_MASK 0x000000FF 1241#define lpfc_cq_eq_id_WORD word1 1242#define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1243#define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1244#define lpfc_cq_eq_id_2_WORD word1 1245 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1246 uint32_t reserved1; 1247}; 1248 1249struct lpfc_mbx_cq_create { 1250 struct mbox_header header; 1251 union { 1252 struct { 1253 uint32_t word0; 1254#define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1255#define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1256#define lpfc_mbx_cq_create_page_size_WORD word0 1257#define lpfc_mbx_cq_create_num_pages_SHIFT 0 1258#define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1259#define lpfc_mbx_cq_create_num_pages_WORD word0 1260 struct cq_context context; 1261 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1262 } request; 1263 struct { 1264 uint32_t word0; 1265#define lpfc_mbx_cq_create_q_id_SHIFT 0 1266#define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1267#define lpfc_mbx_cq_create_q_id_WORD word0 1268 } response; 1269 } u; 1270}; 1271 1272struct lpfc_mbx_cq_create_set { 1273 union lpfc_sli4_cfg_shdr cfg_shdr; 1274 union { 1275 struct { 1276 uint32_t word0; 1277#define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1278#define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1279#define lpfc_mbx_cq_create_set_page_size_WORD word0 1280#define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1281#define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1282#define lpfc_mbx_cq_create_set_num_pages_WORD word0 1283 uint32_t word1; 1284#define lpfc_mbx_cq_create_set_evt_SHIFT 31 1285#define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1286#define lpfc_mbx_cq_create_set_evt_WORD word1 1287#define lpfc_mbx_cq_create_set_valid_SHIFT 29 1288#define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1289#define lpfc_mbx_cq_create_set_valid_WORD word1 1290#define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1291#define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1292#define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1293#define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1294#define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1295#define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1296#define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1297#define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1298#define lpfc_mbx_cq_create_set_autovalid_WORD word1 1299#define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1300#define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1301#define lpfc_mbx_cq_create_set_nodelay_WORD word1 1302#define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1303#define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1304#define lpfc_mbx_cq_create_set_clswm_WORD word1 1305 uint32_t word2; 1306#define lpfc_mbx_cq_create_set_arm_SHIFT 31 1307#define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1308#define lpfc_mbx_cq_create_set_arm_WORD word2 1309#define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1310#define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1311#define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1312#define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1313#define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1314#define lpfc_mbx_cq_create_set_num_cq_WORD word2 1315 uint32_t word3; 1316#define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1317#define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1318#define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1319#define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1320#define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1321#define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1322 uint32_t word4; 1323#define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1324#define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1325#define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1326#define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1327#define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1328#define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1329 uint32_t word5; 1330#define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1331#define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1332#define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1333#define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1334#define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1335#define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1336 uint32_t word6; 1337#define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1338#define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1339#define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1340#define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1341#define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1342#define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1343 uint32_t word7; 1344#define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1345#define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1346#define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1347#define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1348#define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1349#define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1350 uint32_t word8; 1351#define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1352#define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1353#define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1354#define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1355#define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1356#define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1357 uint32_t word9; 1358#define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1359#define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1360#define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1361#define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1362#define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1363#define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1364 uint32_t word10; 1365#define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1366#define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1367#define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1368#define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1369#define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1370#define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1371 struct dma_address page[1]; 1372 } request; 1373 struct { 1374 uint32_t word0; 1375#define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1376#define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1377#define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1378#define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1379#define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1380#define lpfc_mbx_cq_create_set_base_id_WORD word0 1381 } response; 1382 } u; 1383}; 1384 1385struct lpfc_mbx_cq_destroy { 1386 struct mbox_header header; 1387 union { 1388 struct { 1389 uint32_t word0; 1390#define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1391#define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1392#define lpfc_mbx_cq_destroy_q_id_WORD word0 1393 } request; 1394 struct { 1395 uint32_t word0; 1396 } response; 1397 } u; 1398}; 1399 1400struct wq_context { 1401 uint32_t reserved0; 1402 uint32_t reserved1; 1403 uint32_t reserved2; 1404 uint32_t reserved3; 1405}; 1406 1407struct lpfc_mbx_wq_create { 1408 struct mbox_header header; 1409 union { 1410 struct { /* Version 0 Request */ 1411 uint32_t word0; 1412#define lpfc_mbx_wq_create_num_pages_SHIFT 0 1413#define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1414#define lpfc_mbx_wq_create_num_pages_WORD word0 1415#define lpfc_mbx_wq_create_dua_SHIFT 8 1416#define lpfc_mbx_wq_create_dua_MASK 0x00000001 1417#define lpfc_mbx_wq_create_dua_WORD word0 1418#define lpfc_mbx_wq_create_cq_id_SHIFT 16 1419#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1420#define lpfc_mbx_wq_create_cq_id_WORD word0 1421 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1422 uint32_t word9; 1423#define lpfc_mbx_wq_create_bua_SHIFT 0 1424#define lpfc_mbx_wq_create_bua_MASK 0x00000001 1425#define lpfc_mbx_wq_create_bua_WORD word9 1426#define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1427#define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1428#define lpfc_mbx_wq_create_ulp_num_WORD word9 1429 } request; 1430 struct { /* Version 1 Request */ 1431 uint32_t word0; /* Word 0 is the same as in v0 */ 1432 uint32_t word1; 1433#define lpfc_mbx_wq_create_page_size_SHIFT 0 1434#define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1435#define lpfc_mbx_wq_create_page_size_WORD word1 1436#define LPFC_WQ_PAGE_SIZE_4096 0x1 1437#define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1438#define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1439#define lpfc_mbx_wq_create_dpp_req_WORD word1 1440#define lpfc_mbx_wq_create_doe_SHIFT 14 1441#define lpfc_mbx_wq_create_doe_MASK 0x00000001 1442#define lpfc_mbx_wq_create_doe_WORD word1 1443#define lpfc_mbx_wq_create_toe_SHIFT 13 1444#define lpfc_mbx_wq_create_toe_MASK 0x00000001 1445#define lpfc_mbx_wq_create_toe_WORD word1 1446#define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1447#define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1448#define lpfc_mbx_wq_create_wqe_size_WORD word1 1449#define LPFC_WQ_WQE_SIZE_64 0x5 1450#define LPFC_WQ_WQE_SIZE_128 0x6 1451#define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1452#define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1453#define lpfc_mbx_wq_create_wqe_count_WORD word1 1454 uint32_t word2; 1455 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1456 } request_1; 1457 struct { 1458 uint32_t word0; 1459#define lpfc_mbx_wq_create_q_id_SHIFT 0 1460#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1461#define lpfc_mbx_wq_create_q_id_WORD word0 1462 uint32_t doorbell_offset; 1463 uint32_t word2; 1464#define lpfc_mbx_wq_create_bar_set_SHIFT 0 1465#define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1466#define lpfc_mbx_wq_create_bar_set_WORD word2 1467#define WQ_PCI_BAR_0_AND_1 0x00 1468#define WQ_PCI_BAR_2_AND_3 0x01 1469#define WQ_PCI_BAR_4_AND_5 0x02 1470#define lpfc_mbx_wq_create_db_format_SHIFT 16 1471#define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1472#define lpfc_mbx_wq_create_db_format_WORD word2 1473 } response; 1474 struct { 1475 uint32_t word0; 1476#define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1477#define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1478#define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1479#define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1480#define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1481#define lpfc_mbx_wq_create_v1_q_id_WORD word0 1482 uint32_t word1; 1483#define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1484#define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1485#define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1486 uint32_t doorbell_offset; 1487 uint32_t word3; 1488#define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1489#define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1490#define lpfc_mbx_wq_create_dpp_id_WORD word3 1491#define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1492#define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1493#define lpfc_mbx_wq_create_dpp_bar_WORD word3 1494 uint32_t dpp_offset; 1495 } response_1; 1496 } u; 1497}; 1498 1499struct lpfc_mbx_wq_destroy { 1500 struct mbox_header header; 1501 union { 1502 struct { 1503 uint32_t word0; 1504#define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1505#define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1506#define lpfc_mbx_wq_destroy_q_id_WORD word0 1507 } request; 1508 struct { 1509 uint32_t word0; 1510 } response; 1511 } u; 1512}; 1513 1514#define LPFC_HDR_BUF_SIZE 128 1515#define LPFC_DATA_BUF_SIZE 2048 1516#define LPFC_NVMET_DATA_BUF_SIZE 128 1517struct rq_context { 1518 uint32_t word0; 1519#define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1520#define lpfc_rq_context_rqe_count_MASK 0x0000000F 1521#define lpfc_rq_context_rqe_count_WORD word0 1522#define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1523#define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1524#define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1525#define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1526#define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1527#define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1528#define lpfc_rq_context_rqe_count_1_WORD word0 1529#define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1530#define lpfc_rq_context_rqe_size_MASK 0x0000000F 1531#define lpfc_rq_context_rqe_size_WORD word0 1532#define LPFC_RQE_SIZE_8 2 1533#define LPFC_RQE_SIZE_16 3 1534#define LPFC_RQE_SIZE_32 4 1535#define LPFC_RQE_SIZE_64 5 1536#define LPFC_RQE_SIZE_128 6 1537#define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1538#define lpfc_rq_context_page_size_MASK 0x000000FF 1539#define lpfc_rq_context_page_size_WORD word0 1540#define LPFC_RQ_PAGE_SIZE_4096 0x1 1541 uint32_t word1; 1542#define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1543#define lpfc_rq_context_data_size_MASK 0x0000FFFF 1544#define lpfc_rq_context_data_size_WORD word1 1545#define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1546#define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1547#define lpfc_rq_context_hdr_size_WORD word1 1548 uint32_t word2; 1549#define lpfc_rq_context_cq_id_SHIFT 16 1550#define lpfc_rq_context_cq_id_MASK 0x000003FF 1551#define lpfc_rq_context_cq_id_WORD word2 1552#define lpfc_rq_context_buf_size_SHIFT 0 1553#define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1554#define lpfc_rq_context_buf_size_WORD word2 1555#define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1556#define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1557#define lpfc_rq_context_base_cq_WORD word2 1558 uint32_t buffer_size; /* Version 1 Only */ 1559}; 1560 1561struct lpfc_mbx_rq_create { 1562 struct mbox_header header; 1563 union { 1564 struct { 1565 uint32_t word0; 1566#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1567#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1568#define lpfc_mbx_rq_create_num_pages_WORD word0 1569#define lpfc_mbx_rq_create_dua_SHIFT 16 1570#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1571#define lpfc_mbx_rq_create_dua_WORD word0 1572#define lpfc_mbx_rq_create_bqu_SHIFT 17 1573#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1574#define lpfc_mbx_rq_create_bqu_WORD word0 1575#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1576#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1577#define lpfc_mbx_rq_create_ulp_num_WORD word0 1578 struct rq_context context; 1579 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1580 } request; 1581 struct { 1582 uint32_t word0; 1583#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1584#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1585#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1586#define lpfc_mbx_rq_create_q_id_SHIFT 0 1587#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1588#define lpfc_mbx_rq_create_q_id_WORD word0 1589 uint32_t doorbell_offset; 1590 uint32_t word2; 1591#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1592#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1593#define lpfc_mbx_rq_create_bar_set_WORD word2 1594#define lpfc_mbx_rq_create_db_format_SHIFT 16 1595#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1596#define lpfc_mbx_rq_create_db_format_WORD word2 1597 } response; 1598 } u; 1599}; 1600 1601struct lpfc_mbx_rq_create_v2 { 1602 union lpfc_sli4_cfg_shdr cfg_shdr; 1603 union { 1604 struct { 1605 uint32_t word0; 1606#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1607#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1608#define lpfc_mbx_rq_create_num_pages_WORD word0 1609#define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1610#define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1611#define lpfc_mbx_rq_create_rq_cnt_WORD word0 1612#define lpfc_mbx_rq_create_dua_SHIFT 16 1613#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1614#define lpfc_mbx_rq_create_dua_WORD word0 1615#define lpfc_mbx_rq_create_bqu_SHIFT 17 1616#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1617#define lpfc_mbx_rq_create_bqu_WORD word0 1618#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1619#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1620#define lpfc_mbx_rq_create_ulp_num_WORD word0 1621#define lpfc_mbx_rq_create_dim_SHIFT 29 1622#define lpfc_mbx_rq_create_dim_MASK 0x00000001 1623#define lpfc_mbx_rq_create_dim_WORD word0 1624#define lpfc_mbx_rq_create_dfd_SHIFT 30 1625#define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1626#define lpfc_mbx_rq_create_dfd_WORD word0 1627#define lpfc_mbx_rq_create_dnb_SHIFT 31 1628#define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1629#define lpfc_mbx_rq_create_dnb_WORD word0 1630 struct rq_context context; 1631 struct dma_address page[1]; 1632 } request; 1633 struct { 1634 uint32_t word0; 1635#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1636#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1637#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1638#define lpfc_mbx_rq_create_q_id_SHIFT 0 1639#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1640#define lpfc_mbx_rq_create_q_id_WORD word0 1641 uint32_t doorbell_offset; 1642 uint32_t word2; 1643#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1644#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1645#define lpfc_mbx_rq_create_bar_set_WORD word2 1646#define lpfc_mbx_rq_create_db_format_SHIFT 16 1647#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1648#define lpfc_mbx_rq_create_db_format_WORD word2 1649 } response; 1650 } u; 1651}; 1652 1653struct lpfc_mbx_rq_destroy { 1654 struct mbox_header header; 1655 union { 1656 struct { 1657 uint32_t word0; 1658#define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1659#define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1660#define lpfc_mbx_rq_destroy_q_id_WORD word0 1661 } request; 1662 struct { 1663 uint32_t word0; 1664 } response; 1665 } u; 1666}; 1667 1668struct mq_context { 1669 uint32_t word0; 1670#define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1671#define lpfc_mq_context_cq_id_MASK 0x000003FF 1672#define lpfc_mq_context_cq_id_WORD word0 1673#define lpfc_mq_context_ring_size_SHIFT 16 1674#define lpfc_mq_context_ring_size_MASK 0x0000000F 1675#define lpfc_mq_context_ring_size_WORD word0 1676#define LPFC_MQ_RING_SIZE_16 0x5 1677#define LPFC_MQ_RING_SIZE_32 0x6 1678#define LPFC_MQ_RING_SIZE_64 0x7 1679#define LPFC_MQ_RING_SIZE_128 0x8 1680 uint32_t word1; 1681#define lpfc_mq_context_valid_SHIFT 31 1682#define lpfc_mq_context_valid_MASK 0x00000001 1683#define lpfc_mq_context_valid_WORD word1 1684 uint32_t reserved2; 1685 uint32_t reserved3; 1686}; 1687 1688struct lpfc_mbx_mq_create { 1689 struct mbox_header header; 1690 union { 1691 struct { 1692 uint32_t word0; 1693#define lpfc_mbx_mq_create_num_pages_SHIFT 0 1694#define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1695#define lpfc_mbx_mq_create_num_pages_WORD word0 1696 struct mq_context context; 1697 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1698 } request; 1699 struct { 1700 uint32_t word0; 1701#define lpfc_mbx_mq_create_q_id_SHIFT 0 1702#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1703#define lpfc_mbx_mq_create_q_id_WORD word0 1704 } response; 1705 } u; 1706}; 1707 1708struct lpfc_mbx_mq_create_ext { 1709 struct mbox_header header; 1710 union { 1711 struct { 1712 uint32_t word0; 1713#define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1714#define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1715#define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1716#define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1717#define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1718#define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1719 uint32_t async_evt_bmap; 1720#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1721#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1722#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1723#define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1724#define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1725#define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1726#define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1727#define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1728#define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1729#define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1730#define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1731#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1732#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1733#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1734#define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1735#define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1736#define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1737#define LPFC_EVT_CODE_FC_NO_LINK 0x0 1738#define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1739#define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1740#define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1741#define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1742#define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1743#define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1744#define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1745#define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1746#define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1747 struct mq_context context; 1748 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1749 } request; 1750 struct { 1751 uint32_t word0; 1752#define lpfc_mbx_mq_create_q_id_SHIFT 0 1753#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1754#define lpfc_mbx_mq_create_q_id_WORD word0 1755 } response; 1756 } u; 1757#define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1758#define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1759#define LPFC_ASYNC_EVENT_GROUP5 0x20 1760}; 1761 1762struct lpfc_mbx_mq_destroy { 1763 struct mbox_header header; 1764 union { 1765 struct { 1766 uint32_t word0; 1767#define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1768#define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1769#define lpfc_mbx_mq_destroy_q_id_WORD word0 1770 } request; 1771 struct { 1772 uint32_t word0; 1773 } response; 1774 } u; 1775}; 1776 1777/* Start Gen 2 SLI4 Mailbox definitions: */ 1778 1779/* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1780#define LPFC_RSC_TYPE_FCOE_VFI 0x20 1781#define LPFC_RSC_TYPE_FCOE_VPI 0x21 1782#define LPFC_RSC_TYPE_FCOE_RPI 0x22 1783#define LPFC_RSC_TYPE_FCOE_XRI 0x23 1784 1785struct lpfc_mbx_get_rsrc_extent_info { 1786 struct mbox_header header; 1787 union { 1788 struct { 1789 uint32_t word4; 1790#define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1791#define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1792#define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1793 } req; 1794 struct { 1795 uint32_t word4; 1796#define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1797#define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1798#define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1799#define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1800#define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1801#define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1802 } rsp; 1803 } u; 1804}; 1805 1806struct lpfc_mbx_query_fw_config { 1807 struct mbox_header header; 1808 struct { 1809 uint32_t config_number; 1810#define LPFC_FC_FCOE 0x00000007 1811 uint32_t asic_revision; 1812 uint32_t physical_port; 1813 uint32_t function_mode; 1814#define LPFC_FCOE_INI_MODE 0x00000040 1815#define LPFC_FCOE_TGT_MODE 0x00000080 1816#define LPFC_DUA_MODE 0x00000800 1817 uint32_t ulp0_mode; 1818#define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1819#define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1820 uint32_t ulp0_nap_words[12]; 1821 uint32_t ulp1_mode; 1822 uint32_t ulp1_nap_words[12]; 1823 uint32_t function_capabilities; 1824 uint32_t cqid_base; 1825 uint32_t cqid_tot; 1826 uint32_t eqid_base; 1827 uint32_t eqid_tot; 1828 uint32_t ulp0_nap2_words[2]; 1829 uint32_t ulp1_nap2_words[2]; 1830 } rsp; 1831}; 1832 1833struct lpfc_mbx_set_beacon_config { 1834 struct mbox_header header; 1835 uint32_t word4; 1836#define lpfc_mbx_set_beacon_port_num_SHIFT 0 1837#define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1838#define lpfc_mbx_set_beacon_port_num_WORD word4 1839#define lpfc_mbx_set_beacon_port_type_SHIFT 6 1840#define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1841#define lpfc_mbx_set_beacon_port_type_WORD word4 1842#define lpfc_mbx_set_beacon_state_SHIFT 8 1843#define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1844#define lpfc_mbx_set_beacon_state_WORD word4 1845#define lpfc_mbx_set_beacon_duration_SHIFT 16 1846#define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1847#define lpfc_mbx_set_beacon_duration_WORD word4 1848 1849/* COMMON_SET_BEACON_CONFIG_V1 */ 1850#define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1851#define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1852#define lpfc_mbx_set_beacon_duration_v1_WORD word4 1853 uint32_t word5; /* RESERVED */ 1854}; 1855 1856struct lpfc_id_range { 1857 uint32_t word5; 1858#define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1859#define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1860#define lpfc_mbx_rsrc_id_word4_0_WORD word5 1861#define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1862#define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1863#define lpfc_mbx_rsrc_id_word4_1_WORD word5 1864}; 1865 1866struct lpfc_mbx_set_link_diag_state { 1867 struct mbox_header header; 1868 union { 1869 struct { 1870 uint32_t word0; 1871#define lpfc_mbx_set_diag_state_diag_SHIFT 0 1872#define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1873#define lpfc_mbx_set_diag_state_diag_WORD word0 1874#define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1875#define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1876#define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1877#define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1878#define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1879#define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1880#define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1881#define lpfc_mbx_set_diag_state_link_num_WORD word0 1882#define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1883#define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1884#define lpfc_mbx_set_diag_state_link_type_WORD word0 1885 } req; 1886 struct { 1887 uint32_t word0; 1888 } rsp; 1889 } u; 1890}; 1891 1892struct lpfc_mbx_set_link_diag_loopback { 1893 struct mbox_header header; 1894 union { 1895 struct { 1896 uint32_t word0; 1897#define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1898#define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1899#define lpfc_mbx_set_diag_lpbk_type_WORD word0 1900#define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1901#define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1902#define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1903#define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 1904#define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1905#define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1906#define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1907#define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1908#define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1909#define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1910 } req; 1911 struct { 1912 uint32_t word0; 1913 } rsp; 1914 } u; 1915}; 1916 1917struct lpfc_mbx_run_link_diag_test { 1918 struct mbox_header header; 1919 union { 1920 struct { 1921 uint32_t word0; 1922#define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1923#define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1924#define lpfc_mbx_run_diag_test_link_num_WORD word0 1925#define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1926#define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1927#define lpfc_mbx_run_diag_test_link_type_WORD word0 1928 uint32_t word1; 1929#define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1930#define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1931#define lpfc_mbx_run_diag_test_test_id_WORD word1 1932#define lpfc_mbx_run_diag_test_loops_SHIFT 16 1933#define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1934#define lpfc_mbx_run_diag_test_loops_WORD word1 1935 uint32_t word2; 1936#define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1937#define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1938#define lpfc_mbx_run_diag_test_test_ver_WORD word2 1939#define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1940#define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1941#define lpfc_mbx_run_diag_test_err_act_WORD word2 1942 } req; 1943 struct { 1944 uint32_t word0; 1945 } rsp; 1946 } u; 1947}; 1948 1949/* 1950 * struct lpfc_mbx_alloc_rsrc_extents: 1951 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1952 * 6 words of header + 4 words of shared subcommand header + 1953 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1954 * 1955 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1956 * for extents payload. 1957 * 1958 * 212/2 (bytes per extent) = 106 extents. 1959 * 106/2 (extents per word) = 53 words. 1960 * lpfc_id_range id is statically size to 53. 1961 * 1962 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1963 * extent ranges. For ALLOC, the type and cnt are required. 1964 * For GET_ALLOCATED, only the type is required. 1965 */ 1966struct lpfc_mbx_alloc_rsrc_extents { 1967 struct mbox_header header; 1968 union { 1969 struct { 1970 uint32_t word4; 1971#define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1972#define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1973#define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1974#define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1975#define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1976#define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1977 } req; 1978 struct { 1979 uint32_t word4; 1980#define lpfc_mbx_rsrc_cnt_SHIFT 0 1981#define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1982#define lpfc_mbx_rsrc_cnt_WORD word4 1983 struct lpfc_id_range id[53]; 1984 } rsp; 1985 } u; 1986}; 1987 1988/* 1989 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1990 * structure shares the same SHIFT/MASK/WORD defines provided in the 1991 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1992 * the structures defined above. This non-embedded structure provides for the 1993 * maximum number of extents supported by the port. 1994 */ 1995struct lpfc_mbx_nembed_rsrc_extent { 1996 union lpfc_sli4_cfg_shdr cfg_shdr; 1997 uint32_t word4; 1998 struct lpfc_id_range id; 1999}; 2000
2001struct lpfc_mbx_dealloc_rsrc_extents { 2002 struct mbox_header header; 2003 struct { 2004 uint32_t word4; 2005#define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2006#define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2007#define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2008 } req; 2009 2010}; 2011 2012/* Start SLI4 FCoE specific mbox structures. */ 2013 2014struct lpfc_mbx_post_hdr_tmpl { 2015 struct mbox_header header; 2016 uint32_t word10; 2017#define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2018#define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2019#define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2020#define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2021#define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2022#define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2023 uint32_t rpi_paddr_lo; 2024 uint32_t rpi_paddr_hi; 2025}; 2026 2027struct sli4_sge { /* SLI-4 */ 2028 uint32_t addr_hi; 2029 uint32_t addr_lo; 2030 2031 uint32_t word2; 2032#define lpfc_sli4_sge_offset_SHIFT 0 2033#define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2034#define lpfc_sli4_sge_offset_WORD word2 2035#define lpfc_sli4_sge_type_SHIFT 27 2036#define lpfc_sli4_sge_type_MASK 0x0000000F 2037#define lpfc_sli4_sge_type_WORD word2 2038#define LPFC_SGE_TYPE_DATA 0x0 2039#define LPFC_SGE_TYPE_DIF 0x4 2040#define LPFC_SGE_TYPE_LSP 0x5 2041#define LPFC_SGE_TYPE_PEDIF 0x6 2042#define LPFC_SGE_TYPE_PESEED 0x7 2043#define LPFC_SGE_TYPE_DISEED 0x8 2044#define LPFC_SGE_TYPE_ENC 0x9 2045#define LPFC_SGE_TYPE_ATM 0xA 2046#define LPFC_SGE_TYPE_SKIP 0xC 2047#define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2048#define lpfc_sli4_sge_last_MASK 0x00000001 2049#define lpfc_sli4_sge_last_WORD word2 2050 uint32_t sge_len; 2051}; 2052 2053struct sli4_sge_diseed { /* SLI-4 */ 2054 uint32_t ref_tag; 2055 uint32_t ref_tag_tran; 2056 2057 uint32_t word2; 2058#define lpfc_sli4_sge_dif_apptran_SHIFT 0 2059#define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2060#define lpfc_sli4_sge_dif_apptran_WORD word2 2061#define lpfc_sli4_sge_dif_af_SHIFT 24 2062#define lpfc_sli4_sge_dif_af_MASK 0x00000001 2063#define lpfc_sli4_sge_dif_af_WORD word2 2064#define lpfc_sli4_sge_dif_na_SHIFT 25 2065#define lpfc_sli4_sge_dif_na_MASK 0x00000001 2066#define lpfc_sli4_sge_dif_na_WORD word2 2067#define lpfc_sli4_sge_dif_hi_SHIFT 26 2068#define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2069#define lpfc_sli4_sge_dif_hi_WORD word2 2070#define lpfc_sli4_sge_dif_type_SHIFT 27 2071#define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2072#define lpfc_sli4_sge_dif_type_WORD word2 2073#define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2074#define lpfc_sli4_sge_dif_last_MASK 0x00000001 2075#define lpfc_sli4_sge_dif_last_WORD word2 2076 uint32_t word3; 2077#define lpfc_sli4_sge_dif_apptag_SHIFT 0 2078#define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2079#define lpfc_sli4_sge_dif_apptag_WORD word3 2080#define lpfc_sli4_sge_dif_bs_SHIFT 16 2081#define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2082#define lpfc_sli4_sge_dif_bs_WORD word3 2083#define lpfc_sli4_sge_dif_ai_SHIFT 19 2084#define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2085#define lpfc_sli4_sge_dif_ai_WORD word3 2086#define lpfc_sli4_sge_dif_me_SHIFT 20 2087#define lpfc_sli4_sge_dif_me_MASK 0x00000001 2088#define lpfc_sli4_sge_dif_me_WORD word3 2089#define lpfc_sli4_sge_dif_re_SHIFT 21 2090#define lpfc_sli4_sge_dif_re_MASK 0x00000001 2091#define lpfc_sli4_sge_dif_re_WORD word3 2092#define lpfc_sli4_sge_dif_ce_SHIFT 22 2093#define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2094#define lpfc_sli4_sge_dif_ce_WORD word3 2095#define lpfc_sli4_sge_dif_nr_SHIFT 23 2096#define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2097#define lpfc_sli4_sge_dif_nr_WORD word3 2098#define lpfc_sli4_sge_dif_oprx_SHIFT 24 2099#define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2100#define lpfc_sli4_sge_dif_oprx_WORD word3 2101#define lpfc_sli4_sge_dif_optx_SHIFT 28 2102#define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2103#define lpfc_sli4_sge_dif_optx_WORD word3 2104/* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2105}; 2106 2107struct fcf_record { 2108 uint32_t max_rcv_size; 2109 uint32_t fka_adv_period; 2110 uint32_t fip_priority; 2111 uint32_t word3; 2112#define lpfc_fcf_record_mac_0_SHIFT 0 2113#define lpfc_fcf_record_mac_0_MASK 0x000000FF 2114#define lpfc_fcf_record_mac_0_WORD word3 2115#define lpfc_fcf_record_mac_1_SHIFT 8 2116#define lpfc_fcf_record_mac_1_MASK 0x000000FF 2117#define lpfc_fcf_record_mac_1_WORD word3 2118#define lpfc_fcf_record_mac_2_SHIFT 16 2119#define lpfc_fcf_record_mac_2_MASK 0x000000FF 2120#define lpfc_fcf_record_mac_2_WORD word3 2121#define lpfc_fcf_record_mac_3_SHIFT 24 2122#define lpfc_fcf_record_mac_3_MASK 0x000000FF 2123#define lpfc_fcf_record_mac_3_WORD word3 2124 uint32_t word4; 2125#define lpfc_fcf_record_mac_4_SHIFT 0 2126#define lpfc_fcf_record_mac_4_MASK 0x000000FF 2127#define lpfc_fcf_record_mac_4_WORD word4 2128#define lpfc_fcf_record_mac_5_SHIFT 8 2129#define lpfc_fcf_record_mac_5_MASK 0x000000FF 2130#define lpfc_fcf_record_mac_5_WORD word4 2131#define lpfc_fcf_record_fcf_avail_SHIFT 16 2132#define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2133#define lpfc_fcf_record_fcf_avail_WORD word4 2134#define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2135#define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2136#define lpfc_fcf_record_mac_addr_prov_WORD word4 2137#define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2138#define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2139 uint32_t word5; 2140#define lpfc_fcf_record_fab_name_0_SHIFT 0 2141#define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2142#define lpfc_fcf_record_fab_name_0_WORD word5 2143#define lpfc_fcf_record_fab_name_1_SHIFT 8 2144#define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2145#define lpfc_fcf_record_fab_name_1_WORD word5 2146#define lpfc_fcf_record_fab_name_2_SHIFT 16 2147#define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2148#define lpfc_fcf_record_fab_name_2_WORD word5 2149#define lpfc_fcf_record_fab_name_3_SHIFT 24 2150#define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2151#define lpfc_fcf_record_fab_name_3_WORD word5 2152 uint32_t word6; 2153#define lpfc_fcf_record_fab_name_4_SHIFT 0 2154#define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2155#define lpfc_fcf_record_fab_name_4_WORD word6 2156#define lpfc_fcf_record_fab_name_5_SHIFT 8 2157#define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2158#define lpfc_fcf_record_fab_name_5_WORD word6 2159#define lpfc_fcf_record_fab_name_6_SHIFT 16 2160#define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2161#define lpfc_fcf_record_fab_name_6_WORD word6 2162#define lpfc_fcf_record_fab_name_7_SHIFT 24 2163#define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2164#define lpfc_fcf_record_fab_name_7_WORD word6 2165 uint32_t word7; 2166#define lpfc_fcf_record_fc_map_0_SHIFT 0 2167#define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2168#define lpfc_fcf_record_fc_map_0_WORD word7 2169#define lpfc_fcf_record_fc_map_1_SHIFT 8 2170#define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2171#define lpfc_fcf_record_fc_map_1_WORD word7 2172#define lpfc_fcf_record_fc_map_2_SHIFT 16 2173#define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2174#define lpfc_fcf_record_fc_map_2_WORD word7 2175#define lpfc_fcf_record_fcf_valid_SHIFT 24 2176#define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2177#define lpfc_fcf_record_fcf_valid_WORD word7 2178#define lpfc_fcf_record_fcf_fc_SHIFT 25 2179#define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2180#define lpfc_fcf_record_fcf_fc_WORD word7 2181#define lpfc_fcf_record_fcf_sol_SHIFT 31 2182#define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2183#define lpfc_fcf_record_fcf_sol_WORD word7 2184 uint32_t word8; 2185#define lpfc_fcf_record_fcf_index_SHIFT 0 2186#define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2187#define lpfc_fcf_record_fcf_index_WORD word8 2188#define lpfc_fcf_record_fcf_state_SHIFT 16 2189#define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2190#define lpfc_fcf_record_fcf_state_WORD word8 2191 uint8_t vlan_bitmap[512]; 2192 uint32_t word137; 2193#define lpfc_fcf_record_switch_name_0_SHIFT 0 2194#define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2195#define lpfc_fcf_record_switch_name_0_WORD word137 2196#define lpfc_fcf_record_switch_name_1_SHIFT 8 2197#define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2198#define lpfc_fcf_record_switch_name_1_WORD word137 2199#define lpfc_fcf_record_switch_name_2_SHIFT 16 2200#define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2201#define lpfc_fcf_record_switch_name_2_WORD word137 2202#define lpfc_fcf_record_switch_name_3_SHIFT 24 2203#define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2204#define lpfc_fcf_record_switch_name_3_WORD word137 2205 uint32_t word138; 2206#define lpfc_fcf_record_switch_name_4_SHIFT 0 2207#define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2208#define lpfc_fcf_record_switch_name_4_WORD word138 2209#define lpfc_fcf_record_switch_name_5_SHIFT 8 2210#define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2211#define lpfc_fcf_record_switch_name_5_WORD word138 2212#define lpfc_fcf_record_switch_name_6_SHIFT 16 2213#define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2214#define lpfc_fcf_record_switch_name_6_WORD word138 2215#define lpfc_fcf_record_switch_name_7_SHIFT 24 2216#define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2217#define lpfc_fcf_record_switch_name_7_WORD word138 2218}; 2219 2220struct lpfc_mbx_read_fcf_tbl { 2221 union lpfc_sli4_cfg_shdr cfg_shdr; 2222 union { 2223 struct { 2224 uint32_t word10; 2225#define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2226#define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2227#define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2228 } request; 2229 struct { 2230 uint32_t eventag; 2231 } response; 2232 } u; 2233 uint32_t word11; 2234#define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2235#define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2236#define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2237}; 2238 2239struct lpfc_mbx_add_fcf_tbl_entry { 2240 union lpfc_sli4_cfg_shdr cfg_shdr; 2241 uint32_t word10; 2242#define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2243#define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2244#define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2245 struct lpfc_mbx_sge fcf_sge; 2246}; 2247 2248struct lpfc_mbx_del_fcf_tbl_entry { 2249 struct mbox_header header; 2250 uint32_t word10; 2251#define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2252#define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2253#define lpfc_mbx_del_fcf_tbl_count_WORD word10 2254#define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2255#define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2256#define lpfc_mbx_del_fcf_tbl_index_WORD word10 2257}; 2258 2259struct lpfc_mbx_redisc_fcf_tbl { 2260 struct mbox_header header; 2261 uint32_t word10; 2262#define lpfc_mbx_redisc_fcf_count_SHIFT 0 2263#define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2264#define lpfc_mbx_redisc_fcf_count_WORD word10 2265 uint32_t resvd; 2266 uint32_t word12; 2267#define lpfc_mbx_redisc_fcf_index_SHIFT 0 2268#define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2269#define lpfc_mbx_redisc_fcf_index_WORD word12 2270}; 2271 2272/* Status field for embedded SLI_CONFIG mailbox command */ 2273#define STATUS_SUCCESS 0x0 2274#define STATUS_FAILED 0x1 2275#define STATUS_ILLEGAL_REQUEST 0x2 2276#define STATUS_ILLEGAL_FIELD 0x3 2277#define STATUS_INSUFFICIENT_BUFFER 0x4 2278#define STATUS_UNAUTHORIZED_REQUEST 0x5 2279#define STATUS_FLASHROM_SAVE_FAILED 0x17 2280#define STATUS_FLASHROM_RESTORE_FAILED 0x18 2281#define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2282#define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2283#define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2284#define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2285#define STATUS_ASSERT_FAILED 0x1e 2286#define STATUS_INVALID_SESSION 0x1f 2287#define STATUS_INVALID_CONNECTION 0x20 2288#define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2289#define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2290#define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2291#define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2292#define STATUS_FLASHROM_READ_FAILED 0x27 2293#define STATUS_POLL_IOCTL_TIMEOUT 0x28 2294#define STATUS_ERROR_ACITMAIN 0x2a 2295#define STATUS_REBOOT_REQUIRED 0x2c 2296#define STATUS_FCF_IN_USE 0x3a 2297#define STATUS_FCF_TABLE_EMPTY 0x43 2298 2299/* 2300 * Additional status field for embedded SLI_CONFIG mailbox 2301 * command. 2302 */ 2303#define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2304#define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2305#define ADD_STATUS_INVALID_REQUEST 0x4B 2306 2307struct lpfc_mbx_sli4_config { 2308 struct mbox_header header; 2309}; 2310 2311struct lpfc_mbx_init_vfi { 2312 uint32_t word1; 2313#define lpfc_init_vfi_vr_SHIFT 31 2314#define lpfc_init_vfi_vr_MASK 0x00000001 2315#define lpfc_init_vfi_vr_WORD word1 2316#define lpfc_init_vfi_vt_SHIFT 30 2317#define lpfc_init_vfi_vt_MASK 0x00000001 2318#define lpfc_init_vfi_vt_WORD word1 2319#define lpfc_init_vfi_vf_SHIFT 29 2320#define lpfc_init_vfi_vf_MASK 0x00000001 2321#define lpfc_init_vfi_vf_WORD word1 2322#define lpfc_init_vfi_vp_SHIFT 28 2323#define lpfc_init_vfi_vp_MASK 0x00000001 2324#define lpfc_init_vfi_vp_WORD word1 2325#define lpfc_init_vfi_vfi_SHIFT 0 2326#define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2327#define lpfc_init_vfi_vfi_WORD word1 2328 uint32_t word2; 2329#define lpfc_init_vfi_vpi_SHIFT 16 2330#define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2331#define lpfc_init_vfi_vpi_WORD word2 2332#define lpfc_init_vfi_fcfi_SHIFT 0 2333#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2334#define lpfc_init_vfi_fcfi_WORD word2 2335 uint32_t word3; 2336#define lpfc_init_vfi_pri_SHIFT 13 2337#define lpfc_init_vfi_pri_MASK 0x00000007 2338#define lpfc_init_vfi_pri_WORD word3 2339#define lpfc_init_vfi_vf_id_SHIFT 1 2340#define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2341#define lpfc_init_vfi_vf_id_WORD word3 2342 uint32_t word4; 2343#define lpfc_init_vfi_hop_count_SHIFT 24 2344#define lpfc_init_vfi_hop_count_MASK 0x000000FF 2345#define lpfc_init_vfi_hop_count_WORD word4 2346}; 2347#define MBX_VFI_IN_USE 0x9F02 2348 2349 2350struct lpfc_mbx_reg_vfi { 2351 uint32_t word1; 2352#define lpfc_reg_vfi_upd_SHIFT 29 2353#define lpfc_reg_vfi_upd_MASK 0x00000001 2354#define lpfc_reg_vfi_upd_WORD word1 2355#define lpfc_reg_vfi_vp_SHIFT 28 2356#define lpfc_reg_vfi_vp_MASK 0x00000001 2357#define lpfc_reg_vfi_vp_WORD word1 2358#define lpfc_reg_vfi_vfi_SHIFT 0 2359#define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2360#define lpfc_reg_vfi_vfi_WORD word1 2361 uint32_t word2; 2362#define lpfc_reg_vfi_vpi_SHIFT 16 2363#define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2364#define lpfc_reg_vfi_vpi_WORD word2 2365#define lpfc_reg_vfi_fcfi_SHIFT 0 2366#define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2367#define lpfc_reg_vfi_fcfi_WORD word2 2368 uint32_t wwn[2]; 2369 struct ulp_bde64 bde; 2370 uint32_t e_d_tov; 2371 uint32_t r_a_tov; 2372 uint32_t word10; 2373#define lpfc_reg_vfi_nport_id_SHIFT 0 2374#define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2375#define lpfc_reg_vfi_nport_id_WORD word10 2376#define lpfc_reg_vfi_bbcr_SHIFT 27 2377#define lpfc_reg_vfi_bbcr_MASK 0x00000001 2378#define lpfc_reg_vfi_bbcr_WORD word10 2379#define lpfc_reg_vfi_bbscn_SHIFT 28 2380#define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2381#define lpfc_reg_vfi_bbscn_WORD word10 2382}; 2383 2384struct lpfc_mbx_init_vpi { 2385 uint32_t word1; 2386#define lpfc_init_vpi_vfi_SHIFT 16 2387#define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2388#define lpfc_init_vpi_vfi_WORD word1 2389#define lpfc_init_vpi_vpi_SHIFT 0 2390#define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2391#define lpfc_init_vpi_vpi_WORD word1 2392}; 2393 2394struct lpfc_mbx_read_vpi { 2395 uint32_t word1_rsvd; 2396 uint32_t word2; 2397#define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2398#define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2399#define lpfc_mbx_read_vpi_vnportid_WORD word2 2400 uint32_t word3_rsvd; 2401 uint32_t word4; 2402#define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2403#define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2404#define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2405#define lpfc_mbx_read_vpi_pb_SHIFT 15 2406#define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2407#define lpfc_mbx_read_vpi_pb_WORD word4 2408#define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2409#define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2410#define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2411#define lpfc_mbx_read_vpi_ns_SHIFT 30 2412#define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2413#define lpfc_mbx_read_vpi_ns_WORD word4 2414#define lpfc_mbx_read_vpi_hl_SHIFT 31 2415#define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2416#define lpfc_mbx_read_vpi_hl_WORD word4 2417 uint32_t word5_rsvd; 2418 uint32_t word6; 2419#define lpfc_mbx_read_vpi_vpi_SHIFT 0 2420#define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2421#define lpfc_mbx_read_vpi_vpi_WORD word6 2422 uint32_t word7; 2423#define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2424#define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2425#define lpfc_mbx_read_vpi_mac_0_WORD word7 2426#define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2427#define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2428#define lpfc_mbx_read_vpi_mac_1_WORD word7 2429#define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2430#define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2431#define lpfc_mbx_read_vpi_mac_2_WORD word7 2432#define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2433#define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2434#define lpfc_mbx_read_vpi_mac_3_WORD word7 2435 uint32_t word8; 2436#define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2437#define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2438#define lpfc_mbx_read_vpi_mac_4_WORD word8 2439#define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2440#define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2441#define lpfc_mbx_read_vpi_mac_5_WORD word8 2442#define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2443#define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2444#define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2445#define lpfc_mbx_read_vpi_vv_SHIFT 28 2446#define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2447#define lpfc_mbx_read_vpi_vv_WORD word8 2448}; 2449 2450struct lpfc_mbx_unreg_vfi { 2451 uint32_t word1_rsvd; 2452 uint32_t word2; 2453#define lpfc_unreg_vfi_vfi_SHIFT 0 2454#define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2455#define lpfc_unreg_vfi_vfi_WORD word2 2456}; 2457 2458struct lpfc_mbx_resume_rpi { 2459 uint32_t word1; 2460#define lpfc_resume_rpi_index_SHIFT 0 2461#define lpfc_resume_rpi_index_MASK 0x0000FFFF 2462#define lpfc_resume_rpi_index_WORD word1 2463#define lpfc_resume_rpi_ii_SHIFT 30 2464#define lpfc_resume_rpi_ii_MASK 0x00000003 2465#define lpfc_resume_rpi_ii_WORD word1 2466#define RESUME_INDEX_RPI 0 2467#define RESUME_INDEX_VPI 1 2468#define RESUME_INDEX_VFI 2 2469#define RESUME_INDEX_FCFI 3 2470 uint32_t event_tag; 2471}; 2472 2473#define REG_FCF_INVALID_QID 0xFFFF 2474struct lpfc_mbx_reg_fcfi { 2475 uint32_t word1; 2476#define lpfc_reg_fcfi_info_index_SHIFT 0 2477#define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2478#define lpfc_reg_fcfi_info_index_WORD word1 2479#define lpfc_reg_fcfi_fcfi_SHIFT 16 2480#define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2481#define lpfc_reg_fcfi_fcfi_WORD word1 2482 uint32_t word2; 2483#define lpfc_reg_fcfi_rq_id1_SHIFT 0 2484#define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2485#define lpfc_reg_fcfi_rq_id1_WORD word2 2486#define lpfc_reg_fcfi_rq_id0_SHIFT 16 2487#define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2488#define lpfc_reg_fcfi_rq_id0_WORD word2 2489 uint32_t word3; 2490#define lpfc_reg_fcfi_rq_id3_SHIFT 0 2491#define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2492#define lpfc_reg_fcfi_rq_id3_WORD word3 2493#define lpfc_reg_fcfi_rq_id2_SHIFT 16 2494#define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2495#define lpfc_reg_fcfi_rq_id2_WORD word3 2496 uint32_t word4; 2497#define lpfc_reg_fcfi_type_match0_SHIFT 24 2498#define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2499#define lpfc_reg_fcfi_type_match0_WORD word4 2500#define lpfc_reg_fcfi_type_mask0_SHIFT 16 2501#define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2502#define lpfc_reg_fcfi_type_mask0_WORD word4 2503#define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2504#define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2505#define lpfc_reg_fcfi_rctl_match0_WORD word4 2506#define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2507#define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2508#define lpfc_reg_fcfi_rctl_mask0_WORD word4 2509 uint32_t word5; 2510#define lpfc_reg_fcfi_type_match1_SHIFT 24 2511#define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2512#define lpfc_reg_fcfi_type_match1_WORD word5 2513#define lpfc_reg_fcfi_type_mask1_SHIFT 16 2514#define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2515#define lpfc_reg_fcfi_type_mask1_WORD word5 2516#define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2517#define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2518#define lpfc_reg_fcfi_rctl_match1_WORD word5 2519#define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2520#define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2521#define lpfc_reg_fcfi_rctl_mask1_WORD word5 2522 uint32_t word6; 2523#define lpfc_reg_fcfi_type_match2_SHIFT 24 2524#define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2525#define lpfc_reg_fcfi_type_match2_WORD word6 2526#define lpfc_reg_fcfi_type_mask2_SHIFT 16 2527#define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2528#define lpfc_reg_fcfi_type_mask2_WORD word6 2529#define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2530#define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2531#define lpfc_reg_fcfi_rctl_match2_WORD word6 2532#define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2533#define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2534#define lpfc_reg_fcfi_rctl_mask2_WORD word6 2535 uint32_t word7; 2536#define lpfc_reg_fcfi_type_match3_SHIFT 24 2537#define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2538#define lpfc_reg_fcfi_type_match3_WORD word7 2539#define lpfc_reg_fcfi_type_mask3_SHIFT 16 2540#define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2541#define lpfc_reg_fcfi_type_mask3_WORD word7 2542#define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2543#define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2544#define lpfc_reg_fcfi_rctl_match3_WORD word7 2545#define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2546#define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2547#define lpfc_reg_fcfi_rctl_mask3_WORD word7 2548 uint32_t word8; 2549#define lpfc_reg_fcfi_mam_SHIFT 13 2550#define lpfc_reg_fcfi_mam_MASK 0x00000003 2551#define lpfc_reg_fcfi_mam_WORD word8 2552#define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2553#define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2554#define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2555#define lpfc_reg_fcfi_vv_SHIFT 12 2556#define lpfc_reg_fcfi_vv_MASK 0x00000001 2557#define lpfc_reg_fcfi_vv_WORD word8 2558#define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2559#define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2560#define lpfc_reg_fcfi_vlan_tag_WORD word8 2561}; 2562 2563struct lpfc_mbx_reg_fcfi_mrq { 2564 uint32_t word1; 2565#define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2566#define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2567#define lpfc_reg_fcfi_mrq_info_index_WORD word1 2568#define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2569#define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2570#define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2571 uint32_t word2; 2572#define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2573#define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2574#define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2575#define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2576#define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2577#define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2578 uint32_t word3; 2579#define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2580#define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2581#define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2582#define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2583#define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2584#define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2585 uint32_t word4; 2586#define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2587#define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2588#define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2589#define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2590#define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2591#define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2592#define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2593#define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2594#define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2595#define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2596#define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2597#define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2598 uint32_t word5; 2599#define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2600#define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2601#define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2602#define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2603#define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2604#define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2605#define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2606#define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2607#define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2608#define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2609#define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2610#define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2611 uint32_t word6; 2612#define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2613#define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2614#define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2615#define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2616#define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2617#define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2618#define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2619#define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2620#define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2621#define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2622#define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2623#define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2624 uint32_t word7; 2625#define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2626#define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2627#define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2628#define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2629#define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2630#define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2631#define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2632#define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2633#define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2634#define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2635#define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2636#define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2637 uint32_t word8; 2638#define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2639#define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2640#define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2641#define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2642#define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2643#define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2644#define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2645#define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2646#define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2647#define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2648#define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2649#define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2650#define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2651#define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2652#define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2653#define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2654#define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2655#define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2656#define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2657#define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2658#define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2659#define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2660#define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2661#define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2662#define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2663#define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2664#define lpfc_reg_fcfi_mrq_pt7_WORD word8 2665#define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2666#define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2667#define lpfc_reg_fcfi_mrq_pt6_WORD word8 2668#define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2669#define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2670#define lpfc_reg_fcfi_mrq_pt5_WORD word8 2671#define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2672#define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2673#define lpfc_reg_fcfi_mrq_pt4_WORD word8 2674#define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2675#define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2676#define lpfc_reg_fcfi_mrq_pt3_WORD word8 2677#define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2678#define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2679#define lpfc_reg_fcfi_mrq_pt2_WORD word8 2680#define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2681#define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2682#define lpfc_reg_fcfi_mrq_pt1_WORD word8 2683#define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2684#define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2685#define lpfc_reg_fcfi_mrq_pt0_WORD word8 2686#define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2687#define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2688#define lpfc_reg_fcfi_mrq_xmv_WORD word8 2689#define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2690#define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2691#define lpfc_reg_fcfi_mrq_mode_WORD word8 2692#define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2693#define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2694#define lpfc_reg_fcfi_mrq_vv_WORD word8 2695#define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2696#define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2697#define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2698 uint32_t word9; 2699#define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2700#define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2701#define lpfc_reg_fcfi_mrq_policy_WORD word9 2702#define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2703#define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2704#define lpfc_reg_fcfi_mrq_filter_WORD word9 2705#define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2706#define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2707#define lpfc_reg_fcfi_mrq_npairs_WORD word9 2708 uint32_t word10; 2709 uint32_t word11; 2710 uint32_t word12; 2711 uint32_t word13; 2712 uint32_t word14; 2713 uint32_t word15; 2714 uint32_t word16; 2715}; 2716 2717struct lpfc_mbx_unreg_fcfi { 2718 uint32_t word1_rsv; 2719 uint32_t word2; 2720#define lpfc_unreg_fcfi_SHIFT 0 2721#define lpfc_unreg_fcfi_MASK 0x0000FFFF 2722#define lpfc_unreg_fcfi_WORD word2 2723}; 2724 2725struct lpfc_mbx_read_rev { 2726 uint32_t word1; 2727#define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2728#define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2729#define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2730#define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2731#define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2732#define lpfc_mbx_rd_rev_fcoe_WORD word1 2733#define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2734#define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2735#define lpfc_mbx_rd_rev_cee_ver_WORD word1 2736#define LPFC_PREDCBX_CEE_MODE 0 2737#define LPFC_DCBX_CEE_MODE 1 2738#define lpfc_mbx_rd_rev_vpd_SHIFT 29 2739#define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2740#define lpfc_mbx_rd_rev_vpd_WORD word1 2741 uint32_t first_hw_rev; 2742#define LPFC_G7_ASIC_1 0xd 2743 uint32_t second_hw_rev; 2744 uint32_t word4_rsvd; 2745 uint32_t third_hw_rev; 2746 uint32_t word6; 2747#define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2748#define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2749#define lpfc_mbx_rd_rev_fcph_low_WORD word6 2750#define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2751#define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2752#define lpfc_mbx_rd_rev_fcph_high_WORD word6 2753#define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2754#define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2755#define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2756#define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2757#define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2758#define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2759 uint32_t word7_rsvd; 2760 uint32_t fw_id_rev; 2761 uint8_t fw_name[16]; 2762 uint32_t ulp_fw_id_rev; 2763 uint8_t ulp_fw_name[16]; 2764 uint32_t word18_47_rsvd[30]; 2765 uint32_t word48; 2766#define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2767#define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2768#define lpfc_mbx_rd_rev_avail_len_WORD word48 2769 uint32_t vpd_paddr_low; 2770 uint32_t vpd_paddr_high; 2771 uint32_t avail_vpd_len; 2772 uint32_t rsvd_52_63[12]; 2773}; 2774 2775struct lpfc_mbx_read_config { 2776 uint32_t word1; 2777#define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2778#define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2779#define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2780 uint32_t word2; 2781#define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2782#define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2783#define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2784#define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2785#define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2786#define lpfc_mbx_rd_conf_lnk_type_WORD word2 2787#define LPFC_LNK_TYPE_GE 0 2788#define LPFC_LNK_TYPE_FC 1 2789#define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2790#define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2791#define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2792#define lpfc_mbx_rd_conf_trunk_SHIFT 12 2793#define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2794#define lpfc_mbx_rd_conf_trunk_WORD word2 2795#define lpfc_mbx_rd_conf_topology_SHIFT 24 2796#define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2797#define lpfc_mbx_rd_conf_topology_WORD word2 2798 uint32_t rsvd_3; 2799 uint32_t word4; 2800#define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2801#define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2802#define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2803 uint32_t rsvd_5; 2804 uint32_t word6; 2805#define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2806#define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2807#define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2808#define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2809#define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2810#define lpfc_mbx_rd_conf_link_speed_WORD word6 2811 uint32_t rsvd_7; 2812 uint32_t word8; 2813#define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2814#define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2815#define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2816#define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2817#define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2818#define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2819#define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2820#define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2821#define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2822 uint32_t word9; 2823#define lpfc_mbx_rd_conf_lmt_SHIFT 0 2824#define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2825#define lpfc_mbx_rd_conf_lmt_WORD word9 2826 uint32_t rsvd_10; 2827 uint32_t rsvd_11; 2828 uint32_t word12; 2829#define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2830#define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2831#define lpfc_mbx_rd_conf_xri_base_WORD word12 2832#define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2833#define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2834#define lpfc_mbx_rd_conf_xri_count_WORD word12 2835 uint32_t word13; 2836#define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2837#define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2838#define lpfc_mbx_rd_conf_rpi_base_WORD word13 2839#define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2840#define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2841#define lpfc_mbx_rd_conf_rpi_count_WORD word13 2842 uint32_t word14; 2843#define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2844#define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2845#define lpfc_mbx_rd_conf_vpi_base_WORD word14 2846#define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2847#define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2848#define lpfc_mbx_rd_conf_vpi_count_WORD word14 2849 uint32_t word15; 2850#define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2851#define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2852#define lpfc_mbx_rd_conf_vfi_base_WORD word15 2853#define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2854#define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2855#define lpfc_mbx_rd_conf_vfi_count_WORD word15 2856 uint32_t word16; 2857#define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2858#define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2859#define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2860 uint32_t word17; 2861#define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2862#define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2863#define lpfc_mbx_rd_conf_rq_count_WORD word17 2864#define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2865#define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2866#define lpfc_mbx_rd_conf_eq_count_WORD word17 2867 uint32_t word18; 2868#define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2869#define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2870#define lpfc_mbx_rd_conf_wq_count_WORD word18 2871#define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2872#define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2873#define lpfc_mbx_rd_conf_cq_count_WORD word18 2874}; 2875 2876struct lpfc_mbx_request_features { 2877 uint32_t word1; 2878#define lpfc_mbx_rq_ftr_qry_SHIFT 0 2879#define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2880#define lpfc_mbx_rq_ftr_qry_WORD word1 2881 uint32_t word2; 2882#define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2883#define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2884#define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2885#define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2886#define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2887#define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2888#define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2889#define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2890#define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2891#define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2892#define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2893#define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2894#define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2895#define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2896#define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2897#define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2898#define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2899#define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2900#define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2901#define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2902#define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2903#define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2904#define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2905#define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2906#define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2907#define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2908#define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2909#define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2910#define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2911#define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2912#define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2913#define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2914#define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2915 uint32_t word3; 2916#define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2917#define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2918#define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2919#define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2920#define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2921#define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2922#define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2923#define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2924#define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2925#define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2926#define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2927#define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2928#define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2929#define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2930#define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2931#define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2932#define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2933#define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2934#define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2935#define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2936#define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2937#define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2938#define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2939#define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2940#define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2941#define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2942#define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2943#define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2944#define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2945#define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2946}; 2947 2948struct lpfc_mbx_supp_pages { 2949 uint32_t word1; 2950#define qs_SHIFT 0 2951#define qs_MASK 0x00000001 2952#define qs_WORD word1 2953#define wr_SHIFT 1 2954#define wr_MASK 0x00000001 2955#define wr_WORD word1 2956#define pf_SHIFT 8 2957#define pf_MASK 0x000000ff 2958#define pf_WORD word1 2959#define cpn_SHIFT 16 2960#define cpn_MASK 0x000000ff 2961#define cpn_WORD word1 2962 uint32_t word2; 2963#define list_offset_SHIFT 0 2964#define list_offset_MASK 0x000000ff 2965#define list_offset_WORD word2 2966#define next_offset_SHIFT 8 2967#define next_offset_MASK 0x000000ff 2968#define next_offset_WORD word2 2969#define elem_cnt_SHIFT 16 2970#define elem_cnt_MASK 0x000000ff 2971#define elem_cnt_WORD word2 2972 uint32_t word3; 2973#define pn_0_SHIFT 24 2974#define pn_0_MASK 0x000000ff 2975#define pn_0_WORD word3 2976#define pn_1_SHIFT 16 2977#define pn_1_MASK 0x000000ff 2978#define pn_1_WORD word3 2979#define pn_2_SHIFT 8 2980#define pn_2_MASK 0x000000ff 2981#define pn_2_WORD word3 2982#define pn_3_SHIFT 0 2983#define pn_3_MASK 0x000000ff 2984#define pn_3_WORD word3 2985 uint32_t word4; 2986#define pn_4_SHIFT 24 2987#define pn_4_MASK 0x000000ff 2988#define pn_4_WORD word4 2989#define pn_5_SHIFT 16 2990#define pn_5_MASK 0x000000ff 2991#define pn_5_WORD word4 2992#define pn_6_SHIFT 8 2993#define pn_6_MASK 0x000000ff 2994#define pn_6_WORD word4 2995#define pn_7_SHIFT 0 2996#define pn_7_MASK 0x000000ff 2997#define pn_7_WORD word4 2998 uint32_t rsvd[27]; 2999#define LPFC_SUPP_PAGES 0 3000#define LPFC_BLOCK_GUARD_PROFILES 1
3001#define LPFC_SLI4_PARAMETERS 2 3002}; 3003 3004struct lpfc_mbx_memory_dump_type3 { 3005 uint32_t word1; 3006#define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3007#define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3008#define lpfc_mbx_memory_dump_type3_type_WORD word1 3009#define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3010#define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3011#define lpfc_mbx_memory_dump_type3_link_WORD word1 3012 uint32_t word2; 3013#define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3014#define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3015#define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3016#define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3017#define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3018#define lpfc_mbx_memory_dump_type3_offset_WORD word2 3019 uint32_t word3; 3020#define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3021#define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3022#define lpfc_mbx_memory_dump_type3_length_WORD word3 3023 uint32_t addr_lo; 3024 uint32_t addr_hi; 3025 uint32_t return_len; 3026}; 3027 3028#define DMP_PAGE_A0 0xa0 3029#define DMP_PAGE_A2 0xa2 3030#define DMP_SFF_PAGE_A0_SIZE 256 3031#define DMP_SFF_PAGE_A2_SIZE 256 3032 3033#define SFP_WAVELENGTH_LC1310 1310 3034#define SFP_WAVELENGTH_LL1550 1550 3035 3036 3037/* 3038 * * SFF-8472 TABLE 3.4 3039 * */ 3040#define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3041#define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3042#define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3043#define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3044#define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3045#define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3046#define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3047#define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3048#define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3049#define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3050#define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3051#define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3052#define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3053#define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3054#define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3055#define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3056 3057/* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3058 3059#define SSF_IDENTIFIER 0 3060#define SSF_EXT_IDENTIFIER 1 3061#define SSF_CONNECTOR 2 3062#define SSF_TRANSCEIVER_CODE_B0 3 3063#define SSF_TRANSCEIVER_CODE_B1 4 3064#define SSF_TRANSCEIVER_CODE_B2 5 3065#define SSF_TRANSCEIVER_CODE_B3 6 3066#define SSF_TRANSCEIVER_CODE_B4 7 3067#define SSF_TRANSCEIVER_CODE_B5 8 3068#define SSF_TRANSCEIVER_CODE_B6 9 3069#define SSF_TRANSCEIVER_CODE_B7 10 3070#define SSF_ENCODING 11 3071#define SSF_BR_NOMINAL 12 3072#define SSF_RATE_IDENTIFIER 13 3073#define SSF_LENGTH_9UM_KM 14 3074#define SSF_LENGTH_9UM 15 3075#define SSF_LENGTH_50UM_OM2 16 3076#define SSF_LENGTH_62UM_OM1 17 3077#define SFF_LENGTH_COPPER 18 3078#define SSF_LENGTH_50UM_OM3 19 3079#define SSF_VENDOR_NAME 20 3080#define SSF_VENDOR_OUI 36 3081#define SSF_VENDOR_PN 40 3082#define SSF_VENDOR_REV 56 3083#define SSF_WAVELENGTH_B1 60 3084#define SSF_WAVELENGTH_B0 61 3085#define SSF_CC_BASE 63 3086#define SSF_OPTIONS_B1 64 3087#define SSF_OPTIONS_B0 65 3088#define SSF_BR_MAX 66 3089#define SSF_BR_MIN 67 3090#define SSF_VENDOR_SN 68 3091#define SSF_DATE_CODE 84 3092#define SSF_MONITORING_TYPEDIAGNOSTIC 92 3093#define SSF_ENHANCED_OPTIONS 93 3094#define SFF_8472_COMPLIANCE 94 3095#define SSF_CC_EXT 95 3096#define SSF_A0_VENDOR_SPECIFIC 96 3097 3098/* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3099 3100#define SSF_TEMP_HIGH_ALARM 0 3101#define SSF_TEMP_LOW_ALARM 2 3102#define SSF_TEMP_HIGH_WARNING 4 3103#define SSF_TEMP_LOW_WARNING 6 3104#define SSF_VOLTAGE_HIGH_ALARM 8 3105#define SSF_VOLTAGE_LOW_ALARM 10 3106#define SSF_VOLTAGE_HIGH_WARNING 12 3107#define SSF_VOLTAGE_LOW_WARNING 14 3108#define SSF_BIAS_HIGH_ALARM 16 3109#define SSF_BIAS_LOW_ALARM 18 3110#define SSF_BIAS_HIGH_WARNING 20 3111#define SSF_BIAS_LOW_WARNING 22 3112#define SSF_TXPOWER_HIGH_ALARM 24 3113#define SSF_TXPOWER_LOW_ALARM 26 3114#define SSF_TXPOWER_HIGH_WARNING 28 3115#define SSF_TXPOWER_LOW_WARNING 30 3116#define SSF_RXPOWER_HIGH_ALARM 32 3117#define SSF_RXPOWER_LOW_ALARM 34 3118#define SSF_RXPOWER_HIGH_WARNING 36 3119#define SSF_RXPOWER_LOW_WARNING 38 3120#define SSF_EXT_CAL_CONSTANTS 56 3121#define SSF_CC_DMI 95 3122#define SFF_TEMPERATURE_B1 96 3123#define SFF_TEMPERATURE_B0 97 3124#define SFF_VCC_B1 98 3125#define SFF_VCC_B0 99 3126#define SFF_TX_BIAS_CURRENT_B1 100 3127#define SFF_TX_BIAS_CURRENT_B0 101 3128#define SFF_TXPOWER_B1 102 3129#define SFF_TXPOWER_B0 103 3130#define SFF_RXPOWER_B1 104 3131#define SFF_RXPOWER_B0 105 3132#define SSF_STATUS_CONTROL 110 3133#define SSF_ALARM_FLAGS 112 3134#define SSF_WARNING_FLAGS 116 3135#define SSF_EXT_TATUS_CONTROL_B1 118 3136#define SSF_EXT_TATUS_CONTROL_B0 119 3137#define SSF_A2_VENDOR_SPECIFIC 120 3138#define SSF_USER_EEPROM 128 3139#define SSF_VENDOR_CONTROL 148 3140 3141 3142/* 3143 * Tranceiver codes Fibre Channel SFF-8472 3144 * Table 3.5. 3145 */ 3146 3147struct sff_trasnceiver_codes_byte0 { 3148 uint8_t inifiband:4; 3149 uint8_t teng_ethernet:4; 3150}; 3151 3152struct sff_trasnceiver_codes_byte1 { 3153 uint8_t sonet:6; 3154 uint8_t escon:2; 3155}; 3156 3157struct sff_trasnceiver_codes_byte2 { 3158 uint8_t soNet:8; 3159}; 3160 3161struct sff_trasnceiver_codes_byte3 { 3162 uint8_t ethernet:8; 3163}; 3164 3165struct sff_trasnceiver_codes_byte4 { 3166 uint8_t fc_el_lo:1; 3167 uint8_t fc_lw_laser:1; 3168 uint8_t fc_sw_laser:1; 3169 uint8_t fc_md_distance:1; 3170 uint8_t fc_lg_distance:1; 3171 uint8_t fc_int_distance:1; 3172 uint8_t fc_short_distance:1; 3173 uint8_t fc_vld_distance:1; 3174}; 3175 3176struct sff_trasnceiver_codes_byte5 { 3177 uint8_t reserved1:1; 3178 uint8_t reserved2:1; 3179 uint8_t fc_sfp_active:1; /* Active cable */ 3180 uint8_t fc_sfp_passive:1; /* Passive cable */ 3181 uint8_t fc_lw_laser:1; /* Longwave laser */ 3182 uint8_t fc_sw_laser_sl:1; 3183 uint8_t fc_sw_laser_sn:1; 3184 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3185}; 3186 3187struct sff_trasnceiver_codes_byte6 { 3188 uint8_t fc_tm_sm:1; /* Single Mode */ 3189 uint8_t reserved:1; 3190 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3191 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3192 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3193 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3194 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3195}; 3196 3197struct sff_trasnceiver_codes_byte7 { 3198 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3199 uint8_t reserve:1; 3200 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3201 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3202 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3203 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3204 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3205 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3206}; 3207 3208/* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3209struct user_eeprom { 3210 uint8_t vendor_name[16]; 3211 uint8_t vendor_oui[3]; 3212 uint8_t vendor_pn[816]; 3213 uint8_t vendor_rev[4]; 3214 uint8_t vendor_sn[16]; 3215 uint8_t datecode[6]; 3216 uint8_t lot_code[2]; 3217 uint8_t reserved191[57]; 3218}; 3219 3220struct lpfc_mbx_pc_sli4_params { 3221 uint32_t word1; 3222#define qs_SHIFT 0 3223#define qs_MASK 0x00000001 3224#define qs_WORD word1 3225#define wr_SHIFT 1 3226#define wr_MASK 0x00000001 3227#define wr_WORD word1 3228#define pf_SHIFT 8 3229#define pf_MASK 0x000000ff 3230#define pf_WORD word1 3231#define cpn_SHIFT 16 3232#define cpn_MASK 0x000000ff 3233#define cpn_WORD word1 3234 uint32_t word2; 3235#define if_type_SHIFT 0 3236#define if_type_MASK 0x00000007 3237#define if_type_WORD word2 3238#define sli_rev_SHIFT 4 3239#define sli_rev_MASK 0x0000000f 3240#define sli_rev_WORD word2 3241#define sli_family_SHIFT 8 3242#define sli_family_MASK 0x000000ff 3243#define sli_family_WORD word2 3244#define featurelevel_1_SHIFT 16 3245#define featurelevel_1_MASK 0x000000ff 3246#define featurelevel_1_WORD word2 3247#define featurelevel_2_SHIFT 24 3248#define featurelevel_2_MASK 0x0000001f 3249#define featurelevel_2_WORD word2 3250 uint32_t word3; 3251#define fcoe_SHIFT 0 3252#define fcoe_MASK 0x00000001 3253#define fcoe_WORD word3 3254#define fc_SHIFT 1 3255#define fc_MASK 0x00000001 3256#define fc_WORD word3 3257#define nic_SHIFT 2 3258#define nic_MASK 0x00000001 3259#define nic_WORD word3 3260#define iscsi_SHIFT 3 3261#define iscsi_MASK 0x00000001 3262#define iscsi_WORD word3 3263#define rdma_SHIFT 4 3264#define rdma_MASK 0x00000001 3265#define rdma_WORD word3 3266 uint32_t sge_supp_len; 3267#define SLI4_PAGE_SIZE 4096 3268 uint32_t word5; 3269#define if_page_sz_SHIFT 0 3270#define if_page_sz_MASK 0x0000ffff 3271#define if_page_sz_WORD word5 3272#define loopbk_scope_SHIFT 24 3273#define loopbk_scope_MASK 0x0000000f 3274#define loopbk_scope_WORD word5 3275#define rq_db_window_SHIFT 28 3276#define rq_db_window_MASK 0x0000000f 3277#define rq_db_window_WORD word5 3278 uint32_t word6; 3279#define eq_pages_SHIFT 0 3280#define eq_pages_MASK 0x0000000f 3281#define eq_pages_WORD word6 3282#define eqe_size_SHIFT 8 3283#define eqe_size_MASK 0x000000ff 3284#define eqe_size_WORD word6 3285 uint32_t word7; 3286#define cq_pages_SHIFT 0 3287#define cq_pages_MASK 0x0000000f 3288#define cq_pages_WORD word7 3289#define cqe_size_SHIFT 8 3290#define cqe_size_MASK 0x000000ff 3291#define cqe_size_WORD word7 3292 uint32_t word8; 3293#define mq_pages_SHIFT 0 3294#define mq_pages_MASK 0x0000000f 3295#define mq_pages_WORD word8 3296#define mqe_size_SHIFT 8 3297#define mqe_size_MASK 0x000000ff 3298#define mqe_size_WORD word8 3299#define mq_elem_cnt_SHIFT 16 3300#define mq_elem_cnt_MASK 0x000000ff 3301#define mq_elem_cnt_WORD word8 3302 uint32_t word9; 3303#define wq_pages_SHIFT 0 3304#define wq_pages_MASK 0x0000ffff 3305#define wq_pages_WORD word9 3306#define wqe_size_SHIFT 8 3307#define wqe_size_MASK 0x000000ff 3308#define wqe_size_WORD word9 3309 uint32_t word10; 3310#define rq_pages_SHIFT 0 3311#define rq_pages_MASK 0x0000ffff 3312#define rq_pages_WORD word10 3313#define rqe_size_SHIFT 8 3314#define rqe_size_MASK 0x000000ff 3315#define rqe_size_WORD word10 3316 uint32_t word11; 3317#define hdr_pages_SHIFT 0 3318#define hdr_pages_MASK 0x0000000f 3319#define hdr_pages_WORD word11 3320#define hdr_size_SHIFT 8 3321#define hdr_size_MASK 0x0000000f 3322#define hdr_size_WORD word11 3323#define hdr_pp_align_SHIFT 16 3324#define hdr_pp_align_MASK 0x0000ffff 3325#define hdr_pp_align_WORD word11 3326 uint32_t word12; 3327#define sgl_pages_SHIFT 0 3328#define sgl_pages_MASK 0x0000000f 3329#define sgl_pages_WORD word12 3330#define sgl_pp_align_SHIFT 16 3331#define sgl_pp_align_MASK 0x0000ffff 3332#define sgl_pp_align_WORD word12 3333 uint32_t rsvd_13_63[51]; 3334}; 3335#define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3336 &(~((SLI4_PAGE_SIZE)-1))) 3337 3338struct lpfc_sli4_parameters { 3339 uint32_t word0; 3340#define cfg_prot_type_SHIFT 0 3341#define cfg_prot_type_MASK 0x000000FF 3342#define cfg_prot_type_WORD word0 3343 uint32_t word1; 3344#define cfg_ft_SHIFT 0 3345#define cfg_ft_MASK 0x00000001 3346#define cfg_ft_WORD word1 3347#define cfg_sli_rev_SHIFT 4 3348#define cfg_sli_rev_MASK 0x0000000f 3349#define cfg_sli_rev_WORD word1 3350#define cfg_sli_family_SHIFT 8 3351#define cfg_sli_family_MASK 0x0000000f 3352#define cfg_sli_family_WORD word1 3353#define cfg_if_type_SHIFT 12 3354#define cfg_if_type_MASK 0x0000000f 3355#define cfg_if_type_WORD word1 3356#define cfg_sli_hint_1_SHIFT 16 3357#define cfg_sli_hint_1_MASK 0x000000ff 3358#define cfg_sli_hint_1_WORD word1 3359#define cfg_sli_hint_2_SHIFT 24 3360#define cfg_sli_hint_2_MASK 0x0000001f 3361#define cfg_sli_hint_2_WORD word1 3362 uint32_t word2; 3363#define cfg_eqav_SHIFT 31 3364#define cfg_eqav_MASK 0x00000001 3365#define cfg_eqav_WORD word2 3366 uint32_t word3; 3367 uint32_t word4; 3368#define cfg_cqv_SHIFT 14 3369#define cfg_cqv_MASK 0x00000003 3370#define cfg_cqv_WORD word4 3371#define cfg_cqpsize_SHIFT 16 3372#define cfg_cqpsize_MASK 0x000000ff 3373#define cfg_cqpsize_WORD word4 3374#define cfg_cqav_SHIFT 31 3375#define cfg_cqav_MASK 0x00000001 3376#define cfg_cqav_WORD word4 3377 uint32_t word5; 3378 uint32_t word6; 3379#define cfg_mqv_SHIFT 14 3380#define cfg_mqv_MASK 0x00000003 3381#define cfg_mqv_WORD word6 3382 uint32_t word7; 3383 uint32_t word8; 3384#define cfg_wqpcnt_SHIFT 0 3385#define cfg_wqpcnt_MASK 0x0000000f 3386#define cfg_wqpcnt_WORD word8 3387#define cfg_wqsize_SHIFT 8 3388#define cfg_wqsize_MASK 0x0000000f 3389#define cfg_wqsize_WORD word8 3390#define cfg_wqv_SHIFT 14 3391#define cfg_wqv_MASK 0x00000003 3392#define cfg_wqv_WORD word8 3393#define cfg_wqpsize_SHIFT 16 3394#define cfg_wqpsize_MASK 0x000000ff 3395#define cfg_wqpsize_WORD word8 3396 uint32_t word9; 3397 uint32_t word10; 3398#define cfg_rqv_SHIFT 14 3399#define cfg_rqv_MASK 0x00000003 3400#define cfg_rqv_WORD word10 3401 uint32_t word11; 3402#define cfg_rq_db_window_SHIFT 28 3403#define cfg_rq_db_window_MASK 0x0000000f 3404#define cfg_rq_db_window_WORD word11 3405 uint32_t word12; 3406#define cfg_fcoe_SHIFT 0 3407#define cfg_fcoe_MASK 0x00000001 3408#define cfg_fcoe_WORD word12 3409#define cfg_ext_SHIFT 1 3410#define cfg_ext_MASK 0x00000001 3411#define cfg_ext_WORD word12 3412#define cfg_hdrr_SHIFT 2 3413#define cfg_hdrr_MASK 0x00000001 3414#define cfg_hdrr_WORD word12 3415#define cfg_phwq_SHIFT 15 3416#define cfg_phwq_MASK 0x00000001 3417#define cfg_phwq_WORD word12 3418#define cfg_oas_SHIFT 25 3419#define cfg_oas_MASK 0x00000001 3420#define cfg_oas_WORD word12 3421#define cfg_loopbk_scope_SHIFT 28 3422#define cfg_loopbk_scope_MASK 0x0000000f 3423#define cfg_loopbk_scope_WORD word12 3424 uint32_t sge_supp_len; 3425 uint32_t word14; 3426#define cfg_sgl_page_cnt_SHIFT 0 3427#define cfg_sgl_page_cnt_MASK 0x0000000f 3428#define cfg_sgl_page_cnt_WORD word14 3429#define cfg_sgl_page_size_SHIFT 8 3430#define cfg_sgl_page_size_MASK 0x000000ff 3431#define cfg_sgl_page_size_WORD word14 3432#define cfg_sgl_pp_align_SHIFT 16 3433#define cfg_sgl_pp_align_MASK 0x000000ff 3434#define cfg_sgl_pp_align_WORD word14 3435 uint32_t word15; 3436 uint32_t word16; 3437 uint32_t word17; 3438 uint32_t word18; 3439 uint32_t word19; 3440#define cfg_ext_embed_cb_SHIFT 0 3441#define cfg_ext_embed_cb_MASK 0x00000001 3442#define cfg_ext_embed_cb_WORD word19 3443#define cfg_mds_diags_SHIFT 1 3444#define cfg_mds_diags_MASK 0x00000001 3445#define cfg_mds_diags_WORD word19 3446#define cfg_nvme_SHIFT 3 3447#define cfg_nvme_MASK 0x00000001 3448#define cfg_nvme_WORD word19 3449#define cfg_xib_SHIFT 4 3450#define cfg_xib_MASK 0x00000001 3451#define cfg_xib_WORD word19 3452#define cfg_eqdr_SHIFT 8 3453#define cfg_eqdr_MASK 0x00000001 3454#define cfg_eqdr_WORD word19 3455#define cfg_nosr_SHIFT 9 3456#define cfg_nosr_MASK 0x00000001 3457#define cfg_nosr_WORD word19 3458 3459#define cfg_bv1s_SHIFT 10 3460#define cfg_bv1s_MASK 0x00000001 3461#define cfg_bv1s_WORD word19 3462 3463 uint32_t word20; 3464#define cfg_max_tow_xri_SHIFT 0 3465#define cfg_max_tow_xri_MASK 0x0000ffff 3466#define cfg_max_tow_xri_WORD word20 3467 3468 uint32_t word21; /* RESERVED */ 3469 uint32_t word22; /* RESERVED */ 3470 uint32_t word23; /* RESERVED */ 3471 3472 uint32_t word24; 3473#define cfg_frag_field_offset_SHIFT 0 3474#define cfg_frag_field_offset_MASK 0x0000ffff 3475#define cfg_frag_field_offset_WORD word24 3476 3477#define cfg_frag_field_size_SHIFT 16 3478#define cfg_frag_field_size_MASK 0x0000ffff 3479#define cfg_frag_field_size_WORD word24 3480 3481 uint32_t word25; 3482#define cfg_sgl_field_offset_SHIFT 0 3483#define cfg_sgl_field_offset_MASK 0x0000ffff 3484#define cfg_sgl_field_offset_WORD word25 3485 3486#define cfg_sgl_field_size_SHIFT 16 3487#define cfg_sgl_field_size_MASK 0x0000ffff 3488#define cfg_sgl_field_size_WORD word25 3489 3490 uint32_t word26; /* Chain SGE initial value LOW */ 3491 uint32_t word27; /* Chain SGE initial value HIGH */ 3492#define LPFC_NODELAY_MAX_IO 32 3493}; 3494 3495#define LPFC_SET_UE_RECOVERY 0x10 3496#define LPFC_SET_MDS_DIAGS 0x11 3497struct lpfc_mbx_set_feature { 3498 struct mbox_header header; 3499 uint32_t feature; 3500 uint32_t param_len; 3501 uint32_t word6; 3502#define lpfc_mbx_set_feature_UER_SHIFT 0 3503#define lpfc_mbx_set_feature_UER_MASK 0x00000001 3504#define lpfc_mbx_set_feature_UER_WORD word6 3505#define lpfc_mbx_set_feature_mds_SHIFT 0 3506#define lpfc_mbx_set_feature_mds_MASK 0x00000001 3507#define lpfc_mbx_set_feature_mds_WORD word6 3508#define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3509#define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3510#define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3511 uint32_t word7; 3512#define lpfc_mbx_set_feature_UERP_SHIFT 0 3513#define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3514#define lpfc_mbx_set_feature_UERP_WORD word7 3515#define lpfc_mbx_set_feature_UESR_SHIFT 16 3516#define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3517#define lpfc_mbx_set_feature_UESR_WORD word7 3518}; 3519 3520 3521#define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3522struct lpfc_mbx_set_host_data { 3523#define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3524 struct mbox_header header; 3525 uint32_t param_id; 3526 uint32_t param_len; 3527 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3528}; 3529 3530struct lpfc_mbx_set_trunk_mode { 3531 struct mbox_header header; 3532 uint32_t word0; 3533#define lpfc_mbx_set_trunk_mode_WORD word0 3534#define lpfc_mbx_set_trunk_mode_SHIFT 0 3535#define lpfc_mbx_set_trunk_mode_MASK 0xFF 3536 uint32_t word1; 3537 uint32_t word2; 3538}; 3539 3540struct lpfc_mbx_get_sli4_parameters { 3541 struct mbox_header header; 3542 struct lpfc_sli4_parameters sli4_parameters; 3543}; 3544 3545struct lpfc_rscr_desc_generic { 3546#define LPFC_RSRC_DESC_WSIZE 22 3547 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3548}; 3549 3550struct lpfc_rsrc_desc_pcie { 3551 uint32_t word0; 3552#define lpfc_rsrc_desc_pcie_type_SHIFT 0 3553#define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3554#define lpfc_rsrc_desc_pcie_type_WORD word0 3555#define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3556#define lpfc_rsrc_desc_pcie_length_SHIFT 8 3557#define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3558#define lpfc_rsrc_desc_pcie_length_WORD word0 3559 uint32_t word1; 3560#define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3561#define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3562#define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3563 uint32_t reserved; 3564 uint32_t word3; 3565#define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3566#define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3567#define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3568#define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3569#define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3570#define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3571#define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3572#define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3573#define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3574 uint32_t word4; 3575#define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3576#define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3577#define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3578}; 3579 3580struct lpfc_rsrc_desc_fcfcoe { 3581 uint32_t word0; 3582#define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3583#define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3584#define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3585#define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3586#define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3587#define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3588#define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3589#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3590#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3591#define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3592 uint32_t word1; 3593#define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3594#define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3595#define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3596#define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3597#define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3598#define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3599 uint32_t word2; 3600#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3601#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3602#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3603#define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3604#define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3605#define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3606 uint32_t word3; 3607#define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3608#define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3609#define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3610#define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3611#define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3612#define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3613 uint32_t word4; 3614#define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3615#define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3616#define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3617#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3618#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3619#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3620 uint32_t word5; 3621#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3622#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3623#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3624#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3625#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3626#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3627 uint32_t word6; 3628 uint32_t word7; 3629 uint32_t word8; 3630 uint32_t word9; 3631 uint32_t word10; 3632 uint32_t word11; 3633 uint32_t word12; 3634 uint32_t word13; 3635#define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3636#define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3637#define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3638#define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3639#define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3640#define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3641#define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3642#define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3643#define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3644#define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3645#define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3646#define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3647#define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3648#define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3649#define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3650/* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3651 uint32_t bw_min; 3652 uint32_t bw_max; 3653 uint32_t iops_min; 3654 uint32_t iops_max; 3655 uint32_t reserved[4]; 3656}; 3657 3658struct lpfc_func_cfg { 3659#define LPFC_RSRC_DESC_MAX_NUM 2 3660 uint32_t rsrc_desc_count; 3661 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3662}; 3663 3664struct lpfc_mbx_get_func_cfg { 3665 struct mbox_header header; 3666#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3667#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3668#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3669 struct lpfc_func_cfg func_cfg; 3670}; 3671 3672struct lpfc_prof_cfg { 3673#define LPFC_RSRC_DESC_MAX_NUM 2 3674 uint32_t rsrc_desc_count; 3675 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3676}; 3677 3678struct lpfc_mbx_get_prof_cfg { 3679 struct mbox_header header; 3680#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3681#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3682#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3683 union { 3684 struct { 3685 uint32_t word10; 3686#define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3687#define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3688#define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3689#define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3690#define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3691#define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3692 } request; 3693 struct { 3694 struct lpfc_prof_cfg prof_cfg; 3695 } response; 3696 } u; 3697}; 3698 3699struct lpfc_controller_attribute { 3700 uint32_t version_string[8]; 3701 uint32_t manufacturer_name[8]; 3702 uint32_t supported_modes; 3703 uint32_t word17; 3704#define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3705#define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3706#define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3707#define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3708#define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3709#define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3710 uint32_t mbx_da_struct_ver; 3711 uint32_t ep_fw_da_struct_ver; 3712 uint32_t ncsi_ver_str[3]; 3713 uint32_t dflt_ext_timeout; 3714 uint32_t model_number[8]; 3715 uint32_t description[16]; 3716 uint32_t serial_number[8]; 3717 uint32_t ip_ver_str[8]; 3718 uint32_t fw_ver_str[8]; 3719 uint32_t bios_ver_str[8]; 3720 uint32_t redboot_ver_str[8]; 3721 uint32_t driver_ver_str[8]; 3722 uint32_t flash_fw_ver_str[8]; 3723 uint32_t functionality; 3724 uint32_t word105; 3725#define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3726#define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3727#define lpfc_cntl_attr_max_cbd_len_WORD word105 3728#define lpfc_cntl_attr_asic_rev_SHIFT 16 3729#define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3730#define lpfc_cntl_attr_asic_rev_WORD word105 3731#define lpfc_cntl_attr_gen_guid0_SHIFT 24 3732#define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3733#define lpfc_cntl_attr_gen_guid0_WORD word105 3734 uint32_t gen_guid1_12[3]; 3735 uint32_t word109; 3736#define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3737#define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3738#define lpfc_cntl_attr_gen_guid13_14_WORD word109 3739#define lpfc_cntl_attr_gen_guid15_SHIFT 16 3740#define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3741#define lpfc_cntl_attr_gen_guid15_WORD word109 3742#define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3743#define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3744#define lpfc_cntl_attr_hba_port_cnt_WORD word109 3745 uint32_t word110; 3746#define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3747#define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3748#define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3749#define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3750#define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3751#define lpfc_cntl_attr_multi_func_dev_WORD word110 3752 uint32_t word111; 3753#define lpfc_cntl_attr_cache_valid_SHIFT 0 3754#define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3755#define lpfc_cntl_attr_cache_valid_WORD word111 3756#define lpfc_cntl_attr_hba_status_SHIFT 8 3757#define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3758#define lpfc_cntl_attr_hba_status_WORD word111 3759#define lpfc_cntl_attr_max_domain_SHIFT 16 3760#define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3761#define lpfc_cntl_attr_max_domain_WORD word111 3762#define lpfc_cntl_attr_lnk_numb_SHIFT 24 3763#define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3764#define lpfc_cntl_attr_lnk_numb_WORD word111 3765#define lpfc_cntl_attr_lnk_type_SHIFT 30 3766#define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3767#define lpfc_cntl_attr_lnk_type_WORD word111 3768 uint32_t fw_post_status; 3769 uint32_t hba_mtu[8]; 3770 uint32_t word121; 3771 uint32_t reserved1[3]; 3772 uint32_t word125; 3773#define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3774#define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3775#define lpfc_cntl_attr_pci_vendor_id_WORD word125 3776#define lpfc_cntl_attr_pci_device_id_SHIFT 16 3777#define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3778#define lpfc_cntl_attr_pci_device_id_WORD word125 3779 uint32_t word126; 3780#define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3781#define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3782#define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3783#define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3784#define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3785#define lpfc_cntl_attr_pci_subsys_id_WORD word126 3786 uint32_t word127; 3787#define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3788#define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3789#define lpfc_cntl_attr_pci_bus_num_WORD word127 3790#define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3791#define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3792#define lpfc_cntl_attr_pci_dev_num_WORD word127 3793#define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3794#define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3795#define lpfc_cntl_attr_pci_fnc_num_WORD word127 3796#define lpfc_cntl_attr_inf_type_SHIFT 24 3797#define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3798#define lpfc_cntl_attr_inf_type_WORD word127 3799 uint32_t unique_id[2]; 3800 uint32_t word130; 3801#define lpfc_cntl_attr_num_netfil_SHIFT 0 3802#define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3803#define lpfc_cntl_attr_num_netfil_WORD word130 3804 uint32_t reserved2[4]; 3805}; 3806 3807struct lpfc_mbx_get_cntl_attributes { 3808 union lpfc_sli4_cfg_shdr cfg_shdr; 3809 struct lpfc_controller_attribute cntl_attr; 3810}; 3811 3812struct lpfc_mbx_get_port_name { 3813 struct mbox_header header; 3814 union { 3815 struct { 3816 uint32_t word4; 3817#define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3818#define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3819#define lpfc_mbx_get_port_name_lnk_type_WORD word4 3820 } request; 3821 struct { 3822 uint32_t word4; 3823#define lpfc_mbx_get_port_name_name0_SHIFT 0 3824#define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3825#define lpfc_mbx_get_port_name_name0_WORD word4 3826#define lpfc_mbx_get_port_name_name1_SHIFT 8 3827#define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3828#define lpfc_mbx_get_port_name_name1_WORD word4 3829#define lpfc_mbx_get_port_name_name2_SHIFT 16 3830#define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3831#define lpfc_mbx_get_port_name_name2_WORD word4 3832#define lpfc_mbx_get_port_name_name3_SHIFT 24 3833#define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3834#define lpfc_mbx_get_port_name_name3_WORD word4 3835#define LPFC_LINK_NUMBER_0 0 3836#define LPFC_LINK_NUMBER_1 1 3837#define LPFC_LINK_NUMBER_2 2 3838#define LPFC_LINK_NUMBER_3 3 3839 } response; 3840 } u; 3841}; 3842 3843/* Mailbox Completion Queue Error Messages */ 3844#define MB_CQE_STATUS_SUCCESS 0x0 3845#define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3846#define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3847#define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3848#define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3849#define MB_CQE_STATUS_DMA_FAILED 0x5 3850 3851#define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3852struct lpfc_mbx_wr_object { 3853 struct mbox_header header; 3854 union { 3855 struct { 3856 uint32_t word4; 3857#define lpfc_wr_object_eof_SHIFT 31 3858#define lpfc_wr_object_eof_MASK 0x00000001 3859#define lpfc_wr_object_eof_WORD word4 3860#define lpfc_wr_object_eas_SHIFT 29 3861#define lpfc_wr_object_eas_MASK 0x00000001 3862#define lpfc_wr_object_eas_WORD word4 3863#define lpfc_wr_object_write_length_SHIFT 0 3864#define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3865#define lpfc_wr_object_write_length_WORD word4 3866 uint32_t write_offset; 3867 uint32_t object_name[26]; 3868 uint32_t bde_count; 3869 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3870 } request; 3871 struct { 3872 uint32_t actual_write_length; 3873 uint32_t word5; 3874#define lpfc_wr_object_change_status_SHIFT 0 3875#define lpfc_wr_object_change_status_MASK 0x000000FF 3876#define lpfc_wr_object_change_status_WORD word5 3877#define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3878#define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3879#define LPFC_CHANGE_STATUS_FW_RESET 0x02 3880#define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3881#define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3882 } response; 3883 } u; 3884}; 3885 3886/* mailbox queue entry structure */ 3887struct lpfc_mqe { 3888 uint32_t word0; 3889#define lpfc_mqe_status_SHIFT 16 3890#define lpfc_mqe_status_MASK 0x0000FFFF 3891#define lpfc_mqe_status_WORD word0 3892#define lpfc_mqe_command_SHIFT 8 3893#define lpfc_mqe_command_MASK 0x000000FF 3894#define lpfc_mqe_command_WORD word0 3895 union { 3896 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3897 /* sli4 mailbox commands */ 3898 struct lpfc_mbx_sli4_config sli4_config; 3899 struct lpfc_mbx_init_vfi init_vfi; 3900 struct lpfc_mbx_reg_vfi reg_vfi; 3901 struct lpfc_mbx_reg_vfi unreg_vfi; 3902 struct lpfc_mbx_init_vpi init_vpi; 3903 struct lpfc_mbx_resume_rpi resume_rpi; 3904 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3905 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3906 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3907 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3908 struct lpfc_mbx_reg_fcfi reg_fcfi; 3909 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3910 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3911 struct lpfc_mbx_mq_create mq_create; 3912 struct lpfc_mbx_mq_create_ext mq_create_ext; 3913 struct lpfc_mbx_eq_create eq_create; 3914 struct lpfc_mbx_modify_eq_delay eq_delay; 3915 struct lpfc_mbx_cq_create cq_create; 3916 struct lpfc_mbx_cq_create_set cq_create_set; 3917 struct lpfc_mbx_wq_create wq_create; 3918 struct lpfc_mbx_rq_create rq_create; 3919 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3920 struct lpfc_mbx_mq_destroy mq_destroy; 3921 struct lpfc_mbx_eq_destroy eq_destroy; 3922 struct lpfc_mbx_cq_destroy cq_destroy; 3923 struct lpfc_mbx_wq_destroy wq_destroy; 3924 struct lpfc_mbx_rq_destroy rq_destroy; 3925 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3926 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3927 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3928 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3929 struct lpfc_mbx_nembed_cmd nembed_cmd; 3930 struct lpfc_mbx_read_rev read_rev; 3931 struct lpfc_mbx_read_vpi read_vpi; 3932 struct lpfc_mbx_read_config rd_config; 3933 struct lpfc_mbx_request_features req_ftrs; 3934 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3935 struct lpfc_mbx_query_fw_config query_fw_cfg; 3936 struct lpfc_mbx_set_beacon_config beacon_config; 3937 struct lpfc_mbx_supp_pages supp_pages; 3938 struct lpfc_mbx_pc_sli4_params sli4_params; 3939 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3940 struct lpfc_mbx_set_link_diag_state link_diag_state; 3941 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3942 struct lpfc_mbx_run_link_diag_test link_diag_test; 3943 struct lpfc_mbx_get_func_cfg get_func_cfg; 3944 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3945 struct lpfc_mbx_wr_object wr_object; 3946 struct lpfc_mbx_get_port_name get_port_name; 3947 struct lpfc_mbx_set_feature set_feature; 3948 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3949 struct lpfc_mbx_set_host_data set_host_data; 3950 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 3951 struct lpfc_mbx_nop nop; 3952 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 3953 } un; 3954}; 3955 3956struct lpfc_mcqe { 3957 uint32_t word0; 3958#define lpfc_mcqe_status_SHIFT 0 3959#define lpfc_mcqe_status_MASK 0x0000FFFF 3960#define lpfc_mcqe_status_WORD word0 3961#define lpfc_mcqe_ext_status_SHIFT 16 3962#define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3963#define lpfc_mcqe_ext_status_WORD word0 3964 uint32_t mcqe_tag0; 3965 uint32_t mcqe_tag1; 3966 uint32_t trailer; 3967#define lpfc_trailer_valid_SHIFT 31 3968#define lpfc_trailer_valid_MASK 0x00000001 3969#define lpfc_trailer_valid_WORD trailer 3970#define lpfc_trailer_async_SHIFT 30 3971#define lpfc_trailer_async_MASK 0x00000001 3972#define lpfc_trailer_async_WORD trailer 3973#define lpfc_trailer_hpi_SHIFT 29 3974#define lpfc_trailer_hpi_MASK 0x00000001 3975#define lpfc_trailer_hpi_WORD trailer 3976#define lpfc_trailer_completed_SHIFT 28 3977#define lpfc_trailer_completed_MASK 0x00000001 3978#define lpfc_trailer_completed_WORD trailer 3979#define lpfc_trailer_consumed_SHIFT 27 3980#define lpfc_trailer_consumed_MASK 0x00000001 3981#define lpfc_trailer_consumed_WORD trailer 3982#define lpfc_trailer_type_SHIFT 16 3983#define lpfc_trailer_type_MASK 0x000000FF 3984#define lpfc_trailer_type_WORD trailer 3985#define lpfc_trailer_code_SHIFT 8 3986#define lpfc_trailer_code_MASK 0x000000FF 3987#define lpfc_trailer_code_WORD trailer 3988#define LPFC_TRAILER_CODE_LINK 0x1 3989#define LPFC_TRAILER_CODE_FCOE 0x2 3990#define LPFC_TRAILER_CODE_DCBX 0x3 3991#define LPFC_TRAILER_CODE_GRP5 0x5 3992#define LPFC_TRAILER_CODE_FC 0x10 3993#define LPFC_TRAILER_CODE_SLI 0x11 3994}; 3995 3996struct lpfc_acqe_link { 3997 uint32_t word0; 3998#define lpfc_acqe_link_speed_SHIFT 24 3999#define lpfc_acqe_link_speed_MASK 0x000000FF 4000#define lpfc_acqe_link_speed_WORD word0
4001#define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 4002#define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 4003#define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 4004#define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 4005#define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 4006#define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4007#define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4008#define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4009#define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4010#define lpfc_acqe_link_duplex_SHIFT 16 4011#define lpfc_acqe_link_duplex_MASK 0x000000FF 4012#define lpfc_acqe_link_duplex_WORD word0 4013#define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4014#define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4015#define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4016#define lpfc_acqe_link_status_SHIFT 8 4017#define lpfc_acqe_link_status_MASK 0x000000FF 4018#define lpfc_acqe_link_status_WORD word0 4019#define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4020#define LPFC_ASYNC_LINK_STATUS_UP 0x1 4021#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4022#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4023#define lpfc_acqe_link_type_SHIFT 6 4024#define lpfc_acqe_link_type_MASK 0x00000003 4025#define lpfc_acqe_link_type_WORD word0 4026#define lpfc_acqe_link_number_SHIFT 0 4027#define lpfc_acqe_link_number_MASK 0x0000003F 4028#define lpfc_acqe_link_number_WORD word0 4029 uint32_t word1; 4030#define lpfc_acqe_link_fault_SHIFT 0 4031#define lpfc_acqe_link_fault_MASK 0x000000FF 4032#define lpfc_acqe_link_fault_WORD word1 4033#define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4034#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4035#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4036#define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4037#define lpfc_acqe_logical_link_speed_SHIFT 16 4038#define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4039#define lpfc_acqe_logical_link_speed_WORD word1 4040 uint32_t event_tag; 4041 uint32_t trailer; 4042#define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4043#define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4044}; 4045 4046struct lpfc_acqe_fip { 4047 uint32_t index; 4048 uint32_t word1; 4049#define lpfc_acqe_fip_fcf_count_SHIFT 0 4050#define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4051#define lpfc_acqe_fip_fcf_count_WORD word1 4052#define lpfc_acqe_fip_event_type_SHIFT 16 4053#define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4054#define lpfc_acqe_fip_event_type_WORD word1 4055 uint32_t event_tag; 4056 uint32_t trailer; 4057#define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4058#define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4059#define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4060#define LPFC_FIP_EVENT_TYPE_CVL 0x4 4061#define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4062}; 4063 4064struct lpfc_acqe_dcbx { 4065 uint32_t tlv_ttl; 4066 uint32_t reserved; 4067 uint32_t event_tag; 4068 uint32_t trailer; 4069}; 4070 4071struct lpfc_acqe_grp5 { 4072 uint32_t word0; 4073#define lpfc_acqe_grp5_type_SHIFT 6 4074#define lpfc_acqe_grp5_type_MASK 0x00000003 4075#define lpfc_acqe_grp5_type_WORD word0 4076#define lpfc_acqe_grp5_number_SHIFT 0 4077#define lpfc_acqe_grp5_number_MASK 0x0000003F 4078#define lpfc_acqe_grp5_number_WORD word0 4079 uint32_t word1; 4080#define lpfc_acqe_grp5_llink_spd_SHIFT 16 4081#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4082#define lpfc_acqe_grp5_llink_spd_WORD word1 4083 uint32_t event_tag; 4084 uint32_t trailer; 4085}; 4086 4087extern const char *const trunk_errmsg[]; 4088 4089struct lpfc_acqe_fc_la { 4090 uint32_t word0; 4091#define lpfc_acqe_fc_la_speed_SHIFT 24 4092#define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4093#define lpfc_acqe_fc_la_speed_WORD word0 4094#define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4095#define LPFC_FC_LA_SPEED_1G 0x1 4096#define LPFC_FC_LA_SPEED_2G 0x2 4097#define LPFC_FC_LA_SPEED_4G 0x4 4098#define LPFC_FC_LA_SPEED_8G 0x8 4099#define LPFC_FC_LA_SPEED_10G 0xA 4100#define LPFC_FC_LA_SPEED_16G 0x10 4101#define LPFC_FC_LA_SPEED_32G 0x20 4102#define LPFC_FC_LA_SPEED_64G 0x21 4103#define LPFC_FC_LA_SPEED_128G 0x22 4104#define LPFC_FC_LA_SPEED_256G 0x23 4105#define lpfc_acqe_fc_la_topology_SHIFT 16 4106#define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4107#define lpfc_acqe_fc_la_topology_WORD word0 4108#define LPFC_FC_LA_TOP_UNKOWN 0x0 4109#define LPFC_FC_LA_TOP_P2P 0x1 4110#define LPFC_FC_LA_TOP_FCAL 0x2 4111#define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4112#define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4113#define lpfc_acqe_fc_la_att_type_SHIFT 8 4114#define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4115#define lpfc_acqe_fc_la_att_type_WORD word0 4116#define LPFC_FC_LA_TYPE_LINK_UP 0x1 4117#define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4118#define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4119#define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4120#define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4121#define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4122#define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4123#define lpfc_acqe_fc_la_port_type_SHIFT 6 4124#define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4125#define lpfc_acqe_fc_la_port_type_WORD word0 4126#define LPFC_LINK_TYPE_ETHERNET 0x0 4127#define LPFC_LINK_TYPE_FC 0x1 4128#define lpfc_acqe_fc_la_port_number_SHIFT 0 4129#define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4130#define lpfc_acqe_fc_la_port_number_WORD word0 4131 4132/* Attention Type is 0x07 (Trunking Event) word0 */ 4133#define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4134#define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4135#define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4136#define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4137#define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4138#define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4139#define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4140#define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4141#define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4142#define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4143#define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4144#define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4145#define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4146#define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4147#define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4148#define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4149#define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4150#define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4151#define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4152#define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4153#define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4154#define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4155#define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4156#define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4157 uint32_t word1; 4158#define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4159#define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4160#define lpfc_acqe_fc_la_llink_spd_WORD word1 4161#define lpfc_acqe_fc_la_fault_SHIFT 0 4162#define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4163#define lpfc_acqe_fc_la_fault_WORD word1 4164#define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4165#define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4166#define lpfc_acqe_fc_la_trunk_fault_WORD word1 4167#define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4168#define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4169#define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4170#define LPFC_FC_LA_FAULT_NONE 0x0 4171#define LPFC_FC_LA_FAULT_LOCAL 0x1 4172#define LPFC_FC_LA_FAULT_REMOTE 0x2 4173 uint32_t event_tag; 4174 uint32_t trailer; 4175#define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4176#define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4177}; 4178 4179struct lpfc_acqe_misconfigured_event { 4180 struct { 4181 uint32_t word0; 4182#define lpfc_sli_misconfigured_port0_state_SHIFT 0 4183#define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4184#define lpfc_sli_misconfigured_port0_state_WORD word0 4185#define lpfc_sli_misconfigured_port1_state_SHIFT 8 4186#define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4187#define lpfc_sli_misconfigured_port1_state_WORD word0 4188#define lpfc_sli_misconfigured_port2_state_SHIFT 16 4189#define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4190#define lpfc_sli_misconfigured_port2_state_WORD word0 4191#define lpfc_sli_misconfigured_port3_state_SHIFT 24 4192#define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4193#define lpfc_sli_misconfigured_port3_state_WORD word0 4194 uint32_t word1; 4195#define lpfc_sli_misconfigured_port0_op_SHIFT 0 4196#define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4197#define lpfc_sli_misconfigured_port0_op_WORD word1 4198#define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4199#define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4200#define lpfc_sli_misconfigured_port0_severity_WORD word1 4201#define lpfc_sli_misconfigured_port1_op_SHIFT 8 4202#define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4203#define lpfc_sli_misconfigured_port1_op_WORD word1 4204#define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4205#define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4206#define lpfc_sli_misconfigured_port1_severity_WORD word1 4207#define lpfc_sli_misconfigured_port2_op_SHIFT 16 4208#define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4209#define lpfc_sli_misconfigured_port2_op_WORD word1 4210#define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4211#define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4212#define lpfc_sli_misconfigured_port2_severity_WORD word1 4213#define lpfc_sli_misconfigured_port3_op_SHIFT 24 4214#define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4215#define lpfc_sli_misconfigured_port3_op_WORD word1 4216#define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4217#define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4218#define lpfc_sli_misconfigured_port3_severity_WORD word1 4219 } theEvent; 4220#define LPFC_SLI_EVENT_STATUS_VALID 0x00 4221#define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4222#define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4223#define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4224#define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4225#define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4226}; 4227 4228struct lpfc_acqe_sli { 4229 uint32_t event_data1; 4230 uint32_t event_data2; 4231 uint32_t reserved; 4232 uint32_t trailer; 4233#define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4234#define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4235#define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4236#define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4237#define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4238#define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4239#define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4240}; 4241 4242/* 4243 * Define the bootstrap mailbox (bmbx) region used to communicate 4244 * mailbox command between the host and port. The mailbox consists 4245 * of a payload area of 256 bytes and a completion queue of length 4246 * 16 bytes. 4247 */ 4248struct lpfc_bmbx_create { 4249 struct lpfc_mqe mqe; 4250 struct lpfc_mcqe mcqe; 4251}; 4252 4253#define SGL_ALIGN_SZ 64 4254#define SGL_PAGE_SIZE 4096 4255/* align SGL addr on a size boundary - adjust address up */ 4256#define NO_XRI 0xffff 4257 4258struct wqe_common { 4259 uint32_t word6; 4260#define wqe_xri_tag_SHIFT 0 4261#define wqe_xri_tag_MASK 0x0000FFFF 4262#define wqe_xri_tag_WORD word6 4263#define wqe_ctxt_tag_SHIFT 16 4264#define wqe_ctxt_tag_MASK 0x0000FFFF 4265#define wqe_ctxt_tag_WORD word6 4266 uint32_t word7; 4267#define wqe_dif_SHIFT 0 4268#define wqe_dif_MASK 0x00000003 4269#define wqe_dif_WORD word7 4270#define LPFC_WQE_DIF_PASSTHRU 1 4271#define LPFC_WQE_DIF_STRIP 2 4272#define LPFC_WQE_DIF_INSERT 3 4273#define wqe_ct_SHIFT 2 4274#define wqe_ct_MASK 0x00000003 4275#define wqe_ct_WORD word7 4276#define wqe_status_SHIFT 4 4277#define wqe_status_MASK 0x0000000f 4278#define wqe_status_WORD word7 4279#define wqe_cmnd_SHIFT 8 4280#define wqe_cmnd_MASK 0x000000ff 4281#define wqe_cmnd_WORD word7 4282#define wqe_class_SHIFT 16 4283#define wqe_class_MASK 0x00000007 4284#define wqe_class_WORD word7 4285#define wqe_ar_SHIFT 19 4286#define wqe_ar_MASK 0x00000001 4287#define wqe_ar_WORD word7 4288#define wqe_ag_SHIFT wqe_ar_SHIFT 4289#define wqe_ag_MASK wqe_ar_MASK 4290#define wqe_ag_WORD wqe_ar_WORD 4291#define wqe_pu_SHIFT 20 4292#define wqe_pu_MASK 0x00000003 4293#define wqe_pu_WORD word7 4294#define wqe_erp_SHIFT 22 4295#define wqe_erp_MASK 0x00000001 4296#define wqe_erp_WORD word7 4297#define wqe_conf_SHIFT wqe_erp_SHIFT 4298#define wqe_conf_MASK wqe_erp_MASK 4299#define wqe_conf_WORD wqe_erp_WORD 4300#define wqe_lnk_SHIFT 23 4301#define wqe_lnk_MASK 0x00000001 4302#define wqe_lnk_WORD word7 4303#define wqe_tmo_SHIFT 24 4304#define wqe_tmo_MASK 0x000000ff 4305#define wqe_tmo_WORD word7 4306 uint32_t abort_tag; /* word 8 in WQE */ 4307 uint32_t word9; 4308#define wqe_reqtag_SHIFT 0 4309#define wqe_reqtag_MASK 0x0000FFFF 4310#define wqe_reqtag_WORD word9 4311#define wqe_temp_rpi_SHIFT 16 4312#define wqe_temp_rpi_MASK 0x0000FFFF 4313#define wqe_temp_rpi_WORD word9 4314#define wqe_rcvoxid_SHIFT 16 4315#define wqe_rcvoxid_MASK 0x0000FFFF 4316#define wqe_rcvoxid_WORD word9 4317 uint32_t word10; 4318#define wqe_ebde_cnt_SHIFT 0 4319#define wqe_ebde_cnt_MASK 0x0000000f 4320#define wqe_ebde_cnt_WORD word10 4321#define wqe_nvme_SHIFT 4 4322#define wqe_nvme_MASK 0x00000001 4323#define wqe_nvme_WORD word10 4324#define wqe_oas_SHIFT 6 4325#define wqe_oas_MASK 0x00000001 4326#define wqe_oas_WORD word10 4327#define wqe_lenloc_SHIFT 7 4328#define wqe_lenloc_MASK 0x00000003 4329#define wqe_lenloc_WORD word10 4330#define LPFC_WQE_LENLOC_NONE 0 4331#define LPFC_WQE_LENLOC_WORD3 1 4332#define LPFC_WQE_LENLOC_WORD12 2 4333#define LPFC_WQE_LENLOC_WORD4 3 4334#define wqe_qosd_SHIFT 9 4335#define wqe_qosd_MASK 0x00000001 4336#define wqe_qosd_WORD word10 4337#define wqe_xbl_SHIFT 11 4338#define wqe_xbl_MASK 0x00000001 4339#define wqe_xbl_WORD word10 4340#define wqe_iod_SHIFT 13 4341#define wqe_iod_MASK 0x00000001 4342#define wqe_iod_WORD word10 4343#define LPFC_WQE_IOD_NONE 0 4344#define LPFC_WQE_IOD_WRITE 0 4345#define LPFC_WQE_IOD_READ 1 4346#define wqe_dbde_SHIFT 14 4347#define wqe_dbde_MASK 0x00000001 4348#define wqe_dbde_WORD word10 4349#define wqe_wqes_SHIFT 15 4350#define wqe_wqes_MASK 0x00000001 4351#define wqe_wqes_WORD word10 4352/* Note that this field overlaps above fields */ 4353#define wqe_wqid_SHIFT 1 4354#define wqe_wqid_MASK 0x00007fff 4355#define wqe_wqid_WORD word10 4356#define wqe_pri_SHIFT 16 4357#define wqe_pri_MASK 0x00000007 4358#define wqe_pri_WORD word10 4359#define wqe_pv_SHIFT 19 4360#define wqe_pv_MASK 0x00000001 4361#define wqe_pv_WORD word10 4362#define wqe_xc_SHIFT 21 4363#define wqe_xc_MASK 0x00000001 4364#define wqe_xc_WORD word10 4365#define wqe_sr_SHIFT 22 4366#define wqe_sr_MASK 0x00000001 4367#define wqe_sr_WORD word10 4368#define wqe_ccpe_SHIFT 23 4369#define wqe_ccpe_MASK 0x00000001 4370#define wqe_ccpe_WORD word10 4371#define wqe_ccp_SHIFT 24 4372#define wqe_ccp_MASK 0x000000ff 4373#define wqe_ccp_WORD word10 4374 uint32_t word11; 4375#define wqe_cmd_type_SHIFT 0 4376#define wqe_cmd_type_MASK 0x0000000f 4377#define wqe_cmd_type_WORD word11 4378#define wqe_els_id_SHIFT 4 4379#define wqe_els_id_MASK 0x00000003 4380#define wqe_els_id_WORD word11 4381#define LPFC_ELS_ID_FLOGI 3 4382#define LPFC_ELS_ID_FDISC 2 4383#define LPFC_ELS_ID_LOGO 1 4384#define LPFC_ELS_ID_DEFAULT 0 4385#define wqe_irsp_SHIFT 4 4386#define wqe_irsp_MASK 0x00000001 4387#define wqe_irsp_WORD word11 4388#define wqe_pbde_SHIFT 5 4389#define wqe_pbde_MASK 0x00000001 4390#define wqe_pbde_WORD word11 4391#define wqe_sup_SHIFT 6 4392#define wqe_sup_MASK 0x00000001 4393#define wqe_sup_WORD word11 4394#define wqe_wqec_SHIFT 7 4395#define wqe_wqec_MASK 0x00000001 4396#define wqe_wqec_WORD word11 4397#define wqe_irsplen_SHIFT 8 4398#define wqe_irsplen_MASK 0x0000000f 4399#define wqe_irsplen_WORD word11 4400#define wqe_cqid_SHIFT 16 4401#define wqe_cqid_MASK 0x0000ffff 4402#define wqe_cqid_WORD word11 4403#define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4404}; 4405 4406struct wqe_did { 4407 uint32_t word5; 4408#define wqe_els_did_SHIFT 0 4409#define wqe_els_did_MASK 0x00FFFFFF 4410#define wqe_els_did_WORD word5 4411#define wqe_xmit_bls_pt_SHIFT 28 4412#define wqe_xmit_bls_pt_MASK 0x00000003 4413#define wqe_xmit_bls_pt_WORD word5 4414#define wqe_xmit_bls_ar_SHIFT 30 4415#define wqe_xmit_bls_ar_MASK 0x00000001 4416#define wqe_xmit_bls_ar_WORD word5 4417#define wqe_xmit_bls_xo_SHIFT 31 4418#define wqe_xmit_bls_xo_MASK 0x00000001 4419#define wqe_xmit_bls_xo_WORD word5 4420}; 4421 4422struct lpfc_wqe_generic{ 4423 struct ulp_bde64 bde; 4424 uint32_t word3; 4425 uint32_t word4; 4426 uint32_t word5; 4427 struct wqe_common wqe_com; 4428 uint32_t payload[4]; 4429}; 4430 4431struct els_request64_wqe { 4432 struct ulp_bde64 bde; 4433 uint32_t payload_len; 4434 uint32_t word4; 4435#define els_req64_sid_SHIFT 0 4436#define els_req64_sid_MASK 0x00FFFFFF 4437#define els_req64_sid_WORD word4 4438#define els_req64_sp_SHIFT 24 4439#define els_req64_sp_MASK 0x00000001 4440#define els_req64_sp_WORD word4 4441#define els_req64_vf_SHIFT 25 4442#define els_req64_vf_MASK 0x00000001 4443#define els_req64_vf_WORD word4 4444 struct wqe_did wqe_dest; 4445 struct wqe_common wqe_com; /* words 6-11 */ 4446 uint32_t word12; 4447#define els_req64_vfid_SHIFT 1 4448#define els_req64_vfid_MASK 0x00000FFF 4449#define els_req64_vfid_WORD word12 4450#define els_req64_pri_SHIFT 13 4451#define els_req64_pri_MASK 0x00000007 4452#define els_req64_pri_WORD word12 4453 uint32_t word13; 4454#define els_req64_hopcnt_SHIFT 24 4455#define els_req64_hopcnt_MASK 0x000000ff 4456#define els_req64_hopcnt_WORD word13 4457 uint32_t word14; 4458 uint32_t max_response_payload_len; 4459}; 4460 4461struct xmit_els_rsp64_wqe { 4462 struct ulp_bde64 bde; 4463 uint32_t response_payload_len; 4464 uint32_t word4; 4465#define els_rsp64_sid_SHIFT 0 4466#define els_rsp64_sid_MASK 0x00FFFFFF 4467#define els_rsp64_sid_WORD word4 4468#define els_rsp64_sp_SHIFT 24 4469#define els_rsp64_sp_MASK 0x00000001 4470#define els_rsp64_sp_WORD word4 4471 struct wqe_did wqe_dest; 4472 struct wqe_common wqe_com; /* words 6-11 */ 4473 uint32_t word12; 4474#define wqe_rsp_temp_rpi_SHIFT 0 4475#define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4476#define wqe_rsp_temp_rpi_WORD word12 4477 uint32_t rsvd_13_15[3]; 4478}; 4479 4480struct xmit_bls_rsp64_wqe { 4481 uint32_t payload0; 4482/* Payload0 for BA_ACC */ 4483#define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4484#define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4485#define xmit_bls_rsp64_acc_seq_id_WORD payload0 4486#define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4487#define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4488#define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4489/* Payload0 for BA_RJT */ 4490#define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4491#define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4492#define xmit_bls_rsp64_rjt_vspec_WORD payload0 4493#define xmit_bls_rsp64_rjt_expc_SHIFT 8 4494#define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4495#define xmit_bls_rsp64_rjt_expc_WORD payload0 4496#define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4497#define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4498#define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4499 uint32_t word1; 4500#define xmit_bls_rsp64_rxid_SHIFT 0 4501#define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4502#define xmit_bls_rsp64_rxid_WORD word1 4503#define xmit_bls_rsp64_oxid_SHIFT 16 4504#define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4505#define xmit_bls_rsp64_oxid_WORD word1 4506 uint32_t word2; 4507#define xmit_bls_rsp64_seqcnthi_SHIFT 0 4508#define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4509#define xmit_bls_rsp64_seqcnthi_WORD word2 4510#define xmit_bls_rsp64_seqcntlo_SHIFT 16 4511#define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4512#define xmit_bls_rsp64_seqcntlo_WORD word2 4513 uint32_t rsrvd3; 4514 uint32_t rsrvd4; 4515 struct wqe_did wqe_dest; 4516 struct wqe_common wqe_com; /* words 6-11 */ 4517 uint32_t word12; 4518#define xmit_bls_rsp64_temprpi_SHIFT 0 4519#define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4520#define xmit_bls_rsp64_temprpi_WORD word12 4521 uint32_t rsvd_13_15[3]; 4522}; 4523 4524struct wqe_rctl_dfctl { 4525 uint32_t word5; 4526#define wqe_si_SHIFT 2 4527#define wqe_si_MASK 0x000000001 4528#define wqe_si_WORD word5 4529#define wqe_la_SHIFT 3 4530#define wqe_la_MASK 0x000000001 4531#define wqe_la_WORD word5 4532#define wqe_xo_SHIFT 6 4533#define wqe_xo_MASK 0x000000001 4534#define wqe_xo_WORD word5 4535#define wqe_ls_SHIFT 7 4536#define wqe_ls_MASK 0x000000001 4537#define wqe_ls_WORD word5 4538#define wqe_dfctl_SHIFT 8 4539#define wqe_dfctl_MASK 0x0000000ff 4540#define wqe_dfctl_WORD word5 4541#define wqe_type_SHIFT 16 4542#define wqe_type_MASK 0x0000000ff 4543#define wqe_type_WORD word5 4544#define wqe_rctl_SHIFT 24 4545#define wqe_rctl_MASK 0x0000000ff 4546#define wqe_rctl_WORD word5 4547}; 4548 4549struct xmit_seq64_wqe { 4550 struct ulp_bde64 bde; 4551 uint32_t rsvd3; 4552 uint32_t relative_offset; 4553 struct wqe_rctl_dfctl wge_ctl; 4554 struct wqe_common wqe_com; /* words 6-11 */ 4555 uint32_t xmit_len; 4556 uint32_t rsvd_12_15[3]; 4557}; 4558struct xmit_bcast64_wqe { 4559 struct ulp_bde64 bde; 4560 uint32_t seq_payload_len; 4561 uint32_t rsvd4; 4562 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4563 struct wqe_common wqe_com; /* words 6-11 */ 4564 uint32_t rsvd_12_15[4]; 4565}; 4566 4567struct gen_req64_wqe { 4568 struct ulp_bde64 bde; 4569 uint32_t request_payload_len; 4570 uint32_t relative_offset; 4571 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4572 struct wqe_common wqe_com; /* words 6-11 */ 4573 uint32_t rsvd_12_14[3]; 4574 uint32_t max_response_payload_len; 4575}; 4576 4577/* Define NVME PRLI request to fabric. NVME is a 4578 * fabric-only protocol. 4579 * Updated to red-lined v1.08 on Sept 16, 2016 4580 */ 4581struct lpfc_nvme_prli { 4582 uint32_t word1; 4583 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4584#define prli_acc_rsp_code_SHIFT 8 4585#define prli_acc_rsp_code_MASK 0x0000000f 4586#define prli_acc_rsp_code_WORD word1 4587#define prli_estabImagePair_SHIFT 13 4588#define prli_estabImagePair_MASK 0x00000001 4589#define prli_estabImagePair_WORD word1 4590#define prli_type_code_ext_SHIFT 16 4591#define prli_type_code_ext_MASK 0x000000ff 4592#define prli_type_code_ext_WORD word1 4593#define prli_type_code_SHIFT 24 4594#define prli_type_code_MASK 0x000000ff 4595#define prli_type_code_WORD word1 4596 uint32_t word_rsvd2; 4597 uint32_t word_rsvd3; 4598 uint32_t word4; 4599#define prli_fba_SHIFT 0 4600#define prli_fba_MASK 0x00000001 4601#define prli_fba_WORD word4 4602#define prli_disc_SHIFT 3 4603#define prli_disc_MASK 0x00000001 4604#define prli_disc_WORD word4 4605#define prli_tgt_SHIFT 4 4606#define prli_tgt_MASK 0x00000001 4607#define prli_tgt_WORD word4 4608#define prli_init_SHIFT 5 4609#define prli_init_MASK 0x00000001 4610#define prli_init_WORD word4 4611#define prli_conf_SHIFT 7 4612#define prli_conf_MASK 0x00000001 4613#define prli_conf_WORD word4 4614 uint32_t word5; 4615#define prli_fb_sz_SHIFT 0 4616#define prli_fb_sz_MASK 0x0000ffff 4617#define prli_fb_sz_WORD word5 4618#define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4619}; 4620 4621struct create_xri_wqe { 4622 uint32_t rsrvd[5]; /* words 0-4 */ 4623 struct wqe_did wqe_dest; /* word 5 */ 4624 struct wqe_common wqe_com; /* words 6-11 */ 4625 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4626}; 4627 4628#define T_REQUEST_TAG 3 4629#define T_XRI_TAG 1 4630 4631struct abort_cmd_wqe { 4632 uint32_t rsrvd[3]; 4633 uint32_t word3; 4634#define abort_cmd_ia_SHIFT 0 4635#define abort_cmd_ia_MASK 0x000000001 4636#define abort_cmd_ia_WORD word3 4637#define abort_cmd_criteria_SHIFT 8 4638#define abort_cmd_criteria_MASK 0x0000000ff 4639#define abort_cmd_criteria_WORD word3 4640 uint32_t rsrvd4; 4641 uint32_t rsrvd5; 4642 struct wqe_common wqe_com; /* words 6-11 */ 4643 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4644}; 4645 4646struct fcp_iwrite64_wqe { 4647 struct ulp_bde64 bde; 4648 uint32_t word3; 4649#define cmd_buff_len_SHIFT 16 4650#define cmd_buff_len_MASK 0x00000ffff 4651#define cmd_buff_len_WORD word3 4652#define payload_offset_len_SHIFT 0 4653#define payload_offset_len_MASK 0x0000ffff 4654#define payload_offset_len_WORD word3 4655 uint32_t total_xfer_len; 4656 uint32_t initial_xfer_len; 4657 struct wqe_common wqe_com; /* words 6-11 */ 4658 uint32_t rsrvd12; 4659 struct ulp_bde64 ph_bde; /* words 13-15 */ 4660}; 4661 4662struct fcp_iread64_wqe { 4663 struct ulp_bde64 bde; 4664 uint32_t word3; 4665#define cmd_buff_len_SHIFT 16 4666#define cmd_buff_len_MASK 0x00000ffff 4667#define cmd_buff_len_WORD word3 4668#define payload_offset_len_SHIFT 0 4669#define payload_offset_len_MASK 0x0000ffff 4670#define payload_offset_len_WORD word3 4671 uint32_t total_xfer_len; /* word 4 */ 4672 uint32_t rsrvd5; /* word 5 */ 4673 struct wqe_common wqe_com; /* words 6-11 */ 4674 uint32_t rsrvd12; 4675 struct ulp_bde64 ph_bde; /* words 13-15 */ 4676}; 4677 4678struct fcp_icmnd64_wqe { 4679 struct ulp_bde64 bde; /* words 0-2 */ 4680 uint32_t word3; 4681#define cmd_buff_len_SHIFT 16 4682#define cmd_buff_len_MASK 0x00000ffff 4683#define cmd_buff_len_WORD word3 4684#define payload_offset_len_SHIFT 0 4685#define payload_offset_len_MASK 0x0000ffff 4686#define payload_offset_len_WORD word3 4687 uint32_t rsrvd4; /* word 4 */ 4688 uint32_t rsrvd5; /* word 5 */ 4689 struct wqe_common wqe_com; /* words 6-11 */ 4690 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4691}; 4692 4693struct fcp_trsp64_wqe { 4694 struct ulp_bde64 bde; 4695 uint32_t response_len; 4696 uint32_t rsvd_4_5[2]; 4697 struct wqe_common wqe_com; /* words 6-11 */ 4698 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4699}; 4700 4701struct fcp_tsend64_wqe { 4702 struct ulp_bde64 bde; 4703 uint32_t payload_offset_len; 4704 uint32_t relative_offset; 4705 uint32_t reserved; 4706 struct wqe_common wqe_com; /* words 6-11 */ 4707 uint32_t fcp_data_len; /* word 12 */ 4708 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4709}; 4710 4711struct fcp_treceive64_wqe { 4712 struct ulp_bde64 bde; 4713 uint32_t payload_offset_len; 4714 uint32_t relative_offset; 4715 uint32_t reserved; 4716 struct wqe_common wqe_com; /* words 6-11 */ 4717 uint32_t fcp_data_len; /* word 12 */ 4718 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4719}; 4720#define TXRDY_PAYLOAD_LEN 12 4721 4722#define CMD_SEND_FRAME 0xE1 4723 4724struct send_frame_wqe { 4725 struct ulp_bde64 bde; /* words 0-2 */ 4726 uint32_t frame_len; /* word 3 */ 4727 uint32_t fc_hdr_wd0; /* word 4 */ 4728 uint32_t fc_hdr_wd1; /* word 5 */ 4729 struct wqe_common wqe_com; /* words 6-11 */ 4730 uint32_t fc_hdr_wd2; /* word 12 */ 4731 uint32_t fc_hdr_wd3; /* word 13 */ 4732 uint32_t fc_hdr_wd4; /* word 14 */ 4733 uint32_t fc_hdr_wd5; /* word 15 */ 4734}; 4735 4736union lpfc_wqe { 4737 uint32_t words[16]; 4738 struct lpfc_wqe_generic generic; 4739 struct fcp_icmnd64_wqe fcp_icmd; 4740 struct fcp_iread64_wqe fcp_iread; 4741 struct fcp_iwrite64_wqe fcp_iwrite; 4742 struct abort_cmd_wqe abort_cmd; 4743 struct create_xri_wqe create_xri; 4744 struct xmit_bcast64_wqe xmit_bcast64; 4745 struct xmit_seq64_wqe xmit_sequence; 4746 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4747 struct xmit_els_rsp64_wqe xmit_els_rsp; 4748 struct els_request64_wqe els_req; 4749 struct gen_req64_wqe gen_req; 4750 struct fcp_trsp64_wqe fcp_trsp; 4751 struct fcp_tsend64_wqe fcp_tsend; 4752 struct fcp_treceive64_wqe fcp_treceive; 4753 struct send_frame_wqe send_frame; 4754}; 4755 4756union lpfc_wqe128 { 4757 uint32_t words[32]; 4758 struct lpfc_wqe_generic generic; 4759 struct fcp_icmnd64_wqe fcp_icmd; 4760 struct fcp_iread64_wqe fcp_iread; 4761 struct fcp_iwrite64_wqe fcp_iwrite; 4762 struct abort_cmd_wqe abort_cmd; 4763 struct create_xri_wqe create_xri; 4764 struct xmit_bcast64_wqe xmit_bcast64; 4765 struct xmit_seq64_wqe xmit_sequence; 4766 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4767 struct xmit_els_rsp64_wqe xmit_els_rsp; 4768 struct els_request64_wqe els_req; 4769 struct gen_req64_wqe gen_req; 4770 struct fcp_trsp64_wqe fcp_trsp; 4771 struct fcp_tsend64_wqe fcp_tsend; 4772 struct fcp_treceive64_wqe fcp_treceive; 4773 struct send_frame_wqe send_frame; 4774}; 4775 4776#define MAGIC_NUMER_G6 0xFEAA0003 4777#define MAGIC_NUMER_G7 0xFEAA0005 4778 4779struct lpfc_grp_hdr { 4780 uint32_t size; 4781 uint32_t magic_number; 4782 uint32_t word2; 4783#define lpfc_grp_hdr_file_type_SHIFT 24 4784#define lpfc_grp_hdr_file_type_MASK 0x000000FF 4785#define lpfc_grp_hdr_file_type_WORD word2 4786#define lpfc_grp_hdr_id_SHIFT 16 4787#define lpfc_grp_hdr_id_MASK 0x000000FF 4788#define lpfc_grp_hdr_id_WORD word2 4789 uint8_t rev_name[128]; 4790 uint8_t date[12]; 4791 uint8_t revision[32]; 4792}; 4793 4794/* Defines for WQE command type */ 4795#define FCP_COMMAND 0x0 4796#define NVME_READ_CMD 0x0 4797#define FCP_COMMAND_DATA_OUT 0x1 4798#define NVME_WRITE_CMD 0x1 4799#define FCP_COMMAND_TRECEIVE 0x2 4800#define FCP_COMMAND_TRSP 0x3 4801#define FCP_COMMAND_TSEND 0x7 4802#define OTHER_COMMAND 0x8 4803#define ELS_COMMAND_NON_FIP 0xC 4804#define ELS_COMMAND_FIP 0xD 4805 4806#define LPFC_NVME_EMBED_CMD 0x0 4807#define LPFC_NVME_EMBED_WRITE 0x1 4808#define LPFC_NVME_EMBED_READ 0x2 4809 4810/* WQE Commands */ 4811#define CMD_ABORT_XRI_WQE 0x0F 4812#define CMD_XMIT_SEQUENCE64_WQE 0x82 4813#define CMD_XMIT_BCAST64_WQE 0x84 4814#define CMD_ELS_REQUEST64_WQE 0x8A 4815#define CMD_XMIT_ELS_RSP64_WQE 0x95 4816#define CMD_XMIT_BLS_RSP64_WQE 0x97 4817#define CMD_FCP_IWRITE64_WQE 0x98 4818#define CMD_FCP_IREAD64_WQE 0x9A 4819#define CMD_FCP_ICMND64_WQE 0x9C 4820#define CMD_FCP_TSEND64_WQE 0x9F 4821#define CMD_FCP_TRECEIVE64_WQE 0xA1 4822#define CMD_FCP_TRSP64_WQE 0xA3 4823#define CMD_GEN_REQUEST64_WQE 0xC2 4824 4825#define CMD_WQE_MASK 0xff 4826 4827 4828#define LPFC_FW_DUMP 1 4829#define LPFC_FW_RESET 2 4830#define LPFC_DV_RESET 3 4831