LXR linux/drivers/scsi/mvsas/mv

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Marvell 88SE94xx hardware specific head file
   4 *
   5 * Copyright 2007 Red Hat, Inc.
   6 * Copyright 2008 Marvell. <kewei@marvell.com>
   7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
   8*/
   9
  10#ifndef _MVS94XX_REG_H_
  11#define _MVS94XX_REG_H_
  12
  13#include <linux/types.h>
  14
  15#define MAX_LINK_RATE           SAS_LINK_RATE_6_0_GBPS
  16
  17enum VANIR_REVISION_ID {
  18        VANIR_A0_REV            = 0xA0,
  19        VANIR_B0_REV            = 0x01,
  20        VANIR_C0_REV            = 0x02,
  21        VANIR_C1_REV            = 0x03,
  22        VANIR_C2_REV            = 0xC2,
  23};
  24
  25enum host_registers {
  26        MVS_HST_CHIP_CONFIG     = 0x10104,      /* chip configuration */
  27};
  28
  29enum hw_registers {
  30        MVS_GBL_CTL             = 0x04,  /* global control */
  31        MVS_GBL_INT_STAT        = 0x00,  /* global irq status */
  32        MVS_GBL_PI              = 0x0C,  /* ports implemented bitmask */
  33
  34        MVS_PHY_CTL             = 0x40,  /* SOC PHY Control */
  35        MVS_PORTS_IMP           = 0x9C,  /* SOC Port Implemented */
  36
  37        MVS_GBL_PORT_TYPE       = 0xa0,  /* port type */
  38
  39        MVS_CTL                 = 0x100, /* SAS/SATA port configuration */
  40        MVS_PCS                 = 0x104, /* SAS/SATA port control/status */
  41        MVS_CMD_LIST_LO         = 0x108, /* cmd list addr */
  42        MVS_CMD_LIST_HI         = 0x10C,
  43        MVS_RX_FIS_LO           = 0x110, /* RX FIS list addr */
  44        MVS_RX_FIS_HI           = 0x114,
  45        MVS_STP_REG_SET_0       = 0x118, /* STP/SATA Register Set Enable */
  46        MVS_STP_REG_SET_1       = 0x11C,
  47        MVS_TX_CFG              = 0x120, /* TX configuration */
  48        MVS_TX_LO               = 0x124, /* TX (delivery) ring addr */
  49        MVS_TX_HI               = 0x128,
  50
  51        MVS_TX_PROD_IDX         = 0x12C, /* TX producer pointer */
  52        MVS_TX_CONS_IDX         = 0x130, /* TX consumer pointer (RO) */
  53        MVS_RX_CFG              = 0x134, /* RX configuration */
  54        MVS_RX_LO               = 0x138, /* RX (completion) ring addr */
  55        MVS_RX_HI               = 0x13C,
  56        MVS_RX_CONS_IDX         = 0x140, /* RX consumer pointer (RO) */
  57
  58        MVS_INT_COAL            = 0x148, /* Int coalescing config */
  59        MVS_INT_COAL_TMOUT      = 0x14C, /* Int coalescing timeout */
  60        MVS_INT_STAT            = 0x150, /* Central int status */
  61        MVS_INT_MASK            = 0x154, /* Central int enable */
  62        MVS_INT_STAT_SRS_0      = 0x158, /* SATA register set status */
  63        MVS_INT_MASK_SRS_0      = 0x15C,
  64        MVS_INT_STAT_SRS_1      = 0x160,
  65        MVS_INT_MASK_SRS_1      = 0x164,
  66        MVS_NON_NCQ_ERR_0       = 0x168, /* SRS Non-specific NCQ Error */
  67        MVS_NON_NCQ_ERR_1       = 0x16C,
  68        MVS_CMD_ADDR            = 0x170, /* Command register port (addr) */
  69        MVS_CMD_DATA            = 0x174, /* Command register port (data) */
  70        MVS_MEM_PARITY_ERR      = 0x178, /* Memory parity error */
  71
  72                                         /* ports 1-3 follow after this */
  73        MVS_P0_INT_STAT         = 0x180, /* port0 interrupt status */
  74        MVS_P0_INT_MASK         = 0x184, /* port0 interrupt mask */
  75                                         /* ports 5-7 follow after this */
  76        MVS_P4_INT_STAT         = 0x1A0, /* Port4 interrupt status */
  77        MVS_P4_INT_MASK         = 0x1A4, /* Port4 interrupt enable mask */
  78
  79                                         /* ports 1-3 follow after this */
  80        MVS_P0_SER_CTLSTAT      = 0x1D0, /* port0 serial control/status */
  81                                         /* ports 5-7 follow after this */
  82        MVS_P4_SER_CTLSTAT      = 0x1E0, /* port4 serial control/status */
  83
  84                                         /* ports 1-3 follow after this */
  85        MVS_P0_CFG_ADDR         = 0x200, /* port0 phy register address */
  86        MVS_P0_CFG_DATA         = 0x204, /* port0 phy register data */
  87                                         /* ports 5-7 follow after this */
  88        MVS_P4_CFG_ADDR         = 0x220, /* Port4 config address */
  89        MVS_P4_CFG_DATA         = 0x224, /* Port4 config data */
  90
  91                                         /* phys 1-3 follow after this */
  92        MVS_P0_VSR_ADDR         = 0x250, /* phy0 VSR address */
  93        MVS_P0_VSR_DATA         = 0x254, /* phy0 VSR data */
  94                                         /* phys 1-3 follow after this */
  95                                         /* multiplexing */
  96        MVS_P4_VSR_ADDR         = 0x250, /* phy4 VSR address */
  97        MVS_P4_VSR_DATA         = 0x254, /* phy4 VSR data */
  98        MVS_PA_VSR_ADDR         = 0x290, /* All port VSR addr */
  99        MVS_PA_VSR_PORT         = 0x294, /* All port VSR data */
 100        MVS_COMMAND_ACTIVE      = 0x300,
 101};
 102
 103enum pci_cfg_registers {
 104        PCR_PHY_CTL             = 0x40,
 105        PCR_PHY_CTL2            = 0x90,
 106        PCR_DEV_CTRL            = 0x78,
 107        PCR_LINK_STAT           = 0x82,
 108};
 109
 110/*  SAS/SATA Vendor Specific Port Registers */
 111enum sas_sata_vsp_regs {
 112        VSR_PHY_STAT            = 0x00 * 4, /* Phy Interrupt Status */
 113        VSR_PHY_MODE1           = 0x01 * 4, /* phy Interrupt Enable */
 114        VSR_PHY_MODE2           = 0x02 * 4, /* Phy Configuration */
 115        VSR_PHY_MODE3           = 0x03 * 4, /* Phy Status */
 116        VSR_PHY_MODE4           = 0x04 * 4, /* Phy Counter 0 */
 117        VSR_PHY_MODE5           = 0x05 * 4, /* Phy Counter 1 */
 118        VSR_PHY_MODE6           = 0x06 * 4, /* Event Counter Control */
 119        VSR_PHY_MODE7           = 0x07 * 4, /* Event Counter Select */
 120        VSR_PHY_MODE8           = 0x08 * 4, /* Event Counter 0 */
 121        VSR_PHY_MODE9           = 0x09 * 4, /* Event Counter 1 */
 122        VSR_PHY_MODE10          = 0x0A * 4, /* Event Counter 2 */
 123        VSR_PHY_MODE11          = 0x0B * 4, /* Event Counter 3 */
 124        VSR_PHY_ACT_LED         = 0x0C * 4, /* Activity LED control */
 125
 126        VSR_PHY_FFE_CONTROL     = 0x10C,
 127        VSR_PHY_DFE_UPDATE_CRTL = 0x110,
 128        VSR_REF_CLOCK_CRTL      = 0x1A0,
 129};
 130
 131enum chip_register_bits {
 132        PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
 133        PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
 134        PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
 135        PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
 136                        (0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
 137};
 138
 139enum pci_interrupt_cause {
 140        /*  MAIN_IRQ_CAUSE (R10200) Bits*/
 141        MVS_IRQ_COM_IN_I2O_IOP0        = (1 << 0),
 142        MVS_IRQ_COM_IN_I2O_IOP1        = (1 << 1),
 143        MVS_IRQ_COM_IN_I2O_IOP2        = (1 << 2),
 144        MVS_IRQ_COM_IN_I2O_IOP3        = (1 << 3),
 145        MVS_IRQ_COM_OUT_I2O_HOS0       = (1 << 4),
 146        MVS_IRQ_COM_OUT_I2O_HOS1       = (1 << 5),
 147        MVS_IRQ_COM_OUT_I2O_HOS2       = (1 << 6),
 148        MVS_IRQ_COM_OUT_I2O_HOS3       = (1 << 7),
 149        MVS_IRQ_PCIF_TO_CPU_DRBL0      = (1 << 8),
 150        MVS_IRQ_PCIF_TO_CPU_DRBL1      = (1 << 9),
 151        MVS_IRQ_PCIF_TO_CPU_DRBL2      = (1 << 10),
 152        MVS_IRQ_PCIF_TO_CPU_DRBL3      = (1 << 11),
 153        MVS_IRQ_PCIF_DRBL0             = (1 << 12),
 154        MVS_IRQ_PCIF_DRBL1             = (1 << 13),
 155        MVS_IRQ_PCIF_DRBL2             = (1 << 14),
 156        MVS_IRQ_PCIF_DRBL3             = (1 << 15),
 157        MVS_IRQ_XOR_A                  = (1 << 16),
 158        MVS_IRQ_XOR_B                  = (1 << 17),
 159        MVS_IRQ_SAS_A                  = (1 << 18),
 160        MVS_IRQ_SAS_B                  = (1 << 19),
 161        MVS_IRQ_CPU_CNTRL              = (1 << 20),
 162        MVS_IRQ_GPIO                   = (1 << 21),
 163        MVS_IRQ_UART                   = (1 << 22),
 164        MVS_IRQ_SPI                    = (1 << 23),
 165        MVS_IRQ_I2C                    = (1 << 24),
 166        MVS_IRQ_SGPIO                  = (1 << 25),
 167        MVS_IRQ_COM_ERR                = (1 << 29),
 168        MVS_IRQ_I2O_ERR                = (1 << 30),
 169        MVS_IRQ_PCIE_ERR               = (1 << 31),
 170};
 171
 172union reg_phy_cfg {
 173        u32 v;
 174        struct {
 175                u32 phy_reset:1;
 176                u32 sas_support:1;
 177                u32 sata_support:1;
 178                u32 sata_host_mode:1;
 179                /*
 180                 * bit 2: 6Gbps support
 181                 * bit 1: 3Gbps support
 182                 * bit 0: 1.5Gbps support
 183                 */
 184                u32 speed_support:3;
 185                u32 snw_3_support:1;
 186                u32 tx_lnk_parity:1;
 187                /*
 188                 * bit 5: G1 (1.5Gbps) Without SSC
 189                 * bit 4: G1 (1.5Gbps) with SSC
 190                 * bit 3: G2 (3.0Gbps) Without SSC
 191                 * bit 2: G2 (3.0Gbps) with SSC
 192                 * bit 1: G3 (6.0Gbps) without SSC
 193                 * bit 0: G3 (6.0Gbps) with SSC
 194                 */
 195                u32 tx_spt_phs_lnk_rate:6;
 196                /* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
 197                u32 tx_lgcl_lnk_rate:4;
 198                u32 tx_ssc_type:1;
 199                u32 sata_spin_up_spt:1;
 200                u32 sata_spin_up_en:1;
 201                u32 bypass_oob:1;
 202                u32 disable_phy:1;
 203                u32 rsvd:8;
 204        } u;
 205};
 206
 207#define MAX_SG_ENTRY            255
 208
 209struct mvs_prd_imt {
 210#ifndef __BIG_ENDIAN
 211        __le32                  len:22;
 212        u8                      _r_a:2;
 213        u8                      misc_ctl:4;
 214        u8                      inter_sel:4;
 215#else
 216        u32                     inter_sel:4;
 217        u32                     misc_ctl:4;
 218        u32                     _r_a:2;
 219        u32                     len:22;
 220#endif
 221};
 222
 223struct mvs_prd {
 224        /* 64-bit buffer address */
 225        __le64                  addr;
 226        /* 22-bit length */
 227        __le32                  im_len;
 228} __attribute__ ((packed));
 229
 230enum sgpio_registers {
 231        MVS_SGPIO_HOST_OFFSET   = 0x100,        /* offset between hosts */
 232
 233        MVS_SGPIO_CFG0  = 0xc200,
 234        MVS_SGPIO_CFG0_ENABLE   = (1 << 0),     /* enable pins */
 235        MVS_SGPIO_CFG0_BLINKB   = (1 << 1),     /* blink generators */
 236        MVS_SGPIO_CFG0_BLINKA   = (1 << 2),
 237        MVS_SGPIO_CFG0_INVSCLK  = (1 << 3),     /* invert signal? */
 238        MVS_SGPIO_CFG0_INVSLOAD = (1 << 4),
 239        MVS_SGPIO_CFG0_INVSDOUT = (1 << 5),
 240        MVS_SGPIO_CFG0_SLOAD_FALLEDGE = (1 << 6),       /* rise/fall edge? */
 241        MVS_SGPIO_CFG0_SDOUT_FALLEDGE = (1 << 7),
 242        MVS_SGPIO_CFG0_SDIN_RISEEDGE = (1 << 8),
 243        MVS_SGPIO_CFG0_MAN_BITLEN_SHIFT = 18,   /* bits/frame manual mode */
 244        MVS_SGPIO_CFG0_AUT_BITLEN_SHIFT = 24,   /* bits/frame auto mode */
 245
 246        MVS_SGPIO_CFG1  = 0xc204,       /* blink timing register */
 247        MVS_SGPIO_CFG1_LOWA_SHIFT       = 0,    /* A off time */
 248        MVS_SGPIO_CFG1_HIA_SHIFT        = 4,    /* A on time */
 249        MVS_SGPIO_CFG1_LOWB_SHIFT       = 8,    /* B off time */
 250        MVS_SGPIO_CFG1_HIB_SHIFT        = 12,   /* B on time */
 251        MVS_SGPIO_CFG1_MAXACTON_SHIFT   = 16,   /* max activity on time */
 252
 253                /* force activity off time */
 254        MVS_SGPIO_CFG1_FORCEACTOFF_SHIFT        = 20,
 255                /* stretch activity on time */
 256        MVS_SGPIO_CFG1_STRCHACTON_SHIFT = 24,
 257                /* stretch activiity off time */
 258        MVS_SGPIO_CFG1_STRCHACTOFF_SHIFT        = 28,
 259
 260
 261        MVS_SGPIO_CFG2  = 0xc208,       /* clock speed register */
 262        MVS_SGPIO_CFG2_CLK_SHIFT        = 0,
 263        MVS_SGPIO_CFG2_BLINK_SHIFT      = 20,
 264
 265        MVS_SGPIO_CTRL  = 0xc20c,       /* SDOUT/SDIN mode control */
 266        MVS_SGPIO_CTRL_SDOUT_AUTO       = 2,
 267        MVS_SGPIO_CTRL_SDOUT_SHIFT      = 2,
 268
 269        MVS_SGPIO_DSRC  = 0xc220,       /* map ODn bits to drives */
 270
 271        MVS_SGPIO_DCTRL = 0xc238,
 272        MVS_SGPIO_DCTRL_ERR_SHIFT       = 0,
 273        MVS_SGPIO_DCTRL_LOC_SHIFT       = 3,
 274        MVS_SGPIO_DCTRL_ACT_SHIFT       = 5,
 275};
 276
 277enum sgpio_led_status {
 278        LED_OFF = 0,
 279        LED_ON  = 1,
 280        LED_BLINKA      = 2,
 281        LED_BLINKA_INV  = 3,
 282        LED_BLINKA_SOF  = 4,
 283        LED_BLINKA_EOF  = 5,
 284        LED_BLINKB      = 6,
 285        LED_BLINKB_INV  = 7,
 286};
 287
 288#define DEFAULT_SGPIO_BITS ((LED_BLINKA_SOF << \
 289                                MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 3) | \
 290                        (LED_BLINKA_SOF << \
 291                                MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 2) | \
 292                        (LED_BLINKA_SOF << \
 293                                MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 1) | \
 294                        (LED_BLINKA_SOF << \
 295                                MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 0))
 296
 297/*
 298 * these registers are accessed through port vendor
 299 * specific address/data registers
 300 */
 301enum sas_sata_phy_regs {
 302        GENERATION_1_SETTING            = 0x118,
 303        GENERATION_1_2_SETTING          = 0x11C,
 304        GENERATION_2_3_SETTING          = 0x120,
 305        GENERATION_3_4_SETTING          = 0x124,
 306};
 307
 308#define SPI_CTRL_REG_94XX               0xc800
 309#define SPI_ADDR_REG_94XX               0xc804
 310#define SPI_WR_DATA_REG_94XX         0xc808
 311#define SPI_RD_DATA_REG_94XX            0xc80c
 312#define SPI_CTRL_READ_94XX              (1U << 2)
 313#define SPI_ADDR_VLD_94XX               (1U << 1)
 314#define SPI_CTRL_SpiStart_94XX          (1U << 0)
 315
 316static inline int
 317mv_ffc64(u64 v)
 318{
 319        u64 x = ~v;
 320        return x ? __ffs64(x) : -1;
 321}
 322
 323#define r_reg_set_enable(i) \
 324        (((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
 325        mr32(MVS_STP_REG_SET_0))
 326
 327#define w_reg_set_enable(i, tmp) \
 328        (((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
 329        mw32(MVS_STP_REG_SET_0, tmp))
 330
 331extern const struct mvs_dispatch mvs_94xx_dispatch;
 332#endif
 333
 334