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41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44
45static struct scsi_transport_template *pm8001_stt;
46
47
48
49
50
51static const struct pm8001_chip_info pm8001_chips[] = {
52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
57 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
58 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
59 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
60 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
61 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
62 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
63};
64static int pm8001_id;
65
66LIST_HEAD(hba_list);
67
68struct workqueue_struct *pm8001_wq;
69
70
71
72
73static struct scsi_host_template pm8001_sht = {
74 .module = THIS_MODULE,
75 .name = DRV_NAME,
76 .queuecommand = sas_queuecommand,
77 .target_alloc = sas_target_alloc,
78 .slave_configure = sas_slave_configure,
79 .scan_finished = pm8001_scan_finished,
80 .scan_start = pm8001_scan_start,
81 .change_queue_depth = sas_change_queue_depth,
82 .bios_param = sas_bios_param,
83 .can_queue = 1,
84 .this_id = -1,
85 .sg_tablesize = SG_ALL,
86 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
87 .eh_device_reset_handler = sas_eh_device_reset_handler,
88 .eh_target_reset_handler = sas_eh_target_reset_handler,
89 .target_destroy = sas_target_destroy,
90 .ioctl = sas_ioctl,
91 .shost_attrs = pm8001_host_attrs,
92 .track_queue_depth = 1,
93};
94
95
96
97
98static struct sas_domain_function_template pm8001_transport_ops = {
99 .lldd_dev_found = pm8001_dev_found,
100 .lldd_dev_gone = pm8001_dev_gone,
101
102 .lldd_execute_task = pm8001_queue_command,
103 .lldd_control_phy = pm8001_phy_control,
104
105 .lldd_abort_task = pm8001_abort_task,
106 .lldd_abort_task_set = pm8001_abort_task_set,
107 .lldd_clear_aca = pm8001_clear_aca,
108 .lldd_clear_task_set = pm8001_clear_task_set,
109 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
110 .lldd_lu_reset = pm8001_lu_reset,
111 .lldd_query_task = pm8001_query_task,
112};
113
114
115
116
117
118
119static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
120{
121 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
122 struct asd_sas_phy *sas_phy = &phy->sas_phy;
123 phy->phy_state = PHY_LINK_DISABLE;
124 phy->pm8001_ha = pm8001_ha;
125 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
126 sas_phy->class = SAS;
127 sas_phy->iproto = SAS_PROTOCOL_ALL;
128 sas_phy->tproto = 0;
129 sas_phy->type = PHY_TYPE_PHYSICAL;
130 sas_phy->role = PHY_ROLE_INITIATOR;
131 sas_phy->oob_mode = OOB_NOT_CONNECTED;
132 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
133 sas_phy->id = phy_id;
134 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
135 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
136 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
137 sas_phy->lldd_phy = phy;
138}
139
140
141
142
143
144
145static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
146{
147 int i;
148
149 if (!pm8001_ha)
150 return;
151
152 for (i = 0; i < USI_MAX_MEMCNT; i++) {
153 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
154 dma_free_coherent(&pm8001_ha->pdev->dev,
155 (pm8001_ha->memoryMap.region[i].total_len +
156 pm8001_ha->memoryMap.region[i].alignment),
157 pm8001_ha->memoryMap.region[i].virt_ptr,
158 pm8001_ha->memoryMap.region[i].phys_addr);
159 }
160 }
161 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
162 flush_workqueue(pm8001_wq);
163 kfree(pm8001_ha->tags);
164 kfree(pm8001_ha);
165}
166
167#ifdef PM8001_USE_TASKLET
168
169
170
171
172
173
174static void pm8001_tasklet(unsigned long opaque)
175{
176 struct pm8001_hba_info *pm8001_ha;
177 struct isr_param *irq_vector;
178
179 irq_vector = (struct isr_param *)opaque;
180 pm8001_ha = irq_vector->drv_inst;
181 if (unlikely(!pm8001_ha))
182 BUG_ON(1);
183 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
184}
185#endif
186
187
188
189
190
191
192
193
194static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
195{
196 struct isr_param *irq_vector;
197 struct pm8001_hba_info *pm8001_ha;
198 irqreturn_t ret = IRQ_HANDLED;
199 irq_vector = (struct isr_param *)opaque;
200 pm8001_ha = irq_vector->drv_inst;
201
202 if (unlikely(!pm8001_ha))
203 return IRQ_NONE;
204 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
205 return IRQ_NONE;
206#ifdef PM8001_USE_TASKLET
207 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
208#else
209 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
210#endif
211 return ret;
212}
213
214
215
216
217
218
219static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
220{
221 struct pm8001_hba_info *pm8001_ha;
222 irqreturn_t ret = IRQ_HANDLED;
223 struct sas_ha_struct *sha = dev_id;
224 pm8001_ha = sha->lldd_ha;
225 if (unlikely(!pm8001_ha))
226 return IRQ_NONE;
227 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
228 return IRQ_NONE;
229
230#ifdef PM8001_USE_TASKLET
231 tasklet_schedule(&pm8001_ha->tasklet[0]);
232#else
233 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
234#endif
235 return ret;
236}
237
238
239
240
241
242
243static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
244 const struct pci_device_id *ent)
245{
246 int i;
247 spin_lock_init(&pm8001_ha->lock);
248 spin_lock_init(&pm8001_ha->bitmap_lock);
249 PM8001_INIT_DBG(pm8001_ha,
250 pm8001_printk("pm8001_alloc: PHY:%x\n",
251 pm8001_ha->chip->n_phy));
252 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
253 pm8001_phy_init(pm8001_ha, i);
254 pm8001_ha->port[i].wide_port_phymap = 0;
255 pm8001_ha->port[i].port_attached = 0;
256 pm8001_ha->port[i].port_state = 0;
257 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
258 }
259
260 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
261 if (!pm8001_ha->tags)
262 goto err_out;
263
264 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
265 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
266 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
267 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
268
269
270 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
271 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
272 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
273 pm8001_ha->memoryMap.region[IOP].alignment = 32;
274
275 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
276
277 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
278 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
279 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
280 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
281
282 if ((ent->driver_data) != chip_8001) {
283
284 pm8001_ha->memoryMap.region[IB+i].num_elements =
285 PM8001_MPI_QUEUE;
286 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
287 pm8001_ha->memoryMap.region[IB+i].total_len =
288 PM8001_MPI_QUEUE * 128;
289 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
290 } else {
291 pm8001_ha->memoryMap.region[IB+i].num_elements =
292 PM8001_MPI_QUEUE;
293 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
294 pm8001_ha->memoryMap.region[IB+i].total_len =
295 PM8001_MPI_QUEUE * 64;
296 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
297 }
298 }
299
300 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
301
302 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
303 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
304 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
305 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
306
307 if (ent->driver_data != chip_8001) {
308
309 pm8001_ha->memoryMap.region[OB+i].num_elements =
310 PM8001_MPI_QUEUE;
311 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
312 pm8001_ha->memoryMap.region[OB+i].total_len =
313 PM8001_MPI_QUEUE * 128;
314 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
315 } else {
316
317 pm8001_ha->memoryMap.region[OB+i].num_elements =
318 PM8001_MPI_QUEUE;
319 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
320 pm8001_ha->memoryMap.region[OB+i].total_len =
321 PM8001_MPI_QUEUE * 64;
322 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
323 }
324
325 }
326
327 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
328 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
329 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
330
331 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
332 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
333 sizeof(struct pm8001_device);
334 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
335 sizeof(struct pm8001_device);
336
337
338 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
339 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
340 sizeof(struct pm8001_ccb_info);
341 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
342 sizeof(struct pm8001_ccb_info);
343
344
345 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
346
347 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
348 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
349 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
350 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
351 for (i = 0; i < USI_MAX_MEMCNT; i++) {
352 if (pm8001_mem_alloc(pm8001_ha->pdev,
353 &pm8001_ha->memoryMap.region[i].virt_ptr,
354 &pm8001_ha->memoryMap.region[i].phys_addr,
355 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
356 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
357 pm8001_ha->memoryMap.region[i].total_len,
358 pm8001_ha->memoryMap.region[i].alignment) != 0) {
359 PM8001_FAIL_DBG(pm8001_ha,
360 pm8001_printk("Mem%d alloc failed\n",
361 i));
362 goto err_out;
363 }
364 }
365
366 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
367 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
368 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
369 pm8001_ha->devices[i].id = i;
370 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
371 pm8001_ha->devices[i].running_req = 0;
372 }
373 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
374 for (i = 0; i < PM8001_MAX_CCB; i++) {
375 pm8001_ha->ccb_info[i].ccb_dma_handle =
376 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
377 i * sizeof(struct pm8001_ccb_info);
378 pm8001_ha->ccb_info[i].task = NULL;
379 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
380 pm8001_ha->ccb_info[i].device = NULL;
381 ++pm8001_ha->tags_num;
382 }
383 pm8001_ha->flags = PM8001F_INIT_TIME;
384
385 pm8001_tag_init(pm8001_ha);
386 return 0;
387err_out:
388 return 1;
389}
390
391
392
393
394
395
396static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
397{
398 u32 bar;
399 u32 logicalBar = 0;
400 struct pci_dev *pdev;
401
402 pdev = pm8001_ha->pdev;
403
404 for (bar = 0; bar < 6; bar++) {
405
406
407
408
409
410
411
412
413 if ((bar == 1) || (bar == 3))
414 continue;
415 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
416 pm8001_ha->io_mem[logicalBar].membase =
417 pci_resource_start(pdev, bar);
418 pm8001_ha->io_mem[logicalBar].memsize =
419 pci_resource_len(pdev, bar);
420 pm8001_ha->io_mem[logicalBar].memvirtaddr =
421 ioremap(pm8001_ha->io_mem[logicalBar].membase,
422 pm8001_ha->io_mem[logicalBar].memsize);
423 PM8001_INIT_DBG(pm8001_ha,
424 pm8001_printk("PCI: bar %d, logicalBar %d ",
425 bar, logicalBar));
426 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
427 "base addr %llx virt_addr=%llx len=%d\n",
428 (u64)pm8001_ha->io_mem[logicalBar].membase,
429 (u64)(unsigned long)
430 pm8001_ha->io_mem[logicalBar].memvirtaddr,
431 pm8001_ha->io_mem[logicalBar].memsize));
432 } else {
433 pm8001_ha->io_mem[logicalBar].membase = 0;
434 pm8001_ha->io_mem[logicalBar].memsize = 0;
435 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
436 }
437 logicalBar++;
438 }
439 return 0;
440}
441
442
443
444
445
446
447
448static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
449 const struct pci_device_id *ent,
450 struct Scsi_Host *shost)
451
452{
453 struct pm8001_hba_info *pm8001_ha;
454 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
455 int j;
456
457 pm8001_ha = sha->lldd_ha;
458 if (!pm8001_ha)
459 return NULL;
460
461 pm8001_ha->pdev = pdev;
462 pm8001_ha->dev = &pdev->dev;
463 pm8001_ha->chip_id = ent->driver_data;
464 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
465 pm8001_ha->irq = pdev->irq;
466 pm8001_ha->sas = sha;
467 pm8001_ha->shost = shost;
468 pm8001_ha->id = pm8001_id++;
469 pm8001_ha->logging_level = 0x01;
470 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
471
472 if (pm8001_ha->chip_id != chip_8001)
473 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
474 else
475 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
476
477#ifdef PM8001_USE_TASKLET
478
479 if ((!pdev->msix_cap || !pci_msi_enabled())
480 || (pm8001_ha->chip_id == chip_8001))
481 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
482 (unsigned long)&(pm8001_ha->irq_vector[0]));
483 else
484 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
485 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
486 (unsigned long)&(pm8001_ha->irq_vector[j]));
487#endif
488 pm8001_ioremap(pm8001_ha);
489 if (!pm8001_alloc(pm8001_ha, ent))
490 return pm8001_ha;
491 pm8001_free(pm8001_ha);
492 return NULL;
493}
494
495
496
497
498
499static int pci_go_44(struct pci_dev *pdev)
500{
501 int rc;
502
503 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
504 if (rc) {
505 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
506 if (rc)
507 dev_printk(KERN_ERR, &pdev->dev,
508 "32-bit DMA enable failed\n");
509 }
510 return rc;
511}
512
513
514
515
516
517
518static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
519 const struct pm8001_chip_info *chip_info)
520{
521 int phy_nr, port_nr;
522 struct asd_sas_phy **arr_phy;
523 struct asd_sas_port **arr_port;
524 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
525
526 phy_nr = chip_info->n_phy;
527 port_nr = phy_nr;
528 memset(sha, 0x00, sizeof(*sha));
529 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
530 if (!arr_phy)
531 goto exit;
532 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
533 if (!arr_port)
534 goto exit_free2;
535
536 sha->sas_phy = arr_phy;
537 sha->sas_port = arr_port;
538 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
539 if (!sha->lldd_ha)
540 goto exit_free1;
541
542 shost->transportt = pm8001_stt;
543 shost->max_id = PM8001_MAX_DEVICES;
544 shost->max_lun = 8;
545 shost->max_channel = 0;
546 shost->unique_id = pm8001_id;
547 shost->max_cmd_len = 16;
548 shost->can_queue = PM8001_CAN_QUEUE;
549 shost->cmd_per_lun = 32;
550 return 0;
551exit_free1:
552 kfree(arr_port);
553exit_free2:
554 kfree(arr_phy);
555exit:
556 return -1;
557}
558
559
560
561
562
563
564static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
565 const struct pm8001_chip_info *chip_info)
566{
567 int i = 0;
568 struct pm8001_hba_info *pm8001_ha;
569 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
570
571 pm8001_ha = sha->lldd_ha;
572 for (i = 0; i < chip_info->n_phy; i++) {
573 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
574 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
575 sha->sas_phy[i]->sas_addr =
576 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
577 }
578 sha->sas_ha_name = DRV_NAME;
579 sha->dev = pm8001_ha->dev;
580 sha->strict_wide_ports = 1;
581 sha->lldd_module = THIS_MODULE;
582 sha->sas_addr = &pm8001_ha->sas_addr[0];
583 sha->num_phys = chip_info->n_phy;
584 sha->core.shost = shost;
585}
586
587
588
589
590
591
592
593
594static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
595{
596 u8 i, j;
597 u8 sas_add[8];
598#ifdef PM8001_READ_VPD
599
600
601
602
603 DECLARE_COMPLETION_ONSTACK(completion);
604 struct pm8001_ioctl_payload payload;
605 u16 deviceid;
606 int rc;
607
608 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
609 pm8001_ha->nvmd_completion = &completion;
610
611 if (pm8001_ha->chip_id == chip_8001) {
612 if (deviceid == 0x8081 || deviceid == 0x0042) {
613 payload.minor_function = 4;
614 payload.length = 4096;
615 } else {
616 payload.minor_function = 0;
617 payload.length = 128;
618 }
619 } else if ((pm8001_ha->chip_id == chip_8070 ||
620 pm8001_ha->chip_id == chip_8072) &&
621 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
622 payload.minor_function = 4;
623 payload.length = 4096;
624 } else {
625 payload.minor_function = 1;
626 payload.length = 4096;
627 }
628 payload.offset = 0;
629 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
630 if (!payload.func_specific) {
631 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
632 return;
633 }
634 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
635 if (rc) {
636 kfree(payload.func_specific);
637 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
638 return;
639 }
640 wait_for_completion(&completion);
641
642 for (i = 0, j = 0; i <= 7; i++, j++) {
643 if (pm8001_ha->chip_id == chip_8001) {
644 if (deviceid == 0x8081)
645 pm8001_ha->sas_addr[j] =
646 payload.func_specific[0x704 + i];
647 else if (deviceid == 0x0042)
648 pm8001_ha->sas_addr[j] =
649 payload.func_specific[0x010 + i];
650 } else if ((pm8001_ha->chip_id == chip_8070 ||
651 pm8001_ha->chip_id == chip_8072) &&
652 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
653 pm8001_ha->sas_addr[j] =
654 payload.func_specific[0x010 + i];
655 } else
656 pm8001_ha->sas_addr[j] =
657 payload.func_specific[0x804 + i];
658 }
659 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
660 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
661 if (i && ((i % 4) == 0))
662 sas_add[7] = sas_add[7] + 4;
663 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
664 sas_add, SAS_ADDR_SIZE);
665 PM8001_INIT_DBG(pm8001_ha,
666 pm8001_printk("phy %d sas_addr = %016llx\n", i,
667 pm8001_ha->phy[i].dev_sas_addr));
668 }
669 kfree(payload.func_specific);
670#else
671 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
672 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
673 pm8001_ha->phy[i].dev_sas_addr =
674 cpu_to_be64((u64)
675 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
676 }
677 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
678 SAS_ADDR_SIZE);
679#endif
680}
681
682
683
684
685
686static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
687{
688
689#ifdef PM8001_READ_VPD
690
691 DECLARE_COMPLETION_ONSTACK(completion);
692 struct pm8001_ioctl_payload payload;
693 int rc;
694
695 pm8001_ha->nvmd_completion = &completion;
696
697 payload.minor_function = 6;
698 payload.offset = 0;
699 payload.length = 4096;
700 payload.func_specific = kzalloc(4096, GFP_KERNEL);
701 if (!payload.func_specific)
702 return -ENOMEM;
703
704 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
705 if (rc) {
706 kfree(payload.func_specific);
707 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
708 return -ENOMEM;
709 }
710 wait_for_completion(&completion);
711 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
712 kfree(payload.func_specific);
713#endif
714 return 0;
715}
716
717struct pm8001_mpi3_phy_pg_trx_config {
718 u32 LaneLosCfg;
719 u32 LanePgaCfg1;
720 u32 LanePisoCfg1;
721 u32 LanePisoCfg2;
722 u32 LanePisoCfg3;
723 u32 LanePisoCfg4;
724 u32 LanePisoCfg5;
725 u32 LanePisoCfg6;
726 u32 LaneBctCtrl;
727};
728
729
730
731
732
733
734static
735void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
736 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
737{
738 phycfg->LaneLosCfg = 0x00000132;
739 phycfg->LanePgaCfg1 = 0x00203949;
740 phycfg->LanePisoCfg1 = 0x000000FF;
741 phycfg->LanePisoCfg2 = 0xFF000001;
742 phycfg->LanePisoCfg3 = 0xE7011300;
743 phycfg->LanePisoCfg4 = 0x631C40C0;
744 phycfg->LanePisoCfg5 = 0xF8102036;
745 phycfg->LanePisoCfg6 = 0xF74A1000;
746 phycfg->LaneBctCtrl = 0x00FB33F8;
747}
748
749
750
751
752
753
754static
755void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
756 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
757{
758 phycfg->LaneLosCfg = 0x00000132;
759 phycfg->LanePgaCfg1 = 0x00203949;
760 phycfg->LanePisoCfg1 = 0x000000FF;
761 phycfg->LanePisoCfg2 = 0xFF000001;
762 phycfg->LanePisoCfg3 = 0xE7011300;
763 phycfg->LanePisoCfg4 = 0x63349140;
764 phycfg->LanePisoCfg5 = 0xF8102036;
765 phycfg->LanePisoCfg6 = 0xF80D9300;
766 phycfg->LaneBctCtrl = 0x00FB33F8;
767}
768
769
770
771
772
773
774static
775void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
776{
777 switch (pm8001_ha->pdev->subsystem_device) {
778 case 0x0070:
779 case 0x0072:
780 *phymask = 0x0000;
781 break;
782
783 case 0x0071:
784 case 0x0073:
785 *phymask = 0xFFFF;
786 break;
787
788 case 0x0080:
789 *phymask = 0x00F0;
790 break;
791
792 case 0x0081:
793 *phymask = 0x0FF0;
794 break;
795
796 case 0x0082:
797 *phymask = 0xFF00;
798 break;
799
800 default:
801 PM8001_INIT_DBG(pm8001_ha,
802 pm8001_printk("Unknown subsystem device=0x%.04x",
803 pm8001_ha->pdev->subsystem_device));
804 }
805}
806
807
808
809
810
811static
812int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
813{
814 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
815 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
816 int phymask = 0;
817 int i = 0;
818
819 memset(&phycfg_int, 0, sizeof(phycfg_int));
820 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
821
822 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
823 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
824 pm8001_get_phy_mask(pm8001_ha, &phymask);
825
826 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
827 if (phymask & (1 << i)) {
828 pm8001_set_phy_profile_single(pm8001_ha, i,
829 sizeof(phycfg_int) / sizeof(u32),
830 (u32 *)&phycfg_int);
831
832 } else {
833 pm8001_set_phy_profile_single(pm8001_ha, i,
834 sizeof(phycfg_ext) / sizeof(u32),
835 (u32 *)&phycfg_ext);
836 }
837 }
838
839 return 0;
840}
841
842
843
844
845
846static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
847{
848 switch (pm8001_ha->pdev->subsystem_vendor) {
849 case PCI_VENDOR_ID_ATTO:
850 if (pm8001_ha->pdev->device == 0x0042)
851 return 0;
852 else
853 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
854
855 case PCI_VENDOR_ID_ADAPTEC2:
856 case 0:
857 return 0;
858
859 default:
860 return pm8001_get_phy_settings_info(pm8001_ha);
861 }
862}
863
864#ifdef PM8001_USE_MSIX
865
866
867
868
869
870static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
871{
872 u32 i = 0, j = 0;
873 u32 number_of_intr;
874 int flag = 0;
875 int rc;
876 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
877
878
879 if (pm8001_ha->chip_id == chip_8001) {
880 number_of_intr = 1;
881 } else {
882 number_of_intr = PM8001_MAX_MSIX_VEC;
883 flag &= ~IRQF_SHARED;
884 }
885
886 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
887 number_of_intr, PCI_IRQ_MSIX);
888 if (rc < 0)
889 return rc;
890 pm8001_ha->number_of_intr = number_of_intr;
891
892 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
893 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
894 rc, pm8001_ha->number_of_intr));
895
896 for (i = 0; i < number_of_intr; i++) {
897 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
898 DRV_NAME"%d", i);
899 pm8001_ha->irq_vector[i].irq_id = i;
900 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
901
902 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
903 pm8001_interrupt_handler_msix, flag,
904 intr_drvname[i], &(pm8001_ha->irq_vector[i]));
905 if (rc) {
906 for (j = 0; j < i; j++) {
907 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
908 &(pm8001_ha->irq_vector[i]));
909 }
910 pci_free_irq_vectors(pm8001_ha->pdev);
911 break;
912 }
913 }
914
915 return rc;
916}
917#endif
918
919
920
921
922
923static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
924{
925 struct pci_dev *pdev;
926 int rc;
927
928 pdev = pm8001_ha->pdev;
929
930#ifdef PM8001_USE_MSIX
931 if (pdev->msix_cap && pci_msi_enabled())
932 return pm8001_setup_msix(pm8001_ha);
933 else {
934 PM8001_INIT_DBG(pm8001_ha,
935 pm8001_printk("MSIX not supported!!!\n"));
936 goto intx;
937 }
938#endif
939
940intx:
941
942 pm8001_ha->irq_vector[0].irq_id = 0;
943 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
944 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
945 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
946 return rc;
947}
948
949
950
951
952
953
954
955
956
957
958static int pm8001_pci_probe(struct pci_dev *pdev,
959 const struct pci_device_id *ent)
960{
961 unsigned int rc;
962 u32 pci_reg;
963 u8 i = 0;
964 struct pm8001_hba_info *pm8001_ha;
965 struct Scsi_Host *shost = NULL;
966 const struct pm8001_chip_info *chip;
967
968 dev_printk(KERN_INFO, &pdev->dev,
969 "pm80xx: driver version %s\n", DRV_VERSION);
970 rc = pci_enable_device(pdev);
971 if (rc)
972 goto err_out_enable;
973 pci_set_master(pdev);
974
975
976
977
978
979 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
980 pci_reg |= 0x157;
981 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
982 rc = pci_request_regions(pdev, DRV_NAME);
983 if (rc)
984 goto err_out_disable;
985 rc = pci_go_44(pdev);
986 if (rc)
987 goto err_out_regions;
988
989 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
990 if (!shost) {
991 rc = -ENOMEM;
992 goto err_out_regions;
993 }
994 chip = &pm8001_chips[ent->driver_data];
995 SHOST_TO_SAS_HA(shost) =
996 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
997 if (!SHOST_TO_SAS_HA(shost)) {
998 rc = -ENOMEM;
999 goto err_out_free_host;
1000 }
1001
1002 rc = pm8001_prep_sas_ha_init(shost, chip);
1003 if (rc) {
1004 rc = -ENOMEM;
1005 goto err_out_free;
1006 }
1007 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1008
1009 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1010 if (!pm8001_ha) {
1011 rc = -ENOMEM;
1012 goto err_out_free;
1013 }
1014 list_add_tail(&pm8001_ha->list, &hba_list);
1015 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1016 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1017 if (rc) {
1018 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1019 "chip_init failed [ret: %d]\n", rc));
1020 goto err_out_ha_free;
1021 }
1022
1023 rc = scsi_add_host(shost, &pdev->dev);
1024 if (rc)
1025 goto err_out_ha_free;
1026 rc = pm8001_request_irq(pm8001_ha);
1027 if (rc) {
1028 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1029 "pm8001_request_irq failed [ret: %d]\n", rc));
1030 goto err_out_shost;
1031 }
1032
1033 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1034 if (pm8001_ha->chip_id != chip_8001) {
1035 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1036 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1037
1038 pm80xx_set_thermal_config(pm8001_ha);
1039 }
1040
1041 pm8001_init_sas_add(pm8001_ha);
1042
1043 if (pm8001_configure_phy_settings(pm8001_ha))
1044 goto err_out_shost;
1045
1046 pm8001_post_sas_ha_init(shost, chip);
1047 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1048 if (rc)
1049 goto err_out_shost;
1050 scsi_scan_host(pm8001_ha->shost);
1051 pm8001_ha->flags = PM8001F_RUN_TIME;
1052 return 0;
1053
1054err_out_shost:
1055 scsi_remove_host(pm8001_ha->shost);
1056err_out_ha_free:
1057 pm8001_free(pm8001_ha);
1058err_out_free:
1059 kfree(SHOST_TO_SAS_HA(shost));
1060err_out_free_host:
1061 scsi_host_put(shost);
1062err_out_regions:
1063 pci_release_regions(pdev);
1064err_out_disable:
1065 pci_disable_device(pdev);
1066err_out_enable:
1067 return rc;
1068}
1069
1070static void pm8001_pci_remove(struct pci_dev *pdev)
1071{
1072 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1073 struct pm8001_hba_info *pm8001_ha;
1074 int i, j;
1075 pm8001_ha = sha->lldd_ha;
1076 sas_unregister_ha(sha);
1077 sas_remove_host(pm8001_ha->shost);
1078 list_del(&pm8001_ha->list);
1079 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1080 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1081
1082#ifdef PM8001_USE_MSIX
1083 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1084 synchronize_irq(pci_irq_vector(pdev, i));
1085 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1086 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1087 pci_free_irq_vectors(pdev);
1088#else
1089 free_irq(pm8001_ha->irq, sha);
1090#endif
1091#ifdef PM8001_USE_TASKLET
1092
1093 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1094 (pm8001_ha->chip_id == chip_8001))
1095 tasklet_kill(&pm8001_ha->tasklet[0]);
1096 else
1097 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1098 tasklet_kill(&pm8001_ha->tasklet[j]);
1099#endif
1100 scsi_host_put(pm8001_ha->shost);
1101 pm8001_free(pm8001_ha);
1102 kfree(sha->sas_phy);
1103 kfree(sha->sas_port);
1104 kfree(sha);
1105 pci_release_regions(pdev);
1106 pci_disable_device(pdev);
1107}
1108
1109
1110
1111
1112
1113
1114
1115
1116static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1117{
1118 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1119 struct pm8001_hba_info *pm8001_ha;
1120 int i, j;
1121 u32 device_state;
1122 pm8001_ha = sha->lldd_ha;
1123 sas_suspend_ha(sha);
1124 flush_workqueue(pm8001_wq);
1125 scsi_block_requests(pm8001_ha->shost);
1126 if (!pdev->pm_cap) {
1127 dev_err(&pdev->dev, " PCI PM not supported\n");
1128 return -ENODEV;
1129 }
1130 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1131 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1132#ifdef PM8001_USE_MSIX
1133 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1134 synchronize_irq(pci_irq_vector(pdev, i));
1135 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1136 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1137 pci_free_irq_vectors(pdev);
1138#else
1139 free_irq(pm8001_ha->irq, sha);
1140#endif
1141#ifdef PM8001_USE_TASKLET
1142
1143 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1144 (pm8001_ha->chip_id == chip_8001))
1145 tasklet_kill(&pm8001_ha->tasklet[0]);
1146 else
1147 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1148 tasklet_kill(&pm8001_ha->tasklet[j]);
1149#endif
1150 device_state = pci_choose_state(pdev, state);
1151 pm8001_printk("pdev=0x%p, slot=%s, entering "
1152 "operating state [D%d]\n", pdev,
1153 pm8001_ha->name, device_state);
1154 pci_save_state(pdev);
1155 pci_disable_device(pdev);
1156 pci_set_power_state(pdev, device_state);
1157 return 0;
1158}
1159
1160
1161
1162
1163
1164
1165
1166static int pm8001_pci_resume(struct pci_dev *pdev)
1167{
1168 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1169 struct pm8001_hba_info *pm8001_ha;
1170 int rc;
1171 u8 i = 0, j;
1172 u32 device_state;
1173 DECLARE_COMPLETION_ONSTACK(completion);
1174 pm8001_ha = sha->lldd_ha;
1175 device_state = pdev->current_state;
1176
1177 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1178 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1179
1180 pci_set_power_state(pdev, PCI_D0);
1181 pci_enable_wake(pdev, PCI_D0, 0);
1182 pci_restore_state(pdev);
1183 rc = pci_enable_device(pdev);
1184 if (rc) {
1185 pm8001_printk("slot=%s Enable device failed during resume\n",
1186 pm8001_ha->name);
1187 goto err_out_enable;
1188 }
1189
1190 pci_set_master(pdev);
1191 rc = pci_go_44(pdev);
1192 if (rc)
1193 goto err_out_disable;
1194 sas_prep_resume_ha(sha);
1195
1196 if (pm8001_ha->chip_id == chip_8001) {
1197 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1198 PM8001_INIT_DBG(pm8001_ha,
1199 pm8001_printk("chip soft reset successful\n"));
1200 }
1201 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1202 if (rc)
1203 goto err_out_disable;
1204
1205
1206 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1207
1208 rc = pm8001_request_irq(pm8001_ha);
1209 if (rc)
1210 goto err_out_disable;
1211#ifdef PM8001_USE_TASKLET
1212
1213 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1214 (pm8001_ha->chip_id == chip_8001))
1215 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1216 (unsigned long)&(pm8001_ha->irq_vector[0]));
1217 else
1218 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1219 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1220 (unsigned long)&(pm8001_ha->irq_vector[j]));
1221#endif
1222 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1223 if (pm8001_ha->chip_id != chip_8001) {
1224 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1225 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1226 }
1227
1228
1229
1230
1231
1232
1233 if (pm8001_ha->chip_id == chip_8070 ||
1234 pm8001_ha->chip_id == chip_8072) {
1235 mdelay(500);
1236 }
1237
1238
1239
1240 pm8001_ha->flags = PM8001F_RUN_TIME;
1241 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1242 pm8001_ha->phy[i].enable_completion = &completion;
1243 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1244 wait_for_completion(&completion);
1245 }
1246 sas_resume_ha(sha);
1247 return 0;
1248
1249err_out_disable:
1250 scsi_remove_host(pm8001_ha->shost);
1251 pci_disable_device(pdev);
1252err_out_enable:
1253 return rc;
1254}
1255
1256
1257
1258
1259static struct pci_device_id pm8001_pci_table[] = {
1260 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1261 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1262 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1263 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1264
1265 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1266 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1267 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1268 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1269 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1270 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1271 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1272 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1273 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1274 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1275 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1276 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1277 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1278 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1279 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1280 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1281 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1282 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1283 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1284 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1285 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1286 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1287 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1288 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1289 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1290 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1291 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1292 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1293 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1294 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1295 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1296 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1297 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1298 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1299 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1300 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1301 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1302 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1303 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1304 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1305 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1306 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1307 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1308 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1309 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1310 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1311 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1312 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1313 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1314 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1315 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1316 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1317 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1318 { PCI_VENDOR_ID_ATTO, 0x8070,
1319 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1320 { PCI_VENDOR_ID_ATTO, 0x8070,
1321 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1322 { PCI_VENDOR_ID_ATTO, 0x8072,
1323 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1324 { PCI_VENDOR_ID_ATTO, 0x8072,
1325 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1326 { PCI_VENDOR_ID_ATTO, 0x8070,
1327 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1328 { PCI_VENDOR_ID_ATTO, 0x8072,
1329 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1330 { PCI_VENDOR_ID_ATTO, 0x8072,
1331 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1332 {}
1333};
1334
1335static struct pci_driver pm8001_pci_driver = {
1336 .name = DRV_NAME,
1337 .id_table = pm8001_pci_table,
1338 .probe = pm8001_pci_probe,
1339 .remove = pm8001_pci_remove,
1340 .suspend = pm8001_pci_suspend,
1341 .resume = pm8001_pci_resume,
1342};
1343
1344
1345
1346
1347static int __init pm8001_init(void)
1348{
1349 int rc = -ENOMEM;
1350
1351 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1352 if (!pm8001_wq)
1353 goto err;
1354
1355 pm8001_id = 0;
1356 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1357 if (!pm8001_stt)
1358 goto err_wq;
1359 rc = pci_register_driver(&pm8001_pci_driver);
1360 if (rc)
1361 goto err_tp;
1362 return 0;
1363
1364err_tp:
1365 sas_release_transport(pm8001_stt);
1366err_wq:
1367 destroy_workqueue(pm8001_wq);
1368err:
1369 return rc;
1370}
1371
1372static void __exit pm8001_exit(void)
1373{
1374 pci_unregister_driver(&pm8001_pci_driver);
1375 sas_release_transport(pm8001_stt);
1376 destroy_workqueue(pm8001_wq);
1377}
1378
1379module_init(pm8001_init);
1380module_exit(pm8001_exit);
1381
1382MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1383MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1384MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1385MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1386MODULE_DESCRIPTION(
1387 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1388 "SAS/SATA controller driver");
1389MODULE_VERSION(DRV_VERSION);
1390MODULE_LICENSE("GPL");
1391MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1392
1393
