linux/drivers/scsi/pm8001/pm80xx_hwi.h
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   1/*
   2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3 *
   4 * Copyright (c) 2008-2009 USI Co., Ltd.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 * 1. Redistributions of source code must retain the above copyright
  11 *      notice, this list of conditions, and the following disclaimer,
  12 *      without modification.
  13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14 *      substantially similar to the "NO WARRANTY" disclaimer below
  15 *      ("Disclaimer") and any redistribution must be conditioned upon
  16 *      including a substantially similar Disclaimer requirement for further
  17 *      binary redistribution.
  18 * 3. Neither the names of the above-listed copyright holders nor the names
  19 *      of any contributors may be used to endorse or promote products derived
  20 *      from this software without specific prior written permission.
  21 *
  22 * Alternatively, this software may be distributed under the terms of the
  23 * GNU General Public License ("GPL") version 2 as published by the Free
  24 * Software Foundation.
  25 *
  26 * NO WARRANTY
  27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37 * POSSIBILITY OF SUCH DAMAGES.
  38 *
  39 */
  40
  41#ifndef _PMC8001_REG_H_
  42#define _PMC8001_REG_H_
  43
  44#include <linux/types.h>
  45#include <scsi/libsas.h>
  46
  47/* for Request Opcode of IOMB */
  48#define OPC_INB_ECHO                            1       /* 0x000 */
  49#define OPC_INB_PHYSTART                        4       /* 0x004 */
  50#define OPC_INB_PHYSTOP                         5       /* 0x005 */
  51#define OPC_INB_SSPINIIOSTART                   6       /* 0x006 */
  52#define OPC_INB_SSPINITMSTART                   7       /* 0x007 */
  53/* 0x8 RESV IN SPCv */
  54#define OPC_INB_RSVD                            8       /* 0x008 */
  55#define OPC_INB_DEV_HANDLE_ACCEPT               9       /* 0x009 */
  56#define OPC_INB_SSPTGTIOSTART                   10      /* 0x00A */
  57#define OPC_INB_SSPTGTRSPSTART                  11      /* 0x00B */
  58/* 0xC, 0xD, 0xE removed in SPCv */
  59#define OPC_INB_SSP_ABORT                       15      /* 0x00F */
  60#define OPC_INB_DEREG_DEV_HANDLE                16      /* 0x010 */
  61#define OPC_INB_GET_DEV_HANDLE                  17      /* 0x011 */
  62#define OPC_INB_SMP_REQUEST                     18      /* 0x012 */
  63/* 0x13 SMP_RESPONSE is removed in SPCv */
  64#define OPC_INB_SMP_ABORT                       20      /* 0x014 */
  65/* 0x16 RESV IN SPCv */
  66#define OPC_INB_RSVD1                           22      /* 0x016 */
  67#define OPC_INB_SATA_HOST_OPSTART               23      /* 0x017 */
  68#define OPC_INB_SATA_ABORT                      24      /* 0x018 */
  69#define OPC_INB_LOCAL_PHY_CONTROL               25      /* 0x019 */
  70/* 0x1A RESV IN SPCv */
  71#define OPC_INB_RSVD2                           26      /* 0x01A */
  72#define OPC_INB_FW_FLASH_UPDATE                 32      /* 0x020 */
  73#define OPC_INB_GPIO                            34      /* 0x022 */
  74#define OPC_INB_SAS_DIAG_MODE_START_END         35      /* 0x023 */
  75#define OPC_INB_SAS_DIAG_EXECUTE                36      /* 0x024 */
  76/* 0x25 RESV IN SPCv */
  77#define OPC_INB_RSVD3                           37      /* 0x025 */
  78#define OPC_INB_GET_TIME_STAMP                  38      /* 0x026 */
  79#define OPC_INB_PORT_CONTROL                    39      /* 0x027 */
  80#define OPC_INB_GET_NVMD_DATA                   40      /* 0x028 */
  81#define OPC_INB_SET_NVMD_DATA                   41      /* 0x029 */
  82#define OPC_INB_SET_DEVICE_STATE                42      /* 0x02A */
  83#define OPC_INB_GET_DEVICE_STATE                43      /* 0x02B */
  84#define OPC_INB_SET_DEV_INFO                    44      /* 0x02C */
  85/* 0x2D RESV IN SPCv */
  86#define OPC_INB_RSVD4                           45      /* 0x02D */
  87#define OPC_INB_SGPIO_REGISTER                  46      /* 0x02E */
  88#define OPC_INB_PCIE_DIAG_EXEC                  47      /* 0x02F */
  89#define OPC_INB_SET_CONTROLLER_CONFIG           48      /* 0x030 */
  90#define OPC_INB_GET_CONTROLLER_CONFIG           49      /* 0x031 */
  91#define OPC_INB_REG_DEV                         50      /* 0x032 */
  92#define OPC_INB_SAS_HW_EVENT_ACK                51      /* 0x033 */
  93#define OPC_INB_GET_DEVICE_INFO                 52      /* 0x034 */
  94#define OPC_INB_GET_PHY_PROFILE                 53      /* 0x035 */
  95#define OPC_INB_FLASH_OP_EXT                    54      /* 0x036 */
  96#define OPC_INB_SET_PHY_PROFILE                 55      /* 0x037 */
  97#define OPC_INB_KEK_MANAGEMENT                  256     /* 0x100 */
  98#define OPC_INB_DEK_MANAGEMENT                  257     /* 0x101 */
  99#define OPC_INB_SSP_INI_DIF_ENC_IO              258     /* 0x102 */
 100#define OPC_INB_SATA_DIF_ENC_IO                 259     /* 0x103 */
 101
 102/* for Response Opcode of IOMB */
 103#define OPC_OUB_ECHO                                    1       /* 0x001 */
 104#define OPC_OUB_RSVD                                    4       /* 0x004 */
 105#define OPC_OUB_SSP_COMP                                5       /* 0x005 */
 106#define OPC_OUB_SMP_COMP                                6       /* 0x006 */
 107#define OPC_OUB_LOCAL_PHY_CNTRL                         7       /* 0x007 */
 108#define OPC_OUB_RSVD1                                   10      /* 0x00A */
 109#define OPC_OUB_DEREG_DEV                               11      /* 0x00B */
 110#define OPC_OUB_GET_DEV_HANDLE                          12      /* 0x00C */
 111#define OPC_OUB_SATA_COMP                               13      /* 0x00D */
 112#define OPC_OUB_SATA_EVENT                              14      /* 0x00E */
 113#define OPC_OUB_SSP_EVENT                               15      /* 0x00F */
 114#define OPC_OUB_RSVD2                                   16      /* 0x010 */
 115/* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
 116#define OPC_OUB_SSP_RECV_EVENT                          18      /* 0x012 */
 117#define OPC_OUB_RSVD3                                   19      /* 0x013 */
 118#define OPC_OUB_FW_FLASH_UPDATE                         20      /* 0x014 */
 119#define OPC_OUB_GPIO_RESPONSE                           22      /* 0x016 */
 120#define OPC_OUB_GPIO_EVENT                              23      /* 0x017 */
 121#define OPC_OUB_GENERAL_EVENT                           24      /* 0x018 */
 122#define OPC_OUB_SSP_ABORT_RSP                           26      /* 0x01A */
 123#define OPC_OUB_SATA_ABORT_RSP                          27      /* 0x01B */
 124#define OPC_OUB_SAS_DIAG_MODE_START_END                 28      /* 0x01C */
 125#define OPC_OUB_SAS_DIAG_EXECUTE                        29      /* 0x01D */
 126#define OPC_OUB_GET_TIME_STAMP                          30      /* 0x01E */
 127#define OPC_OUB_RSVD4                                   31      /* 0x01F */
 128#define OPC_OUB_PORT_CONTROL                            32      /* 0x020 */
 129#define OPC_OUB_SKIP_ENTRY                              33      /* 0x021 */
 130#define OPC_OUB_SMP_ABORT_RSP                           34      /* 0x022 */
 131#define OPC_OUB_GET_NVMD_DATA                           35      /* 0x023 */
 132#define OPC_OUB_SET_NVMD_DATA                           36      /* 0x024 */
 133#define OPC_OUB_DEVICE_HANDLE_REMOVAL                   37      /* 0x025 */
 134#define OPC_OUB_SET_DEVICE_STATE                        38      /* 0x026 */
 135#define OPC_OUB_GET_DEVICE_STATE                        39      /* 0x027 */
 136#define OPC_OUB_SET_DEV_INFO                            40      /* 0x028 */
 137#define OPC_OUB_RSVD5                                   41      /* 0x029 */
 138#define OPC_OUB_HW_EVENT                                1792    /* 0x700 */
 139#define OPC_OUB_DEV_HANDLE_ARRIV                        1824    /* 0x720 */
 140#define OPC_OUB_THERM_HW_EVENT                          1840    /* 0x730 */
 141#define OPC_OUB_SGPIO_RESP                              2094    /* 0x82E */
 142#define OPC_OUB_PCIE_DIAG_EXECUTE                       2095    /* 0x82F */
 143#define OPC_OUB_DEV_REGIST                              2098    /* 0x832 */
 144#define OPC_OUB_SAS_HW_EVENT_ACK                        2099    /* 0x833 */
 145#define OPC_OUB_GET_DEVICE_INFO                         2100    /* 0x834 */
 146/* spcv specific commands */
 147#define OPC_OUB_PHY_START_RESP                          2052    /* 0x804 */
 148#define OPC_OUB_PHY_STOP_RESP                           2053    /* 0x805 */
 149#define OPC_OUB_SET_CONTROLLER_CONFIG                   2096    /* 0x830 */
 150#define OPC_OUB_GET_CONTROLLER_CONFIG                   2097    /* 0x831 */
 151#define OPC_OUB_GET_PHY_PROFILE                         2101    /* 0x835 */
 152#define OPC_OUB_FLASH_OP_EXT                            2102    /* 0x836 */
 153#define OPC_OUB_SET_PHY_PROFILE                         2103    /* 0x837 */
 154#define OPC_OUB_KEK_MANAGEMENT_RESP                     2304    /* 0x900 */
 155#define OPC_OUB_DEK_MANAGEMENT_RESP                     2305    /* 0x901 */
 156#define OPC_OUB_SSP_COALESCED_COMP_RESP                 2306    /* 0x902 */
 157
 158/* for phy start*/
 159#define SSC_DISABLE_15                  (0x01 << 16)
 160#define SSC_DISABLE_30                  (0x02 << 16)
 161#define SSC_DISABLE_60                  (0x04 << 16)
 162#define SAS_ASE                         (0x01 << 15)
 163#define SPINHOLD_DISABLE                (0x00 << 14)
 164#define SPINHOLD_ENABLE                 (0x01 << 14)
 165#define LINKMODE_SAS                    (0x01 << 12)
 166#define LINKMODE_DSATA                  (0x02 << 12)
 167#define LINKMODE_AUTO                   (0x03 << 12)
 168#define LINKRATE_15                     (0x01 << 8)
 169#define LINKRATE_30                     (0x02 << 8)
 170#define LINKRATE_60                     (0x04 << 8)
 171#define LINKRATE_120                    (0x08 << 8)
 172
 173/*phy_stop*/
 174#define PHY_STOP_SUCCESS                0x00
 175#define PHY_STOP_ERR_DEVICE_ATTACHED    0x1046
 176
 177/* phy_profile */
 178#define SAS_PHY_ANALOG_SETTINGS_PAGE    0x04
 179#define PHY_DWORD_LENGTH                0xC
 180
 181/* Thermal related */
 182#define THERMAL_ENABLE                  0x1
 183#define THERMAL_LOG_ENABLE              0x1
 184#define THERMAL_PAGE_CODE_7H            0x6
 185#define THERMAL_PAGE_CODE_8H            0x7
 186#define LTEMPHIL                         70
 187#define RTEMPHIL                        100
 188
 189/* Encryption info */
 190#define SCRATCH_PAD3_ENC_DISABLED       0x00000000
 191#define SCRATCH_PAD3_ENC_DIS_ERR        0x00000001
 192#define SCRATCH_PAD3_ENC_ENA_ERR        0x00000002
 193#define SCRATCH_PAD3_ENC_READY          0x00000003
 194#define SCRATCH_PAD3_ENC_MASK           SCRATCH_PAD3_ENC_READY
 195
 196#define SCRATCH_PAD3_XTS_ENABLED                (1 << 14)
 197#define SCRATCH_PAD3_SMA_ENABLED                (1 << 4)
 198#define SCRATCH_PAD3_SMB_ENABLED                (1 << 5)
 199#define SCRATCH_PAD3_SMF_ENABLED                0
 200#define SCRATCH_PAD3_SM_MASK                    0x000000F0
 201#define SCRATCH_PAD3_ERR_CODE                   0x00FF0000
 202
 203#define SEC_MODE_SMF                            0x0
 204#define SEC_MODE_SMA                            0x100
 205#define SEC_MODE_SMB                            0x200
 206#define CIPHER_MODE_ECB                         0x00000001
 207#define CIPHER_MODE_XTS                         0x00000002
 208#define KEK_MGMT_SUBOP_KEYCARDUPDATE            0x4
 209
 210/* SAS protocol timer configuration page */
 211#define SAS_PROTOCOL_TIMER_CONFIG_PAGE  0x04
 212#define STP_MCT_TMO                     32
 213#define SSP_MCT_TMO                     32
 214#define SAS_MAX_OPEN_TIME                               5
 215#define SMP_MAX_CONN_TIMER              0xFF
 216#define STP_FRM_TIMER                   0
 217#define STP_IDLE_TIME                   5 /* 5 us; controller default */
 218#define SAS_MFD                         0
 219#define SAS_OPNRJT_RTRY_INTVL           2
 220#define SAS_DOPNRJT_RTRY_TMO            128
 221#define SAS_COPNRJT_RTRY_TMO            128
 222
 223/*
 224  Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
 225  Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
 226  is DOPNRJT_RTRY_TMO
 227*/
 228#define SAS_DOPNRJT_RTRY_THR            23438
 229#define SAS_COPNRJT_RTRY_THR            23438
 230#define SAS_MAX_AIP                     0x200000
 231#define IT_NEXUS_TIMEOUT       0x7D0
 232#define PORT_RECOVERY_TIMEOUT  ((IT_NEXUS_TIMEOUT/100) + 30)
 233/* Port recovery timeout, 10000 ms for PM8006 controller */
 234#define CHIP_8006_PORT_RECOVERY_TIMEOUT 0x640000
 235
 236#ifdef __LITTLE_ENDIAN_BITFIELD
 237struct sas_identify_frame_local {
 238        /* Byte 0 */
 239        u8  frame_type:4;
 240        u8  dev_type:3;
 241        u8  _un0:1;
 242
 243        /* Byte 1 */
 244        u8  _un1;
 245
 246        /* Byte 2 */
 247        union {
 248                struct {
 249                        u8  _un20:1;
 250                        u8  smp_iport:1;
 251                        u8  stp_iport:1;
 252                        u8  ssp_iport:1;
 253                        u8  _un247:4;
 254                };
 255                u8 initiator_bits;
 256        };
 257
 258        /* Byte 3 */
 259        union {
 260                struct {
 261                        u8  _un30:1;
 262                        u8 smp_tport:1;
 263                        u8 stp_tport:1;
 264                        u8 ssp_tport:1;
 265                        u8 _un347:4;
 266                };
 267                u8 target_bits;
 268        };
 269
 270        /* Byte 4 - 11 */
 271        u8 _un4_11[8];
 272
 273        /* Byte 12 - 19 */
 274        u8 sas_addr[SAS_ADDR_SIZE];
 275
 276        /* Byte 20 */
 277        u8 phy_id;
 278
 279        u8 _un21_27[7];
 280
 281} __packed;
 282
 283#elif defined(__BIG_ENDIAN_BITFIELD)
 284struct sas_identify_frame_local {
 285        /* Byte 0 */
 286        u8  _un0:1;
 287        u8  dev_type:3;
 288        u8  frame_type:4;
 289
 290        /* Byte 1 */
 291        u8  _un1;
 292
 293        /* Byte 2 */
 294        union {
 295                struct {
 296                        u8  _un247:4;
 297                        u8  ssp_iport:1;
 298                        u8  stp_iport:1;
 299                        u8  smp_iport:1;
 300                        u8  _un20:1;
 301                };
 302                u8 initiator_bits;
 303        };
 304
 305        /* Byte 3 */
 306        union {
 307                struct {
 308                        u8 _un347:4;
 309                        u8 ssp_tport:1;
 310                        u8 stp_tport:1;
 311                        u8 smp_tport:1;
 312                        u8 _un30:1;
 313                };
 314                u8 target_bits;
 315        };
 316
 317        /* Byte 4 - 11 */
 318        u8 _un4_11[8];
 319
 320        /* Byte 12 - 19 */
 321        u8 sas_addr[SAS_ADDR_SIZE];
 322
 323        /* Byte 20 */
 324        u8 phy_id;
 325
 326        u8 _un21_27[7];
 327} __packed;
 328#else
 329#error "Bitfield order not defined!"
 330#endif
 331
 332struct mpi_msg_hdr {
 333        __le32  header; /* Bits [11:0] - Message operation code */
 334        /* Bits [15:12] - Message Category */
 335        /* Bits [21:16] - Outboundqueue ID for the
 336        operation completion message */
 337        /* Bits [23:22] - Reserved */
 338        /* Bits [28:24] - Buffer Count, indicates how
 339        many buffer are allocated for the massage */
 340        /* Bits [30:29] - Reserved */
 341        /* Bits [31] - Message Valid bit */
 342} __attribute__((packed, aligned(4)));
 343
 344/*
 345 * brief the data structure of PHY Start Command
 346 * use to describe enable the phy (128 bytes)
 347 */
 348struct phy_start_req {
 349        __le32  tag;
 350        __le32  ase_sh_lm_slr_phyid;
 351        struct sas_identify_frame_local sas_identify; /* 28 Bytes */
 352        __le32 spasti;
 353        u32     reserved[21];
 354} __attribute__((packed, aligned(4)));
 355
 356/*
 357 * brief the data structure of PHY Start Command
 358 * use to disable the phy (128 bytes)
 359 */
 360struct phy_stop_req {
 361        __le32  tag;
 362        __le32  phy_id;
 363        u32     reserved[29];
 364} __attribute__((packed, aligned(4)));
 365
 366/* set device bits fis - device to host */
 367struct set_dev_bits_fis {
 368        u8      fis_type;       /* 0xA1*/
 369        u8      n_i_pmport;
 370        /* b7 : n Bit. Notification bit. If set device needs attention. */
 371        /* b6 : i Bit. Interrupt Bit */
 372        /* b5-b4: reserved2 */
 373        /* b3-b0: PM Port */
 374        u8      status;
 375        u8      error;
 376        u32     _r_a;
 377} __attribute__ ((packed));
 378/* PIO setup FIS - device to host */
 379struct pio_setup_fis {
 380        u8      fis_type;       /* 0x5f */
 381        u8      i_d_pmPort;
 382        /* b7 : reserved */
 383        /* b6 : i bit. Interrupt bit */
 384        /* b5 : d bit. data transfer direction. set to 1 for device to host
 385        xfer */
 386        /* b4 : reserved */
 387        /* b3-b0: PM Port */
 388        u8      status;
 389        u8      error;
 390        u8      lbal;
 391        u8      lbam;
 392        u8      lbah;
 393        u8      device;
 394        u8      lbal_exp;
 395        u8      lbam_exp;
 396        u8      lbah_exp;
 397        u8      _r_a;
 398        u8      sector_count;
 399        u8      sector_count_exp;
 400        u8      _r_b;
 401        u8      e_status;
 402        u8      _r_c[2];
 403        u8      transfer_count;
 404} __attribute__ ((packed));
 405
 406/*
 407 * brief the data structure of SATA Completion Response
 408 * use to describe the sata task response (64 bytes)
 409 */
 410struct sata_completion_resp {
 411        __le32  tag;
 412        __le32  status;
 413        __le32  param;
 414        u32     sata_resp[12];
 415} __attribute__((packed, aligned(4)));
 416
 417/*
 418 * brief the data structure of SAS HW Event Notification
 419 * use to alert the host about the hardware event(64 bytes)
 420 */
 421/* updated outbound struct for spcv */
 422
 423struct hw_event_resp {
 424        __le32  lr_status_evt_portid;
 425        __le32  evt_param;
 426        __le32  phyid_npip_portstate;
 427        struct sas_identify_frame       sas_identify;
 428        struct dev_to_host_fis  sata_fis;
 429} __attribute__((packed, aligned(4)));
 430
 431/*
 432 * brief the data structure for thermal event notification
 433 */
 434
 435struct thermal_hw_event {
 436        __le32  thermal_event;
 437        __le32  rht_lht;
 438} __attribute__((packed, aligned(4)));
 439
 440/*
 441 * brief the data structure of REGISTER DEVICE Command
 442 * use to describe MPI REGISTER DEVICE Command (64 bytes)
 443 */
 444
 445struct reg_dev_req {
 446        __le32  tag;
 447        __le32  phyid_portid;
 448        __le32  dtype_dlr_mcn_ir_retry;
 449        __le32  firstburstsize_ITNexustimeout;
 450        u8      sas_addr[SAS_ADDR_SIZE];
 451        __le32  upper_device_id;
 452        u32     reserved[24];
 453} __attribute__((packed, aligned(4)));
 454
 455/*
 456 * brief the data structure of DEREGISTER DEVICE Command
 457 * use to request spc to remove all internal resources associated
 458 * with the device id (64 bytes)
 459 */
 460
 461struct dereg_dev_req {
 462        __le32  tag;
 463        __le32  device_id;
 464        u32     reserved[29];
 465} __attribute__((packed, aligned(4)));
 466
 467/*
 468 * brief the data structure of DEVICE_REGISTRATION Response
 469 * use to notify the completion of the device registration (64 bytes)
 470 */
 471struct dev_reg_resp {
 472        __le32  tag;
 473        __le32  status;
 474        __le32  device_id;
 475        u32     reserved[12];
 476} __attribute__((packed, aligned(4)));
 477
 478/*
 479 * brief the data structure of Local PHY Control Command
 480 * use to issue PHY CONTROL to local phy (64 bytes)
 481 */
 482struct local_phy_ctl_req {
 483        __le32  tag;
 484        __le32  phyop_phyid;
 485        u32     reserved1[29];
 486} __attribute__((packed, aligned(4)));
 487
 488/**
 489 * brief the data structure of Local Phy Control Response
 490 * use to describe MPI Local Phy Control Response (64 bytes)
 491 */
 492 struct local_phy_ctl_resp {
 493        __le32  tag;
 494        __le32  phyop_phyid;
 495        __le32  status;
 496        u32     reserved[12];
 497} __attribute__((packed, aligned(4)));
 498
 499#define OP_BITS 0x0000FF00
 500#define ID_BITS 0x000000FF
 501
 502/*
 503 * brief the data structure of PORT Control Command
 504 * use to control port properties (64 bytes)
 505 */
 506
 507struct port_ctl_req {
 508        __le32  tag;
 509        __le32  portop_portid;
 510        __le32  param0;
 511        __le32  param1;
 512        u32     reserved1[27];
 513} __attribute__((packed, aligned(4)));
 514
 515/*
 516 * brief the data structure of HW Event Ack Command
 517 * use to acknowledge receive HW event (64 bytes)
 518 */
 519struct hw_event_ack_req {
 520        __le32  tag;
 521        __le32  phyid_sea_portid;
 522        __le32  param0;
 523        __le32  param1;
 524        u32     reserved1[27];
 525} __attribute__((packed, aligned(4)));
 526
 527/*
 528 * brief the data structure of PHY_START Response Command
 529 * indicates the completion of PHY_START command (64 bytes)
 530 */
 531struct phy_start_resp {
 532        __le32  tag;
 533        __le32  status;
 534        __le32  phyid;
 535        u32     reserved[12];
 536} __attribute__((packed, aligned(4)));
 537
 538/*
 539 * brief the data structure of PHY_STOP Response Command
 540 * indicates the completion of PHY_STOP command (64 bytes)
 541 */
 542struct phy_stop_resp {
 543        __le32  tag;
 544        __le32  status;
 545        __le32  phyid;
 546        u32     reserved[12];
 547} __attribute__((packed, aligned(4)));
 548
 549/*
 550 * brief the data structure of SSP Completion Response
 551 * use to indicate a SSP Completion (n bytes)
 552 */
 553struct ssp_completion_resp {
 554        __le32  tag;
 555        __le32  status;
 556        __le32  param;
 557        __le32  ssptag_rescv_rescpad;
 558        struct ssp_response_iu ssp_resp_iu;
 559        __le32  residual_count;
 560} __attribute__((packed, aligned(4)));
 561
 562#define SSP_RESCV_BIT   0x00010000
 563
 564/*
 565 * brief the data structure of SATA EVNET response
 566 * use to indicate a SATA Completion (64 bytes)
 567 */
 568struct sata_event_resp {
 569        __le32 tag;
 570        __le32 event;
 571        __le32 port_id;
 572        __le32 device_id;
 573        u32 reserved;
 574        __le32 event_param0;
 575        __le32 event_param1;
 576        __le32 sata_addr_h32;
 577        __le32 sata_addr_l32;
 578        __le32 e_udt1_udt0_crc;
 579        __le32 e_udt5_udt4_udt3_udt2;
 580        __le32 a_udt1_udt0_crc;
 581        __le32 a_udt5_udt4_udt3_udt2;
 582        __le32 hwdevid_diferr;
 583        __le32 err_framelen_byteoffset;
 584        __le32 err_dataframe;
 585} __attribute__((packed, aligned(4)));
 586
 587/*
 588 * brief the data structure of SSP EVNET esponse
 589 * use to indicate a SSP Completion (64 bytes)
 590 */
 591struct ssp_event_resp {
 592        __le32 tag;
 593        __le32 event;
 594        __le32 port_id;
 595        __le32 device_id;
 596        __le32 ssp_tag;
 597        __le32 event_param0;
 598        __le32 event_param1;
 599        __le32 sas_addr_h32;
 600        __le32 sas_addr_l32;
 601        __le32 e_udt1_udt0_crc;
 602        __le32 e_udt5_udt4_udt3_udt2;
 603        __le32 a_udt1_udt0_crc;
 604        __le32 a_udt5_udt4_udt3_udt2;
 605        __le32 hwdevid_diferr;
 606        __le32 err_framelen_byteoffset;
 607        __le32 err_dataframe;
 608} __attribute__((packed, aligned(4)));
 609
 610/**
 611 * brief the data structure of General Event Notification Response
 612 * use to describe MPI General Event Notification Response (64 bytes)
 613 */
 614struct general_event_resp {
 615        __le32  status;
 616        __le32  inb_IOMB_payload[14];
 617} __attribute__((packed, aligned(4)));
 618
 619#define GENERAL_EVENT_PAYLOAD   14
 620#define OPCODE_BITS     0x00000fff
 621
 622/*
 623 * brief the data structure of SMP Request Command
 624 * use to describe MPI SMP REQUEST Command (64 bytes)
 625 */
 626struct smp_req {
 627        __le32  tag;
 628        __le32  device_id;
 629        __le32  len_ip_ir;
 630        /* Bits [0] - Indirect response */
 631        /* Bits [1] - Indirect Payload */
 632        /* Bits [15:2] - Reserved */
 633        /* Bits [23:16] - direct payload Len */
 634        /* Bits [31:24] - Reserved */
 635        u8      smp_req16[16];
 636        union {
 637                u8      smp_req[32];
 638                struct {
 639                        __le64 long_req_addr;/* sg dma address, LE */
 640                        __le32 long_req_size;/* LE */
 641                        u32     _r_a;
 642                        __le64 long_resp_addr;/* sg dma address, LE */
 643                        __le32 long_resp_size;/* LE */
 644                        u32     _r_b;
 645                        } long_smp_req;/* sequencer extension */
 646        };
 647        __le32  rsvd[16];
 648} __attribute__((packed, aligned(4)));
 649/*
 650 * brief the data structure of SMP Completion Response
 651 * use to describe MPI SMP Completion Response (64 bytes)
 652 */
 653struct smp_completion_resp {
 654        __le32  tag;
 655        __le32  status;
 656        __le32  param;
 657        u8      _r_a[252];
 658} __attribute__((packed, aligned(4)));
 659
 660/*
 661 *brief the data structure of SSP SMP SATA Abort Command
 662 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
 663 */
 664struct task_abort_req {
 665        __le32  tag;
 666        __le32  device_id;
 667        __le32  tag_to_abort;
 668        __le32  abort_all;
 669        u32     reserved[27];
 670} __attribute__((packed, aligned(4)));
 671
 672/* These flags used for SSP SMP & SATA Abort */
 673#define ABORT_MASK              0x3
 674#define ABORT_SINGLE            0x0
 675#define ABORT_ALL               0x1
 676
 677/**
 678 * brief the data structure of SSP SATA SMP Abort Response
 679 * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
 680 */
 681struct task_abort_resp {
 682        __le32  tag;
 683        __le32  status;
 684        __le32  scp;
 685        u32     reserved[12];
 686} __attribute__((packed, aligned(4)));
 687
 688/**
 689 * brief the data structure of SAS Diagnostic Start/End Command
 690 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
 691 */
 692struct sas_diag_start_end_req {
 693        __le32  tag;
 694        __le32  operation_phyid;
 695        u32     reserved[29];
 696} __attribute__((packed, aligned(4)));
 697
 698/**
 699 * brief the data structure of SAS Diagnostic Execute Command
 700 * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
 701 */
 702struct sas_diag_execute_req {
 703        __le32  tag;
 704        __le32  cmdtype_cmddesc_phyid;
 705        __le32  pat1_pat2;
 706        __le32  threshold;
 707        __le32  codepat_errmsk;
 708        __le32  pmon;
 709        __le32  pERF1CTL;
 710        u32     reserved[24];
 711} __attribute__((packed, aligned(4)));
 712
 713#define SAS_DIAG_PARAM_BYTES 24
 714
 715/*
 716 * brief the data structure of Set Device State Command
 717 * use to describe MPI Set Device State Command (64 bytes)
 718 */
 719struct set_dev_state_req {
 720        __le32  tag;
 721        __le32  device_id;
 722        __le32  nds;
 723        u32     reserved[28];
 724} __attribute__((packed, aligned(4)));
 725
 726/*
 727 * brief the data structure of SATA Start Command
 728 * use to describe MPI SATA IO Start Command (64 bytes)
 729 * Note: This structure is common for normal / encryption I/O
 730 */
 731
 732struct sata_start_req {
 733        __le32  tag;
 734        __le32  device_id;
 735        __le32  data_len;
 736        __le32  ncqtag_atap_dir_m_dad;
 737        struct host_to_dev_fis  sata_fis;
 738        u32     reserved1;
 739        u32     reserved2;      /* dword 11. rsvd for normal I/O. */
 740                                /* EPLE Descl for enc I/O */
 741        u32     addr_low;       /* dword 12. rsvd for enc I/O */
 742        u32     addr_high;      /* dword 13. reserved for enc I/O */
 743        __le32  len;            /* dword 14: length for normal I/O. */
 744                                /* EPLE Desch for enc I/O */
 745        __le32  esgl;           /* dword 15. rsvd for enc I/O */
 746        __le32  atapi_scsi_cdb[4];      /* dword 16-19. rsvd for enc I/O */
 747        /* The below fields are reserved for normal I/O */
 748        __le32  key_index_mode; /* dword 20 */
 749        __le32  sector_cnt_enss;/* dword 21 */
 750        __le32  keytagl;        /* dword 22 */
 751        __le32  keytagh;        /* dword 23 */
 752        __le32  twk_val0;       /* dword 24 */
 753        __le32  twk_val1;       /* dword 25 */
 754        __le32  twk_val2;       /* dword 26 */
 755        __le32  twk_val3;       /* dword 27 */
 756        __le32  enc_addr_low;   /* dword 28. Encryption SGL address high */
 757        __le32  enc_addr_high;  /* dword 29. Encryption SGL address low */
 758        __le32  enc_len;        /* dword 30. Encryption length */
 759        __le32  enc_esgl;       /* dword 31. Encryption esgl bit */
 760} __attribute__((packed, aligned(4)));
 761
 762/**
 763 * brief the data structure of SSP INI TM Start Command
 764 * use to describe MPI SSP INI TM Start Command (64 bytes)
 765 */
 766struct ssp_ini_tm_start_req {
 767        __le32  tag;
 768        __le32  device_id;
 769        __le32  relate_tag;
 770        __le32  tmf;
 771        u8      lun[8];
 772        __le32  ds_ads_m;
 773        u32     reserved[24];
 774} __attribute__((packed, aligned(4)));
 775
 776struct ssp_info_unit {
 777        u8      lun[8];/* SCSI Logical Unit Number */
 778        u8      reserved1;/* reserved */
 779        u8      efb_prio_attr;
 780        /* B7 : enabledFirstBurst */
 781        /* B6-3 : taskPriority */
 782        /* B2-0 : taskAttribute */
 783        u8      reserved2;      /* reserved */
 784        u8      additional_cdb_len;
 785        /* B7-2 : additional_cdb_len */
 786        /* B1-0 : reserved */
 787        u8      cdb[16];/* The SCSI CDB up to 16 bytes length */
 788} __attribute__((packed, aligned(4)));
 789
 790/**
 791 * brief the data structure of SSP INI IO Start Command
 792 * use to describe MPI SSP INI IO Start Command (64 bytes)
 793 * Note: This structure is common for normal / encryption I/O
 794 */
 795struct ssp_ini_io_start_req {
 796        __le32  tag;
 797        __le32  device_id;
 798        __le32  data_len;
 799        __le32  dad_dir_m_tlr;
 800        struct ssp_info_unit    ssp_iu;
 801        __le32  addr_low;       /* dword 12: sgl low for normal I/O. */
 802                                /* epl_descl for encryption I/O */
 803        __le32  addr_high;      /* dword 13: sgl hi for normal I/O */
 804                                /* dpl_descl for encryption I/O */
 805        __le32  len;            /* dword 14: len for normal I/O. */
 806                                /* edpl_desch for encryption I/O */
 807        __le32  esgl;           /* dword 15: ESGL bit for normal I/O. */
 808                                /* user defined tag mask for enc I/O */
 809        /* The below fields are reserved for normal I/O */
 810        u8      udt[12];        /* dword 16-18 */
 811        __le32  sectcnt_ios;    /* dword 19 */
 812        __le32  key_cmode;      /* dword 20 */
 813        __le32  ks_enss;        /* dword 21 */
 814        __le32  keytagl;        /* dword 22 */
 815        __le32  keytagh;        /* dword 23 */
 816        __le32  twk_val0;       /* dword 24 */
 817        __le32  twk_val1;       /* dword 25 */
 818        __le32  twk_val2;       /* dword 26 */
 819        __le32  twk_val3;       /* dword 27 */
 820        __le32  enc_addr_low;   /* dword 28: Encryption sgl addr low */
 821        __le32  enc_addr_high;  /* dword 29: Encryption sgl addr hi */
 822        __le32  enc_len;        /* dword 30: Encryption length */
 823        __le32  enc_esgl;       /* dword 31: ESGL bit for encryption */
 824} __attribute__((packed, aligned(4)));
 825
 826/**
 827 * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
 828 * use to initiate SSP I/O operation with optional DIF/ENC
 829 */
 830struct ssp_dif_enc_io_req {
 831        __le32  tag;
 832        __le32  device_id;
 833        __le32  data_len;
 834        __le32  dirMTlr;
 835        __le32  sspiu0;
 836        __le32  sspiu1;
 837        __le32  sspiu2;
 838        __le32  sspiu3;
 839        __le32  sspiu4;
 840        __le32  sspiu5;
 841        __le32  sspiu6;
 842        __le32  epl_des;
 843        __le32  dpl_desl_ndplr;
 844        __le32  dpl_desh;
 845        __le32  uum_uuv_bss_difbits;
 846        u8      udt[12];
 847        __le32  sectcnt_ios;
 848        __le32  key_cmode;
 849        __le32  ks_enss;
 850        __le32  keytagl;
 851        __le32  keytagh;
 852        __le32  twk_val0;
 853        __le32  twk_val1;
 854        __le32  twk_val2;
 855        __le32  twk_val3;
 856        __le32  addr_low;
 857        __le32  addr_high;
 858        __le32  len;
 859        __le32  esgl;
 860} __attribute__((packed, aligned(4)));
 861
 862/**
 863 * brief the data structure of Firmware download
 864 * use to describe MPI FW DOWNLOAD Command (64 bytes)
 865 */
 866struct fw_flash_Update_req {
 867        __le32  tag;
 868        __le32  cur_image_offset;
 869        __le32  cur_image_len;
 870        __le32  total_image_len;
 871        u32     reserved0[7];
 872        __le32  sgl_addr_lo;
 873        __le32  sgl_addr_hi;
 874        __le32  len;
 875        __le32  ext_reserved;
 876        u32     reserved1[16];
 877} __attribute__((packed, aligned(4)));
 878
 879#define FWFLASH_IOMB_RESERVED_LEN 0x07
 880/**
 881 * brief the data structure of FW_FLASH_UPDATE Response
 882 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
 883 *
 884 */
 885 struct fw_flash_Update_resp {
 886        __le32  tag;
 887        __le32  status;
 888        u32     reserved[13];
 889} __attribute__((packed, aligned(4)));
 890
 891/**
 892 * brief the data structure of Get NVM Data Command
 893 * use to get data from NVM in HBA(64 bytes)
 894 */
 895struct get_nvm_data_req {
 896        __le32  tag;
 897        __le32  len_ir_vpdd;
 898        __le32  vpd_offset;
 899        u32     reserved[8];
 900        __le32  resp_addr_lo;
 901        __le32  resp_addr_hi;
 902        __le32  resp_len;
 903        u32     reserved1[17];
 904} __attribute__((packed, aligned(4)));
 905
 906struct set_nvm_data_req {
 907        __le32  tag;
 908        __le32  len_ir_vpdd;
 909        __le32  vpd_offset;
 910        u32     reserved[8];
 911        __le32  resp_addr_lo;
 912        __le32  resp_addr_hi;
 913        __le32  resp_len;
 914        u32     reserved1[17];
 915} __attribute__((packed, aligned(4)));
 916
 917/**
 918 * brief the data structure for SET CONTROLLER CONFIG COMMAND
 919 * use to modify controller configuration
 920 */
 921struct set_ctrl_cfg_req {
 922        __le32  tag;
 923        __le32  cfg_pg[14];
 924        u32     reserved[16];
 925} __attribute__((packed, aligned(4)));
 926
 927/**
 928 * brief the data structure for GET CONTROLLER CONFIG COMMAND
 929 * use to get controller configuration page
 930 */
 931struct get_ctrl_cfg_req {
 932        __le32  tag;
 933        __le32  pgcd;
 934        __le32  int_vec;
 935        u32     reserved[28];
 936} __attribute__((packed, aligned(4)));
 937
 938/**
 939 * brief the data structure for KEK_MANAGEMENT COMMAND
 940 * use for KEK management
 941 */
 942struct kek_mgmt_req {
 943        __le32  tag;
 944        __le32  new_curidx_ksop;
 945        u32     reserved;
 946        __le32  kblob[12];
 947        u32     reserved1[16];
 948} __attribute__((packed, aligned(4)));
 949
 950/**
 951 * brief the data structure for DEK_MANAGEMENT COMMAND
 952 * use for DEK management
 953 */
 954struct dek_mgmt_req {
 955        __le32  tag;
 956        __le32  kidx_dsop;
 957        __le32  dekidx;
 958        __le32  addr_l;
 959        __le32  addr_h;
 960        __le32  nent;
 961        __le32  dbf_tblsize;
 962        u32     reserved[24];
 963} __attribute__((packed, aligned(4)));
 964
 965/**
 966 * brief the data structure for SET PHY PROFILE COMMAND
 967 * use to retrive phy specific information
 968 */
 969struct set_phy_profile_req {
 970        __le32  tag;
 971        __le32  ppc_phyid;
 972        u32     reserved[29];
 973} __attribute__((packed, aligned(4)));
 974
 975/**
 976 * brief the data structure for GET PHY PROFILE COMMAND
 977 * use to retrive phy specific information
 978 */
 979struct get_phy_profile_req {
 980        __le32  tag;
 981        __le32  ppc_phyid;
 982        __le32  profile[29];
 983} __attribute__((packed, aligned(4)));
 984
 985/**
 986 * brief the data structure for EXT FLASH PARTITION
 987 * use to manage ext flash partition
 988 */
 989struct ext_flash_partition_req {
 990        __le32  tag;
 991        __le32  cmd;
 992        __le32  offset;
 993        __le32  len;
 994        u32     reserved[7];
 995        __le32  addr_low;
 996        __le32  addr_high;
 997        __le32  len1;
 998        __le32  ext;
 999        u32     reserved1[16];
1000} __attribute__((packed, aligned(4)));

1001
1002#define TWI_DEVICE      0x0
1003#define C_SEEPROM       0x1
1004#define VPD_FLASH       0x4
1005#define AAP1_RDUMP      0x5
1006#define IOP_RDUMP       0x6
1007#define EXPAN_ROM       0x7
1008
1009#define IPMode          0x80000000
1010#define NVMD_TYPE       0x0000000F
1011#define NVMD_STAT       0x0000FFFF
1012#define NVMD_LEN        0xFF000000
1013/**
1014 * brief the data structure of Get NVMD Data Response
1015 * use to describe MPI Get NVMD Data Response (64 bytes)
1016 */
1017struct get_nvm_data_resp {
1018        __le32          tag;
1019        __le32          ir_tda_bn_dps_das_nvm;
1020        __le32          dlen_status;
1021        __le32          nvm_data[12];
1022} __attribute__((packed, aligned(4)));
1023
1024/**
1025 * brief the data structure of SAS Diagnostic Start/End Response
1026 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
1027 *
1028 */
1029struct sas_diag_start_end_resp {
1030        __le32          tag;
1031        __le32          status;
1032        u32             reserved[13];
1033} __attribute__((packed, aligned(4)));
1034
1035/**
1036 * brief the data structure of SAS Diagnostic Execute Response
1037 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
1038 *
1039 */
1040struct sas_diag_execute_resp {
1041        __le32          tag;
1042        __le32          cmdtype_cmddesc_phyid;
1043        __le32          Status;
1044        __le32          ReportData;
1045        u32             reserved[11];
1046} __attribute__((packed, aligned(4)));
1047
1048/**
1049 * brief the data structure of Set Device State Response
1050 * use to describe MPI Set Device State Response (64 bytes)
1051 *
1052 */
1053struct set_dev_state_resp {
1054        __le32          tag;
1055        __le32          status;
1056        __le32          device_id;
1057        __le32          pds_nds;
1058        u32             reserved[11];
1059} __attribute__((packed, aligned(4)));
1060
1061/* new outbound structure for spcv - begins */
1062/**
1063 * brief the data structure for SET CONTROLLER CONFIG COMMAND
1064 * use to modify controller configuration
1065 */
1066struct set_ctrl_cfg_resp {
1067        __le32 tag;
1068        __le32 status;
1069        __le32 err_qlfr_pgcd;
1070        u32 reserved[12];
1071} __attribute__((packed, aligned(4)));
1072
1073struct get_ctrl_cfg_resp {
1074        __le32 tag;
1075        __le32 status;
1076        __le32 err_qlfr;
1077        __le32 confg_page[12];
1078} __attribute__((packed, aligned(4)));
1079
1080struct kek_mgmt_resp {
1081        __le32 tag;
1082        __le32 status;
1083        __le32 kidx_new_curr_ksop;
1084        __le32 err_qlfr;
1085        u32 reserved[11];
1086} __attribute__((packed, aligned(4)));
1087
1088struct dek_mgmt_resp {
1089        __le32 tag;
1090        __le32 status;
1091        __le32 kekidx_tbls_dsop;
1092        __le32 dekidx;
1093        __le32 err_qlfr;
1094        u32 reserved[10];
1095} __attribute__((packed, aligned(4)));
1096
1097struct get_phy_profile_resp {
1098        __le32 tag;
1099        __le32 status;
1100        __le32 ppc_phyid;
1101        __le32 ppc_specific_rsp[12];
1102} __attribute__((packed, aligned(4)));
1103
1104struct flash_op_ext_resp {
1105        __le32 tag;
1106        __le32 cmd;
1107        __le32 status;
1108        __le32 epart_size;
1109        __le32 epart_sect_size;
1110        u32 reserved[10];
1111} __attribute__((packed, aligned(4)));
1112
1113struct set_phy_profile_resp {
1114        __le32 tag;
1115        __le32 status;
1116        __le32 ppc_phyid;
1117        __le32 ppc_specific_rsp[12];
1118} __attribute__((packed, aligned(4)));
1119
1120struct ssp_coalesced_comp_resp {
1121        __le32 coal_cnt;
1122        __le32 tag0;
1123        __le32 ssp_tag0;
1124        __le32 tag1;
1125        __le32 ssp_tag1;
1126        __le32 add_tag_ssp_tag[10];
1127} __attribute__((packed, aligned(4)));
1128
1129/* new outbound structure for spcv - ends */
1130
1131/* brief data structure for SAS protocol timer configuration page.
1132 *
1133 */
1134struct SASProtocolTimerConfig {
1135        __le32 pageCode;                        /* 0 */
1136        __le32 MST_MSI;                         /* 1 */
1137        __le32 STP_SSP_MCT_TMO;                 /* 2 */
1138        __le32 STP_FRM_TMO;                     /* 3 */
1139        __le32 STP_IDLE_TMO;                    /* 4 */
1140        __le32 OPNRJT_RTRY_INTVL;               /* 5 */
1141        __le32 Data_Cmd_OPNRJT_RTRY_TMO;        /* 6 */
1142        __le32 Data_Cmd_OPNRJT_RTRY_THR;        /* 7 */
1143        __le32 MAX_AIP;                         /* 8 */
1144} __attribute__((packed, aligned(4)));
1145
1146typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1147
1148#define NDS_BITS 0x0F
1149#define PDS_BITS 0xF0
1150
1151/*
1152 * HW Events type
1153 */
1154
1155#define HW_EVENT_RESET_START                    0x01
1156#define HW_EVENT_CHIP_RESET_COMPLETE            0x02
1157#define HW_EVENT_PHY_STOP_STATUS                0x03
1158#define HW_EVENT_SAS_PHY_UP                     0x04
1159#define HW_EVENT_SATA_PHY_UP                    0x05
1160#define HW_EVENT_SATA_SPINUP_HOLD               0x06
1161#define HW_EVENT_PHY_DOWN                       0x07
1162#define HW_EVENT_PORT_INVALID                   0x08
1163#define HW_EVENT_BROADCAST_CHANGE               0x09
1164#define HW_EVENT_PHY_ERROR                      0x0A
1165#define HW_EVENT_BROADCAST_SES                  0x0B
1166#define HW_EVENT_INBOUND_CRC_ERROR              0x0C
1167#define HW_EVENT_HARD_RESET_RECEIVED            0x0D
1168#define HW_EVENT_MALFUNCTION                    0x0E
1169#define HW_EVENT_ID_FRAME_TIMEOUT               0x0F
1170#define HW_EVENT_BROADCAST_EXP                  0x10
1171#define HW_EVENT_PHY_START_STATUS               0x11
1172#define HW_EVENT_LINK_ERR_INVALID_DWORD         0x12
1173#define HW_EVENT_LINK_ERR_DISPARITY_ERROR       0x13
1174#define HW_EVENT_LINK_ERR_CODE_VIOLATION        0x14
1175#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH   0x15
1176#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED      0x16
1177#define HW_EVENT_PORT_RECOVERY_TIMER_TMO        0x17
1178#define HW_EVENT_PORT_RECOVER                   0x18
1179#define HW_EVENT_PORT_RESET_TIMER_TMO           0x19
1180#define HW_EVENT_PORT_RESET_COMPLETE            0x20
1181#define EVENT_BROADCAST_ASYNCH_EVENT            0x21
1182
1183/* port state */
1184#define PORT_NOT_ESTABLISHED                    0x00
1185#define PORT_VALID                              0x01
1186#define PORT_LOSTCOMM                           0x02
1187#define PORT_IN_RESET                           0x04
1188#define PORT_3RD_PARTY_RESET                    0x07
1189#define PORT_INVALID                            0x08
1190
1191/*
1192 * SSP/SMP/SATA IO Completion Status values
1193 */
1194
1195#define IO_SUCCESS                              0x00
1196#define IO_ABORTED                              0x01
1197#define IO_OVERFLOW                             0x02
1198#define IO_UNDERFLOW                            0x03
1199#define IO_FAILED                               0x04
1200#define IO_ABORT_RESET                          0x05
1201#define IO_NOT_VALID                            0x06
1202#define IO_NO_DEVICE                            0x07
1203#define IO_ILLEGAL_PARAMETER                    0x08
1204#define IO_LINK_FAILURE                         0x09
1205#define IO_PROG_ERROR                           0x0A
1206
1207#define IO_EDC_IN_ERROR                         0x0B
1208#define IO_EDC_OUT_ERROR                        0x0C
1209#define IO_ERROR_HW_TIMEOUT                     0x0D
1210#define IO_XFER_ERROR_BREAK                     0x0E
1211#define IO_XFER_ERROR_PHY_NOT_READY             0x0F
1212#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED        0x10
1213#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION                0x11
1214#define IO_OPEN_CNX_ERROR_BREAK                         0x12
1215#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS                 0x13
1216#define IO_OPEN_CNX_ERROR_BAD_DESTINATION               0x14
1217#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1218#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY            0x16
1219#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION             0x17
1220/* This error code 0x18 is not used on SPCv */
1221#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR                 0x18
1222#define IO_XFER_ERROR_NAK_RECEIVED                      0x19
1223#define IO_XFER_ERROR_ACK_NAK_TIMEOUT                   0x1A
1224#define IO_XFER_ERROR_PEER_ABORTED                      0x1B
1225#define IO_XFER_ERROR_RX_FRAME                          0x1C
1226#define IO_XFER_ERROR_DMA                               0x1D
1227#define IO_XFER_ERROR_CREDIT_TIMEOUT                    0x1E
1228#define IO_XFER_ERROR_SATA_LINK_TIMEOUT                 0x1F
1229#define IO_XFER_ERROR_SATA                              0x20
1230
1231/* This error code 0x22 is not used on SPCv */
1232#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST               0x22
1233#define IO_XFER_ERROR_REJECTED_NCQ_MODE                 0x21
1234#define IO_XFER_ERROR_ABORTED_NCQ_MODE                  0x23
1235#define IO_XFER_OPEN_RETRY_TIMEOUT                      0x24
1236/* This error code 0x25 is not used on SPCv */
1237#define IO_XFER_SMP_RESP_CONNECTION_ERROR               0x25
1238#define IO_XFER_ERROR_UNEXPECTED_PHASE                  0x26
1239#define IO_XFER_ERROR_XFER_RDY_OVERRUN                  0x27
1240#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED             0x28
1241#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT         0x30
1242
1243/* The following error code 0x31 and 0x32 are not using (obsolete) */
1244#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK    0x31
1245#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1246
1247#define IO_XFER_ERROR_OFFSET_MISMATCH                   0x34
1248#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN                0x35
1249#define IO_XFER_CMD_FRAME_ISSUED                        0x36
1250#define IO_ERROR_INTERNAL_SMP_RESOURCE                  0x37
1251#define IO_PORT_IN_RESET                                0x38
1252#define IO_DS_NON_OPERATIONAL                           0x39
1253#define IO_DS_IN_RECOVERY                               0x3A
1254#define IO_TM_TAG_NOT_FOUND                             0x3B
1255#define IO_XFER_PIO_SETUP_ERROR                         0x3C
1256#define IO_SSP_EXT_IU_ZERO_LEN_ERROR                    0x3D
1257#define IO_DS_IN_ERROR                                  0x3E
1258#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY              0x3F
1259#define IO_ABORT_IN_PROGRESS                            0x40
1260#define IO_ABORT_DELAYED                                0x41
1261#define IO_INVALID_LENGTH                               0x42
1262
1263/********** additional response event values *****************/
1264
1265#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT          0x43
1266#define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED    0x44
1267#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO        0x45
1268#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST         0x46
1269#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE    0x47
1270#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1271#define IO_DS_INVALID                                   0x49
1272/* WARNING: the value is not contiguous from here */
1273#define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR     0x52
1274#define IO_XFER_DMA_ACTIVATE_TIMEOUT            0x53
1275#define IO_XFER_ERROR_INTERNAL_CRC_ERROR        0x54
1276#define MPI_IO_RQE_BUSY_FULL                    0x55
1277#define IO_XFER_ERR_EOB_DATA_OVERRUN            0x56
1278#define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME     0x57
1279#define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED        0x58
1280
1281#define MPI_ERR_IO_RESOURCE_UNAVAILABLE         0x1004
1282#define MPI_ERR_ATAPI_DEVICE_BUSY               0x1024
1283
1284#define IO_XFR_ERROR_DEK_KEY_CACHE_MISS         0x2040
1285/*
1286 * An encryption IO request failed due to DEK Key Tag mismatch.
1287 * The key tag supplied in the encryption IOMB does not match with
1288 * the Key Tag in the referenced DEK Entry.
1289 */
1290#define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH       0x2041
1291#define IO_XFR_ERROR_CIPHER_MODE_INVALID        0x2042
1292/*
1293 * An encryption I/O request failed because the initial value (IV)
1294 * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1295 */
1296#define IO_XFR_ERROR_DEK_IV_MISMATCH            0x2043
1297/* An encryption I/O request failed due to an internal RAM ECC or
1298 * interface error while unwrapping the DEK. */
1299#define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR    0x2044
1300/* An encryption I/O request failed due to an internal RAM ECC or
1301 * interface error while unwrapping the DEK. */
1302#define IO_XFR_ERROR_INTERNAL_RAM               0x2045
1303/*
1304 * An encryption I/O request failed
1305 * because the DEK index specified in the I/O was outside the bounds of
1306 * the total number of entries in the host DEK table.
1307 */
1308#define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1309
1310/* define DIF IO response error status code */
1311#define IO_XFR_ERROR_DIF_MISMATCH                       0x3000
1312#define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH       0x3001
1313#define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH         0x3002
1314#define IO_XFR_ERROR_DIF_CRC_MISMATCH                   0x3003
1315
1316/* define operator management response status and error qualifier code */
1317#define OPR_MGMT_OP_NOT_SUPPORTED                       0x2060
1318#define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL          0x2061
1319#define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND           0x2062
1320#define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH         0x2063
1321#define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED       0x2064
1322#define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL            0x2022
1323#define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE    0x2023
1324/***************** additional response event values ***************/
1325
1326/* WARNING: This error code must always be the last number.
1327 * If you add error code, modify this code also
1328 * It is used as an index
1329 */
1330#define IO_ERROR_UNKNOWN_GENERIC                        0x2023
1331
1332/* MSGU CONFIGURATION TABLE*/
1333
1334#define SPCv_MSGU_CFG_TABLE_UPDATE              0x001
1335#define SPCv_MSGU_CFG_TABLE_RESET               0x002
1336#define SPCv_MSGU_CFG_TABLE_FREEZE              0x004
1337#define SPCv_MSGU_CFG_TABLE_UNFREEZE            0x008
1338#define MSGU_IBDB_SET                           0x00
1339#define MSGU_HOST_INT_STATUS                    0x08
1340#define MSGU_HOST_INT_MASK                      0x0C
1341#define MSGU_IOPIB_INT_STATUS                   0x18
1342#define MSGU_IOPIB_INT_MASK                     0x1C
1343#define MSGU_IBDB_CLEAR                         0x20
1344
1345#define MSGU_MSGU_CONTROL                       0x24
1346#define MSGU_ODR                                0x20
1347#define MSGU_ODCR                               0x28
1348
1349#define MSGU_ODMR                               0x30
1350#define MSGU_ODMR_U                             0x34
1351#define MSGU_ODMR_CLR                           0x38
1352#define MSGU_ODMR_CLR_U                         0x3C
1353#define MSGU_OD_RSVD                            0x40
1354
1355#define MSGU_SCRATCH_PAD_0                      0x44
1356#define MSGU_SCRATCH_PAD_1                      0x48
1357#define MSGU_SCRATCH_PAD_2                      0x4C
1358#define MSGU_SCRATCH_PAD_3                      0x50
1359#define MSGU_HOST_SCRATCH_PAD_0                 0x54
1360#define MSGU_HOST_SCRATCH_PAD_1                 0x58
1361#define MSGU_HOST_SCRATCH_PAD_2                 0x5C
1362#define MSGU_HOST_SCRATCH_PAD_3                 0x60
1363#define MSGU_HOST_SCRATCH_PAD_4                 0x64
1364#define MSGU_HOST_SCRATCH_PAD_5                 0x68
1365#define MSGU_HOST_SCRATCH_PAD_6                 0x6C
1366#define MSGU_HOST_SCRATCH_PAD_7                 0x70
1367
1368/* bit definition for ODMR register */
1369#define ODMR_MASK_ALL                   0xFFFFFFFF/* mask all
1370                                        interrupt vector */
1371#define ODMR_CLEAR_ALL                  0       /* clear all
1372                                        interrupt vector */
1373/* bit definition for ODCR register */
1374#define ODCR_CLEAR_ALL                  0xFFFFFFFF /* mask all
1375                                        interrupt vector*/
1376/* MSIX Interupts */
1377#define MSIX_TABLE_OFFSET               0x2000
1378#define MSIX_TABLE_ELEMENT_SIZE         0x10
1379#define MSIX_INTERRUPT_CONTROL_OFFSET   0xC
1380#define MSIX_TABLE_BASE                 (MSIX_TABLE_OFFSET + \
1381                                        MSIX_INTERRUPT_CONTROL_OFFSET)
1382#define MSIX_INTERRUPT_DISABLE          0x1
1383#define MSIX_INTERRUPT_ENABLE           0x0
1384
1385/* state definition for Scratch Pad1 register */
1386#define SCRATCH_PAD_RAAE_READY          0x3
1387#define SCRATCH_PAD_ILA_READY           0xC
1388#define SCRATCH_PAD_BOOT_LOAD_SUCCESS   0x0
1389#define SCRATCH_PAD_IOP0_READY          0xC00
1390#define SCRATCH_PAD_IOP1_READY          0x3000
1391#define SCRATCH_PAD_MIPSALL_READY       (SCRATCH_PAD_IOP1_READY | \
1392                                        SCRATCH_PAD_IOP0_READY | \
1393                                        SCRATCH_PAD_RAAE_READY)
1394
1395/* boot loader state */
1396#define SCRATCH_PAD1_BOOTSTATE_MASK             0x70    /* Bit 4-6 */
1397#define SCRATCH_PAD1_BOOTSTATE_SUCESS           0x0     /* Load successful */
1398#define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM      0x10    /* HDA SEEPROM */
1399#define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP    0x20    /* HDA BootStrap Pins */
1400#define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET    0x30    /* HDA Soft Reset */
1401#define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR       0x40    /* HDA critical error */
1402#define SCRATCH_PAD1_BOOTSTATE_R1               0x50    /* Reserved */
1403#define SCRATCH_PAD1_BOOTSTATE_R2               0x60    /* Reserved */
1404#define SCRATCH_PAD1_BOOTSTATE_FATAL            0x70    /* Fatal Error */
1405
1406 /* state definition for Scratch Pad2 register */
1407#define SCRATCH_PAD2_POR                0x00    /* power on state */
1408#define SCRATCH_PAD2_SFR                0x01    /* soft reset state */
1409#define SCRATCH_PAD2_ERR                0x02    /* error state */
1410#define SCRATCH_PAD2_RDY                0x03    /* ready state */
1411#define SCRATCH_PAD2_FWRDY_RST          0x04    /* FW rdy for soft reset flag */
1412#define SCRATCH_PAD2_IOPRDY_RST         0x08    /* IOP ready for soft reset */
1413#define SCRATCH_PAD2_STATE_MASK         0xFFFFFFF4 /* ScratchPad 2
1414 Mask, bit1-0 State */
1415#define SCRATCH_PAD2_RESERVED           0x000003FC/* Scratch Pad1
1416 Reserved bit 2 to 9 */
1417
1418#define SCRATCH_PAD_ERROR_MASK          0xFFFFFC00 /* Error mask bits */
1419#define SCRATCH_PAD_STATE_MASK          0x00000003 /* State Mask bits */
1420
1421/* main configuration offset - byte offset */
1422#define MAIN_SIGNATURE_OFFSET           0x00 /* DWORD 0x00 */
1423#define MAIN_INTERFACE_REVISION         0x04 /* DWORD 0x01 */
1424#define MAIN_FW_REVISION                0x08 /* DWORD 0x02 */
1425#define MAIN_MAX_OUTSTANDING_IO_OFFSET  0x0C /* DWORD 0x03 */
1426#define MAIN_MAX_SGL_OFFSET             0x10 /* DWORD 0x04 */
1427#define MAIN_CNTRL_CAP_OFFSET           0x14 /* DWORD 0x05 */
1428#define MAIN_GST_OFFSET                 0x18 /* DWORD 0x06 */
1429#define MAIN_IBQ_OFFSET                 0x1C /* DWORD 0x07 */
1430#define MAIN_OBQ_OFFSET                 0x20 /* DWORD 0x08 */
1431#define MAIN_IQNPPD_HPPD_OFFSET         0x24 /* DWORD 0x09 */
1432
1433/* 0x28 - 0x4C - RSVD */
1434#define MAIN_EVENT_CRC_CHECK            0x48 /* DWORD 0x12 */
1435#define MAIN_EVENT_LOG_ADDR_HI          0x50 /* DWORD 0x14 */
1436#define MAIN_EVENT_LOG_ADDR_LO          0x54 /* DWORD 0x15 */
1437#define MAIN_EVENT_LOG_BUFF_SIZE        0x58 /* DWORD 0x16 */
1438#define MAIN_EVENT_LOG_OPTION           0x5C /* DWORD 0x17 */
1439#define MAIN_PCS_EVENT_LOG_ADDR_HI      0x60 /* DWORD 0x18 */
1440#define MAIN_PCS_EVENT_LOG_ADDR_LO      0x64 /* DWORD 0x19 */
1441#define MAIN_PCS_EVENT_LOG_BUFF_SIZE    0x68 /* DWORD 0x1A */
1442#define MAIN_PCS_EVENT_LOG_OPTION       0x6C /* DWORD 0x1B */
1443#define MAIN_FATAL_ERROR_INTERRUPT      0x70 /* DWORD 0x1C */
1444#define MAIN_FATAL_ERROR_RDUMP0_OFFSET  0x74 /* DWORD 0x1D */
1445#define MAIN_FATAL_ERROR_RDUMP0_LENGTH  0x78 /* DWORD 0x1E */
1446#define MAIN_FATAL_ERROR_RDUMP1_OFFSET  0x7C /* DWORD 0x1F */
1447#define MAIN_FATAL_ERROR_RDUMP1_LENGTH  0x80 /* DWORD 0x20 */
1448#define MAIN_GPIO_LED_FLAGS_OFFSET      0x84 /* DWORD 0x21 */
1449#define MAIN_ANALOG_SETUP_OFFSET        0x88 /* DWORD 0x22 */
1450
1451#define MAIN_INT_VECTOR_TABLE_OFFSET    0x8C /* DWORD 0x23 */
1452#define MAIN_SAS_PHY_ATTR_TABLE_OFFSET  0x90 /* DWORD 0x24 */
1453#define MAIN_PORT_RECOVERY_TIMER        0x94 /* DWORD 0x25 */
1454#define MAIN_INT_REASSERTION_DELAY      0x98 /* DWORD 0x26 */
1455#define MAIN_MPI_ILA_RELEASE_TYPE       0xA4 /* DWORD 0x29 */
1456#define MAIN_MPI_INACTIVE_FW_VERSION    0XB0 /* DWORD 0x2C */
1457
1458/* Gereral Status Table offset - byte offset */
1459#define GST_GSTLEN_MPIS_OFFSET          0x00
1460#define GST_IQ_FREEZE_STATE0_OFFSET     0x04
1461#define GST_IQ_FREEZE_STATE1_OFFSET     0x08
1462#define GST_MSGUTCNT_OFFSET             0x0C
1463#define GST_IOPTCNT_OFFSET              0x10
1464/* 0x14 - 0x34 - RSVD */
1465#define GST_GPIO_INPUT_VAL              0x38
1466/* 0x3c - 0x40 - RSVD */
1467#define GST_RERRINFO_OFFSET0            0x44
1468#define GST_RERRINFO_OFFSET1            0x48
1469#define GST_RERRINFO_OFFSET2            0x4c
1470#define GST_RERRINFO_OFFSET3            0x50
1471#define GST_RERRINFO_OFFSET4            0x54
1472#define GST_RERRINFO_OFFSET5            0x58
1473#define GST_RERRINFO_OFFSET6            0x5c
1474#define GST_RERRINFO_OFFSET7            0x60
1475
1476/* General Status Table - MPI state */
1477#define GST_MPI_STATE_UNINIT            0x00
1478#define GST_MPI_STATE_INIT              0x01
1479#define GST_MPI_STATE_TERMINATION       0x02
1480#define GST_MPI_STATE_ERROR             0x03
1481#define GST_MPI_STATE_MASK              0x07
1482
1483/* Per SAS PHY Attributes */
1484
1485#define PSPA_PHYSTATE0_OFFSET           0x00 /* Dword V */
1486#define PSPA_OB_HW_EVENT_PID0_OFFSET    0x04 /* DWORD V+1 */
1487#define PSPA_PHYSTATE1_OFFSET           0x08 /* Dword V+2 */
1488#define PSPA_OB_HW_EVENT_PID1_OFFSET    0x0C /* DWORD V+3 */
1489#define PSPA_PHYSTATE2_OFFSET           0x10 /* Dword V+4 */
1490#define PSPA_OB_HW_EVENT_PID2_OFFSET    0x14 /* DWORD V+5 */
1491#define PSPA_PHYSTATE3_OFFSET           0x18 /* Dword V+6 */
1492#define PSPA_OB_HW_EVENT_PID3_OFFSET    0x1C /* DWORD V+7 */
1493#define PSPA_PHYSTATE4_OFFSET           0x20 /* Dword V+8 */
1494#define PSPA_OB_HW_EVENT_PID4_OFFSET    0x24 /* DWORD V+9 */
1495#define PSPA_PHYSTATE5_OFFSET           0x28 /* Dword V+10 */
1496#define PSPA_OB_HW_EVENT_PID5_OFFSET    0x2C /* DWORD V+11 */
1497#define PSPA_PHYSTATE6_OFFSET           0x30 /* Dword V+12 */
1498#define PSPA_OB_HW_EVENT_PID6_OFFSET    0x34 /* DWORD V+13 */
1499#define PSPA_PHYSTATE7_OFFSET           0x38 /* Dword V+14 */
1500#define PSPA_OB_HW_EVENT_PID7_OFFSET    0x3C /* DWORD V+15 */
1501#define PSPA_PHYSTATE8_OFFSET           0x40 /* DWORD V+16 */
1502#define PSPA_OB_HW_EVENT_PID8_OFFSET    0x44 /* DWORD V+17 */
1503#define PSPA_PHYSTATE9_OFFSET           0x48 /* DWORD V+18 */
1504#define PSPA_OB_HW_EVENT_PID9_OFFSET    0x4C /* DWORD V+19 */
1505#define PSPA_PHYSTATE10_OFFSET          0x50 /* DWORD V+20 */
1506#define PSPA_OB_HW_EVENT_PID10_OFFSET   0x54 /* DWORD V+21 */
1507#define PSPA_PHYSTATE11_OFFSET          0x58 /* DWORD V+22 */
1508#define PSPA_OB_HW_EVENT_PID11_OFFSET   0x5C /* DWORD V+23 */
1509#define PSPA_PHYSTATE12_OFFSET          0x60 /* DWORD V+24 */
1510#define PSPA_OB_HW_EVENT_PID12_OFFSET   0x64 /* DWORD V+25 */
1511#define PSPA_PHYSTATE13_OFFSET          0x68 /* DWORD V+26 */
1512#define PSPA_OB_HW_EVENT_PID13_OFFSET   0x6c /* DWORD V+27 */
1513#define PSPA_PHYSTATE14_OFFSET          0x70 /* DWORD V+28 */
1514#define PSPA_OB_HW_EVENT_PID14_OFFSET   0x74 /* DWORD V+29 */
1515#define PSPA_PHYSTATE15_OFFSET          0x78 /* DWORD V+30 */
1516#define PSPA_OB_HW_EVENT_PID15_OFFSET   0x7c /* DWORD V+31 */
1517/* end PSPA */
1518
1519/* inbound queue configuration offset - byte offset */
1520#define IB_PROPERITY_OFFSET             0x00
1521#define IB_BASE_ADDR_HI_OFFSET          0x04
1522#define IB_BASE_ADDR_LO_OFFSET          0x08
1523#define IB_CI_BASE_ADDR_HI_OFFSET       0x0C
1524#define IB_CI_BASE_ADDR_LO_OFFSET       0x10
1525#define IB_PIPCI_BAR                    0x14
1526#define IB_PIPCI_BAR_OFFSET             0x18
1527#define IB_RESERVED_OFFSET              0x1C
1528
1529/* outbound queue configuration offset - byte offset */
1530#define OB_PROPERITY_OFFSET             0x00
1531#define OB_BASE_ADDR_HI_OFFSET          0x04
1532#define OB_BASE_ADDR_LO_OFFSET          0x08
1533#define OB_PI_BASE_ADDR_HI_OFFSET       0x0C
1534#define OB_PI_BASE_ADDR_LO_OFFSET       0x10
1535#define OB_CIPCI_BAR                    0x14
1536#define OB_CIPCI_BAR_OFFSET             0x18
1537#define OB_INTERRUPT_COALES_OFFSET      0x1C
1538#define OB_DYNAMIC_COALES_OFFSET        0x20
1539#define OB_PROPERTY_INT_ENABLE          0x40000000
1540
1541#define MBIC_NMI_ENABLE_VPE0_IOP        0x000418
1542#define MBIC_NMI_ENABLE_VPE0_AAP1       0x000418
1543/* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1544#define PCIE_EVENT_INTERRUPT_ENABLE     0x003040
1545#define PCIE_EVENT_INTERRUPT            0x003044
1546#define PCIE_ERROR_INTERRUPT_ENABLE     0x003048
1547#define PCIE_ERROR_INTERRUPT            0x00304C
1548
1549/* SPCV soft reset */
1550#define SPC_REG_SOFT_RESET 0x00001000
1551#define SPCv_NORMAL_RESET_VALUE         0x1
1552
1553#define SPCv_SOFT_RESET_READ_MASK               0xC0
1554#define SPCv_SOFT_RESET_NO_RESET                0x0
1555#define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED    0x40
1556#define SPCv_SOFT_RESET_HDA_MODE_OCCURED        0x80
1557#define SPCv_SOFT_RESET_CHIP_RESET_OCCURED      0xC0
1558
1559/* signature definition for host scratch pad0 register */
1560#define SPC_SOFT_RESET_SIGNATURE        0x252acbcd
1561/* Signature for Soft Reset */
1562
1563/* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1564#define SPC_REG_RESET                   0x000000/* reset register */
1565
1566/* bit definition for SPC_RESET register */
1567#define SPC_REG_RESET_OSSP              0x00000001
1568#define SPC_REG_RESET_RAAE              0x00000002
1569#define SPC_REG_RESET_PCS_SPBC          0x00000004
1570#define SPC_REG_RESET_PCS_IOP_SS        0x00000008
1571#define SPC_REG_RESET_PCS_AAP1_SS       0x00000010
1572#define SPC_REG_RESET_PCS_AAP2_SS       0x00000020
1573#define SPC_REG_RESET_PCS_LM            0x00000040
1574#define SPC_REG_RESET_PCS               0x00000080
1575#define SPC_REG_RESET_GSM               0x00000100
1576#define SPC_REG_RESET_DDR2              0x00010000
1577#define SPC_REG_RESET_BDMA_CORE         0x00020000
1578#define SPC_REG_RESET_BDMA_SXCBI        0x00040000
1579#define SPC_REG_RESET_PCIE_AL_SXCBI     0x00080000
1580#define SPC_REG_RESET_PCIE_PWR          0x00100000
1581#define SPC_REG_RESET_PCIE_SFT          0x00200000
1582#define SPC_REG_RESET_PCS_SXCBI         0x00400000
1583#define SPC_REG_RESET_LMS_SXCBI         0x00800000
1584#define SPC_REG_RESET_PMIC_SXCBI        0x01000000
1585#define SPC_REG_RESET_PMIC_CORE         0x02000000
1586#define SPC_REG_RESET_PCIE_PC_SXCBI     0x04000000
1587#define SPC_REG_RESET_DEVICE            0x80000000
1588
1589/* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1590#define SPCV_IBW_AXI_TRANSLATION_LOW    0x001010
1591
1592#define MBIC_AAP1_ADDR_BASE             0x060000
1593#define MBIC_IOP_ADDR_BASE              0x070000
1594#define GSM_ADDR_BASE                   0x0700000
1595/* Dynamic map through Bar4 - 0x00700000 */
1596#define GSM_CONFIG_RESET                0x00000000
1597#define RAM_ECC_DB_ERR                  0x00000018
1598#define GSM_READ_ADDR_PARITY_INDIC      0x00000058
1599#define GSM_WRITE_ADDR_PARITY_INDIC     0x00000060
1600#define GSM_WRITE_DATA_PARITY_INDIC     0x00000068
1601#define GSM_READ_ADDR_PARITY_CHECK      0x00000038
1602#define GSM_WRITE_ADDR_PARITY_CHECK     0x00000040
1603#define GSM_WRITE_DATA_PARITY_CHECK     0x00000048
1604
1605#define RB6_ACCESS_REG                  0x6A0000
1606#define HDAC_EXEC_CMD                   0x0002
1607#define HDA_C_PA                        0xcb
1608#define HDA_SEQ_ID_BITS                 0x00ff0000
1609#define HDA_GSM_OFFSET_BITS             0x00FFFFFF
1610#define HDA_GSM_CMD_OFFSET_BITS         0x42C0
1611#define HDA_GSM_RSP_OFFSET_BITS         0x42E0
1612
1613#define MBIC_AAP1_ADDR_BASE             0x060000
1614#define MBIC_IOP_ADDR_BASE              0x070000
1615#define GSM_ADDR_BASE                   0x0700000
1616#define SPC_TOP_LEVEL_ADDR_BASE         0x000000
1617#define GSM_CONFIG_RESET_VALUE          0x00003b00
1618#define GPIO_ADDR_BASE                  0x00090000
1619#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET   0x0000010c
1620
1621/* RB6 offset */
1622#define SPC_RB6_OFFSET                  0x80C0
1623/* Magic number of soft reset for RB6 */
1624#define RB6_MAGIC_NUMBER_RST            0x1234
1625
1626/* Device Register status */
1627#define DEVREG_SUCCESS                                  0x00
1628#define DEVREG_FAILURE_OUT_OF_RESOURCE                  0x01
1629#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED        0x02
1630#define DEVREG_FAILURE_INVALID_PHY_ID                   0x03
1631#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED        0x04
1632#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE             0x05
1633#define DEVREG_FAILURE_PORT_NOT_VALID_STATE             0x06
1634#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID            0x07
1635
1636
1637#define MEMBASE_II_SHIFT_REGISTER       0x1010
1638#endif
1639
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