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5
6
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
23#include <linux/interrupt.h>
24#include <linux/workqueue.h>
25#include <linux/firmware.h>
26#include <linux/aer.h>
27#include <linux/mutex.h>
28#include <linux/btree.h>
29
30#include <scsi/scsi.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_transport_fc.h>
35#include <scsi/scsi_bsg_fc.h>
36
37#include "qla_bsg.h"
38#include "qla_dsd.h"
39#include "qla_nx.h"
40#include "qla_nx2.h"
41#include "qla_nvme.h"
42#define QLA2XXX_DRIVER_NAME "qla2xxx"
43#define QLA2XXX_APIDEV "ql2xapidev"
44#define QLA2XXX_MANUFACTURER "QLogic Corporation"
45
46
47
48
49
50
51#define MAILBOX_REGISTER_COUNT_2100 8
52#define MAILBOX_REGISTER_COUNT_2200 24
53#define MAILBOX_REGISTER_COUNT 32
54
55#define QLA2200A_RISC_ROM_VER 4
56#define FPM_2300 6
57#define FPM_2310 7
58
59#include "qla_settings.h"
60
61#define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
62
63
64
65
66#define BIT_0 0x1
67#define BIT_1 0x2
68#define BIT_2 0x4
69#define BIT_3 0x8
70#define BIT_4 0x10
71#define BIT_5 0x20
72#define BIT_6 0x40
73#define BIT_7 0x80
74#define BIT_8 0x100
75#define BIT_9 0x200
76#define BIT_10 0x400
77#define BIT_11 0x800
78#define BIT_12 0x1000
79#define BIT_13 0x2000
80#define BIT_14 0x4000
81#define BIT_15 0x8000
82#define BIT_16 0x10000
83#define BIT_17 0x20000
84#define BIT_18 0x40000
85#define BIT_19 0x80000
86#define BIT_20 0x100000
87#define BIT_21 0x200000
88#define BIT_22 0x400000
89#define BIT_23 0x800000
90#define BIT_24 0x1000000
91#define BIT_25 0x2000000
92#define BIT_26 0x4000000
93#define BIT_27 0x8000000
94#define BIT_28 0x10000000
95#define BIT_29 0x20000000
96#define BIT_30 0x40000000
97#define BIT_31 0x80000000
98
99#define LSB(x) ((uint8_t)(x))
100#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
101
102#define LSW(x) ((uint16_t)(x))
103#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
104
105#define LSD(x) ((uint32_t)((uint64_t)(x)))
106#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
107
108#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
109
110
111
112
113
114#define RD_REG_BYTE(addr) readb(addr)
115#define RD_REG_WORD(addr) readw(addr)
116#define RD_REG_DWORD(addr) readl(addr)
117#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
118#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
119#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
120#define WRT_REG_BYTE(addr, data) writeb(data,addr)
121#define WRT_REG_WORD(addr, data) writew(data,addr)
122#define WRT_REG_DWORD(addr, data) writel(data,addr)
123
124
125
126
127#define QLA83XX_LED_PORT0 0x00201320
128#define QLA83XX_LED_PORT1 0x00201328
129#define QLA83XX_IDC_DEV_STATE 0x22102384
130#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
131#define QLA83XX_IDC_MINOR_VERSION 0x22102398
132#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
133#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
134#define QLA83XX_IDC_CONTROL 0x22102390
135#define QLA83XX_IDC_AUDIT 0x22102394
136#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
137#define QLA83XX_DRIVER_LOCKID 0x22102104
138#define QLA83XX_DRIVER_LOCK 0x8111c028
139#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
140#define QLA83XX_FLASH_LOCKID 0x22102100
141#define QLA83XX_FLASH_LOCK 0x8111c010
142#define QLA83XX_FLASH_UNLOCK 0x8111c014
143#define QLA83XX_DEV_PARTINFO1 0x221023e0
144#define QLA83XX_DEV_PARTINFO2 0x221023e4
145#define QLA83XX_FW_HEARTBEAT 0x221020b0
146#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
147#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
148
149
150#define IDC_DEVICE_STATE_CHANGE BIT_0
151#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
152#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
153#define IDC_HEARTBEAT_FAILURE BIT_3
154
155
156#define ERR_LEVEL_NON_FATAL 0x1
157#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
158#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
159
160
161#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
162#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
163
164
165#define QLA83XX_NIC_CORE_RESET 0x1
166#define QLA83XX_IDC_STATE_HANDLER 0x2
167#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
168
169
170#define QLA83XX_IDC_RESET_DISABLED BIT_0
171#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
172
173
174#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
175#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
176#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
177
178
179#define QLA83XX_CLASS_TYPE_NONE 0x0
180#define QLA83XX_CLASS_TYPE_NIC 0x1
181#define QLA83XX_CLASS_TYPE_FCOE 0x2
182#define QLA83XX_CLASS_TYPE_ISCSI 0x3
183
184
185#define IDC_LOCK_RECOVERY_STAGE1 0x1
186
187
188#define IDC_LOCK_RECOVERY_STAGE2 0x2
189
190
191#define IDC_AUDIT_TIMESTAMP 0x0
192
193
194
195#define IDC_AUDIT_COMPLETION 0x1
196
197
198
199
200#define PORT_0_2031 0x00201340
201#define PORT_1_2031 0x00201350
202#define LASER_ON_2031 0x01800100
203#define LASER_OFF_2031 0x01800180
204
205
206
207
208
209#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
210#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
211
212
213
214
215#define WWN_SIZE 8
216#define MAX_FIBRE_DEVICES_2100 512
217#define MAX_FIBRE_DEVICES_2400 2048
218#define MAX_FIBRE_DEVICES_LOOP 128
219#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
220#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
221#define MAX_FIBRE_LUNS 0xFFFF
222#define MAX_HOST_COUNT 16
223
224
225
226
227#define MAX_BUSES 1
228#define MIN_LUNS 8
229#define MAX_LUNS MAX_FIBRE_LUNS
230#define MAX_CMDS_PER_LUN 255
231
232
233
234
235#define SNS_LAST_LOOP_ID_2100 0xfe
236#define SNS_LAST_LOOP_ID_2300 0x7ff
237
238#define LAST_LOCAL_LOOP_ID 0x7d
239#define SNS_FL_PORT 0x7e
240#define FABRIC_CONTROLLER 0x7f
241#define SIMPLE_NAME_SERVER 0x80
242#define SNS_FIRST_LOOP_ID 0x81
243#define MANAGEMENT_SERVER 0xfe
244#define BROADCAST 0xff
245
246
247
248
249
250#define NPH_LAST_HANDLE 0x7ee
251#define NPH_MGMT_SERVER 0x7ef
252#define NPH_SNS 0x7fc
253#define NPH_FABRIC_CONTROLLER 0x7fd
254#define NPH_F_PORT 0x7fe
255#define NPH_IP_BROADCAST 0x7ff
256
257#define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
258
259#define MAX_CMDSZ 16
260#include "qla_fw.h"
261
262struct name_list_extended {
263 struct get_name_list_extended *l;
264 dma_addr_t ldma;
265 struct list_head fcports;
266 u32 size;
267 u8 sent;
268};
269
270
271
272#define PORT_RETRY_TIME 1
273#define LOOP_DOWN_TIMEOUT 60
274#define LOOP_DOWN_TIME 255
275#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
276
277#define DEFAULT_OUTSTANDING_COMMANDS 4096
278#define MIN_OUTSTANDING_COMMANDS 128
279
280
281#define REQUEST_ENTRY_CNT_2100 128
282#define REQUEST_ENTRY_CNT_2200 2048
283#define REQUEST_ENTRY_CNT_24XX 2048
284#define REQUEST_ENTRY_CNT_83XX 8192
285#define RESPONSE_ENTRY_CNT_83XX 4096
286#define RESPONSE_ENTRY_CNT_2100 64
287#define RESPONSE_ENTRY_CNT_2300 512
288#define RESPONSE_ENTRY_CNT_MQ 128
289#define ATIO_ENTRY_CNT_24XX 4096
290#define RESPONSE_ENTRY_CNT_FX00 256
291#define FW_DEF_EXCHANGES_CNT 2048
292#define FW_MAX_EXCHANGES_CNT (32 * 1024)
293#define REDUCE_EXCHANGES_CNT (8 * 1024)
294
295struct req_que;
296struct qla_tgt_sess;
297
298
299
300
301struct srb_cmd {
302 struct scsi_cmnd *cmd;
303 uint32_t request_sense_length;
304 uint32_t fw_sense_length;
305 uint8_t *request_sense_ptr;
306 void *ctx;
307};
308
309
310
311
312#define SRB_DMA_VALID BIT_0
313#define SRB_FCP_CMND_DMA_VALID BIT_12
314#define SRB_CRC_CTX_DMA_VALID BIT_2
315#define SRB_CRC_PROT_DMA_VALID BIT_4
316#define SRB_CRC_CTX_DSD_VALID BIT_5
317#define SRB_WAKEUP_ON_COMP BIT_6
318#define SRB_DIF_BUNDL_DMA_VALID BIT_7
319
320
321#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
322
323
324
325
326typedef union {
327 uint32_t b24 : 24;
328
329 struct {
330#ifdef __BIG_ENDIAN
331 uint8_t domain;
332 uint8_t area;
333 uint8_t al_pa;
334#elif defined(__LITTLE_ENDIAN)
335 uint8_t al_pa;
336 uint8_t area;
337 uint8_t domain;
338#else
339#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
340#endif
341 uint8_t rsvd_1;
342 } b;
343} port_id_t;
344#define INVALID_PORT_ID 0xFFFFFF
345
346struct els_logo_payload {
347 uint8_t opcode;
348 uint8_t rsvd[3];
349 uint8_t s_id[3];
350 uint8_t rsvd1[1];
351 uint8_t wwpn[WWN_SIZE];
352};
353
354struct els_plogi_payload {
355 uint8_t opcode;
356 uint8_t rsvd[3];
357 uint8_t data[112];
358};
359
360struct ct_arg {
361 void *iocb;
362 u16 nport_handle;
363 dma_addr_t req_dma;
364 dma_addr_t rsp_dma;
365 u32 req_size;
366 u32 rsp_size;
367 u32 req_allocated_size;
368 u32 rsp_allocated_size;
369 void *req;
370 void *rsp;
371 port_id_t id;
372};
373
374
375
376
377struct srb_iocb {
378 union {
379 struct {
380 uint16_t flags;
381#define SRB_LOGIN_RETRIED BIT_0
382#define SRB_LOGIN_COND_PLOGI BIT_1
383#define SRB_LOGIN_SKIP_PRLI BIT_2
384#define SRB_LOGIN_NVME_PRLI BIT_3
385#define SRB_LOGIN_PRLI_ONLY BIT_4
386 uint16_t data[2];
387 u32 iop[2];
388 } logio;
389 struct {
390#define ELS_DCMD_TIMEOUT 20
391#define ELS_DCMD_LOGO 0x5
392 uint32_t flags;
393 uint32_t els_cmd;
394 struct completion comp;
395 struct els_logo_payload *els_logo_pyld;
396 dma_addr_t els_logo_pyld_dma;
397 } els_logo;
398 struct {
399#define ELS_DCMD_PLOGI 0x3
400 uint32_t flags;
401 uint32_t els_cmd;
402 struct completion comp;
403 struct els_plogi_payload *els_plogi_pyld;
404 struct els_plogi_payload *els_resp_pyld;
405 u32 tx_size;
406 u32 rx_size;
407 dma_addr_t els_plogi_pyld_dma;
408 dma_addr_t els_resp_pyld_dma;
409 uint32_t fw_status[3];
410 __le16 comp_status;
411 __le16 len;
412 } els_plogi;
413 struct {
414
415
416
417
418
419 uint64_t lun;
420 uint32_t flags;
421 uint32_t data;
422 struct completion comp;
423 __le16 comp_status;
424 } tmf;
425 struct {
426#define SRB_FXDISC_REQ_DMA_VALID BIT_0
427#define SRB_FXDISC_RESP_DMA_VALID BIT_1
428#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
429#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
430#define FXDISC_TIMEOUT 20
431 uint8_t flags;
432 uint32_t req_len;
433 uint32_t rsp_len;
434 void *req_addr;
435 void *rsp_addr;
436 dma_addr_t req_dma_handle;
437 dma_addr_t rsp_dma_handle;
438 __le32 adapter_id;
439 __le32 adapter_id_hi;
440 __le16 req_func_type;
441 __le32 req_data;
442 __le32 req_data_extra;
443 __le32 result;
444 __le32 seq_number;
445 __le16 fw_flags;
446 struct completion fxiocb_comp;
447 __le32 reserved_0;
448 uint8_t reserved_1;
449 } fxiocb;
450 struct {
451 uint32_t cmd_hndl;
452 __le16 comp_status;
453 __le16 req_que_no;
454 struct completion comp;
455 } abt;
456 struct ct_arg ctarg;
457#define MAX_IOCB_MB_REG 28
458#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
459 struct {
460 __le16 in_mb[MAX_IOCB_MB_REG];
461 __le16 out_mb[MAX_IOCB_MB_REG];
462 void *out, *in;
463 dma_addr_t out_dma, in_dma;
464 struct completion comp;
465 int rc;
466 } mbx;
467 struct {
468 struct imm_ntfy_from_isp *ntfy;
469 } nack;
470 struct {
471 __le16 comp_status;
472 uint16_t rsp_pyld_len;
473 uint8_t aen_op;
474 void *desc;
475
476
477 int cmd_len;
478 int rsp_len;
479 dma_addr_t cmd_dma;
480 dma_addr_t rsp_dma;
481 enum nvmefc_fcp_datadir dir;
482 uint32_t dl;
483 uint32_t timeout_sec;
484 struct list_head entry;
485 } nvme;
486 struct {
487 u16 cmd;
488 u16 vp_index;
489 } ctrlvp;
490 } u;
491
492 struct timer_list timer;
493 void (*timeout)(void *);
494};
495
496
497#define SRB_LOGIN_CMD 1
498#define SRB_LOGOUT_CMD 2
499#define SRB_ELS_CMD_RPT 3
500#define SRB_ELS_CMD_HST 4
501#define SRB_CT_CMD 5
502#define SRB_ADISC_CMD 6
503#define SRB_TM_CMD 7
504#define SRB_SCSI_CMD 8
505#define SRB_BIDI_CMD 9
506#define SRB_FXIOCB_DCMD 10
507#define SRB_FXIOCB_BCMD 11
508#define SRB_ABT_CMD 12
509#define SRB_ELS_DCMD 13
510#define SRB_MB_IOCB 14
511#define SRB_CT_PTHRU_CMD 15
512#define SRB_NACK_PLOGI 16
513#define SRB_NACK_PRLI 17
514#define SRB_NACK_LOGO 18
515#define SRB_NVME_CMD 19
516#define SRB_NVME_LS 20
517#define SRB_PRLI_CMD 21
518#define SRB_CTRL_VP 22
519#define SRB_PRLO_CMD 23
520
521enum {
522 TYPE_SRB,
523 TYPE_TGT_CMD,
524 TYPE_TGT_TMCMD,
525};
526
527typedef struct srb {
528
529
530
531
532 uint8_t cmd_type;
533 uint8_t pad[3];
534 atomic_t ref_count;
535 struct kref cmd_kref;
536 void *priv;
537 wait_queue_head_t nvme_ls_waitq;
538 struct fc_port *fcport;
539 struct scsi_qla_host *vha;
540 uint32_t handle;
541 uint16_t flags;
542 uint16_t type;
543 const char *name;
544 int iocbs;
545 struct qla_qpair *qpair;
546 struct list_head elem;
547 u32 gen1;
548 u32 gen2;
549 int rc;
550 int retry_count;
551 struct completion *comp;
552 union {
553 struct srb_iocb iocb_cmd;
554 struct bsg_job *bsg_job;
555 struct srb_cmd scmd;
556 } u;
557 void (*done)(void *, int);
558 void (*free)(void *);
559 void (*put_fn)(struct kref *kref);
560} srb_t;
561
562#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
563#define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
564#define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
565
566#define GET_CMD_SENSE_LEN(sp) \
567 (sp->u.scmd.request_sense_length)
568#define SET_CMD_SENSE_LEN(sp, len) \
569 (sp->u.scmd.request_sense_length = len)
570#define GET_CMD_SENSE_PTR(sp) \
571 (sp->u.scmd.request_sense_ptr)
572#define SET_CMD_SENSE_PTR(sp, ptr) \
573 (sp->u.scmd.request_sense_ptr = ptr)
574#define GET_FW_SENSE_LEN(sp) \
575 (sp->u.scmd.fw_sense_length)
576#define SET_FW_SENSE_LEN(sp, len) \
577 (sp->u.scmd.fw_sense_length = len)
578
579struct msg_echo_lb {
580 dma_addr_t send_dma;
581 dma_addr_t rcv_dma;
582 uint16_t req_sg_cnt;
583 uint16_t rsp_sg_cnt;
584 uint16_t options;
585 uint32_t transfer_size;
586 uint32_t iteration_count;
587};
588
589
590
591
592struct device_reg_2xxx {
593 uint16_t flash_address;
594 uint16_t flash_data;
595 uint16_t unused_1[1];
596 uint16_t ctrl_status;
597#define CSR_FLASH_64K_BANK BIT_3
598#define CSR_FLASH_ENABLE BIT_1
599#define CSR_ISP_SOFT_RESET BIT_0
600
601 uint16_t ictrl;
602#define ICR_EN_INT BIT_15
603#define ICR_EN_RISC BIT_3
604
605 uint16_t istatus;
606#define ISR_RISC_INT BIT_3
607
608 uint16_t semaphore;
609 uint16_t nvram;
610#define NVR_DESELECT 0
611#define NVR_BUSY BIT_15
612#define NVR_WRT_ENABLE BIT_14
613#define NVR_PR_ENABLE BIT_13
614#define NVR_DATA_IN BIT_3
615#define NVR_DATA_OUT BIT_2
616#define NVR_SELECT BIT_1
617#define NVR_CLOCK BIT_0
618
619#define NVR_WAIT_CNT 20000
620
621 union {
622 struct {
623 uint16_t mailbox0;
624 uint16_t mailbox1;
625 uint16_t mailbox2;
626 uint16_t mailbox3;
627 uint16_t mailbox4;
628 uint16_t mailbox5;
629 uint16_t mailbox6;
630 uint16_t mailbox7;
631 uint16_t unused_2[59];
632 } __attribute__((packed)) isp2100;
633 struct {
634
635 uint16_t req_q_in;
636 uint16_t req_q_out;
637
638 uint16_t rsp_q_in;
639 uint16_t rsp_q_out;
640
641
642 uint32_t host_status;
643#define HSR_RISC_INT BIT_15
644#define HSR_RISC_PAUSED BIT_8
645
646
647 uint16_t host_semaphore;
648 uint16_t unused_3[17];
649 uint16_t mailbox0;
650 uint16_t mailbox1;
651 uint16_t mailbox2;
652 uint16_t mailbox3;
653 uint16_t mailbox4;
654 uint16_t mailbox5;
655 uint16_t mailbox6;
656 uint16_t mailbox7;
657 uint16_t mailbox8;
658 uint16_t mailbox9;
659 uint16_t mailbox10;
660 uint16_t mailbox11;
661 uint16_t mailbox12;
662 uint16_t mailbox13;
663 uint16_t mailbox14;
664 uint16_t mailbox15;
665 uint16_t mailbox16;
666 uint16_t mailbox17;
667 uint16_t mailbox18;
668 uint16_t mailbox19;
669 uint16_t mailbox20;
670 uint16_t mailbox21;
671 uint16_t mailbox22;
672 uint16_t mailbox23;
673 uint16_t mailbox24;
674 uint16_t mailbox25;
675 uint16_t mailbox26;
676 uint16_t mailbox27;
677 uint16_t mailbox28;
678 uint16_t mailbox29;
679 uint16_t mailbox30;
680 uint16_t mailbox31;
681 uint16_t fb_cmd;
682 uint16_t unused_4[10];
683 } __attribute__((packed)) isp2300;
684 } u;
685
686 uint16_t fpm_diag_config;
687 uint16_t unused_5[0x4];
688 uint16_t risc_hw;
689 uint16_t unused_5_1;
690 uint16_t pcr;
691 uint16_t unused_6[0x5];
692 uint16_t mctr;
693 uint16_t unused_7[0x3];
694 uint16_t fb_cmd_2100;
695 uint16_t unused_8[0x3];
696 uint16_t hccr;
697#define HCCR_HOST_INT BIT_7
698#define HCCR_RISC_PAUSE BIT_5
699
700#define HCCR_RESET_RISC 0x1000
701#define HCCR_PAUSE_RISC 0x2000
702#define HCCR_RELEASE_RISC 0x3000
703#define HCCR_SET_HOST_INT 0x5000
704#define HCCR_CLR_HOST_INT 0x6000
705#define HCCR_CLR_RISC_INT 0x7000
706#define HCCR_DISABLE_PARITY_PAUSE 0x4001
707#define HCCR_ENABLE_PARITY 0xA000
708
709 uint16_t unused_9[5];
710 uint16_t gpiod;
711 uint16_t gpioe;
712#define GPIO_LED_MASK 0x00C0
713#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
714#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
715#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
716#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
717#define GPIO_LED_ALL_OFF 0x0000
718#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
719#define GPIO_LED_RGA_ON 0x00C1
720
721 union {
722 struct {
723 uint16_t unused_10[8];
724 uint16_t mailbox8;
725 uint16_t mailbox9;
726 uint16_t mailbox10;
727 uint16_t mailbox11;
728 uint16_t mailbox12;
729 uint16_t mailbox13;
730 uint16_t mailbox14;
731 uint16_t mailbox15;
732 uint16_t mailbox16;
733 uint16_t mailbox17;
734 uint16_t mailbox18;
735 uint16_t mailbox19;
736 uint16_t mailbox20;
737 uint16_t mailbox21;
738 uint16_t mailbox22;
739 uint16_t mailbox23;
740 } __attribute__((packed)) isp2200;
741 } u_end;
742};
743
744struct device_reg_25xxmq {
745 uint32_t req_q_in;
746 uint32_t req_q_out;
747 uint32_t rsp_q_in;
748 uint32_t rsp_q_out;
749 uint32_t atio_q_in;
750 uint32_t atio_q_out;
751};
752
753
754struct device_reg_fx00 {
755 uint32_t mailbox0;
756 uint32_t mailbox1;
757 uint32_t mailbox2;
758 uint32_t mailbox3;
759 uint32_t mailbox4;
760 uint32_t mailbox5;
761 uint32_t mailbox6;
762 uint32_t mailbox7;
763 uint32_t mailbox8;
764 uint32_t mailbox9;
765 uint32_t mailbox10;
766 uint32_t mailbox11;
767 uint32_t mailbox12;
768 uint32_t mailbox13;
769 uint32_t mailbox14;
770 uint32_t mailbox15;
771 uint32_t mailbox16;
772 uint32_t mailbox17;
773 uint32_t mailbox18;
774 uint32_t mailbox19;
775 uint32_t mailbox20;
776 uint32_t mailbox21;
777 uint32_t mailbox22;
778 uint32_t mailbox23;
779 uint32_t mailbox24;
780 uint32_t mailbox25;
781 uint32_t mailbox26;
782 uint32_t mailbox27;
783 uint32_t mailbox28;
784 uint32_t mailbox29;
785 uint32_t mailbox30;
786 uint32_t mailbox31;
787 uint32_t aenmailbox0;
788 uint32_t aenmailbox1;
789 uint32_t aenmailbox2;
790 uint32_t aenmailbox3;
791 uint32_t aenmailbox4;
792 uint32_t aenmailbox5;
793 uint32_t aenmailbox6;
794 uint32_t aenmailbox7;
795
796 uint32_t req_q_in;
797 uint32_t req_q_out;
798
799 uint32_t rsp_q_in;
800 uint32_t rsp_q_out;
801
802 uint32_t initval0;
803 uint32_t initval1;
804 uint32_t initval2;
805 uint32_t initval3;
806 uint32_t initval4;
807 uint32_t initval5;
808 uint32_t initval6;
809 uint32_t initval7;
810 uint32_t fwheartbeat;
811 uint32_t pseudoaen;
812};
813
814
815
816typedef union {
817 struct device_reg_2xxx isp;
818 struct device_reg_24xx isp24;
819 struct device_reg_25xxmq isp25mq;
820 struct device_reg_82xx isp82;
821 struct device_reg_fx00 ispfx00;
822} __iomem device_reg_t;
823
824#define ISP_REQ_Q_IN(ha, reg) \
825 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
826 &(reg)->u.isp2100.mailbox4 : \
827 &(reg)->u.isp2300.req_q_in)
828#define ISP_REQ_Q_OUT(ha, reg) \
829 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
830 &(reg)->u.isp2100.mailbox4 : \
831 &(reg)->u.isp2300.req_q_out)
832#define ISP_RSP_Q_IN(ha, reg) \
833 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
834 &(reg)->u.isp2100.mailbox5 : \
835 &(reg)->u.isp2300.rsp_q_in)
836#define ISP_RSP_Q_OUT(ha, reg) \
837 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
838 &(reg)->u.isp2100.mailbox5 : \
839 &(reg)->u.isp2300.rsp_q_out)
840
841#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
842#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
843
844#define MAILBOX_REG(ha, reg, num) \
845 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
846 (num < 8 ? \
847 &(reg)->u.isp2100.mailbox0 + (num) : \
848 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
849 &(reg)->u.isp2300.mailbox0 + (num))
850#define RD_MAILBOX_REG(ha, reg, num) \
851 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
852#define WRT_MAILBOX_REG(ha, reg, num, data) \
853 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
854
855#define FB_CMD_REG(ha, reg) \
856 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
857 &(reg)->fb_cmd_2100 : \
858 &(reg)->u.isp2300.fb_cmd)
859#define RD_FB_CMD_REG(ha, reg) \
860 RD_REG_WORD(FB_CMD_REG(ha, reg))
861#define WRT_FB_CMD_REG(ha, reg, data) \
862 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
863
864typedef struct {
865 uint32_t out_mb;
866 uint32_t in_mb;
867 uint16_t mb[MAILBOX_REGISTER_COUNT];
868 long buf_size;
869 void *bufp;
870 uint32_t tov;
871 uint8_t flags;
872#define MBX_DMA_IN BIT_0
873#define MBX_DMA_OUT BIT_1
874#define IOCTL_CMD BIT_2
875} mbx_cmd_t;
876
877struct mbx_cmd_32 {
878 uint32_t out_mb;
879 uint32_t in_mb;
880 uint32_t mb[MAILBOX_REGISTER_COUNT];
881 long buf_size;
882 void *bufp;
883 uint32_t tov;
884 uint8_t flags;
885#define MBX_DMA_IN BIT_0
886#define MBX_DMA_OUT BIT_1
887#define IOCTL_CMD BIT_2
888};
889
890
891#define MBX_TOV_SECONDS 30
892
893
894
895
896#define PROD_ID_1 0x4953
897#define PROD_ID_2 0x0000
898#define PROD_ID_2a 0x5020
899#define PROD_ID_3 0x2020
900
901
902
903
904#define MBS_FRM_ALIVE 0
905#define MBS_CHKSUM_ERR 1
906#define MBS_BUSY 4
907
908
909
910
911#define MBS_COMMAND_COMPLETE 0x4000
912#define MBS_INVALID_COMMAND 0x4001
913#define MBS_HOST_INTERFACE_ERROR 0x4002
914#define MBS_TEST_FAILED 0x4003
915#define MBS_COMMAND_ERROR 0x4005
916#define MBS_COMMAND_PARAMETER_ERROR 0x4006
917#define MBS_PORT_ID_USED 0x4007
918#define MBS_LOOP_ID_USED 0x4008
919#define MBS_ALL_IDS_IN_USE 0x4009
920#define MBS_NOT_LOGGED_IN 0x400A
921#define MBS_LINK_DOWN_ERROR 0x400B
922#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
923
924
925
926
927#define MBA_ASYNC_EVENT 0x8000
928#define MBA_RESET 0x8001
929#define MBA_SYSTEM_ERR 0x8002
930#define MBA_REQ_TRANSFER_ERR 0x8003
931#define MBA_RSP_TRANSFER_ERR 0x8004
932#define MBA_WAKEUP_THRES 0x8005
933#define MBA_LIP_OCCURRED 0x8010
934
935#define MBA_LOOP_UP 0x8011
936#define MBA_LOOP_DOWN 0x8012
937#define MBA_LIP_RESET 0x8013
938#define MBA_PORT_UPDATE 0x8014
939#define MBA_RSCN_UPDATE 0x8015
940#define MBA_LIP_F8 0x8016
941#define MBA_LOOP_INIT_ERR 0x8017
942#define MBA_FABRIC_AUTH_REQ 0x801b
943#define MBA_SCSI_COMPLETION 0x8020
944#define MBA_CTIO_COMPLETION 0x8021
945#define MBA_IP_COMPLETION 0x8022
946#define MBA_IP_RECEIVE 0x8023
947#define MBA_IP_BROADCAST 0x8024
948#define MBA_IP_LOW_WATER_MARK 0x8025
949#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
950#define MBA_IP_HDR_DATA_SPLIT 0x8027
951
952#define MBA_TRACE_NOTIFICATION 0x8028
953#define MBA_POINT_TO_POINT 0x8030
954#define MBA_CMPLT_1_16BIT 0x8031
955#define MBA_CMPLT_2_16BIT 0x8032
956#define MBA_CMPLT_3_16BIT 0x8033
957#define MBA_CMPLT_4_16BIT 0x8034
958#define MBA_CMPLT_5_16BIT 0x8035
959#define MBA_CHG_IN_CONNECTION 0x8036
960#define MBA_RIO_RESPONSE 0x8040
961#define MBA_ZIO_RESPONSE 0x8040
962#define MBA_CMPLT_2_32BIT 0x8042
963#define MBA_BYPASS_NOTIFICATION 0x8043
964#define MBA_DISCARD_RND_FRAME 0x8048
965#define MBA_REJECTED_FCP_CMD 0x8049
966#define MBA_FW_NOT_STARTED 0x8050
967#define MBA_FW_STARTING 0x8051
968#define MBA_FW_RESTART_CMPLT 0x8060
969#define MBA_INIT_REQUIRED 0x8061
970#define MBA_SHUTDOWN_REQUESTED 0x8062
971#define MBA_TEMPERATURE_ALERT 0x8070
972#define MBA_DPORT_DIAGNOSTICS 0x8080
973#define MBA_TRANS_INSERT 0x8130
974#define MBA_FW_INIT_FAILURE 0x8401
975#define MBA_MIRROR_LUN_CHANGE 0x8402
976
977#define MBA_FW_POLL_STATE 0x8600
978#define MBA_FW_RESET_FCT 0x8502
979#define MBA_FW_INIT_INPROGRESS 0x8500
980
981#define MBA_IDC_AEN 0x8200
982
983
984#define INTR_ROM_MB_SUCCESS 0x1
985#define INTR_ROM_MB_FAILED 0x2
986#define INTR_MB_SUCCESS 0x10
987#define INTR_MB_FAILED 0x11
988#define INTR_ASYNC_EVENT 0x12
989#define INTR_RSP_QUE_UPDATE 0x13
990#define INTR_RSP_QUE_UPDATE_83XX 0x14
991#define INTR_ATIO_QUE_UPDATE 0x1C
992#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
993#define INTR_ATIO_QUE_UPDATE_27XX 0x1E
994
995
996#define MBS_LB_RESET 0x17
997
998
999
1000#define FO1_AE_ON_LIPF8 BIT_0
1001#define FO1_AE_ALL_LIP_RESET BIT_1
1002#define FO1_CTIO_RETRY BIT_3
1003#define FO1_DISABLE_LIP_F7_SW BIT_4
1004#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1005#define FO1_DISABLE_GPIO6_7 BIT_6
1006#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1007#define FO1_SET_EMPHASIS_SWING BIT_8
1008#define FO1_AE_AUTO_BYPASS BIT_9
1009#define FO1_ENABLE_PURE_IOCB BIT_10
1010#define FO1_AE_PLOGI_RJT BIT_11
1011#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1012#define FO1_AE_QUEUE_FULL BIT_13
1013
1014#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1015#define FO2_REV_LOOPBACK BIT_1
1016
1017#define FO3_ENABLE_EMERG_IOCB BIT_0
1018#define FO3_AE_RND_ERROR BIT_1
1019
1020
1021#define ADD_FO_COUNT 3
1022#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
1023#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1024
1025#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1026
1027#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1028
1029
1030
1031
1032#define MBC_LOAD_RAM 1
1033#define MBC_EXECUTE_FIRMWARE 2
1034#define MBC_READ_RAM_WORD 5
1035#define MBC_MAILBOX_REGISTER_TEST 6
1036#define MBC_VERIFY_CHECKSUM 7
1037#define MBC_GET_FIRMWARE_VERSION 8
1038#define MBC_LOAD_RISC_RAM 9
1039#define MBC_DUMP_RISC_RAM 0xa
1040#define MBC_SECURE_FLASH_UPDATE 0xa
1041#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
1042#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
1043#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
1044#define MBC_READ_RAM_EXTENDED 0xf
1045#define MBC_IOCB_COMMAND 0x12
1046#define MBC_STOP_FIRMWARE 0x14
1047#define MBC_ABORT_COMMAND 0x15
1048#define MBC_ABORT_DEVICE 0x16
1049#define MBC_ABORT_TARGET 0x17
1050#define MBC_RESET 0x18
1051#define MBC_GET_ADAPTER_LOOP_ID 0x20
1052#define MBC_GET_SET_ZIO_THRESHOLD 0x21
1053#define MBC_GET_RETRY_COUNT 0x22
1054#define MBC_DISABLE_VI 0x24
1055#define MBC_ENABLE_VI 0x25
1056#define MBC_GET_FIRMWARE_OPTION 0x28
1057#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34
1058#define MBC_SET_FIRMWARE_OPTION 0x38
1059#define MBC_LOOP_PORT_BYPASS 0x40
1060#define MBC_LOOP_PORT_ENABLE 0x41
1061#define MBC_GET_RESOURCE_COUNTS 0x42
1062#define MBC_NON_PARTICIPATE 0x43
1063#define MBC_DIAGNOSTIC_ECHO 0x44
1064#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
1065#define MBC_ONLINE_SELF_TEST 0x46
1066#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
1067#define MBC_CONFIGURE_VF 0x4b
1068#define MBC_RESET_LINK_STATUS 0x52
1069#define MBC_IOCB_COMMAND_A64 0x54
1070#define MBC_PORT_LOGOUT 0x56
1071#define MBC_SEND_RNID_ELS 0x57
1072#define MBC_SET_RNID_PARAMS 0x59
1073#define MBC_GET_RNID_PARAMS 0x5a
1074#define MBC_DATA_RATE 0x5d
1075#define MBC_INITIALIZE_FIRMWARE 0x60
1076#define MBC_INITIATE_LIP 0x62
1077
1078#define MBC_GET_FC_AL_POSITION_MAP 0x63
1079#define MBC_GET_PORT_DATABASE 0x64
1080#define MBC_CLEAR_ACA 0x65
1081#define MBC_TARGET_RESET 0x66
1082#define MBC_CLEAR_TASK_SET 0x67
1083#define MBC_ABORT_TASK_SET 0x68
1084#define MBC_GET_FIRMWARE_STATE 0x69
1085#define MBC_GET_PORT_NAME 0x6a
1086#define MBC_GET_LINK_STATUS 0x6b
1087#define MBC_LIP_RESET 0x6c
1088#define MBC_SEND_SNS_COMMAND 0x6e
1089
1090#define MBC_LOGIN_FABRIC_PORT 0x6f
1091#define MBC_SEND_CHANGE_REQUEST 0x70
1092#define MBC_LOGOUT_FABRIC_PORT 0x71
1093#define MBC_LIP_FULL_LOGIN 0x72
1094#define MBC_LOGIN_LOOP_PORT 0x74
1095#define MBC_PORT_NODE_NAME_LIST 0x75
1096#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
1097#define MBC_UNLOAD_IP 0x79
1098#define MBC_GET_ID_LIST 0x7C
1099#define MBC_SEND_LFA_COMMAND 0x7D
1100#define MBC_LUN_RESET 0x7E
1101
1102
1103
1104
1105
1106#define MBC_MR_DRV_SHUTDOWN 0x6A
1107
1108
1109
1110
1111#define MBC_WRITE_SERDES 0x3
1112#define MBC_READ_SERDES 0x4
1113#define MBC_LOAD_DUMP_MPI_RAM 0x5
1114#define MBC_SERDES_PARAMS 0x10
1115#define MBC_GET_IOCB_STATUS 0x12
1116#define MBC_PORT_PARAMS 0x1A
1117#define MBC_GET_TIMEOUT_PARAMS 0x22
1118#define MBC_TRACE_CONTROL 0x27
1119#define MBC_GEN_SYSTEM_ERROR 0x2a
1120#define MBC_WRITE_SFP 0x30
1121#define MBC_READ_SFP 0x31
1122#define MBC_SET_TIMEOUT_PARAMS 0x32
1123#define MBC_DPORT_DIAGNOSTICS 0x47
1124#define MBC_MID_INITIALIZE_FIRMWARE 0x48
1125#define MBC_MID_GET_VP_DATABASE 0x49
1126#define MBC_MID_GET_VP_ENTRY 0x4a
1127#define MBC_HOST_MEMORY_COPY 0x53
1128#define MBC_SEND_RNFT_ELS 0x5e
1129#define MBC_GET_LINK_PRIV_STATS 0x6d
1130#define MBC_LINK_INITIALIZATION 0x72
1131#define MBC_SET_VENDOR_ID 0x76
1132#define MBC_PORT_RESET 0x120
1133#define MBC_SET_PORT_CONFIG 0x122
1134#define MBC_GET_PORT_CONFIG 0x123
1135
1136
1137
1138
1139#define MBC_WRITE_MPI_REGISTER 0x01
1140
1141
1142
1143
1144#define MBC_SET_GET_ETH_SERDES_REG 0x150
1145#define HCS_WRITE_SERDES 0x3
1146#define HCS_READ_SERDES 0x4
1147
1148
1149#define FCAL_MAP_SIZE 128
1150
1151
1152#define MBX_31 BIT_31
1153#define MBX_30 BIT_30
1154#define MBX_29 BIT_29
1155#define MBX_28 BIT_28
1156#define MBX_27 BIT_27
1157#define MBX_26 BIT_26
1158#define MBX_25 BIT_25
1159#define MBX_24 BIT_24
1160#define MBX_23 BIT_23
1161#define MBX_22 BIT_22
1162#define MBX_21 BIT_21
1163#define MBX_20 BIT_20
1164#define MBX_19 BIT_19
1165#define MBX_18 BIT_18
1166#define MBX_17 BIT_17
1167#define MBX_16 BIT_16
1168#define MBX_15 BIT_15
1169#define MBX_14 BIT_14
1170#define MBX_13 BIT_13
1171#define MBX_12 BIT_12
1172#define MBX_11 BIT_11
1173#define MBX_10 BIT_10
1174#define MBX_9 BIT_9
1175#define MBX_8 BIT_8
1176#define MBX_7 BIT_7
1177#define MBX_6 BIT_6
1178#define MBX_5 BIT_5
1179#define MBX_4 BIT_4
1180#define MBX_3 BIT_3
1181#define MBX_2 BIT_2
1182#define MBX_1 BIT_1
1183#define MBX_0 BIT_0
1184
1185#define RNID_TYPE_PORT_LOGIN 0x7
1186#define RNID_TYPE_SET_VERSION 0x9
1187#define RNID_TYPE_ASIC_TEMP 0xC
1188
1189
1190
1191
1192#define FSTATE_CONFIG_WAIT 0
1193#define FSTATE_WAIT_AL_PA 1
1194#define FSTATE_WAIT_LOGIN 2
1195#define FSTATE_READY 3
1196#define FSTATE_LOSS_OF_SYNC 4
1197#define FSTATE_ERROR 5
1198#define FSTATE_REINIT 6
1199#define FSTATE_NON_PART 7
1200
1201#define FSTATE_CONFIG_CORRECT 0
1202#define FSTATE_P2P_RCV_LIP 1
1203#define FSTATE_P2P_CHOOSE_LOOP 2
1204#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1205#define FSTATE_FATAL_ERROR 4
1206#define FSTATE_LOOP_BACK_CONN 5
1207
1208#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1209#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1210#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1211#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1212#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1213#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1214#define QLA27XX_DEFAULT_IMAGE 0
1215#define QLA27XX_PRIMARY_IMAGE 1
1216#define QLA27XX_SECONDARY_IMAGE 2
1217
1218
1219
1220
1221
1222#define PORT_DATABASE_SIZE 128
1223typedef struct {
1224 uint8_t options;
1225 uint8_t control;
1226 uint8_t master_state;
1227 uint8_t slave_state;
1228 uint8_t reserved[2];
1229 uint8_t hard_address;
1230 uint8_t reserved_1;
1231 uint8_t port_id[4];
1232 uint8_t node_name[WWN_SIZE];
1233 uint8_t port_name[WWN_SIZE];
1234 uint16_t execution_throttle;
1235 uint16_t execution_count;
1236 uint8_t reset_count;
1237 uint8_t reserved_2;
1238 uint16_t resource_allocation;
1239 uint16_t current_allocation;
1240 uint16_t queue_head;
1241 uint16_t queue_tail;
1242 uint16_t transmit_execution_list_next;
1243 uint16_t transmit_execution_list_previous;
1244 uint16_t common_features;
1245 uint16_t total_concurrent_sequences;
1246 uint16_t RO_by_information_category;
1247 uint8_t recipient;
1248 uint8_t initiator;
1249 uint16_t receive_data_size;
1250 uint16_t concurrent_sequences;
1251 uint16_t open_sequences_per_exchange;
1252 uint16_t lun_abort_flags;
1253 uint16_t lun_stop_flags;
1254 uint16_t stop_queue_head;
1255 uint16_t stop_queue_tail;
1256 uint16_t port_retry_timer;
1257 uint16_t next_sequence_id;
1258 uint16_t frame_count;
1259 uint16_t PRLI_payload_length;
1260 uint8_t prli_svc_param_word_0[2];
1261
1262 uint8_t prli_svc_param_word_3[2];
1263
1264 uint16_t loop_id;
1265 uint16_t extended_lun_info_list_pointer;
1266 uint16_t extended_lun_stop_list_pointer;
1267} port_database_t;
1268
1269
1270
1271
1272#define PD_STATE_DISCOVERY 0
1273#define PD_STATE_WAIT_DISCOVERY_ACK 1
1274#define PD_STATE_PORT_LOGIN 2
1275#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1276#define PD_STATE_PROCESS_LOGIN 4
1277#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1278#define PD_STATE_PORT_LOGGED_IN 6
1279#define PD_STATE_PORT_UNAVAILABLE 7
1280#define PD_STATE_PROCESS_LOGOUT 8
1281#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1282#define PD_STATE_PORT_LOGOUT 10
1283#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1284
1285
1286#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1287#define QLA_ZIO_DISABLED 0
1288#define QLA_ZIO_DEFAULT_TIMER 2
1289
1290
1291
1292
1293
1294#define ICB_VERSION 1
1295typedef struct {
1296 uint8_t version;
1297 uint8_t reserved_1;
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318 uint8_t firmware_options[2];
1319
1320 uint16_t frame_payload_size;
1321 uint16_t max_iocb_allocation;
1322 uint16_t execution_throttle;
1323 uint8_t retry_count;
1324 uint8_t retry_delay;
1325 uint8_t port_name[WWN_SIZE];
1326 uint16_t hard_address;
1327 uint8_t inquiry_data;
1328 uint8_t login_timeout;
1329 uint8_t node_name[WWN_SIZE];
1330
1331 uint16_t request_q_outpointer;
1332 uint16_t response_q_inpointer;
1333 uint16_t request_q_length;
1334 uint16_t response_q_length;
1335 __le64 request_q_address __packed;
1336 __le64 response_q_address __packed;
1337
1338 uint16_t lun_enables;
1339 uint8_t command_resource_count;
1340 uint8_t immediate_notify_resource_count;
1341 uint16_t timeout;
1342 uint8_t reserved_2[2];
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363 uint8_t add_firmware_options[2];
1364
1365 uint8_t response_accumulation_timer;
1366 uint8_t interrupt_delay_timer;
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387 uint8_t special_options[2];
1388
1389 uint8_t reserved_3[26];
1390} init_cb_t;
1391
1392
1393
1394
1395#define GLSO_SEND_RPS BIT_0
1396#define GLSO_USE_DID BIT_3
1397
1398struct link_statistics {
1399 uint32_t link_fail_cnt;
1400 uint32_t loss_sync_cnt;
1401 uint32_t loss_sig_cnt;
1402 uint32_t prim_seq_err_cnt;
1403 uint32_t inval_xmit_word_cnt;
1404 uint32_t inval_crc_cnt;
1405 uint32_t lip_cnt;
1406 uint32_t link_up_cnt;
1407 uint32_t link_down_loop_init_tmo;
1408 uint32_t link_down_los;
1409 uint32_t link_down_loss_rcv_clk;
1410 uint32_t reserved0[5];
1411 uint32_t port_cfg_chg;
1412 uint32_t reserved1[11];
1413 uint32_t rsp_q_full;
1414 uint32_t atio_q_full;
1415 uint32_t drop_ae;
1416 uint32_t els_proto_err;
1417 uint32_t reserved2;
1418 uint32_t tx_frames;
1419 uint32_t rx_frames;
1420 uint32_t discarded_frames;
1421 uint32_t dropped_frames;
1422 uint32_t reserved3;
1423 uint32_t nos_rcvd;
1424 uint32_t reserved4[4];
1425 uint32_t tx_prjt;
1426 uint32_t rcv_exfail;
1427 uint32_t rcv_abts;
1428 uint32_t seq_frm_miss;
1429 uint32_t corr_err;
1430 uint32_t mb_rqst;
1431 uint32_t nport_full;
1432 uint32_t eofa;
1433 uint32_t reserved5;
1434 uint32_t fpm_recv_word_cnt_lo;
1435 uint32_t fpm_recv_word_cnt_hi;
1436 uint32_t fpm_disc_word_cnt_lo;
1437 uint32_t fpm_disc_word_cnt_hi;
1438 uint32_t fpm_xmit_word_cnt_lo;
1439 uint32_t fpm_xmit_word_cnt_hi;
1440 uint32_t reserved6[70];
1441};
1442
1443
1444
1445
1446#define NV_START_BIT BIT_2
1447#define NV_WRITE_OP (BIT_26+BIT_24)
1448#define NV_READ_OP (BIT_26+BIT_25)
1449#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1450#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1451#define NV_DELAY_COUNT 10
1452
1453
1454
1455
1456typedef struct {
1457
1458
1459
1460 uint8_t id[4];
1461 uint8_t nvram_version;
1462 uint8_t reserved_0;
1463
1464
1465
1466
1467 uint8_t parameter_block_version;
1468 uint8_t reserved_1;
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489 uint8_t firmware_options[2];
1490
1491 uint16_t frame_payload_size;
1492 uint16_t max_iocb_allocation;
1493 uint16_t execution_throttle;
1494 uint8_t retry_count;
1495 uint8_t retry_delay;
1496 uint8_t port_name[WWN_SIZE];
1497 uint16_t hard_address;
1498 uint8_t inquiry_data;
1499 uint8_t login_timeout;
1500 uint8_t node_name[WWN_SIZE];
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521 uint8_t add_firmware_options[2];
1522
1523 uint8_t response_accumulation_timer;
1524 uint8_t interrupt_delay_timer;
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545 uint8_t special_options[2];
1546
1547
1548 uint8_t reserved_2[22];
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587 uint8_t seriallink_options[4];
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610 uint8_t host_p[2];
1611
1612 uint8_t boot_node_name[WWN_SIZE];
1613 uint8_t boot_lun_number;
1614 uint8_t reset_delay;
1615 uint8_t port_down_retry_count;
1616 uint8_t boot_id_number;
1617 uint16_t max_luns_per_target;
1618 uint8_t fcode_boot_port_name[WWN_SIZE];
1619 uint8_t alternate_port_name[WWN_SIZE];
1620 uint8_t alternate_node_name[WWN_SIZE];
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632 uint8_t efi_parameters;
1633
1634 uint8_t link_down_timeout;
1635
1636 uint8_t adapter_id[16];
1637
1638 uint8_t alt1_boot_node_name[WWN_SIZE];
1639 uint16_t alt1_boot_lun_number;
1640 uint8_t alt2_boot_node_name[WWN_SIZE];
1641 uint16_t alt2_boot_lun_number;
1642 uint8_t alt3_boot_node_name[WWN_SIZE];
1643 uint16_t alt3_boot_lun_number;
1644 uint8_t alt4_boot_node_name[WWN_SIZE];
1645 uint16_t alt4_boot_lun_number;
1646 uint8_t alt5_boot_node_name[WWN_SIZE];
1647 uint16_t alt5_boot_lun_number;
1648 uint8_t alt6_boot_node_name[WWN_SIZE];
1649 uint16_t alt6_boot_lun_number;
1650 uint8_t alt7_boot_node_name[WWN_SIZE];
1651 uint16_t alt7_boot_lun_number;
1652
1653 uint8_t reserved_3[2];
1654
1655
1656 uint8_t model_number[16];
1657
1658
1659 uint8_t oem_specific[16];
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682 uint8_t adapter_features[2];
1683
1684 uint8_t reserved_4[16];
1685
1686
1687 uint16_t subsystem_vendor_id_2200;
1688
1689
1690 uint16_t subsystem_device_id_2200;
1691
1692 uint8_t reserved_5;
1693 uint8_t checksum;
1694} nvram_t;
1695
1696
1697
1698
1699typedef struct {
1700 uint8_t entry_type;
1701 uint8_t entry_count;
1702 uint8_t sys_define;
1703 uint8_t entry_status;
1704 uint32_t handle;
1705 uint8_t data[52];
1706 uint32_t signature;
1707#define RESPONSE_PROCESSED 0xDEADDEAD
1708} response_t;
1709
1710
1711
1712
1713struct atio {
1714 uint8_t entry_type;
1715 uint8_t entry_count;
1716 __le16 attr_n_length;
1717 uint8_t data[56];
1718 uint32_t signature;
1719#define ATIO_PROCESSED 0xDEADDEAD
1720};
1721
1722typedef union {
1723 uint16_t extended;
1724 struct {
1725 uint8_t reserved;
1726 uint8_t standard;
1727 } id;
1728} target_id_t;
1729
1730#define SET_TARGET_ID(ha, to, from) \
1731do { \
1732 if (HAS_EXTENDED_IDS(ha)) \
1733 to.extended = cpu_to_le16(from); \
1734 else \
1735 to.id.standard = (uint8_t)from; \
1736} while (0)
1737
1738
1739
1740
1741#define COMMAND_TYPE 0x11
1742typedef struct {
1743 uint8_t entry_type;
1744 uint8_t entry_count;
1745 uint8_t sys_define;
1746 uint8_t entry_status;
1747 uint32_t handle;
1748 target_id_t target;
1749 uint16_t lun;
1750 uint16_t control_flags;
1751#define CF_WRITE BIT_6
1752#define CF_READ BIT_5
1753#define CF_SIMPLE_TAG BIT_3
1754#define CF_ORDERED_TAG BIT_2
1755#define CF_HEAD_TAG BIT_1
1756 uint16_t reserved_1;
1757 uint16_t timeout;
1758 uint16_t dseg_count;
1759 uint8_t scsi_cdb[MAX_CMDSZ];
1760 uint32_t byte_count;
1761 union {
1762 struct dsd32 dsd32[3];
1763 struct dsd64 dsd64[2];
1764 };
1765} cmd_entry_t;
1766
1767
1768
1769
1770#define COMMAND_A64_TYPE 0x19
1771typedef struct {
1772 uint8_t entry_type;
1773 uint8_t entry_count;
1774 uint8_t sys_define;
1775 uint8_t entry_status;
1776 uint32_t handle;
1777 target_id_t target;
1778 uint16_t lun;
1779 uint16_t control_flags;
1780 uint16_t reserved_1;
1781 uint16_t timeout;
1782 uint16_t dseg_count;
1783 uint8_t scsi_cdb[MAX_CMDSZ];
1784 uint32_t byte_count;
1785 struct dsd64 dsd[2];
1786} cmd_a64_entry_t, request_t;
1787
1788
1789
1790
1791#define CONTINUE_TYPE 0x02
1792typedef struct {
1793 uint8_t entry_type;
1794 uint8_t entry_count;
1795 uint8_t sys_define;
1796 uint8_t entry_status;
1797 uint32_t reserved;
1798 struct dsd32 dsd[7];
1799} cont_entry_t;
1800
1801
1802
1803
1804#define CONTINUE_A64_TYPE 0x0A
1805typedef struct {
1806 uint8_t entry_type;
1807 uint8_t entry_count;
1808 uint8_t sys_define;
1809 uint8_t entry_status;
1810 struct dsd64 dsd[5];
1811} cont_a64_entry_t;
1812
1813#define PO_MODE_DIF_INSERT 0
1814#define PO_MODE_DIF_REMOVE 1
1815#define PO_MODE_DIF_PASS 2
1816#define PO_MODE_DIF_REPLACE 3
1817#define PO_MODE_DIF_TCP_CKSUM 6
1818#define PO_ENABLE_INCR_GUARD_SEED BIT_3
1819#define PO_DISABLE_GUARD_CHECK BIT_4
1820#define PO_DISABLE_INCR_REF_TAG BIT_5
1821#define PO_DIS_HEADER_MODE BIT_7
1822#define PO_ENABLE_DIF_BUNDLING BIT_8
1823#define PO_DIS_FRAME_MODE BIT_9
1824#define PO_DIS_VALD_APP_ESC BIT_10
1825#define PO_DIS_VALD_APP_REF_ESC BIT_11
1826
1827#define PO_DIS_APP_TAG_REPL BIT_12
1828#define PO_DIS_REF_TAG_REPL BIT_13
1829#define PO_DIS_APP_TAG_VALD BIT_14
1830#define PO_DIS_REF_TAG_VALD BIT_15
1831
1832
1833
1834
1835struct crc_context {
1836 uint32_t handle;
1837 __le32 ref_tag;
1838 __le16 app_tag;
1839 uint8_t ref_tag_mask[4];
1840 uint8_t app_tag_mask[2];
1841 __le16 guard_seed;
1842 __le16 prot_opts;
1843 __le16 blk_size;
1844 uint16_t runt_blk_guard;
1845
1846 __le32 byte_count;
1847
1848 union {
1849 struct {
1850 uint32_t reserved_1;
1851 uint16_t reserved_2;
1852 uint16_t reserved_3;
1853 uint32_t reserved_4;
1854 struct dsd64 data_dsd;
1855 uint32_t reserved_5[2];
1856 uint32_t reserved_6;
1857 } nobundling;
1858 struct {
1859 __le32 dif_byte_count;
1860
1861 uint16_t reserved_1;
1862 __le16 dseg_count;
1863 uint32_t reserved_2;
1864 struct dsd64 data_dsd;
1865 struct dsd64 dif_dsd;
1866 } bundling;
1867 } u;
1868
1869 struct fcp_cmnd fcp_cmnd;
1870 dma_addr_t crc_ctx_dma;
1871
1872 struct list_head dsd_list;
1873
1874
1875 struct list_head ldif_dsd_list;
1876 u8 no_ldif_dsd;
1877
1878 struct list_head ldif_dma_hndl_list;
1879 u32 dif_bundl_len;
1880 u8 no_dif_bundl;
1881
1882};
1883
1884#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1885#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1886
1887
1888
1889
1890#define STATUS_TYPE 0x03
1891typedef struct {
1892 uint8_t entry_type;
1893 uint8_t entry_count;
1894 uint8_t sys_define;
1895 uint8_t entry_status;
1896 uint32_t handle;
1897 uint16_t scsi_status;
1898 uint16_t comp_status;
1899 uint16_t state_flags;
1900 uint16_t status_flags;
1901 uint16_t rsp_info_len;
1902 uint16_t req_sense_length;
1903 uint32_t residual_length;
1904 uint8_t rsp_info[8];
1905 uint8_t req_sense_data[32];
1906} sts_entry_t;
1907
1908
1909
1910
1911#define RF_RQ_DMA_ERROR BIT_6
1912#define RF_INV_E_ORDER BIT_5
1913#define RF_INV_E_COUNT BIT_4
1914#define RF_INV_E_PARAM BIT_3
1915#define RF_INV_E_TYPE BIT_2
1916#define RF_BUSY BIT_1
1917#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1918 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1919#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1920 RF_INV_E_TYPE)
1921
1922
1923
1924
1925#define SS_MASK 0xfff
1926#define SS_RESIDUAL_UNDER BIT_11
1927#define SS_RESIDUAL_OVER BIT_10
1928#define SS_SENSE_LEN_VALID BIT_9
1929#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1930#define SS_SCSI_STATUS_BYTE 0xff
1931
1932#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1933#define SS_BUSY_CONDITION BIT_3
1934#define SS_CONDITION_MET BIT_2
1935#define SS_CHECK_CONDITION BIT_1
1936
1937
1938
1939
1940#define CS_COMPLETE 0x0
1941#define CS_INCOMPLETE 0x1
1942#define CS_DMA 0x2
1943#define CS_TRANSPORT 0x3
1944#define CS_RESET 0x4
1945#define CS_ABORTED 0x5
1946#define CS_TIMEOUT 0x6
1947#define CS_DATA_OVERRUN 0x7
1948#define CS_DIF_ERROR 0xC
1949
1950#define CS_DATA_UNDERRUN 0x15
1951#define CS_QUEUE_FULL 0x1C
1952#define CS_PORT_UNAVAILABLE 0x28
1953
1954#define CS_PORT_LOGGED_OUT 0x29
1955#define CS_PORT_CONFIG_CHG 0x2A
1956#define CS_PORT_BUSY 0x2B
1957#define CS_COMPLETE_CHKCOND 0x30
1958#define CS_IOCB_ERROR 0x31
1959
1960#define CS_BAD_PAYLOAD 0x80
1961#define CS_UNKNOWN 0x81
1962#define CS_RETRY 0x82
1963#define CS_LOOP_DOWN_ABORT 0x83
1964
1965#define CS_BIDIR_RD_OVERRUN 0x700
1966#define CS_BIDIR_RD_WR_OVERRUN 0x707
1967#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1968#define CS_BIDIR_RD_UNDERRUN 0x1500
1969#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1970#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1971#define CS_BIDIR_DMA 0x200
1972
1973
1974
1975#define SF_ABTS_TERMINATED BIT_10
1976#define SF_LOGOUT_SENT BIT_13
1977
1978
1979
1980
1981#define STATUS_CONT_TYPE 0x10
1982typedef struct {
1983 uint8_t entry_type;
1984 uint8_t entry_count;
1985 uint8_t sys_define;
1986 uint8_t entry_status;
1987 uint8_t data[60];
1988} sts_cont_entry_t;
1989
1990
1991
1992
1993
1994#define STATUS_TYPE_21 0x21
1995typedef struct {
1996 uint8_t entry_type;
1997 uint8_t entry_count;
1998 uint8_t handle_count;
1999 uint8_t entry_status;
2000 uint32_t handle[15];
2001} sts21_entry_t;
2002
2003
2004
2005
2006
2007#define STATUS_TYPE_22 0x22
2008typedef struct {
2009 uint8_t entry_type;
2010 uint8_t entry_count;
2011 uint8_t handle_count;
2012 uint8_t entry_status;
2013 uint16_t handle[30];
2014} sts22_entry_t;
2015
2016
2017
2018
2019#define MARKER_TYPE 0x04
2020typedef struct {
2021 uint8_t entry_type;
2022 uint8_t entry_count;
2023 uint8_t handle_count;
2024 uint8_t entry_status;
2025 uint32_t sys_define_2;
2026 target_id_t target;
2027 uint8_t modifier;
2028#define MK_SYNC_ID_LUN 0
2029#define MK_SYNC_ID 1
2030#define MK_SYNC_ALL 2
2031#define MK_SYNC_LIP 3
2032
2033
2034 uint8_t reserved_1;
2035 uint16_t sequence_number;
2036 uint16_t lun;
2037 uint8_t reserved_2[48];
2038} mrk_entry_t;
2039
2040
2041
2042
2043#define MS_IOCB_TYPE 0x29
2044typedef struct {
2045 uint8_t entry_type;
2046 uint8_t entry_count;
2047 uint8_t handle_count;
2048 uint8_t entry_status;
2049 uint32_t handle1;
2050 target_id_t loop_id;
2051 uint16_t status;
2052 uint16_t control_flags;
2053 uint16_t reserved2;
2054 uint16_t timeout;
2055 uint16_t cmd_dsd_count;
2056 uint16_t total_dsd_count;
2057 uint8_t type;
2058 uint8_t r_ctl;
2059 uint16_t rx_id;
2060 uint16_t reserved3;
2061 uint32_t handle2;
2062 uint32_t rsp_bytecount;
2063 uint32_t req_bytecount;
2064 struct dsd64 req_dsd;
2065 struct dsd64 rsp_dsd;
2066} ms_iocb_entry_t;
2067
2068
2069
2070
2071
2072#define MBX_IOCB_TYPE 0x39
2073struct mbx_entry {
2074 uint8_t entry_type;
2075 uint8_t entry_count;
2076 uint8_t sys_define1;
2077
2078#define SOURCE_SCSI 0x00
2079#define SOURCE_IP 0x01
2080#define SOURCE_VI 0x02
2081#define SOURCE_SCTP 0x03
2082#define SOURCE_MP 0x04
2083#define SOURCE_MPIOCTL 0x05
2084#define SOURCE_ASYNC_IOCB 0x07
2085
2086 uint8_t entry_status;
2087
2088 uint32_t handle;
2089 target_id_t loop_id;
2090
2091 uint16_t status;
2092 uint16_t state_flags;
2093 uint16_t status_flags;
2094
2095 uint32_t sys_define2[2];
2096
2097 uint16_t mb0;
2098 uint16_t mb1;
2099 uint16_t mb2;
2100 uint16_t mb3;
2101 uint16_t mb6;
2102 uint16_t mb7;
2103 uint16_t mb9;
2104 uint16_t mb10;
2105 uint32_t reserved_2[2];
2106 uint8_t node_name[WWN_SIZE];
2107 uint8_t port_name[WWN_SIZE];
2108};
2109
2110#ifndef IMMED_NOTIFY_TYPE
2111#define IMMED_NOTIFY_TYPE 0x0D
2112
2113
2114
2115
2116
2117
2118
2119struct imm_ntfy_from_isp {
2120 uint8_t entry_type;
2121 uint8_t entry_count;
2122 uint8_t sys_define;
2123 uint8_t entry_status;
2124 union {
2125 struct {
2126 uint32_t sys_define_2;
2127 target_id_t target;
2128 uint16_t lun;
2129 uint8_t target_id;
2130 uint8_t reserved_1;
2131 uint16_t status_modifier;
2132 uint16_t status;
2133 uint16_t task_flags;
2134 uint16_t seq_id;
2135 uint16_t srr_rx_id;
2136 uint32_t srr_rel_offs;
2137 uint16_t srr_ui;
2138#define SRR_IU_DATA_IN 0x1
2139#define SRR_IU_DATA_OUT 0x5
2140#define SRR_IU_STATUS 0x7
2141 uint16_t srr_ox_id;
2142 uint8_t reserved_2[28];
2143 } isp2x;
2144 struct {
2145 uint32_t reserved;
2146 uint16_t nport_handle;
2147 uint16_t reserved_2;
2148 uint16_t flags;
2149#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2150#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2151 uint16_t srr_rx_id;
2152 uint16_t status;
2153 uint8_t status_subcode;
2154 uint8_t fw_handle;
2155 uint32_t exchange_address;
2156 uint32_t srr_rel_offs;
2157 uint16_t srr_ui;
2158 uint16_t srr_ox_id;
2159 union {
2160 struct {
2161 uint8_t node_name[8];
2162 } plogi;
2163 struct {
2164
2165 uint16_t wd3_lo;
2166 uint8_t resv0[6];
2167 } prli;
2168 struct {
2169 uint8_t port_id[3];
2170 uint8_t resv1;
2171 uint16_t nport_handle;
2172 uint16_t resv2;
2173 } req_els;
2174 } u;
2175 uint8_t port_name[8];
2176 uint8_t resv3[3];
2177 uint8_t vp_index;
2178 uint32_t reserved_5;
2179 uint8_t port_id[3];
2180 uint8_t reserved_6;
2181 } isp24;
2182 } u;
2183 uint16_t reserved_7;
2184 uint16_t ox_id;
2185} __packed;
2186#endif
2187
2188
2189
2190
2191#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2192#define REQUEST_ENTRY_SIZE (sizeof(request_t))
2193
2194
2195
2196
2197
2198
2199typedef struct {
2200 port_id_t d_id;
2201 uint8_t node_name[WWN_SIZE];
2202 uint8_t port_name[WWN_SIZE];
2203 uint8_t fabric_port_name[WWN_SIZE];
2204 uint16_t fp_speed;
2205 uint8_t fc4_type;
2206 uint8_t fc4f_nvme;
2207} sw_info_t;
2208
2209
2210#define FC4_TYPE_FCP_SCSI 0x08
2211#define FC4_TYPE_NVME 0x28
2212#define FC4_TYPE_OTHER 0x0
2213#define FC4_TYPE_UNKNOWN 0xff
2214
2215
2216struct mbx_24xx_entry {
2217 uint8_t entry_type;
2218 uint8_t entry_count;
2219 uint8_t sys_define1;
2220 uint8_t entry_status;
2221 uint32_t handle;
2222 uint16_t mb[28];
2223};
2224
2225#define IOCB_SIZE 64
2226
2227
2228
2229
2230typedef enum {
2231 FCT_UNKNOWN,
2232 FCT_RSCN,
2233 FCT_SWITCH,
2234 FCT_BROADCAST,
2235 FCT_INITIATOR,
2236 FCT_TARGET,
2237 FCT_NVME_INITIATOR = 0x10,
2238 FCT_NVME_TARGET = 0x20,
2239 FCT_NVME_DISCOVERY = 0x40,
2240 FCT_NVME = 0xf0,
2241} fc_port_type_t;
2242
2243enum qla_sess_deletion {
2244 QLA_SESS_DELETION_NONE = 0,
2245 QLA_SESS_DELETION_IN_PROGRESS,
2246 QLA_SESS_DELETED,
2247};
2248
2249enum qlt_plogi_link_t {
2250 QLT_PLOGI_LINK_SAME_WWN,
2251 QLT_PLOGI_LINK_CONFLICT,
2252 QLT_PLOGI_LINK_MAX
2253};
2254
2255struct qlt_plogi_ack_t {
2256 struct list_head list;
2257 struct imm_ntfy_from_isp iocb;
2258 port_id_t id;
2259 int ref_count;
2260 void *fcport;
2261};
2262
2263struct ct_sns_desc {
2264 struct ct_sns_pkt *ct_sns;
2265 dma_addr_t ct_sns_dma;
2266};
2267
2268enum discovery_state {
2269 DSC_DELETED,
2270 DSC_GNN_ID,
2271 DSC_GNL,
2272 DSC_LOGIN_PEND,
2273 DSC_LOGIN_FAILED,
2274 DSC_GPDB,
2275 DSC_UPD_FCPORT,
2276 DSC_LOGIN_COMPLETE,
2277 DSC_ADISC,
2278 DSC_DELETE_PEND,
2279};
2280
2281enum login_state {
2282 DSC_LS_LLIOCB_SENT = 2,
2283 DSC_LS_PLOGI_PEND,
2284 DSC_LS_PLOGI_COMP,
2285 DSC_LS_PRLI_PEND,
2286 DSC_LS_PRLI_COMP,
2287 DSC_LS_PORT_UNAVAIL,
2288 DSC_LS_PRLO_PEND = 9,
2289 DSC_LS_LOGO_PEND,
2290};
2291
2292enum fcport_mgt_event {
2293 FCME_RELOGIN = 1,
2294 FCME_RSCN,
2295 FCME_PLOGI_DONE,
2296 FCME_PRLI_DONE,
2297 FCME_GNL_DONE,
2298 FCME_GPSC_DONE,
2299 FCME_GPDB_DONE,
2300 FCME_GPNID_DONE,
2301 FCME_GFFID_DONE,
2302 FCME_ADISC_DONE,
2303 FCME_GNNID_DONE,
2304 FCME_GFPNID_DONE,
2305 FCME_ELS_PLOGI_DONE,
2306};
2307
2308enum rscn_addr_format {
2309 RSCN_PORT_ADDR,
2310 RSCN_AREA_ADDR,
2311 RSCN_DOM_ADDR,
2312 RSCN_FAB_ADDR,
2313};
2314
2315
2316
2317
2318typedef struct fc_port {
2319 struct list_head list;
2320 struct scsi_qla_host *vha;
2321
2322 uint8_t node_name[WWN_SIZE];
2323 uint8_t port_name[WWN_SIZE];
2324 port_id_t d_id;
2325 uint16_t loop_id;
2326 uint16_t old_loop_id;
2327
2328 unsigned int conf_compl_supported:1;
2329 unsigned int deleted:2;
2330 unsigned int free_pending:1;
2331 unsigned int local:1;
2332 unsigned int logout_on_delete:1;
2333 unsigned int logo_ack_needed:1;
2334 unsigned int keep_nport_handle:1;
2335 unsigned int send_els_logo:1;
2336 unsigned int login_pause:1;
2337 unsigned int login_succ:1;
2338 unsigned int query:1;
2339 unsigned int id_changed:1;
2340 unsigned int scan_needed:1;
2341
2342 struct completion nvme_del_done;
2343 uint32_t nvme_prli_service_param;
2344#define NVME_PRLI_SP_CONF BIT_7
2345#define NVME_PRLI_SP_INITIATOR BIT_5
2346#define NVME_PRLI_SP_TARGET BIT_4
2347#define NVME_PRLI_SP_DISCOVERY BIT_3
2348#define NVME_PRLI_SP_FIRST_BURST BIT_0
2349 uint8_t nvme_flag;
2350 uint32_t nvme_first_burst_size;
2351#define NVME_FLAG_REGISTERED 4
2352#define NVME_FLAG_DELETING 2
2353#define NVME_FLAG_RESETTING 1
2354
2355 struct fc_port *conflict;
2356 unsigned char logout_completed;
2357 int generation;
2358
2359 struct se_session *se_sess;
2360 struct kref sess_kref;
2361 struct qla_tgt *tgt;
2362 unsigned long expires;
2363 struct list_head del_list_entry;
2364 struct work_struct free_work;
2365 struct work_struct reg_work;
2366 uint64_t jiffies_at_registration;
2367 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2368
2369 uint16_t tgt_id;
2370 uint16_t old_tgt_id;
2371 uint16_t sec_since_registration;
2372
2373 uint8_t fcp_prio;
2374
2375 uint8_t fabric_port_name[WWN_SIZE];
2376 uint16_t fp_speed;
2377
2378 fc_port_type_t port_type;
2379
2380 atomic_t state;
2381 uint32_t flags;
2382
2383 int login_retry;
2384
2385 struct fc_rport *rport, *drport;
2386 u32 supported_classes;
2387
2388 uint8_t fc4_type;
2389 uint8_t fc4f_nvme;
2390 uint8_t scan_state;
2391 uint8_t n2n_flag;
2392
2393 unsigned long last_queue_full;
2394 unsigned long last_ramp_up;
2395
2396 uint16_t port_id;
2397
2398 struct nvme_fc_remote_port *nvme_remote_port;
2399
2400 unsigned long retry_delay_timestamp;
2401 struct qla_tgt_sess *tgt_session;
2402 struct ct_sns_desc ct_desc;
2403 enum discovery_state disc_state;
2404 enum discovery_state next_disc_state;
2405 enum login_state fw_login_state;
2406 unsigned long dm_login_expire;
2407 unsigned long plogi_nack_done_deadline;
2408
2409 u32 login_gen, last_login_gen;
2410 u32 rscn_gen, last_rscn_gen;
2411 u32 chip_reset;
2412 struct list_head gnl_entry;
2413 struct work_struct del_work;
2414 u8 iocb[IOCB_SIZE];
2415 u8 current_login_state;
2416 u8 last_login_state;
2417 u16 n2n_link_reset_cnt;
2418 u16 n2n_chip_reset;
2419} fc_port_t;
2420
2421#define QLA_FCPORT_SCAN 1
2422#define QLA_FCPORT_FOUND 2
2423
2424struct event_arg {
2425 enum fcport_mgt_event event;
2426 fc_port_t *fcport;
2427 srb_t *sp;
2428 port_id_t id;
2429 u16 data[2], rc;
2430 u8 port_name[WWN_SIZE];
2431 u32 iop[2];
2432};
2433
2434#include "qla_mr.h"
2435
2436
2437
2438
2439#define FCS_UNCONFIGURED 1
2440#define FCS_DEVICE_DEAD 2
2441#define FCS_DEVICE_LOST 3
2442#define FCS_ONLINE 4
2443
2444extern const char *const port_state_str[5];
2445
2446
2447
2448
2449#define FCF_FABRIC_DEVICE BIT_0
2450#define FCF_LOGIN_NEEDED BIT_1
2451#define FCF_FCP2_DEVICE BIT_2
2452#define FCF_ASYNC_SENT BIT_3
2453#define FCF_CONF_COMP_SUPPORTED BIT_4
2454#define FCF_ASYNC_ACTIVE BIT_5
2455
2456
2457#define FC_NO_LOOP_ID 0x1000
2458
2459
2460
2461
2462
2463
2464
2465#define CT_REJECT_RESPONSE 0x8001
2466#define CT_ACCEPT_RESPONSE 0x8002
2467#define CT_REASON_INVALID_COMMAND_CODE 0x01
2468#define CT_REASON_CANNOT_PERFORM 0x09
2469#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2470#define CT_EXPL_ALREADY_REGISTERED 0x10
2471#define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2472#define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2473#define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2474#define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2475#define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2476#define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2477#define CT_EXPL_HBA_NOT_REGISTERED 0x17
2478#define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2479#define CT_EXPL_PORT_NOT_REGISTERED 0x21
2480#define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2481#define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2482
2483#define NS_N_PORT_TYPE 0x01
2484#define NS_NL_PORT_TYPE 0x02
2485#define NS_NX_PORT_TYPE 0x7F
2486
2487#define GA_NXT_CMD 0x100
2488#define GA_NXT_REQ_SIZE (16 + 4)
2489#define GA_NXT_RSP_SIZE (16 + 620)
2490
2491#define GPN_FT_CMD 0x172
2492#define GPN_FT_REQ_SIZE (16 + 4)
2493#define GNN_FT_CMD 0x173
2494#define GNN_FT_REQ_SIZE (16 + 4)
2495
2496#define GID_PT_CMD 0x1A1
2497#define GID_PT_REQ_SIZE (16 + 4)
2498
2499#define GPN_ID_CMD 0x112
2500#define GPN_ID_REQ_SIZE (16 + 4)
2501#define GPN_ID_RSP_SIZE (16 + 8)
2502
2503#define GNN_ID_CMD 0x113
2504#define GNN_ID_REQ_SIZE (16 + 4)
2505#define GNN_ID_RSP_SIZE (16 + 8)
2506
2507#define GFT_ID_CMD 0x117
2508#define GFT_ID_REQ_SIZE (16 + 4)
2509#define GFT_ID_RSP_SIZE (16 + 32)
2510
2511#define GID_PN_CMD 0x121
2512#define GID_PN_REQ_SIZE (16 + 8)
2513#define GID_PN_RSP_SIZE (16 + 4)
2514
2515#define RFT_ID_CMD 0x217
2516#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2517#define RFT_ID_RSP_SIZE 16
2518
2519#define RFF_ID_CMD 0x21F
2520#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2521#define RFF_ID_RSP_SIZE 16
2522
2523#define RNN_ID_CMD 0x213
2524#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2525#define RNN_ID_RSP_SIZE 16
2526
2527#define RSNN_NN_CMD 0x239
2528#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2529#define RSNN_NN_RSP_SIZE 16
2530
2531#define GFPN_ID_CMD 0x11C
2532#define GFPN_ID_REQ_SIZE (16 + 4)
2533#define GFPN_ID_RSP_SIZE (16 + 8)
2534
2535#define GPSC_CMD 0x127
2536#define GPSC_REQ_SIZE (16 + 8)
2537#define GPSC_RSP_SIZE (16 + 2 + 2)
2538
2539#define GFF_ID_CMD 0x011F
2540#define GFF_ID_REQ_SIZE (16 + 4)
2541#define GFF_ID_RSP_SIZE (16 + 128)
2542
2543
2544
2545
2546#define FDMI_HBA_ATTR_COUNT 9
2547#define FDMIV2_HBA_ATTR_COUNT 17
2548#define FDMI_HBA_NODE_NAME 0x1
2549#define FDMI_HBA_MANUFACTURER 0x2
2550#define FDMI_HBA_SERIAL_NUMBER 0x3
2551#define FDMI_HBA_MODEL 0x4
2552#define FDMI_HBA_MODEL_DESCRIPTION 0x5
2553#define FDMI_HBA_HARDWARE_VERSION 0x6
2554#define FDMI_HBA_DRIVER_VERSION 0x7
2555#define FDMI_HBA_OPTION_ROM_VERSION 0x8
2556#define FDMI_HBA_FIRMWARE_VERSION 0x9
2557#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2558#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2559#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2560#define FDMI_HBA_VENDOR_ID 0xd
2561#define FDMI_HBA_NUM_PORTS 0xe
2562#define FDMI_HBA_FABRIC_NAME 0xf
2563#define FDMI_HBA_BOOT_BIOS_NAME 0x10
2564#define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2565
2566struct ct_fdmi_hba_attr {
2567 uint16_t type;
2568 uint16_t len;
2569 union {
2570 uint8_t node_name[WWN_SIZE];
2571 uint8_t manufacturer[64];
2572 uint8_t serial_num[32];
2573 uint8_t model[16+1];
2574 uint8_t model_desc[80];
2575 uint8_t hw_version[32];
2576 uint8_t driver_version[32];
2577 uint8_t orom_version[16];
2578 uint8_t fw_version[32];
2579 uint8_t os_version[128];
2580 uint32_t max_ct_len;
2581 } a;
2582};
2583
2584struct ct_fdmi_hba_attributes {
2585 uint32_t count;
2586 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2587};
2588
2589struct ct_fdmiv2_hba_attr {
2590 uint16_t type;
2591 uint16_t len;
2592 union {
2593 uint8_t node_name[WWN_SIZE];
2594 uint8_t manufacturer[64];
2595 uint8_t serial_num[32];
2596 uint8_t model[16+1];
2597 uint8_t model_desc[80];
2598 uint8_t hw_version[16];
2599 uint8_t driver_version[32];
2600 uint8_t orom_version[16];
2601 uint8_t fw_version[32];
2602 uint8_t os_version[128];
2603 uint32_t max_ct_len;
2604 uint8_t sym_name[256];
2605 uint32_t vendor_id;
2606 uint32_t num_ports;
2607 uint8_t fabric_name[WWN_SIZE];
2608 uint8_t bios_name[32];
2609 uint8_t vendor_identifier[8];
2610 } a;
2611};
2612
2613struct ct_fdmiv2_hba_attributes {
2614 uint32_t count;
2615 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2616};
2617
2618
2619
2620
2621#define FDMI_PORT_ATTR_COUNT 6
2622#define FDMIV2_PORT_ATTR_COUNT 16
2623#define FDMI_PORT_FC4_TYPES 0x1
2624#define FDMI_PORT_SUPPORT_SPEED 0x2
2625#define FDMI_PORT_CURRENT_SPEED 0x3
2626#define FDMI_PORT_MAX_FRAME_SIZE 0x4
2627#define FDMI_PORT_OS_DEVICE_NAME 0x5
2628#define FDMI_PORT_HOST_NAME 0x6
2629#define FDMI_PORT_NODE_NAME 0x7
2630#define FDMI_PORT_NAME 0x8
2631#define FDMI_PORT_SYM_NAME 0x9
2632#define FDMI_PORT_TYPE 0xa
2633#define FDMI_PORT_SUPP_COS 0xb
2634#define FDMI_PORT_FABRIC_NAME 0xc
2635#define FDMI_PORT_FC4_TYPE 0xd
2636#define FDMI_PORT_STATE 0x101
2637#define FDMI_PORT_COUNT 0x102
2638#define FDMI_PORT_ID 0x103
2639
2640#define FDMI_PORT_SPEED_1GB 0x1
2641#define FDMI_PORT_SPEED_2GB 0x2
2642#define FDMI_PORT_SPEED_10GB 0x4
2643#define FDMI_PORT_SPEED_4GB 0x8
2644#define FDMI_PORT_SPEED_8GB 0x10
2645#define FDMI_PORT_SPEED_16GB 0x20
2646#define FDMI_PORT_SPEED_32GB 0x40
2647#define FDMI_PORT_SPEED_64GB 0x80
2648#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2649
2650#define FC_CLASS_2 0x04
2651#define FC_CLASS_3 0x08
2652#define FC_CLASS_2_3 0x0C
2653
2654struct ct_fdmiv2_port_attr {
2655 uint16_t type;
2656 uint16_t len;
2657 union {
2658 uint8_t fc4_types[32];
2659 uint32_t sup_speed;
2660 uint32_t cur_speed;
2661 uint32_t max_frame_size;
2662 uint8_t os_dev_name[32];
2663 uint8_t host_name[256];
2664 uint8_t node_name[WWN_SIZE];
2665 uint8_t port_name[WWN_SIZE];
2666 uint8_t port_sym_name[128];
2667 uint32_t port_type;
2668 uint32_t port_supported_cos;
2669 uint8_t fabric_name[WWN_SIZE];
2670 uint8_t port_fc4_type[32];
2671 uint32_t port_state;
2672 uint32_t num_ports;
2673 uint32_t port_id;
2674 } a;
2675};
2676
2677
2678
2679
2680struct ct_fdmiv2_port_attributes {
2681 uint32_t count;
2682 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2683};
2684
2685struct ct_fdmi_port_attr {
2686 uint16_t type;
2687 uint16_t len;
2688 union {
2689 uint8_t fc4_types[32];
2690 uint32_t sup_speed;
2691 uint32_t cur_speed;
2692 uint32_t max_frame_size;
2693 uint8_t os_dev_name[32];
2694 uint8_t host_name[256];
2695 } a;
2696};
2697
2698struct ct_fdmi_port_attributes {
2699 uint32_t count;
2700 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2701};
2702
2703
2704#define GRHL_CMD 0x100
2705#define GHAT_CMD 0x101
2706#define GRPL_CMD 0x102
2707#define GPAT_CMD 0x110
2708
2709#define RHBA_CMD 0x200
2710#define RHBA_RSP_SIZE 16
2711
2712#define RHAT_CMD 0x201
2713#define RPRT_CMD 0x210
2714
2715#define RPA_CMD 0x211
2716#define RPA_RSP_SIZE 16
2717
2718#define DHBA_CMD 0x300
2719#define DHBA_REQ_SIZE (16 + 8)
2720#define DHBA_RSP_SIZE 16
2721
2722#define DHAT_CMD 0x301
2723#define DPRT_CMD 0x310
2724#define DPA_CMD 0x311
2725
2726
2727struct ct_cmd_hdr {
2728 uint8_t revision;
2729 uint8_t in_id[3];
2730 uint8_t gs_type;
2731 uint8_t gs_subtype;
2732 uint8_t options;
2733 uint8_t reserved;
2734};
2735
2736
2737struct ct_sns_req {
2738 struct ct_cmd_hdr header;
2739 uint16_t command;
2740 uint16_t max_rsp_size;
2741 uint8_t fragment_id;
2742 uint8_t reserved[3];
2743
2744 union {
2745
2746 struct {
2747 uint8_t reserved;
2748 uint8_t port_id[3];
2749 } port_id;
2750
2751 struct {
2752 uint8_t reserved;
2753 uint8_t domain;
2754 uint8_t area;
2755 uint8_t port_type;
2756 } gpn_ft;
2757
2758 struct {
2759 uint8_t port_type;
2760 uint8_t domain;
2761 uint8_t area;
2762 uint8_t reserved;
2763 } gid_pt;
2764
2765 struct {
2766 uint8_t reserved;
2767 uint8_t port_id[3];
2768 uint8_t fc4_types[32];
2769 } rft_id;
2770
2771 struct {
2772 uint8_t reserved;
2773 uint8_t port_id[3];
2774 uint16_t reserved2;
2775 uint8_t fc4_feature;
2776 uint8_t fc4_type;
2777 } rff_id;
2778
2779 struct {
2780 uint8_t reserved;
2781 uint8_t port_id[3];
2782 uint8_t node_name[8];
2783 } rnn_id;
2784
2785 struct {
2786 uint8_t node_name[8];
2787 uint8_t name_len;
2788 uint8_t sym_node_name[255];
2789 } rsnn_nn;
2790
2791 struct {
2792 uint8_t hba_identifier[8];
2793 } ghat;
2794
2795 struct {
2796 uint8_t hba_identifier[8];
2797 uint32_t entry_count;
2798 uint8_t port_name[8];
2799 struct ct_fdmi_hba_attributes attrs;
2800 } rhba;
2801
2802 struct {
2803 uint8_t hba_identifier[8];
2804 uint32_t entry_count;
2805 uint8_t port_name[8];
2806 struct ct_fdmiv2_hba_attributes attrs;
2807 } rhba2;
2808
2809 struct {
2810 uint8_t hba_identifier[8];
2811 struct ct_fdmi_hba_attributes attrs;
2812 } rhat;
2813
2814 struct {
2815 uint8_t port_name[8];
2816 struct ct_fdmi_port_attributes attrs;
2817 } rpa;
2818
2819 struct {
2820 uint8_t port_name[8];
2821 struct ct_fdmiv2_port_attributes attrs;
2822 } rpa2;
2823
2824 struct {
2825 uint8_t port_name[8];
2826 } dhba;
2827
2828 struct {
2829 uint8_t port_name[8];
2830 } dhat;
2831
2832 struct {
2833 uint8_t port_name[8];
2834 } dprt;
2835
2836 struct {
2837 uint8_t port_name[8];
2838 } dpa;
2839
2840 struct {
2841 uint8_t port_name[8];
2842 } gpsc;
2843
2844 struct {
2845 uint8_t reserved;
2846 uint8_t port_id[3];
2847 } gff_id;
2848
2849 struct {
2850 uint8_t port_name[8];
2851 } gid_pn;
2852 } req;
2853};
2854
2855
2856struct ct_rsp_hdr {
2857 struct ct_cmd_hdr header;
2858 uint16_t response;
2859 uint16_t residual;
2860 uint8_t fragment_id;
2861 uint8_t reason_code;
2862 uint8_t explanation_code;
2863 uint8_t vendor_unique;
2864};
2865
2866struct ct_sns_gid_pt_data {
2867 uint8_t control_byte;
2868 uint8_t port_id[3];
2869};
2870
2871
2872struct ct_sns_gpnft_rsp {
2873 struct {
2874 struct ct_cmd_hdr header;
2875 uint16_t response;
2876 uint16_t residual;
2877 uint8_t fragment_id;
2878 uint8_t reason_code;
2879 uint8_t explanation_code;
2880 uint8_t vendor_unique;
2881 };
2882
2883 struct ct_sns_gpn_ft_data {
2884 u8 control_byte;
2885 u8 port_id[3];
2886 u32 reserved;
2887 u8 port_name[8];
2888 } entries[1];
2889};
2890
2891
2892struct ct_sns_rsp {
2893 struct ct_rsp_hdr header;
2894
2895 union {
2896 struct {
2897 uint8_t port_type;
2898 uint8_t port_id[3];
2899 uint8_t port_name[8];
2900 uint8_t sym_port_name_len;
2901 uint8_t sym_port_name[255];
2902 uint8_t node_name[8];
2903 uint8_t sym_node_name_len;
2904 uint8_t sym_node_name[255];
2905 uint8_t init_proc_assoc[8];
2906 uint8_t node_ip_addr[16];
2907 uint8_t class_of_service[4];
2908 uint8_t fc4_types[32];
2909 uint8_t ip_address[16];
2910 uint8_t fabric_port_name[8];
2911 uint8_t reserved;
2912 uint8_t hard_address[3];
2913 } ga_nxt;
2914
2915 struct {
2916
2917 struct ct_sns_gid_pt_data
2918 entries[MAX_FIBRE_DEVICES_MAX];
2919 } gid_pt;
2920
2921 struct {
2922 uint8_t port_name[8];
2923 } gpn_id;
2924
2925 struct {
2926 uint8_t node_name[8];
2927 } gnn_id;
2928
2929 struct {
2930 uint8_t fc4_types[32];
2931 } gft_id;
2932
2933 struct {
2934 uint32_t entry_count;
2935 uint8_t port_name[8];
2936 struct ct_fdmi_hba_attributes attrs;
2937 } ghat;
2938
2939 struct {
2940 uint8_t port_name[8];
2941 } gfpn_id;
2942
2943 struct {
2944 uint16_t speeds;
2945 uint16_t speed;
2946 } gpsc;
2947
2948#define GFF_FCP_SCSI_OFFSET 7
2949#define GFF_NVME_OFFSET 23
2950 struct {
2951 uint8_t fc4_features[128];
2952 } gff_id;
2953 struct {
2954 uint8_t reserved;
2955 uint8_t port_id[3];
2956 } gid_pn;
2957 } rsp;
2958};
2959
2960struct ct_sns_pkt {
2961 union {
2962 struct ct_sns_req req;
2963 struct ct_sns_rsp rsp;
2964 } p;
2965};
2966
2967struct ct_sns_gpnft_pkt {
2968 union {
2969 struct ct_sns_req req;
2970 struct ct_sns_gpnft_rsp rsp;
2971 } p;
2972};
2973
2974enum scan_flags_t {
2975 SF_SCANNING = BIT_0,
2976 SF_QUEUED = BIT_1,
2977};
2978
2979enum fc4type_t {
2980 FS_FC4TYPE_FCP = BIT_0,
2981 FS_FC4TYPE_NVME = BIT_1,
2982};
2983
2984struct fab_scan_rp {
2985 port_id_t id;
2986 enum fc4type_t fc4type;
2987 u8 port_name[8];
2988 u8 node_name[8];
2989};
2990
2991struct fab_scan {
2992 struct fab_scan_rp *l;
2993 u32 size;
2994 u16 scan_retry;
2995#define MAX_SCAN_RETRIES 5
2996 enum scan_flags_t scan_flags;
2997 struct delayed_work scan_work;
2998};
2999
3000
3001
3002
3003#define RFT_ID_SNS_SCMD_LEN 22
3004#define RFT_ID_SNS_CMD_SIZE 60
3005#define RFT_ID_SNS_DATA_SIZE 16
3006
3007#define RNN_ID_SNS_SCMD_LEN 10
3008#define RNN_ID_SNS_CMD_SIZE 36
3009#define RNN_ID_SNS_DATA_SIZE 16
3010
3011#define GA_NXT_SNS_SCMD_LEN 6
3012#define GA_NXT_SNS_CMD_SIZE 28
3013#define GA_NXT_SNS_DATA_SIZE (620 + 16)
3014
3015#define GID_PT_SNS_SCMD_LEN 6
3016#define GID_PT_SNS_CMD_SIZE 28
3017
3018
3019
3020
3021#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3022
3023#define GPN_ID_SNS_SCMD_LEN 6
3024#define GPN_ID_SNS_CMD_SIZE 28
3025#define GPN_ID_SNS_DATA_SIZE (8 + 16)
3026
3027#define GNN_ID_SNS_SCMD_LEN 6
3028#define GNN_ID_SNS_CMD_SIZE 28
3029#define GNN_ID_SNS_DATA_SIZE (8 + 16)
3030
3031struct sns_cmd_pkt {
3032 union {
3033 struct {
3034 uint16_t buffer_length;
3035 uint16_t reserved_1;
3036 __le64 buffer_address __packed;
3037 uint16_t subcommand_length;
3038 uint16_t reserved_2;
3039 uint16_t subcommand;
3040 uint16_t size;
3041 uint32_t reserved_3;
3042 uint8_t param[36];
3043 } cmd;
3044
3045 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3046 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3047 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3048 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3049 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3050 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3051 } p;
3052};
3053
3054struct fw_blob {
3055 char *name;
3056 uint32_t segs[4];
3057 const struct firmware *fw;
3058};
3059
3060
3061struct gid_list_info {
3062 uint8_t al_pa;
3063 uint8_t area;
3064 uint8_t domain;
3065 uint8_t loop_id_2100;
3066 uint16_t loop_id;
3067 uint16_t reserved_1;
3068};
3069
3070
3071typedef struct vport_info {
3072 uint8_t port_name[WWN_SIZE];
3073 uint8_t node_name[WWN_SIZE];
3074 int vp_id;
3075 uint16_t loop_id;
3076 unsigned long host_no;
3077 uint8_t port_id[3];
3078 int loop_state;
3079} vport_info_t;
3080
3081typedef struct vport_params {
3082 uint8_t port_name[WWN_SIZE];
3083 uint8_t node_name[WWN_SIZE];
3084 uint32_t options;
3085#define VP_OPTS_RETRY_ENABLE BIT_0
3086#define VP_OPTS_VP_DISABLE BIT_1
3087} vport_params_t;
3088
3089
3090#define VP_RET_CODE_OK 0
3091#define VP_RET_CODE_FATAL 1
3092#define VP_RET_CODE_WRONG_ID 2
3093#define VP_RET_CODE_WWPN 3
3094#define VP_RET_CODE_RESOURCES 4
3095#define VP_RET_CODE_NO_MEM 5
3096#define VP_RET_CODE_NOT_FOUND 6
3097
3098struct qla_hw_data;
3099struct rsp_que;
3100
3101
3102
3103struct isp_operations {
3104
3105 int (*pci_config) (struct scsi_qla_host *);
3106 int (*reset_chip)(struct scsi_qla_host *);
3107 int (*chip_diag) (struct scsi_qla_host *);
3108 void (*config_rings) (struct scsi_qla_host *);
3109 int (*reset_adapter)(struct scsi_qla_host *);
3110 int (*nvram_config) (struct scsi_qla_host *);
3111 void (*update_fw_options) (struct scsi_qla_host *);
3112 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3113
3114 char * (*pci_info_str) (struct scsi_qla_host *, char *);
3115 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3116
3117 irq_handler_t intr_handler;
3118 void (*enable_intrs) (struct qla_hw_data *);
3119 void (*disable_intrs) (struct qla_hw_data *);
3120
3121 int (*abort_command) (srb_t *);
3122 int (*target_reset) (struct fc_port *, uint64_t, int);
3123 int (*lun_reset) (struct fc_port *, uint64_t, int);
3124 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3125 uint8_t, uint8_t, uint16_t *, uint8_t);
3126 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3127 uint8_t, uint8_t);
3128
3129 uint16_t (*calc_req_entries) (uint16_t);
3130 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3131 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3132 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3133 uint32_t);
3134
3135 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3136 uint32_t, uint32_t);
3137 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3138 uint32_t);
3139
3140 void (*fw_dump) (struct scsi_qla_host *, int);
3141
3142 int (*beacon_on) (struct scsi_qla_host *);
3143 int (*beacon_off) (struct scsi_qla_host *);
3144 void (*beacon_blink) (struct scsi_qla_host *);
3145
3146 void *(*read_optrom)(struct scsi_qla_host *, void *,
3147 uint32_t, uint32_t);
3148 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3149 uint32_t);
3150
3151 int (*get_flash_version) (struct scsi_qla_host *, void *);
3152 int (*start_scsi) (srb_t *);
3153 int (*start_scsi_mq) (srb_t *);
3154 int (*abort_isp) (struct scsi_qla_host *);
3155 int (*iospace_config)(struct qla_hw_data *);
3156 int (*initialize_adapter)(struct scsi_qla_host *);
3157};
3158
3159
3160
3161#define QLA_MSIX_CHIP_REV_24XX 3
3162#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3163#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3164
3165#define QLA_BASE_VECTORS 2
3166#define QLA_MSIX_RSP_Q 0x01
3167#define QLA_ATIO_VECTOR 0x02
3168#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3169
3170#define QLA_MIDX_DEFAULT 0
3171#define QLA_MIDX_RSP_Q 1
3172#define QLA_PCI_MSIX_CONTROL 0xa2
3173#define QLA_83XX_PCI_MSIX_CONTROL 0x92
3174
3175struct scsi_qla_host;
3176
3177
3178#define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1
3179
3180struct qla_msix_entry {
3181 int have_irq;
3182 int in_use;
3183 uint32_t vector;
3184 uint16_t entry;
3185 char name[30];
3186 void *handle;
3187 int cpuid;
3188};
3189
3190#define WATCH_INTERVAL 1
3191
3192
3193enum qla_work_type {
3194 QLA_EVT_AEN,
3195 QLA_EVT_IDC_ACK,
3196 QLA_EVT_ASYNC_LOGIN,
3197 QLA_EVT_ASYNC_LOGOUT,
3198 QLA_EVT_ASYNC_LOGOUT_DONE,
3199 QLA_EVT_ASYNC_ADISC,
3200 QLA_EVT_UEVENT,
3201 QLA_EVT_AENFX,
3202 QLA_EVT_GPNID,
3203 QLA_EVT_UNMAP,
3204 QLA_EVT_NEW_SESS,
3205 QLA_EVT_GPDB,
3206 QLA_EVT_PRLI,
3207 QLA_EVT_GPSC,
3208 QLA_EVT_GNL,
3209 QLA_EVT_NACK,
3210 QLA_EVT_RELOGIN,
3211 QLA_EVT_ASYNC_PRLO,
3212 QLA_EVT_ASYNC_PRLO_DONE,
3213 QLA_EVT_GPNFT,
3214 QLA_EVT_GPNFT_DONE,
3215 QLA_EVT_GNNFT_DONE,
3216 QLA_EVT_GNNID,
3217 QLA_EVT_GFPNID,
3218 QLA_EVT_SP_RETRY,
3219 QLA_EVT_IIDMA,
3220 QLA_EVT_ELS_PLOGI,
3221};
3222
3223
3224struct qla_work_evt {
3225 struct list_head list;
3226 enum qla_work_type type;
3227 u32 flags;
3228#define QLA_EVT_FLAG_FREE 0x1
3229
3230 union {
3231 struct {
3232 enum fc_host_event_code code;
3233 u32 data;
3234 } aen;
3235 struct {
3236#define QLA_IDC_ACK_REGS 7
3237 uint16_t mb[QLA_IDC_ACK_REGS];
3238 } idc_ack;
3239 struct {
3240 struct fc_port *fcport;
3241#define QLA_LOGIO_LOGIN_RETRIED BIT_0
3242 u16 data[2];
3243 } logio;
3244 struct {
3245 u32 code;
3246#define QLA_UEVENT_CODE_FW_DUMP 0
3247 } uevent;
3248 struct {
3249 uint32_t evtcode;
3250 uint32_t mbx[8];
3251 uint32_t count;
3252 } aenfx;
3253 struct {
3254 srb_t *sp;
3255 } iosb;
3256 struct {
3257 port_id_t id;
3258 } gpnid;
3259 struct {
3260 port_id_t id;
3261 u8 port_name[8];
3262 u8 node_name[8];
3263 void *pla;
3264 u8 fc4_type;
3265 } new_sess;
3266 struct {
3267 fc_port_t *fcport;
3268 u8 opt;
3269 } fcport;
3270 struct {
3271 fc_port_t *fcport;
3272 u8 iocb[IOCB_SIZE];
3273 int type;
3274 } nack;
3275 struct {
3276 u8 fc4_type;
3277 srb_t *sp;
3278 } gpnft;
3279 } u;
3280};
3281
3282struct qla_chip_state_84xx {
3283 struct list_head list;
3284 struct kref kref;
3285
3286 void *bus;
3287 spinlock_t access_lock;
3288 struct mutex fw_update_mutex;
3289 uint32_t fw_update;
3290 uint32_t op_fw_version;
3291 uint32_t op_fw_size;
3292 uint32_t op_fw_seq_size;
3293 uint32_t diag_fw_version;
3294 uint32_t gold_fw_version;
3295};
3296
3297struct qla_dif_statistics {
3298 uint64_t dif_input_bytes;
3299 uint64_t dif_output_bytes;
3300 uint64_t dif_input_requests;
3301 uint64_t dif_output_requests;
3302 uint32_t dif_guard_err;
3303 uint32_t dif_ref_tag_err;
3304 uint32_t dif_app_tag_err;
3305};
3306
3307struct qla_statistics {
3308 uint32_t total_isp_aborts;
3309 uint64_t input_bytes;
3310 uint64_t output_bytes;
3311 uint64_t input_requests;
3312 uint64_t output_requests;
3313 uint32_t control_requests;
3314
3315 uint64_t jiffies_at_last_reset;
3316 uint32_t stat_max_pend_cmds;
3317 uint32_t stat_max_qfull_cmds_alloc;
3318 uint32_t stat_max_qfull_cmds_dropped;
3319
3320 struct qla_dif_statistics qla_dif_stats;
3321};
3322
3323struct bidi_statistics {
3324 unsigned long long io_count;
3325 unsigned long long transfer_bytes;
3326};
3327
3328struct qla_tc_param {
3329 struct scsi_qla_host *vha;
3330 uint32_t blk_sz;
3331 uint32_t bufflen;
3332 struct scatterlist *sg;
3333 struct scatterlist *prot_sg;
3334 struct crc_context *ctx;
3335 uint8_t *ctx_dsd_alloced;
3336};
3337
3338
3339#define MBC_INITIALIZE_MULTIQ 0x1f
3340#define QLA_QUE_PAGE 0X1000
3341#define QLA_MQ_SIZE 32
3342#define QLA_MAX_QUEUES 256
3343#define ISP_QUE_REG(ha, id) \
3344 ((ha->mqenable || IS_QLA83XX(ha) || \
3345 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3346 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3347 ((void __iomem *)ha->iobase))
3348#define QLA_REQ_QUE_ID(tag) \
3349 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3350#define QLA_DEFAULT_QUE_QOS 5
3351#define QLA_PRECONFIG_VPORTS 32
3352#define QLA_MAX_VPORTS_QLA24XX 128
3353#define QLA_MAX_VPORTS_QLA25XX 256
3354
3355struct qla_tgt_counters {
3356 uint64_t qla_core_sbt_cmd;
3357 uint64_t core_qla_que_buf;
3358 uint64_t qla_core_ret_ctio;
3359 uint64_t core_qla_snd_status;
3360 uint64_t qla_core_ret_sta_ctio;
3361 uint64_t core_qla_free_cmd;
3362 uint64_t num_q_full_sent;
3363 uint64_t num_alloc_iocb_failed;
3364 uint64_t num_term_xchg_sent;
3365};
3366
3367struct qla_qpair;
3368
3369
3370struct rsp_que {
3371 dma_addr_t dma;
3372 response_t *ring;
3373 response_t *ring_ptr;
3374 uint32_t __iomem *rsp_q_in;
3375 uint32_t __iomem *rsp_q_out;
3376 uint16_t ring_index;
3377 uint16_t out_ptr;
3378 uint16_t *in_ptr;
3379 uint16_t length;
3380 uint16_t options;
3381 uint16_t rid;
3382 uint16_t id;
3383 uint16_t vp_idx;
3384 struct qla_hw_data *hw;
3385 struct qla_msix_entry *msix;
3386 struct req_que *req;
3387 srb_t *status_srb;
3388 struct qla_qpair *qpair;
3389
3390 dma_addr_t dma_fx00;
3391 response_t *ring_fx00;
3392 uint16_t length_fx00;
3393 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3394};
3395
3396
3397struct req_que {
3398 dma_addr_t dma;
3399 request_t *ring;
3400 request_t *ring_ptr;
3401 uint32_t __iomem *req_q_in;
3402 uint32_t __iomem *req_q_out;
3403 uint16_t ring_index;
3404 uint16_t in_ptr;
3405 uint16_t *out_ptr;
3406 uint16_t cnt;
3407 uint16_t length;
3408 uint16_t options;
3409 uint16_t rid;
3410 uint16_t id;
3411 uint16_t qos;
3412 uint16_t vp_idx;
3413 struct rsp_que *rsp;
3414 srb_t **outstanding_cmds;
3415 uint32_t current_outstanding_cmd;
3416 uint16_t num_outstanding_cmds;
3417 int max_q_depth;
3418
3419 dma_addr_t dma_fx00;
3420 request_t *ring_fx00;
3421 uint16_t length_fx00;
3422 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3423};
3424
3425
3426struct qla_qpair {
3427 spinlock_t qp_lock;
3428 atomic_t ref_count;
3429 uint32_t lun_cnt;
3430
3431
3432
3433
3434 spinlock_t *qp_lock_ptr;
3435 struct scsi_qla_host *vha;
3436 u32 chip_reset;
3437
3438
3439
3440
3441
3442
3443 uint32_t online:1;
3444
3445 uint32_t difdix_supported:1;
3446 uint32_t delete_in_progress:1;
3447 uint32_t fw_started:1;
3448 uint32_t enable_class_2:1;
3449 uint32_t enable_explicit_conf:1;
3450 uint32_t use_shadow_reg:1;
3451
3452 uint16_t id;
3453 uint16_t vp_idx;
3454 mempool_t *srb_mempool;
3455
3456 struct pci_dev *pdev;
3457 void (*reqq_start_iocbs)(struct qla_qpair *);
3458
3459
3460 struct req_que *req;
3461 struct rsp_que *rsp;
3462 struct atio_que *atio;
3463 struct qla_msix_entry *msix;
3464 struct qla_hw_data *hw;
3465 struct work_struct q_work;
3466 struct list_head qp_list_elem;
3467 struct list_head hints_list;
3468 uint16_t cpuid;
3469 uint16_t retry_term_cnt;
3470 uint32_t retry_term_exchg_addr;
3471 uint64_t retry_term_jiff;
3472 struct qla_tgt_counters tgt_counters;
3473};
3474
3475
3476struct qlfc_fw {
3477 void *fw_buf;
3478 dma_addr_t fw_dma;
3479 uint32_t len;
3480};
3481
3482struct scsi_qlt_host {
3483 void *target_lport_ptr;
3484 struct mutex tgt_mutex;
3485 struct mutex tgt_host_action_mutex;
3486 struct qla_tgt *qla_tgt;
3487};
3488
3489struct qlt_hw_data {
3490
3491 uint32_t node_name_set:1;
3492
3493 dma_addr_t atio_dma;
3494 struct atio *atio_ring;
3495 struct atio *atio_ring_ptr;
3496 uint16_t atio_ring_index;
3497 uint16_t atio_q_length;
3498 uint32_t __iomem *atio_q_in;
3499 uint32_t __iomem *atio_q_out;
3500
3501 struct qla_tgt_func_tmpl *tgt_ops;
3502 struct qla_tgt_vp_map *tgt_vp_map;
3503
3504 int saved_set;
3505 uint16_t saved_exchange_count;
3506 uint32_t saved_firmware_options_1;
3507 uint32_t saved_firmware_options_2;
3508 uint32_t saved_firmware_options_3;
3509 uint8_t saved_firmware_options[2];
3510 uint8_t saved_add_firmware_options[2];
3511
3512 uint8_t tgt_node_name[WWN_SIZE];
3513
3514 struct dentry *dfs_tgt_sess;
3515 struct dentry *dfs_tgt_port_database;
3516 struct dentry *dfs_naqp;
3517
3518 struct list_head q_full_list;
3519 uint32_t num_pend_cmds;
3520 uint32_t num_qfull_cmds_alloc;
3521 uint32_t num_qfull_cmds_dropped;
3522 spinlock_t q_full_lock;
3523 uint32_t leak_exchg_thresh_hold;
3524 spinlock_t sess_lock;
3525 int num_act_qpairs;
3526#define DEFAULT_NAQP 2
3527 spinlock_t atio_lock ____cacheline_aligned;
3528 struct btree_head32 host_map;
3529};
3530
3531#define MAX_QFULL_CMDS_ALLOC 8192
3532#define Q_FULL_THRESH_HOLD_PERCENT 90
3533#define Q_FULL_THRESH_HOLD(ha) \
3534 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3535
3536#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75
3537
3538
3539
3540
3541struct qla_hw_data {
3542 struct pci_dev *pdev;
3543
3544#define SRB_MIN_REQ 128
3545 mempool_t *srb_mempool;
3546
3547 volatile struct {
3548 uint32_t mbox_int :1;
3549 uint32_t mbox_busy :1;
3550 uint32_t disable_risc_code_load :1;
3551 uint32_t enable_64bit_addressing :1;
3552 uint32_t enable_lip_reset :1;
3553 uint32_t enable_target_reset :1;
3554 uint32_t enable_lip_full_login :1;
3555 uint32_t enable_led_scheme :1;
3556
3557 uint32_t msi_enabled :1;
3558 uint32_t msix_enabled :1;
3559 uint32_t disable_serdes :1;
3560 uint32_t gpsc_supported :1;
3561 uint32_t npiv_supported :1;
3562 uint32_t pci_channel_io_perm_failure :1;
3563 uint32_t fce_enabled :1;
3564 uint32_t fac_supported :1;
3565
3566 uint32_t chip_reset_done :1;
3567 uint32_t running_gold_fw :1;
3568 uint32_t eeh_busy :1;
3569 uint32_t disable_msix_handshake :1;
3570 uint32_t fcp_prio_enabled :1;
3571 uint32_t isp82xx_fw_hung:1;
3572 uint32_t nic_core_hung:1;
3573
3574 uint32_t quiesce_owner:1;
3575 uint32_t nic_core_reset_hdlr_active:1;
3576 uint32_t nic_core_reset_owner:1;
3577 uint32_t isp82xx_no_md_cap:1;
3578 uint32_t host_shutting_down:1;
3579 uint32_t idc_compl_status:1;
3580 uint32_t mr_reset_hdlr_active:1;
3581 uint32_t mr_intr_valid:1;
3582
3583 uint32_t dport_enabled:1;
3584 uint32_t fawwpn_enabled:1;
3585 uint32_t exlogins_enabled:1;
3586 uint32_t exchoffld_enabled:1;
3587
3588 uint32_t lip_ae:1;
3589 uint32_t n2n_ae:1;
3590 uint32_t fw_started:1;
3591 uint32_t fw_init_done:1;
3592
3593 uint32_t detected_lr_sfp:1;
3594 uint32_t using_lr_setting:1;
3595 uint32_t rida_fmt2:1;
3596 uint32_t purge_mbox:1;
3597 uint32_t n2n_bigger:1;
3598 uint32_t secure_adapter:1;
3599 uint32_t secure_fw:1;
3600 } flags;
3601
3602 uint16_t max_exchg;
3603 uint16_t long_range_distance;
3604#define LR_DISTANCE_5K 1
3605#define LR_DISTANCE_10K 0
3606
3607
3608
3609
3610
3611
3612
3613
3614 spinlock_t hardware_lock ____cacheline_aligned;
3615 int bars;
3616 int mem_only;
3617 device_reg_t *iobase;
3618 resource_size_t pio_address;
3619
3620#define MIN_IOBASE_LEN 0x100
3621 dma_addr_t bar0_hdl;
3622
3623 void __iomem *cregbase;
3624 dma_addr_t bar2_hdl;
3625#define BAR0_LEN_FX00 (1024 * 1024)
3626#define BAR2_LEN_FX00 (128 * 1024)
3627
3628 uint32_t rqstq_intr_code;
3629 uint32_t mbx_intr_code;
3630 uint32_t req_que_len;
3631 uint32_t rsp_que_len;
3632 uint32_t req_que_off;
3633 uint32_t rsp_que_off;
3634
3635
3636 device_reg_t *mqiobase;
3637 device_reg_t *msixbase;
3638 uint16_t msix_count;
3639 uint8_t mqenable;
3640 struct req_que **req_q_map;
3641 struct rsp_que **rsp_q_map;
3642 struct qla_qpair **queue_pair_map;
3643 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3644 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3645 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3646 / sizeof(unsigned long)];
3647 uint8_t max_req_queues;
3648 uint8_t max_rsp_queues;
3649 uint8_t max_qpairs;
3650 uint8_t num_qpairs;
3651 struct qla_qpair *base_qpair;
3652 struct qla_npiv_entry *npiv_info;
3653 uint16_t nvram_npiv_size;
3654
3655 uint16_t switch_cap;
3656#define FLOGI_SEQ_DEL BIT_8
3657#define FLOGI_MID_SUPPORT BIT_10
3658#define FLOGI_VSAN_SUPPORT BIT_12
3659#define FLOGI_SP_SUPPORT BIT_13
3660
3661 uint8_t port_no;
3662 uint8_t exch_starvation;
3663
3664
3665 uint8_t loop_down_abort_time;
3666 atomic_t loop_down_timer;
3667 uint8_t link_down_timeout;
3668 uint16_t max_loop_id;
3669 uint16_t max_fibre_devices;
3670
3671 uint16_t fb_rev;
3672 uint16_t min_external_loopid;
3673
3674#define PORT_SPEED_UNKNOWN 0xFFFF
3675#define PORT_SPEED_1GB 0x00
3676#define PORT_SPEED_2GB 0x01
3677#define PORT_SPEED_AUTO 0x02
3678#define PORT_SPEED_4GB 0x03
3679#define PORT_SPEED_8GB 0x04
3680#define PORT_SPEED_16GB 0x05
3681#define PORT_SPEED_32GB 0x06
3682#define PORT_SPEED_64GB 0x07
3683#define PORT_SPEED_10GB 0x13
3684 uint16_t link_data_rate;
3685 uint16_t set_data_rate;
3686
3687 uint8_t current_topology;
3688 uint8_t prev_topology;
3689#define ISP_CFG_NL 1
3690#define ISP_CFG_N 2
3691#define ISP_CFG_FL 4
3692#define ISP_CFG_F 8
3693
3694 uint8_t operating_mode;
3695#define LOOP 0
3696#define P2P 1
3697#define LOOP_P2P 2
3698#define P2P_LOOP 3
3699 uint8_t interrupts_on;
3700 uint32_t isp_abort_cnt;
3701#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3702#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3703#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3704#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3705#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3706#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3707#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3708#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3709#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
3710#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
3711#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
3712#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
3713#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
3714
3715 uint32_t isp_type;
3716#define DT_ISP2100 BIT_0
3717#define DT_ISP2200 BIT_1
3718#define DT_ISP2300 BIT_2
3719#define DT_ISP2312 BIT_3
3720#define DT_ISP2322 BIT_4
3721#define DT_ISP6312 BIT_5
3722#define DT_ISP6322 BIT_6
3723#define DT_ISP2422 BIT_7
3724#define DT_ISP2432 BIT_8
3725#define DT_ISP5422 BIT_9
3726#define DT_ISP5432 BIT_10
3727#define DT_ISP2532 BIT_11
3728#define DT_ISP8432 BIT_12
3729#define DT_ISP8001 BIT_13
3730#define DT_ISP8021 BIT_14
3731#define DT_ISP2031 BIT_15
3732#define DT_ISP8031 BIT_16
3733#define DT_ISPFX00 BIT_17
3734#define DT_ISP8044 BIT_18
3735#define DT_ISP2071 BIT_19
3736#define DT_ISP2271 BIT_20
3737#define DT_ISP2261 BIT_21
3738#define DT_ISP2061 BIT_22
3739#define DT_ISP2081 BIT_23
3740#define DT_ISP2089 BIT_24
3741#define DT_ISP2281 BIT_25
3742#define DT_ISP2289 BIT_26
3743#define DT_ISP_LAST (DT_ISP2289 << 1)
3744
3745 uint32_t device_type;
3746#define DT_T10_PI BIT_25
3747#define DT_IIDMA BIT_26
3748#define DT_FWI2 BIT_27
3749#define DT_ZIO_SUPPORTED BIT_28
3750#define DT_OEM_001 BIT_29
3751#define DT_ISP2200A BIT_30
3752#define DT_EXTENDED_IDS BIT_31
3753
3754#define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3755#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3756#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3757#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3758#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3759#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3760#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3761#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3762#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3763#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3764#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3765#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3766#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3767#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3768#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3769#define IS_QLA81XX(ha) (IS_QLA8001(ha))
3770#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3771#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3772#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3773#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3774#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3775#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3776#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3777#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3778#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
3779#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
3780
3781#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3782 IS_QLA6312(ha) || IS_QLA6322(ha))
3783#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3784#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3785#define IS_QLA25XX(ha) (IS_QLA2532(ha))
3786#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3787#define IS_QLA84XX(ha) (IS_QLA8432(ha))
3788#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3789#define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
3790#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3791 IS_QLA84XX(ha))
3792#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3793 IS_QLA8031(ha) || IS_QLA8044(ha))
3794#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3795#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3796 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3797 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3798 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
3799 IS_QLA28XX(ha))
3800#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3801 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3802#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3803#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3804 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3805#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3806 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3807#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3808
3809#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3810#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3811#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3812#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3813#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3814#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3815#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3816#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3817 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3818#define IS_BIDI_CAPABLE(ha) \
3819 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3820
3821#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3822 ((ha)->fw_attributes_ext[0] & BIT_0))
3823#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3824#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3825#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3826#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3827 IS_QLA28XX(ha))
3828#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3829 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3830#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3831 IS_QLA28XX(ha))
3832#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3833#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
3834#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3835 IS_QLA28XX(ha))
3836#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3837 IS_QLA28XX(ha))
3838#define IS_EXCHG_OFFLD_CAPABLE(ha) \
3839 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3840#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3841 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3842 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3843#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
3844 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3845
3846
3847 uint8_t serial0;
3848 uint8_t serial1;
3849 uint8_t serial2;
3850
3851
3852#define MAX_NVRAM_SIZE 4096
3853#define VPD_OFFSET MAX_NVRAM_SIZE / 2
3854 uint16_t nvram_size;
3855 uint16_t nvram_base;
3856 void *nvram;
3857 uint16_t vpd_size;
3858 uint16_t vpd_base;
3859 void *vpd;
3860
3861 uint16_t loop_reset_delay;
3862 uint8_t retry_count;
3863 uint8_t login_timeout;
3864 uint16_t r_a_tov;
3865 int port_down_retry_count;
3866 uint8_t mbx_count;
3867 uint8_t aen_mbx_count;
3868 atomic_t num_pend_mbx_stage1;
3869 atomic_t num_pend_mbx_stage2;
3870 atomic_t num_pend_mbx_stage3;
3871 uint16_t frame_payload_size;
3872
3873 uint32_t login_retry_count;
3874
3875 ms_iocb_entry_t *ms_iocb;
3876 dma_addr_t ms_iocb_dma;
3877 struct ct_sns_pkt *ct_sns;
3878 dma_addr_t ct_sns_dma;
3879
3880 struct sns_cmd_pkt *sns_cmd;
3881 dma_addr_t sns_cmd_dma;
3882
3883#define SFP_DEV_SIZE 512
3884#define SFP_BLOCK_SIZE 64
3885 void *sfp_data;
3886 dma_addr_t sfp_data_dma;
3887
3888 void *flt;
3889 dma_addr_t flt_dma;
3890
3891#define XGMAC_DATA_SIZE 4096
3892 void *xgmac_data;
3893 dma_addr_t xgmac_data_dma;
3894
3895#define DCBX_TLV_DATA_SIZE 4096
3896 void *dcbx_tlv;
3897 dma_addr_t dcbx_tlv_dma;
3898
3899 struct task_struct *dpc_thread;
3900 uint8_t dpc_active;
3901
3902 dma_addr_t gid_list_dma;
3903 struct gid_list_info *gid_list;
3904 int gid_list_info_size;
3905
3906
3907#define DMA_POOL_SIZE 256
3908 struct dma_pool *s_dma_pool;
3909
3910 dma_addr_t init_cb_dma;
3911 init_cb_t *init_cb;
3912 int init_cb_size;
3913 dma_addr_t ex_init_cb_dma;
3914 struct ex_init_cb_81xx *ex_init_cb;
3915
3916 void *async_pd;
3917 dma_addr_t async_pd_dma;
3918
3919#define ENABLE_EXTENDED_LOGIN BIT_7
3920
3921
3922 void *exlogin_buf;
3923 dma_addr_t exlogin_buf_dma;
3924 int exlogin_size;
3925
3926#define ENABLE_EXCHANGE_OFFLD BIT_2
3927
3928
3929 void *exchoffld_buf;
3930 dma_addr_t exchoffld_buf_dma;
3931 int exchoffld_size;
3932 int exchoffld_count;
3933
3934
3935 struct els_plogi_payload plogi_els_payld;
3936
3937 void *swl;
3938
3939
3940 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3941 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3942 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3943
3944 mbx_cmd_t *mcp;
3945 struct mbx_cmd_32 *mcp32;
3946
3947 unsigned long mbx_cmd_flags;
3948#define MBX_INTERRUPT 1
3949#define MBX_INTR_WAIT 2
3950#define MBX_UPDATE_FLASH_ACTIVE 3
3951
3952 struct mutex vport_lock;
3953 spinlock_t vport_slock;
3954 struct mutex mq_lock;
3955 struct completion mbx_cmd_comp;
3956 struct completion mbx_intr_comp;
3957 struct completion dcbx_comp;
3958 struct completion lb_portup_comp;
3959
3960#define DCBX_COMP_TIMEOUT 20
3961#define LB_PORTUP_COMP_TIMEOUT 10
3962
3963 int notify_dcbx_comp;
3964 int notify_lb_portup_comp;
3965 struct mutex selflogin_lock;
3966
3967
3968 uint16_t fw_major_version;
3969 uint16_t fw_minor_version;
3970 uint16_t fw_subminor_version;
3971 uint16_t fw_attributes;
3972 uint16_t fw_attributes_h;
3973#define FW_ATTR_H_NVME_FBURST BIT_1
3974#define FW_ATTR_H_NVME BIT_10
3975#define FW_ATTR_H_NVME_UPDATED BIT_14
3976
3977 uint16_t fw_attributes_ext[2];
3978 uint32_t fw_memory_size;
3979 uint32_t fw_transfer_size;
3980 uint32_t fw_srisc_address;
3981#define RISC_START_ADDRESS_2100 0x1000
3982#define RISC_START_ADDRESS_2300 0x800
3983#define RISC_START_ADDRESS_2400 0x100000
3984
3985 uint16_t orig_fw_tgt_xcb_count;
3986 uint16_t cur_fw_tgt_xcb_count;
3987 uint16_t orig_fw_xcb_count;
3988 uint16_t cur_fw_xcb_count;
3989 uint16_t orig_fw_iocb_count;
3990 uint16_t cur_fw_iocb_count;
3991 uint16_t fw_max_fcf_count;
3992
3993 uint32_t fw_shared_ram_start;
3994 uint32_t fw_shared_ram_end;
3995 uint32_t fw_ddr_ram_start;
3996 uint32_t fw_ddr_ram_end;
3997
3998 uint16_t fw_options[16];
3999 uint8_t fw_seriallink_options[4];
4000 uint16_t fw_seriallink_options24[4];
4001
4002 uint8_t serdes_version[3];
4003 uint8_t mpi_version[3];
4004 uint32_t mpi_capabilities;
4005 uint8_t phy_version[3];
4006 uint8_t pep_version[3];
4007
4008
4009 struct fwdt {
4010 void *template;
4011 ulong length;
4012 ulong dump_size;
4013 } fwdt[2];
4014 struct qla2xxx_fw_dump *fw_dump;
4015 uint32_t fw_dump_len;
4016 u32 fw_dump_alloc_len;
4017 bool fw_dumped;
4018 bool fw_dump_mpi;
4019 unsigned long fw_dump_cap_flags;
4020#define RISC_PAUSE_CMPL 0
4021#define DMA_SHUTDOWN_CMPL 1
4022#define ISP_RESET_CMPL 2
4023#define RISC_RDY_AFT_RESET 3
4024#define RISC_SRAM_DUMP_CMPL 4
4025#define RISC_EXT_MEM_DUMP_CMPL 5
4026#define ISP_MBX_RDY 6
4027#define ISP_SOFT_RESET_CMPL 7
4028 int fw_dump_reading;
4029 int prev_minidump_failed;
4030 dma_addr_t eft_dma;
4031 void *eft;
4032
4033#define MCTP_DUMP_SIZE 0x086064
4034 dma_addr_t mctp_dump_dma;
4035 void *mctp_dump;
4036 int mctp_dumped;
4037 int mctp_dump_reading;
4038 uint32_t chain_offset;
4039 struct dentry *dfs_dir;
4040 struct dentry *dfs_fce;
4041 struct dentry *dfs_tgt_counters;
4042 struct dentry *dfs_fw_resource_cnt;
4043
4044 dma_addr_t fce_dma;
4045 void *fce;
4046 uint32_t fce_bufs;
4047 uint16_t fce_mb[8];
4048 uint64_t fce_wr, fce_rd;
4049 struct mutex fce_mutex;
4050
4051 uint32_t pci_attr;
4052 uint16_t chip_revision;
4053
4054 uint16_t product_id[4];
4055
4056 uint8_t model_number[16+1];
4057 char model_desc[80];
4058 uint8_t adapter_id[16+1];
4059
4060
4061 char *optrom_buffer;
4062 uint32_t optrom_size;
4063 int optrom_state;
4064#define QLA_SWAITING 0
4065#define QLA_SREADING 1
4066#define QLA_SWRITING 2
4067 uint32_t optrom_region_start;
4068 uint32_t optrom_region_size;
4069 struct mutex optrom_mutex;
4070
4071
4072#define ROM_CODE_TYPE_BIOS 0
4073#define ROM_CODE_TYPE_FCODE 1
4074#define ROM_CODE_TYPE_EFI 3
4075 uint8_t bios_revision[2];
4076 uint8_t efi_revision[2];
4077 uint8_t fcode_revision[16];
4078 uint32_t fw_revision[4];
4079
4080 uint32_t gold_fw_version[4];
4081
4082
4083 uint32_t flash_conf_off;
4084 uint32_t flash_data_off;
4085 uint32_t nvram_conf_off;
4086 uint32_t nvram_data_off;
4087
4088 uint32_t fdt_wrt_disable;
4089 uint32_t fdt_wrt_enable;
4090 uint32_t fdt_erase_cmd;
4091 uint32_t fdt_block_size;
4092 uint32_t fdt_unprotect_sec_cmd;
4093 uint32_t fdt_protect_sec_cmd;
4094 uint32_t fdt_wrt_sts_reg_cmd;
4095
4096 struct {
4097 uint32_t flt_region_flt;
4098 uint32_t flt_region_fdt;
4099 uint32_t flt_region_boot;
4100 uint32_t flt_region_boot_sec;
4101 uint32_t flt_region_fw;
4102 uint32_t flt_region_fw_sec;
4103 uint32_t flt_region_vpd_nvram;
4104 uint32_t flt_region_vpd_nvram_sec;
4105 uint32_t flt_region_vpd;
4106 uint32_t flt_region_vpd_sec;
4107 uint32_t flt_region_nvram;
4108 uint32_t flt_region_nvram_sec;
4109 uint32_t flt_region_npiv_conf;
4110 uint32_t flt_region_gold_fw;
4111 uint32_t flt_region_fcp_prio;
4112 uint32_t flt_region_bootload;
4113 uint32_t flt_region_img_status_pri;
4114 uint32_t flt_region_img_status_sec;
4115 uint32_t flt_region_aux_img_status_pri;
4116 uint32_t flt_region_aux_img_status_sec;
4117 };
4118 uint8_t active_image;
4119
4120
4121 uint16_t beacon_blink_led;
4122 uint8_t beacon_color_state;
4123#define QLA_LED_GRN_ON 0x01
4124#define QLA_LED_YLW_ON 0x02
4125#define QLA_LED_ABR_ON 0x04
4126#define QLA_LED_ALL_ON 0x07
4127
4128 uint16_t zio_mode;
4129 uint16_t zio_timer;
4130
4131 struct qla_msix_entry *msix_entries;
4132
4133 struct list_head vp_list;
4134 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4135 sizeof(unsigned long)];
4136 uint16_t num_vhosts;
4137 uint16_t num_vsans;
4138 uint16_t max_npiv_vports;
4139 int cur_vport_count;
4140
4141 struct qla_chip_state_84xx *cs84xx;
4142 struct isp_operations *isp_ops;
4143 struct workqueue_struct *wq;
4144 struct qlfc_fw fw_buf;
4145
4146
4147 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4148
4149 struct dma_pool *dl_dma_pool;
4150#define DSD_LIST_DMA_POOL_SIZE 512
4151
4152 struct dma_pool *fcp_cmnd_dma_pool;
4153 mempool_t *ctx_mempool;
4154#define FCP_CMND_DMA_POOL_SIZE 512
4155
4156 void __iomem *nx_pcibase;
4157 void __iomem *nxdb_rd_ptr;
4158 void __iomem *nxdb_wr_ptr;
4159
4160 uint32_t crb_win;
4161 uint32_t curr_window;
4162 uint32_t ddr_mn_window;
4163 unsigned long mn_win_crb;
4164 unsigned long ms_win_crb;
4165 int qdr_sn_window;
4166 uint32_t fcoe_dev_init_timeout;
4167 uint32_t fcoe_reset_timeout;
4168 rwlock_t hw_lock;
4169 uint16_t portnum;
4170 int link_width;
4171 struct fw_blob *hablob;
4172 struct qla82xx_legacy_intr_set nx_legacy_intr;
4173
4174 uint16_t gbl_dsd_inuse;
4175 uint16_t gbl_dsd_avail;
4176 struct list_head gbl_dsd_list;
4177#define NUM_DSD_CHAIN 4096
4178
4179 uint8_t fw_type;
4180 __le32 file_prd_off;
4181
4182 uint32_t md_template_size;
4183 void *md_tmplt_hdr;
4184 dma_addr_t md_tmplt_hdr_dma;
4185 void *md_dump;
4186 uint32_t md_dump_size;
4187
4188 void *loop_id_map;
4189
4190
4191 uint32_t idc_audit_ts;
4192 uint32_t idc_extend_tmo;
4193
4194
4195 struct workqueue_struct *dpc_lp_wq;
4196 struct work_struct idc_aen;
4197
4198 struct workqueue_struct *dpc_hp_wq;
4199 struct work_struct nic_core_reset;
4200 struct work_struct idc_state_handler;
4201 struct work_struct nic_core_unrecoverable;
4202 struct work_struct board_disable;
4203
4204 struct mr_data_fx00 mr;
4205 uint32_t chip_reset;
4206
4207 struct qlt_hw_data tgt;
4208 int allow_cna_fw_dump;
4209 uint32_t fw_ability_mask;
4210 uint16_t min_supported_speed;
4211 uint16_t max_supported_speed;
4212
4213
4214 struct dma_pool *dif_bundl_pool;
4215 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4216 struct {
4217 struct {
4218 struct list_head head;
4219 uint count;
4220 } good;
4221 struct {
4222 struct list_head head;
4223 uint count;
4224 } unusable;
4225 } pool;
4226
4227 unsigned long long dif_bundle_crossed_pages;
4228 unsigned long long dif_bundle_reads;
4229 unsigned long long dif_bundle_writes;
4230 unsigned long long dif_bundle_kallocs;
4231 unsigned long long dif_bundle_dma_allocs;
4232
4233 atomic_t nvme_active_aen_cnt;
4234 uint16_t nvme_last_rptd_aen;
4235
4236 atomic_t zio_threshold;
4237 uint16_t last_zio_threshold;
4238
4239#define DEFAULT_ZIO_THRESHOLD 5
4240};
4241
4242struct active_regions {
4243 uint8_t global;
4244 struct {
4245 uint8_t board_config;
4246 uint8_t vpd_nvram;
4247 uint8_t npiv_config_0_1;
4248 uint8_t npiv_config_2_3;
4249 } aux;
4250};
4251
4252#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4253#define FW_ABILITY_MAX_SPEED_16G 0x0
4254#define FW_ABILITY_MAX_SPEED_32G 0x1
4255#define FW_ABILITY_MAX_SPEED(ha) \
4256 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4257
4258#define QLA_GET_DATA_RATE 0
4259#define QLA_SET_DATA_RATE_NOLR 1
4260#define QLA_SET_DATA_RATE_LR 2
4261
4262
4263
4264
4265typedef struct scsi_qla_host {
4266 struct list_head list;
4267 struct list_head vp_fcports;
4268 struct list_head work_list;
4269 spinlock_t work_lock;
4270 struct work_struct iocb_work;
4271
4272
4273 struct Scsi_Host *host;
4274 unsigned long host_no;
4275 uint8_t host_str[16];
4276
4277 volatile struct {
4278 uint32_t init_done :1;
4279 uint32_t online :1;
4280 uint32_t reset_active :1;
4281
4282 uint32_t management_server_logged_in :1;
4283 uint32_t process_response_queue :1;
4284 uint32_t difdix_supported:1;
4285 uint32_t delete_progress:1;
4286
4287 uint32_t fw_tgt_reported:1;
4288 uint32_t bbcr_enable:1;
4289 uint32_t qpairs_available:1;
4290 uint32_t qpairs_req_created:1;
4291 uint32_t qpairs_rsp_created:1;
4292 uint32_t nvme_enabled:1;
4293 uint32_t nvme_first_burst:1;
4294 } flags;
4295
4296 atomic_t loop_state;
4297#define LOOP_TIMEOUT 1
4298#define LOOP_DOWN 2
4299#define LOOP_UP 3
4300#define LOOP_UPDATE 4
4301#define LOOP_READY 5
4302#define LOOP_DEAD 6
4303
4304 unsigned long relogin_jif;
4305 unsigned long dpc_flags;
4306#define RESET_MARKER_NEEDED 0
4307#define RESET_ACTIVE 1
4308#define ISP_ABORT_NEEDED 2
4309#define ABORT_ISP_ACTIVE 3
4310#define LOOP_RESYNC_NEEDED 4
4311#define LOOP_RESYNC_ACTIVE 5
4312#define LOCAL_LOOP_UPDATE 6
4313#define RSCN_UPDATE 7
4314#define RELOGIN_NEEDED 8
4315#define REGISTER_FC4_NEEDED 9
4316#define ISP_ABORT_RETRY 10
4317#define BEACON_BLINK_NEEDED 11
4318#define REGISTER_FDMI_NEEDED 12
4319#define FCPORT_UPDATE_NEEDED 13
4320#define VP_DPC_NEEDED 14
4321#define UNLOADING 15
4322#define NPIV_CONFIG_NEEDED 16
4323#define ISP_UNRECOVERABLE 17
4324#define FCOE_CTX_RESET_NEEDED 18
4325#define MPI_RESET_NEEDED 19
4326#define ISP_QUIESCE_NEEDED 20
4327#define N2N_LINK_RESET 21
4328#define PORT_UPDATE_NEEDED 22
4329#define FX00_RESET_RECOVERY 23
4330#define FX00_TARGET_SCAN 24
4331#define FX00_CRITEMP_RECOVERY 25
4332#define FX00_HOST_INFO_RESEND 26
4333#define QPAIR_ONLINE_CHECK_NEEDED 27
4334#define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4335#define DETECT_SFP_CHANGE 29
4336#define N2N_LOGIN_NEEDED 30
4337#define IOCB_WORK_ACTIVE 31
4338#define SET_ZIO_THRESHOLD_NEEDED 32
4339#define ISP_ABORT_TO_ROM 33
4340
4341 unsigned long pci_flags;
4342#define PFLG_DISCONNECTED 0
4343#define PFLG_DRIVER_REMOVING 1
4344#define PFLG_DRIVER_PROBING 2
4345
4346 uint32_t device_flags;
4347#define SWITCH_FOUND BIT_0
4348#define DFLG_NO_CABLE BIT_1
4349#define DFLG_DEV_FAILED BIT_5
4350
4351
4352 uint16_t loop_id;
4353 uint16_t self_login_loop_id;
4354
4355
4356 fc_port_t bidir_fcport;
4357
4358
4359
4360
4361 port_id_t d_id;
4362 uint8_t marker_needed;
4363 uint16_t mgmt_svr_loop_id;
4364
4365
4366
4367
4368 uint8_t loop_down_abort_time;
4369 atomic_t loop_down_timer;
4370 uint8_t link_down_timeout;
4371
4372 uint32_t timer_active;
4373 struct timer_list timer;
4374
4375 uint8_t node_name[WWN_SIZE];
4376 uint8_t port_name[WWN_SIZE];
4377 uint8_t fabric_node_name[WWN_SIZE];
4378
4379 struct nvme_fc_local_port *nvme_local_port;
4380 struct completion nvme_del_done;
4381
4382 uint16_t fcoe_vlan_id;
4383 uint16_t fcoe_fcf_idx;
4384 uint8_t fcoe_vn_port_mac[6];
4385
4386
4387 struct list_head qla_cmd_list;
4388 struct list_head qla_sess_op_cmd_list;
4389 struct list_head unknown_atio_list;
4390 spinlock_t cmd_list_lock;
4391 struct delayed_work unknown_atio_work;
4392
4393
4394 atomic_t generation_tick;
4395
4396 int total_fcport_update_gen;
4397
4398 struct list_head logo_list;
4399
4400 struct list_head plogi_ack_list;
4401
4402 struct list_head qp_list;
4403
4404 uint32_t vp_abort_cnt;
4405
4406 struct fc_vport *fc_vport;
4407 uint16_t vp_idx;
4408 struct qla_qpair *qpair;
4409
4410 unsigned long vp_flags;
4411#define VP_IDX_ACQUIRED 0
4412#define VP_CREATE_NEEDED 1
4413#define VP_BIND_NEEDED 2
4414#define VP_DELETE_NEEDED 3
4415#define VP_SCR_NEEDED 4
4416#define VP_CONFIG_OK 5
4417 atomic_t vp_state;
4418#define VP_OFFLINE 0
4419#define VP_ACTIVE 1
4420#define VP_FAILED 2
4421
4422 uint16_t vp_err_state;
4423 uint16_t vp_prev_err_state;
4424#define VP_ERR_UNKWN 0
4425#define VP_ERR_PORTDWN 1
4426#define VP_ERR_FAB_UNSUPPORTED 2
4427#define VP_ERR_FAB_NORESOURCES 3
4428#define VP_ERR_FAB_LOGOUT 4
4429#define VP_ERR_ADAP_NORESOURCES 5
4430 struct qla_hw_data *hw;
4431 struct scsi_qlt_host vha_tgt;
4432 struct req_que *req;
4433 int fw_heartbeat_counter;
4434 int seconds_since_last_heartbeat;
4435 struct fc_host_statistics fc_host_stat;
4436 struct qla_statistics qla_stats;
4437 struct bidi_statistics bidi_stats;
4438 atomic_t vref_count;
4439 struct qla8044_reset_template reset_tmplt;
4440 uint16_t bbcr;
4441
4442 uint16_t u_ql2xexchoffld;
4443 uint16_t u_ql2xiniexchg;
4444 uint16_t qlini_mode;
4445 uint16_t ql2xexchoffld;
4446 uint16_t ql2xiniexchg;
4447
4448 struct name_list_extended gnl;
4449
4450 int fcport_count;
4451 wait_queue_head_t fcport_waitQ;
4452 wait_queue_head_t vref_waitq;
4453 uint8_t min_supported_speed;
4454 uint8_t n2n_node_name[WWN_SIZE];
4455 uint8_t n2n_port_name[WWN_SIZE];
4456 uint16_t n2n_id;
4457 struct list_head gpnid_list;
4458 struct fab_scan scan;
4459
4460 unsigned int irq_offset;
4461} scsi_qla_host_t;
4462
4463struct qla27xx_image_status {
4464 uint8_t image_status_mask;
4465 uint16_t generation;
4466 uint8_t ver_major;
4467 uint8_t ver_minor;
4468 uint8_t bitmap;
4469 uint8_t reserved[2];
4470 uint32_t checksum;
4471 uint32_t signature;
4472} __packed;
4473
4474
4475#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4476#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4477#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4478#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4479
4480#define SET_VP_IDX 1
4481#define SET_AL_PA 2
4482#define RESET_VP_IDX 3
4483#define RESET_AL_PA 4
4484struct qla_tgt_vp_map {
4485 uint8_t idx;
4486 scsi_qla_host_t *vha;
4487};
4488
4489struct qla2_sgx {
4490 dma_addr_t dma_addr;
4491 uint32_t dma_len;
4492
4493 uint32_t tot_bytes;
4494 struct scatterlist *cur_sg;
4495
4496
4497 uint32_t bytes_consumed;
4498 uint32_t num_bytes;
4499 uint32_t tot_partial;
4500
4501
4502 uint32_t num_sg;
4503 srb_t *sp;
4504};
4505
4506#define QLA_FW_STARTED(_ha) { \
4507 int i; \
4508 _ha->flags.fw_started = 1; \
4509 _ha->base_qpair->fw_started = 1; \
4510 for (i = 0; i < _ha->max_qpairs; i++) { \
4511 if (_ha->queue_pair_map[i]) \
4512 _ha->queue_pair_map[i]->fw_started = 1; \
4513 } \
4514}
4515
4516#define QLA_FW_STOPPED(_ha) { \
4517 int i; \
4518 _ha->flags.fw_started = 0; \
4519 _ha->base_qpair->fw_started = 0; \
4520 for (i = 0; i < _ha->max_qpairs; i++) { \
4521 if (_ha->queue_pair_map[i]) \
4522 _ha->queue_pair_map[i]->fw_started = 0; \
4523 } \
4524}
4525
4526
4527#define SFUB_CHECKSUM_SIZE 4
4528
4529struct secure_flash_update_block {
4530 uint32_t block_info;
4531 uint32_t signature_lo;
4532 uint32_t signature_hi;
4533 uint32_t signature_upper[0x3e];
4534};
4535
4536struct secure_flash_update_block_pk {
4537 uint32_t block_info;
4538 uint32_t signature_lo;
4539 uint32_t signature_hi;
4540 uint32_t signature_upper[0x3e];
4541 uint32_t public_key[0x41];
4542};
4543
4544
4545
4546
4547#define LOOP_TRANSITION(ha) \
4548 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4549 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4550 atomic_read(&ha->loop_state) == LOOP_DOWN)
4551
4552#define STATE_TRANSITION(ha) \
4553 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4554 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4555
4556#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4557 atomic_inc(&__vha->vref_count); \
4558 mb(); \
4559 if (__vha->flags.delete_progress) { \
4560 atomic_dec(&__vha->vref_count); \
4561 wake_up(&__vha->vref_waitq); \
4562 __bail = 1; \
4563 } else { \
4564 __bail = 0; \
4565 } \
4566} while (0)
4567
4568#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4569 atomic_dec(&__vha->vref_count); \
4570 wake_up(&__vha->vref_waitq); \
4571} while (0) \
4572
4573#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4574 atomic_inc(&__qpair->ref_count); \
4575 mb(); \
4576 if (__qpair->delete_in_progress) { \
4577 atomic_dec(&__qpair->ref_count); \
4578 __bail = 1; \
4579 } else { \
4580 __bail = 0; \
4581 } \
4582} while (0)
4583
4584#define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4585 atomic_dec(&__qpair->ref_count); \
4586
4587
4588#define QLA_ENA_CONF(_ha) {\
4589 int i;\
4590 _ha->base_qpair->enable_explicit_conf = 1; \
4591 for (i = 0; i < _ha->max_qpairs; i++) { \
4592 if (_ha->queue_pair_map[i]) \
4593 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4594 } \
4595}
4596
4597#define QLA_DIS_CONF(_ha) {\
4598 int i;\
4599 _ha->base_qpair->enable_explicit_conf = 0; \
4600 for (i = 0; i < _ha->max_qpairs; i++) { \
4601 if (_ha->queue_pair_map[i]) \
4602 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4603 } \
4604}
4605
4606
4607
4608
4609#define MBS_MASK 0x3fff
4610
4611#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4612#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4613#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4614#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4615#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4616#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4617#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4618#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4619#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4620#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4621
4622#define QLA_FUNCTION_TIMEOUT 0x100
4623#define QLA_FUNCTION_PARAMETER_ERROR 0x101
4624#define QLA_FUNCTION_FAILED 0x102
4625#define QLA_MEMORY_ALLOC_FAILED 0x103
4626#define QLA_LOCK_TIMEOUT 0x104
4627#define QLA_ABORTED 0x105
4628#define QLA_SUSPENDED 0x106
4629#define QLA_BUSY 0x107
4630#define QLA_ALREADY_REGISTERED 0x109
4631
4632#define NVRAM_DELAY() udelay(10)
4633
4634
4635
4636
4637#define OPTROM_SIZE_2300 0x20000
4638#define OPTROM_SIZE_2322 0x100000
4639#define OPTROM_SIZE_24XX 0x100000
4640#define OPTROM_SIZE_25XX 0x200000
4641#define OPTROM_SIZE_81XX 0x400000
4642#define OPTROM_SIZE_82XX 0x800000
4643#define OPTROM_SIZE_83XX 0x1000000
4644#define OPTROM_SIZE_28XX 0x2000000
4645
4646#define OPTROM_BURST_SIZE 0x1000
4647#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4648
4649#define QLA_DSDS_PER_IOCB 37
4650
4651#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4652
4653#define QLA_SG_ALL 1024
4654
4655enum nexus_wait_type {
4656 WAIT_HOST = 0,
4657 WAIT_TARGET,
4658 WAIT_LUN,
4659};
4660
4661
4662struct sff_8247_a0 {
4663 u8 txid;
4664 u8 ext_txid;
4665 u8 connector;
4666
4667 u8 eth_infi_cc3;
4668 u8 sonet_cc4[2];
4669 u8 eth_cc6;
4670
4671#define FC_LL_VL BIT_7
4672#define FC_LL_S BIT_6
4673#define FC_LL_I BIT_5
4674#define FC_LL_L BIT_4
4675#define FC_LL_M BIT_3
4676#define FC_LL_SA BIT_2
4677#define FC_LL_LC BIT_1
4678#define FC_LL_EL BIT_0
4679 u8 fc_ll_cc7;
4680
4681#define FC_TEC_EL BIT_7
4682#define FC_TEC_SN BIT_6
4683#define FC_TEC_SL BIT_5
4684#define FC_TEC_LL BIT_4
4685#define FC_TEC_ACT BIT_3
4686#define FC_TEC_PAS BIT_2
4687 u8 fc_tec_cc8;
4688
4689#define FC_MED_TW BIT_7
4690#define FC_MED_TP BIT_6
4691#define FC_MED_MI BIT_5
4692#define FC_MED_TV BIT_4
4693#define FC_MED_M6 BIT_3
4694#define FC_MED_M5 BIT_2
4695#define FC_MED_SM BIT_0
4696 u8 fc_med_cc9;
4697
4698#define FC_SP_12 BIT_7
4699#define FC_SP_8 BIT_6
4700#define FC_SP_16 BIT_5
4701#define FC_SP_4 BIT_4
4702#define FC_SP_32 BIT_3
4703#define FC_SP_2 BIT_2
4704#define FC_SP_1 BIT_0
4705 u8 fc_sp_cc10;
4706 u8 encode;
4707 u8 bitrate;
4708 u8 rate_id;
4709 u8 length_km;
4710 u8 length_100m;
4711 u8 length_50um_10m;
4712 u8 length_62um_10m;
4713 u8 length_om4_10m;
4714 u8 length_om3_10m;
4715#define SFF_VEN_NAME_LEN 16
4716 u8 vendor_name[SFF_VEN_NAME_LEN];
4717 u8 tx_compat;
4718 u8 vendor_oui[3];
4719#define SFF_PART_NAME_LEN 16
4720 u8 vendor_pn[SFF_PART_NAME_LEN];
4721 u8 vendor_rev[4];
4722 u8 wavelength[2];
4723 u8 resv;
4724 u8 cc_base;
4725 u8 options[2];
4726 u8 br_max;
4727 u8 br_min;
4728 u8 vendor_sn[16];
4729 u8 date_code[8];
4730 u8 diag;
4731 u8 enh_options;
4732 u8 sff_revision;
4733 u8 cc_ext;
4734 u8 vendor_specific[32];
4735 u8 resv2[128];
4736};
4737
4738#define AUTO_DETECT_SFP_SUPPORT(_vha)\
4739 (ql2xautodetectsfp && !_vha->vp_idx && \
4740 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4741 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw) || \
4742 IS_QLA28XX(_vha->hw)))
4743
4744#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
4745
4746#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4747 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
4748
4749#define SAVE_TOPO(_ha) { \
4750 if (_ha->current_topology) \
4751 _ha->prev_topology = _ha->current_topology; \
4752}
4753
4754#define N2N_TOPO(ha) \
4755 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
4756 ha->current_topology == ISP_CFG_N || \
4757 !ha->current_topology)
4758
4759#include "qla_target.h"
4760#include "qla_gbl.h"
4761#include "qla_dbg.h"
4762#include "qla_inline.h"
4763#endif
4764