LXR linux/drivers/scsi/qla2xxx/qla

   1/*
   2 * QLogic Fibre Channel HBA Driver
   3 * Copyright (c)  2003-2014 QLogic Corporation
   4 *
   5 * See LICENSE.qla2xxx for copyright and licensing details.
   6 */
   7#ifndef __QLA_FW_H
   8#define __QLA_FW_H
   9
  10#include <linux/nvme.h>
  11#include <linux/nvme-fc.h>
  12
  13#include "qla_dsd.h"
  14
  15#define MBS_CHECKSUM_ERROR      0x4010
  16#define MBS_INVALID_PRODUCT_KEY 0x4020
  17
  18/*
  19 * Firmware Options.
  20 */
  21#define FO1_ENABLE_PUREX        BIT_10
  22#define FO1_DISABLE_LED_CTRL    BIT_6
  23#define FO1_ENABLE_8016         BIT_0
  24#define FO2_ENABLE_SEL_CLASS2   BIT_5
  25#define FO3_NO_ABTS_ON_LINKDOWN BIT_14
  26#define FO3_HOLD_STS_IOCB       BIT_12
  27
  28/*
  29 * Port Database structure definition for ISP 24xx.
  30 */
  31#define PDO_FORCE_ADISC         BIT_1
  32#define PDO_FORCE_PLOGI         BIT_0
  33
  34
  35#define PORT_DATABASE_24XX_SIZE         64
  36struct port_database_24xx {
  37        uint16_t flags;
  38#define PDF_TASK_RETRY_ID       BIT_14
  39#define PDF_FC_TAPE             BIT_7
  40#define PDF_ACK0_CAPABLE        BIT_6
  41#define PDF_FCP2_CONF           BIT_5
  42#define PDF_CLASS_2             BIT_4
  43#define PDF_HARD_ADDR           BIT_1
  44
  45        /*
  46         * for NVMe, the login_state field has been
  47         * split into nibbles.
  48         * The lower nibble is for FCP.
  49         * The upper nibble is for NVMe.
  50         */
  51        uint8_t current_login_state;
  52        uint8_t last_login_state;
  53#define PDS_PLOGI_PENDING       0x03
  54#define PDS_PLOGI_COMPLETE      0x04
  55#define PDS_PRLI_PENDING        0x05
  56#define PDS_PRLI_COMPLETE       0x06
  57#define PDS_PORT_UNAVAILABLE    0x07
  58#define PDS_PRLO_PENDING        0x09
  59#define PDS_LOGO_PENDING        0x11
  60#define PDS_PRLI2_PENDING       0x12
  61
  62        uint8_t hard_address[3];
  63        uint8_t reserved_1;
  64
  65        uint8_t port_id[3];
  66        uint8_t sequence_id;
  67
  68        uint16_t port_timer;
  69
  70        uint16_t nport_handle;                  /* N_PORT handle. */
  71
  72        uint16_t receive_data_size;
  73        uint16_t reserved_2;
  74
  75        uint8_t prli_svc_param_word_0[2];       /* Big endian */
  76                                                /* Bits 15-0 of word 0 */
  77        uint8_t prli_svc_param_word_3[2];       /* Big endian */
  78                                                /* Bits 15-0 of word 3 */
  79
  80        uint8_t port_name[WWN_SIZE];
  81        uint8_t node_name[WWN_SIZE];
  82
  83        uint8_t reserved_3[4];
  84        uint16_t prli_nvme_svc_param_word_0;    /* Bits 15-0 of word 0 */
  85        uint16_t prli_nvme_svc_param_word_3;    /* Bits 15-0 of word 3 */
  86        uint16_t nvme_first_burst_size;
  87        uint8_t reserved_4[14];
  88};
  89
  90/*
  91 * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
  92 * However, in this case it returns 1st 40 bytes.
  93 */
  94struct get_name_list_extended {
  95        __le16 flags;
  96        u8 current_login_state;
  97        u8 last_login_state;
  98        u8 hard_address[3];
  99        u8 reserved_1;
 100        u8 port_id[3];
 101        u8 sequence_id;
 102        __le16 port_timer;
 103        __le16 nport_handle;                    /* N_PORT handle. */
 104        __le16 receive_data_size;
 105        __le16 reserved_2;
 106
 107        /* PRLI SVC Param are Big endian */
 108        u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
 109        u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
 110        u8 port_name[WWN_SIZE];
 111        u8 node_name[WWN_SIZE];
 112};
 113
 114/* MB 75h: This is the short version of the database */
 115struct get_name_list {
 116        u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
 117        __le16 nport_handle;
 118        u8 reserved;
 119};
 120
 121struct vp_database_24xx {
 122        uint16_t vp_status;
 123        uint8_t  options;
 124        uint8_t  id;
 125        uint8_t  port_name[WWN_SIZE];
 126        uint8_t  node_name[WWN_SIZE];
 127        uint16_t port_id_low;
 128        uint16_t port_id_high;
 129};
 130
 131struct nvram_24xx {
 132        /* NVRAM header. */
 133        uint8_t id[4];
 134        uint16_t nvram_version;
 135        uint16_t reserved_0;
 136
 137        /* Firmware Initialization Control Block. */
 138        uint16_t version;
 139        uint16_t reserved_1;
 140        __le16 frame_payload_size;
 141        uint16_t execution_throttle;
 142        uint16_t exchange_count;
 143        uint16_t hard_address;
 144
 145        uint8_t port_name[WWN_SIZE];
 146        uint8_t node_name[WWN_SIZE];
 147
 148        uint16_t login_retry_count;
 149        uint16_t link_down_on_nos;
 150        uint16_t interrupt_delay_timer;
 151        uint16_t login_timeout;
 152
 153        uint32_t firmware_options_1;
 154        uint32_t firmware_options_2;
 155        uint32_t firmware_options_3;
 156
 157        /* Offset 56. */
 158
 159        /*
 160         * BIT 0     = Control Enable
 161         * BIT 1-15  =
 162         *
 163         * BIT 0-7   = Reserved
 164         * BIT 8-10  = Output Swing 1G
 165         * BIT 11-13 = Output Emphasis 1G
 166         * BIT 14-15 = Reserved
 167         *
 168         * BIT 0-7   = Reserved
 169         * BIT 8-10  = Output Swing 2G
 170         * BIT 11-13 = Output Emphasis 2G
 171         * BIT 14-15 = Reserved
 172         *
 173         * BIT 0-7   = Reserved
 174         * BIT 8-10  = Output Swing 4G
 175         * BIT 11-13 = Output Emphasis 4G
 176         * BIT 14-15 = Reserved
 177         */
 178        uint16_t seriallink_options[4];
 179
 180        uint16_t reserved_2[16];
 181
 182        /* Offset 96. */
 183        uint16_t reserved_3[16];
 184
 185        /* PCIe table entries. */
 186        uint16_t reserved_4[16];
 187
 188        /* Offset 160. */
 189        uint16_t reserved_5[16];
 190
 191        /* Offset 192. */
 192        uint16_t reserved_6[16];
 193
 194        /* Offset 224. */
 195        uint16_t reserved_7[16];
 196
 197        /*
 198         * BIT 0  = Enable spinup delay
 199         * BIT 1  = Disable BIOS
 200         * BIT 2  = Enable Memory Map BIOS
 201         * BIT 3  = Enable Selectable Boot
 202         * BIT 4  = Disable RISC code load
 203         * BIT 5  = Disable Serdes
 204         * BIT 6  =
 205         * BIT 7  =
 206         *
 207         * BIT 8  =
 208         * BIT 9  =
 209         * BIT 10 = Enable lip full login
 210         * BIT 11 = Enable target reset
 211         * BIT 12 =
 212         * BIT 13 =
 213         * BIT 14 =
 214         * BIT 15 = Enable alternate WWN
 215         *
 216         * BIT 16-31 =
 217         */
 218        uint32_t host_p;
 219
 220        uint8_t alternate_port_name[WWN_SIZE];
 221        uint8_t alternate_node_name[WWN_SIZE];
 222
 223        uint8_t boot_port_name[WWN_SIZE];
 224        uint16_t boot_lun_number;
 225        uint16_t reserved_8;
 226
 227        uint8_t alt1_boot_port_name[WWN_SIZE];
 228        uint16_t alt1_boot_lun_number;
 229        uint16_t reserved_9;
 230
 231        uint8_t alt2_boot_port_name[WWN_SIZE];
 232        uint16_t alt2_boot_lun_number;
 233        uint16_t reserved_10;
 234
 235        uint8_t alt3_boot_port_name[WWN_SIZE];
 236        uint16_t alt3_boot_lun_number;
 237        uint16_t reserved_11;
 238
 239        /*
 240         * BIT 0 = Selective Login
 241         * BIT 1 = Alt-Boot Enable
 242         * BIT 2 = Reserved
 243         * BIT 3 = Boot Order List
 244         * BIT 4 = Reserved
 245         * BIT 5 = Selective LUN
 246         * BIT 6 = Reserved
 247         * BIT 7-31 =
 248         */
 249        uint32_t efi_parameters;
 250
 251        uint8_t reset_delay;
 252        uint8_t reserved_12;
 253        uint16_t reserved_13;
 254
 255        uint16_t boot_id_number;
 256        uint16_t reserved_14;
 257
 258        uint16_t max_luns_per_target;
 259        uint16_t reserved_15;
 260
 261        uint16_t port_down_retry_count;
 262        uint16_t link_down_timeout;
 263
 264        /* FCode parameters. */
 265        uint16_t fcode_parameter;
 266
 267        uint16_t reserved_16[3];
 268
 269        /* Offset 352. */
 270        uint8_t prev_drv_ver_major;
 271        uint8_t prev_drv_ver_submajob;
 272        uint8_t prev_drv_ver_minor;
 273        uint8_t prev_drv_ver_subminor;
 274
 275        uint16_t prev_bios_ver_major;
 276        uint16_t prev_bios_ver_minor;
 277
 278        uint16_t prev_efi_ver_major;
 279        uint16_t prev_efi_ver_minor;
 280
 281        uint16_t prev_fw_ver_major;
 282        uint8_t prev_fw_ver_minor;
 283        uint8_t prev_fw_ver_subminor;
 284
 285        uint16_t reserved_17[8];
 286
 287        /* Offset 384. */
 288        uint16_t reserved_18[16];
 289
 290        /* Offset 416. */
 291        uint16_t reserved_19[16];
 292
 293        /* Offset 448. */
 294        uint16_t reserved_20[16];
 295
 296        /* Offset 480. */
 297        uint8_t model_name[16];
 298
 299        uint16_t reserved_21[2];
 300
 301        /* Offset 500. */
 302        /* HW Parameter Block. */
 303        uint16_t pcie_table_sig;
 304        uint16_t pcie_table_offset;
 305
 306        uint16_t subsystem_vendor_id;
 307        uint16_t subsystem_device_id;
 308
 309        uint32_t checksum;
 310};
 311
 312/*
 313 * ISP Initialization Control Block.
 314 * Little endian except where noted.
 315 */
 316#define ICB_VERSION 1
 317struct init_cb_24xx {
 318        uint16_t version;
 319        uint16_t reserved_1;
 320
 321        uint16_t frame_payload_size;
 322        uint16_t execution_throttle;
 323        uint16_t exchange_count;
 324
 325        uint16_t hard_address;
 326
 327        uint8_t port_name[WWN_SIZE];            /* Big endian. */
 328        uint8_t node_name[WWN_SIZE];            /* Big endian. */
 329
 330        uint16_t response_q_inpointer;
 331        uint16_t request_q_outpointer;
 332
 333        uint16_t login_retry_count;
 334
 335        uint16_t prio_request_q_outpointer;
 336
 337        uint16_t response_q_length;
 338        uint16_t request_q_length;
 339
 340        uint16_t link_down_on_nos;              /* Milliseconds. */
 341
 342        uint16_t prio_request_q_length;
 343
 344        __le64   request_q_address __packed;
 345        __le64   response_q_address __packed;
 346        __le64   prio_request_q_address __packed;
 347
 348        uint16_t msix;
 349        uint16_t msix_atio;
 350        uint8_t reserved_2[4];
 351
 352        uint16_t atio_q_inpointer;
 353        uint16_t atio_q_length;
 354        __le64   atio_q_address __packed;
 355
 356        uint16_t interrupt_delay_timer;         /* 100us increments. */
 357        uint16_t login_timeout;
 358
 359        /*
 360         * BIT 0  = Enable Hard Loop Id
 361         * BIT 1  = Enable Fairness
 362         * BIT 2  = Enable Full-Duplex
 363         * BIT 3  = Reserved
 364         * BIT 4  = Enable Target Mode
 365         * BIT 5  = Disable Initiator Mode
 366         * BIT 6  = Acquire FA-WWN
 367         * BIT 7  = Enable D-port Diagnostics
 368         *
 369         * BIT 8  = Reserved
 370         * BIT 9  = Non Participating LIP
 371         * BIT 10 = Descending Loop ID Search
 372         * BIT 11 = Acquire Loop ID in LIPA
 373         * BIT 12 = Reserved
 374         * BIT 13 = Full Login after LIP
 375         * BIT 14 = Node Name Option
 376         * BIT 15-31 = Reserved
 377         */
 378        uint32_t firmware_options_1;
 379
 380        /*
 381         * BIT 0  = Operation Mode bit 0
 382         * BIT 1  = Operation Mode bit 1
 383         * BIT 2  = Operation Mode bit 2
 384         * BIT 3  = Operation Mode bit 3
 385         * BIT 4  = Connection Options bit 0
 386         * BIT 5  = Connection Options bit 1
 387         * BIT 6  = Connection Options bit 2
 388         * BIT 7  = Enable Non part on LIHA failure
 389         *
 390         * BIT 8  = Enable Class 2
 391         * BIT 9  = Enable ACK0
 392         * BIT 10 = Reserved
 393         * BIT 11 = Enable FC-SP Security
 394         * BIT 12 = FC Tape Enable
 395         * BIT 13 = Reserved
 396         * BIT 14 = Enable Target PRLI Control
 397         * BIT 15-31 = Reserved
 398         */
 399        uint32_t firmware_options_2;
 400
 401        /*
 402         * BIT 0  = Reserved
 403         * BIT 1  = Soft ID only
 404         * BIT 2  = Reserved
 405         * BIT 3  = Reserved
 406         * BIT 4  = FCP RSP Payload bit 0
 407         * BIT 5  = FCP RSP Payload bit 1
 408         * BIT 6  = Enable Receive Out-of-Order data frame handling
 409         * BIT 7  = Disable Automatic PLOGI on Local Loop
 410         *
 411         * BIT 8  = Reserved
 412         * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
 413         * BIT 10 = Reserved
 414         * BIT 11 = Reserved
 415         * BIT 12 = Reserved
 416         * BIT 13 = Data Rate bit 0
 417         * BIT 14 = Data Rate bit 1
 418         * BIT 15 = Data Rate bit 2
 419         * BIT 16 = Enable 75 ohm Termination Select
 420         * BIT 17-28 = Reserved
 421         * BIT 29 = Enable response queue 0 in index shadowing
 422         * BIT 30 = Enable request queue 0 out index shadowing
 423         * BIT 31 = Reserved
 424         */
 425        uint32_t firmware_options_3;
 426        uint16_t qos;
 427        uint16_t rid;
 428        uint8_t  reserved_3[20];
 429};
 430
 431/*
 432 * ISP queue - command entry structure definition.
 433 */
 434#define COMMAND_BIDIRECTIONAL 0x75
 435struct cmd_bidir {
 436        uint8_t entry_type;             /* Entry type. */
 437        uint8_t entry_count;            /* Entry count. */
 438        uint8_t sys_define;             /* System defined */
 439        uint8_t entry_status;           /* Entry status. */
 440
 441        uint32_t handle;                /* System handle. */
 442
 443        uint16_t nport_handle;          /* N_PORT hanlde. */
 444
 445        uint16_t timeout;               /* Commnad timeout. */
 446
 447        uint16_t wr_dseg_count;         /* Write Data segment count. */
 448        uint16_t rd_dseg_count;         /* Read Data segment count. */
 449
 450        struct scsi_lun lun;            /* FCP LUN (BE). */
 451
 452        uint16_t control_flags;         /* Control flags. */
 453#define BD_WRAP_BACK                    BIT_3
 454#define BD_READ_DATA                    BIT_1
 455#define BD_WRITE_DATA                   BIT_0
 456
 457        uint16_t fcp_cmnd_dseg_len;             /* Data segment length. */
 458        __le64   fcp_cmnd_dseg_address __packed;/* Data segment address. */
 459
 460        uint16_t reserved[2];                   /* Reserved */
 461
 462        uint32_t rd_byte_count;                 /* Total Byte count Read. */
 463        uint32_t wr_byte_count;                 /* Total Byte count write. */
 464
 465        uint8_t port_id[3];                     /* PortID of destination port.*/
 466        uint8_t vp_index;
 467
 468        struct dsd64 fcp_dsd;
 469};
 470
 471#define COMMAND_TYPE_6  0x48            /* Command Type 6 entry */
 472struct cmd_type_6 {
 473        uint8_t entry_type;             /* Entry type. */
 474        uint8_t entry_count;            /* Entry count. */
 475        uint8_t sys_define;             /* System defined. */
 476        uint8_t entry_status;           /* Entry Status. */
 477
 478        uint32_t handle;                /* System handle. */
 479
 480        uint16_t nport_handle;          /* N_PORT handle. */
 481        uint16_t timeout;               /* Command timeout. */
 482
 483        uint16_t dseg_count;            /* Data segment count. */
 484
 485        uint16_t fcp_rsp_dsd_len;       /* FCP_RSP DSD length. */
 486
 487        struct scsi_lun lun;            /* FCP LUN (BE). */
 488
 489        uint16_t control_flags;         /* Control flags. */
 490#define CF_DIF_SEG_DESCR_ENABLE         BIT_3
 491#define CF_DATA_SEG_DESCR_ENABLE        BIT_2
 492#define CF_READ_DATA                    BIT_1
 493#define CF_WRITE_DATA                   BIT_0
 494
 495        uint16_t fcp_cmnd_dseg_len;     /* Data segment length. */
 496                                        /* Data segment address. */
 497        __le64   fcp_cmnd_dseg_address __packed;
 498                                        /* Data segment address. */
 499        __le64   fcp_rsp_dseg_address __packed;
 500
 501        uint32_t byte_count;            /* Total byte count. */
 502
 503        uint8_t port_id[3];             /* PortID of destination port. */
 504        uint8_t vp_index;
 505
 506        struct dsd64 fcp_dsd;
 507};
 508
 509#define COMMAND_TYPE_7  0x18            /* Command Type 7 entry */
 510struct cmd_type_7 {
 511        uint8_t entry_type;             /* Entry type. */
 512        uint8_t entry_count;            /* Entry count. */
 513        uint8_t sys_define;             /* System defined. */
 514        uint8_t entry_status;           /* Entry Status. */
 515
 516        uint32_t handle;                /* System handle. */
 517
 518        uint16_t nport_handle;          /* N_PORT handle. */
 519        uint16_t timeout;               /* Command timeout. */
 520#define FW_MAX_TIMEOUT          0x1999
 521
 522        uint16_t dseg_count;            /* Data segment count. */
 523        uint16_t reserved_1;
 524
 525        struct scsi_lun lun;            /* FCP LUN (BE). */
 526
 527        uint16_t task_mgmt_flags;       /* Task management flags. */
 528#define TMF_CLEAR_ACA           BIT_14
 529#define TMF_TARGET_RESET        BIT_13
 530#define TMF_LUN_RESET           BIT_12
 531#define TMF_CLEAR_TASK_SET      BIT_10
 532#define TMF_ABORT_TASK_SET      BIT_9
 533#define TMF_DSD_LIST_ENABLE     BIT_2
 534#define TMF_READ_DATA           BIT_1
 535#define TMF_WRITE_DATA          BIT_0
 536
 537        uint8_t task;
 538#define TSK_SIMPLE              0
 539#define TSK_HEAD_OF_QUEUE       1
 540#define TSK_ORDERED             2
 541#define TSK_ACA                 4
 542#define TSK_UNTAGGED            5
 543
 544        uint8_t crn;
 545
 546        uint8_t fcp_cdb[MAX_CMDSZ];     /* SCSI command words. */
 547        uint32_t byte_count;            /* Total byte count. */
 548
 549        uint8_t port_id[3];             /* PortID of destination port. */
 550        uint8_t vp_index;
 551
 552        struct dsd64 dsd;
 553};
 554
 555#define COMMAND_TYPE_CRC_2      0x6A    /* Command Type CRC_2 (Type 6)
 556                                         * (T10-DIF) */
 557struct cmd_type_crc_2 {
 558        uint8_t entry_type;             /* Entry type. */
 559        uint8_t entry_count;            /* Entry count. */
 560        uint8_t sys_define;             /* System defined. */
 561        uint8_t entry_status;           /* Entry Status. */
 562
 563        uint32_t handle;                /* System handle. */
 564
 565        uint16_t nport_handle;          /* N_PORT handle. */
 566        uint16_t timeout;               /* Command timeout. */
 567
 568        uint16_t dseg_count;            /* Data segment count. */
 569
 570        uint16_t fcp_rsp_dseg_len;      /* FCP_RSP DSD length. */
 571
 572        struct scsi_lun lun;            /* FCP LUN (BE). */
 573
 574        uint16_t control_flags;         /* Control flags. */
 575
 576        uint16_t fcp_cmnd_dseg_len;     /* Data segment length. */
 577        __le64   fcp_cmnd_dseg_address __packed;
 578                                        /* Data segment address. */
 579        __le64   fcp_rsp_dseg_address __packed;
 580
 581        uint32_t byte_count;            /* Total byte count. */
 582
 583        uint8_t port_id[3];             /* PortID of destination port. */
 584        uint8_t vp_index;
 585
 586        __le64   crc_context_address __packed;  /* Data segment address. */
 587        uint16_t crc_context_len;               /* Data segment length. */
 588        uint16_t reserved_1;                    /* MUST be set to 0. */
 589};
 590
 591
 592/*
 593 * ISP queue - status entry structure definition.
 594 */
 595#define STATUS_TYPE     0x03            /* Status entry. */
 596struct sts_entry_24xx {
 597        uint8_t entry_type;             /* Entry type. */
 598        uint8_t entry_count;            /* Entry count. */
 599        uint8_t sys_define;             /* System defined. */
 600        uint8_t entry_status;           /* Entry Status. */
 601
 602        uint32_t handle;                /* System handle. */
 603
 604        uint16_t comp_status;           /* Completion status. */
 605        uint16_t ox_id;                 /* OX_ID used by the firmware. */
 606
 607        uint32_t residual_len;          /* FW calc residual transfer length. */
 608
 609        union {
 610                uint16_t reserved_1;
 611                uint16_t nvme_rsp_pyld_len;
 612        };
 613
 614        uint16_t state_flags;           /* State flags. */
 615#define SF_TRANSFERRED_DATA     BIT_11
 616#define SF_NVME_ERSP            BIT_6
 617#define SF_FCP_RSP_DMA          BIT_0
 618
 619        uint16_t retry_delay;
 620        uint16_t scsi_status;           /* SCSI status. */
 621#define SS_CONFIRMATION_REQ             BIT_12
 622
 623        uint32_t rsp_residual_count;    /* FCP RSP residual count. */
 624
 625        uint32_t sense_len;             /* FCP SENSE length. */
 626
 627        union {
 628                struct {
 629                        uint32_t rsp_data_len;  /* FCP response data length  */
 630                        uint8_t data[28];       /* FCP rsp/sense information */
 631                };
 632                struct nvme_fc_ersp_iu nvme_ersp;
 633                uint8_t nvme_ersp_data[32];
 634        };
 635
 636        /*
 637         * If DIF Error is set in comp_status, these additional fields are
 638         * defined:
 639         *
 640         * !!! NOTE: Firmware sends expected/actual DIF data in big endian
 641         * format; but all of the "data" field gets swab32-d in the beginning
 642         * of qla2x00_status_entry().
 643         *
 644         * &data[10] : uint8_t report_runt_bg[2];       - computed guard
 645         * &data[12] : uint8_t actual_dif[8];           - DIF Data received
 646         * &data[20] : uint8_t expected_dif[8];         - DIF Data computed
 647        */
 648};
 649
 650
 651/*
 652 * Status entry completion status
 653 */
 654#define CS_DATA_REASSEMBLY_ERROR 0x11   /* Data Reassembly Error.. */
 655#define CS_ABTS_BY_TARGET       0x13    /* Target send ABTS to abort IOCB. */
 656#define CS_FW_RESOURCE          0x2C    /* Firmware Resource Unavailable. */
 657#define CS_TASK_MGMT_OVERRUN    0x30    /* Task management overrun (8+). */
 658#define CS_ABORT_BY_TARGET      0x47    /* Abort By Target. */
 659
 660/*
 661 * ISP queue - marker entry structure definition.
 662 */
 663#define MARKER_TYPE     0x04            /* Marker entry. */
 664struct mrk_entry_24xx {
 665        uint8_t entry_type;             /* Entry type. */
 666        uint8_t entry_count;            /* Entry count. */
 667        uint8_t handle_count;           /* Handle count. */
 668        uint8_t entry_status;           /* Entry Status. */
 669
 670        uint32_t handle;                /* System handle. */
 671
 672        uint16_t nport_handle;          /* N_PORT handle. */
 673
 674        uint8_t modifier;               /* Modifier (7-0). */
 675#define MK_SYNC_ID_LUN  0               /* Synchronize ID/LUN */
 676#define MK_SYNC_ID      1               /* Synchronize ID */
 677#define MK_SYNC_ALL     2               /* Synchronize all ID/LUN */
 678        uint8_t reserved_1;
 679
 680        uint8_t reserved_2;
 681        uint8_t vp_index;
 682
 683        uint16_t reserved_3;
 684
 685        uint8_t lun[8];                 /* FCP LUN (BE). */
 686        uint8_t reserved_4[40];
 687};
 688
 689/*
 690 * ISP queue - CT Pass-Through entry structure definition.
 691 */
 692#define CT_IOCB_TYPE            0x29    /* CT Pass-Through IOCB entry */
 693struct ct_entry_24xx {
 694        uint8_t entry_type;             /* Entry type. */
 695        uint8_t entry_count;            /* Entry count. */
 696        uint8_t sys_define;             /* System Defined. */
 697        uint8_t entry_status;           /* Entry Status. */
 698
 699        uint32_t handle;                /* System handle. */
 700
 701        uint16_t comp_status;           /* Completion status. */
 702
 703        uint16_t nport_handle;          /* N_PORT handle. */
 704
 705        uint16_t cmd_dsd_count;
 706
 707        uint8_t vp_index;
 708        uint8_t reserved_1;
 709
 710        uint16_t timeout;               /* Command timeout. */
 711        uint16_t reserved_2;
 712
 713        uint16_t rsp_dsd_count;
 714
 715        uint8_t reserved_3[10];
 716
 717        uint32_t rsp_byte_count;
 718        uint32_t cmd_byte_count;
 719
 720        struct dsd64 dsd[2];
 721};
 722
 723/*
 724 * ISP queue - ELS Pass-Through entry structure definition.
 725 */
 726#define ELS_IOCB_TYPE           0x53    /* ELS Pass-Through IOCB entry */
 727struct els_entry_24xx {
 728        uint8_t entry_type;             /* Entry type. */
 729        uint8_t entry_count;            /* Entry count. */
 730        uint8_t sys_define;             /* System Defined. */
 731        uint8_t entry_status;           /* Entry Status. */
 732
 733        uint32_t handle;                /* System handle. */
 734
 735        uint16_t reserved_1;
 736
 737        uint16_t nport_handle;          /* N_PORT handle. */
 738
 739        uint16_t tx_dsd_count;
 740
 741        uint8_t vp_index;
 742        uint8_t sof_type;
 743#define EST_SOFI3               (1 << 4)
 744#define EST_SOFI2               (3 << 4)
 745
 746        uint32_t rx_xchg_address;       /* Receive exchange address. */
 747        uint16_t rx_dsd_count;
 748
 749        uint8_t opcode;
 750        uint8_t reserved_2;
 751
 752        uint8_t port_id[3];
 753        uint8_t s_id[3];
 754
 755        uint16_t control_flags;         /* Control flags. */
 756#define ECF_PAYLOAD_DESCR_MASK  (BIT_15|BIT_14|BIT_13)
 757#define EPD_ELS_COMMAND         (0 << 13)
 758#define EPD_ELS_ACC             (1 << 13)
 759#define EPD_ELS_RJT             (2 << 13)
 760#define EPD_RX_XCHG             (3 << 13)
 761#define ECF_CLR_PASSTHRU_PEND   BIT_12
 762#define ECF_INCL_FRAME_HDR      BIT_11
 763
 764        uint32_t rx_byte_count;
 765        uint32_t tx_byte_count;
 766
 767        __le64   tx_address __packed;   /* Data segment 0 address. */
 768        uint32_t tx_len;                /* Data segment 0 length. */
 769        __le64   rx_address __packed;   /* Data segment 1 address. */
 770        uint32_t rx_len;                /* Data segment 1 length. */
 771};
 772
 773struct els_sts_entry_24xx {
 774        uint8_t entry_type;             /* Entry type. */
 775        uint8_t entry_count;            /* Entry count. */
 776        uint8_t sys_define;             /* System Defined. */
 777        uint8_t entry_status;           /* Entry Status. */
 778
 779        uint32_t handle;                /* System handle. */
 780
 781        uint16_t comp_status;
 782
 783        uint16_t nport_handle;          /* N_PORT handle. */
 784
 785        uint16_t reserved_1;
 786
 787        uint8_t vp_index;
 788        uint8_t sof_type;
 789
 790        uint32_t rx_xchg_address;       /* Receive exchange address. */
 791        uint16_t reserved_2;
 792
 793        uint8_t opcode;
 794        uint8_t reserved_3;
 795
 796        uint8_t port_id[3];
 797        uint8_t reserved_4;
 798
 799        uint16_t reserved_5;
 800
 801        uint16_t control_flags;         /* Control flags. */
 802        uint32_t total_byte_count;
 803        uint32_t error_subcode_1;
 804        uint32_t error_subcode_2;
 805};
 806/*
 807 * ISP queue - Mailbox Command entry structure definition.
 808 */
 809#define MBX_IOCB_TYPE   0x39
 810struct mbx_entry_24xx {
 811        uint8_t entry_type;             /* Entry type. */
 812        uint8_t entry_count;            /* Entry count. */
 813        uint8_t handle_count;           /* Handle count. */
 814        uint8_t entry_status;           /* Entry Status. */
 815
 816        uint32_t handle;                /* System handle. */
 817
 818        uint16_t mbx[28];
 819};
 820
 821
 822#define LOGINOUT_PORT_IOCB_TYPE 0x52    /* Login/Logout Port entry. */
 823struct logio_entry_24xx {
 824        uint8_t entry_type;             /* Entry type. */
 825        uint8_t entry_count;            /* Entry count. */
 826        uint8_t sys_define;             /* System defined. */
 827        uint8_t entry_status;           /* Entry Status. */
 828
 829        uint32_t handle;                /* System handle. */
 830
 831        uint16_t comp_status;           /* Completion status. */
 832#define CS_LOGIO_ERROR          0x31    /* Login/Logout IOCB error. */
 833
 834        uint16_t nport_handle;          /* N_PORT handle. */
 835
 836        uint16_t control_flags;         /* Control flags. */
 837                                        /* Modifiers. */
 838#define LCF_INCLUDE_SNS         BIT_10  /* Include SNS (FFFFFC) during LOGO. */
 839#define LCF_FCP2_OVERRIDE       BIT_9   /* Set/Reset word 3 of PRLI. */
 840#define LCF_CLASS_2             BIT_8   /* Enable class 2 during PLOGI. */
 841#define LCF_FREE_NPORT          BIT_7   /* Release NPORT handle after LOGO. */
 842#define LCF_EXPL_LOGO           BIT_6   /* Perform an explicit LOGO. */
 843#define LCF_NVME_PRLI           BIT_6   /* Perform NVME FC4 PRLI */
 844#define LCF_SKIP_PRLI           BIT_5   /* Skip PRLI after PLOGI. */
 845#define LCF_IMPL_LOGO_ALL       BIT_5   /* Implicit LOGO to all ports. */
 846#define LCF_COND_PLOGI          BIT_4   /* PLOGI only if not logged-in. */
 847#define LCF_IMPL_LOGO           BIT_4   /* Perform an implicit LOGO. */
 848#define LCF_IMPL_PRLO           BIT_4   /* Perform an implicit PRLO. */
 849                                        /* Commands. */
 850#define LCF_COMMAND_PLOGI       0x00    /* PLOGI. */
 851#define LCF_COMMAND_PRLI        0x01    /* PRLI. */
 852#define LCF_COMMAND_PDISC       0x02    /* PDISC. */
 853#define LCF_COMMAND_ADISC       0x03    /* ADISC. */
 854#define LCF_COMMAND_LOGO        0x08    /* LOGO. */
 855#define LCF_COMMAND_PRLO        0x09    /* PRLO. */
 856#define LCF_COMMAND_TPRLO       0x0A    /* TPRLO. */
 857
 858        uint8_t vp_index;
 859        uint8_t reserved_1;
 860
 861        uint8_t port_id[3];             /* PortID of destination port. */
 862
 863        uint8_t rsp_size;               /* Response size in 32bit words. */
 864
 865        uint32_t io_parameter[11];      /* General I/O parameters. */
 866#define LSC_SCODE_NOLINK        0x01
 867#define LSC_SCODE_NOIOCB        0x02
 868#define LSC_SCODE_NOXCB         0x03
 869#define LSC_SCODE_CMD_FAILED    0x04
 870#define LSC_SCODE_NOFABRIC      0x05
 871#define LSC_SCODE_FW_NOT_READY  0x07
 872#define LSC_SCODE_NOT_LOGGED_IN 0x09
 873#define LSC_SCODE_NOPCB         0x0A
 874
 875#define LSC_SCODE_ELS_REJECT    0x18
 876#define LSC_SCODE_CMD_PARAM_ERR 0x19
 877#define LSC_SCODE_PORTID_USED   0x1A
 878#define LSC_SCODE_NPORT_USED    0x1B
 879#define LSC_SCODE_NONPORT       0x1C
 880#define LSC_SCODE_LOGGED_IN     0x1D
 881#define LSC_SCODE_NOFLOGI_ACC   0x1F
 882};
 883
 884#define TSK_MGMT_IOCB_TYPE      0x14
 885struct tsk_mgmt_entry {
 886        uint8_t entry_type;             /* Entry type. */
 887        uint8_t entry_count;            /* Entry count. */
 888        uint8_t handle_count;           /* Handle count. */
 889        uint8_t entry_status;           /* Entry Status. */
 890
 891        uint32_t handle;                /* System handle. */
 892
 893        uint16_t nport_handle;          /* N_PORT handle. */
 894
 895        uint16_t reserved_1;
 896
 897        uint16_t delay;                 /* Activity delay in seconds. */
 898
 899        uint16_t timeout;               /* Command timeout. */
 900
 901        struct scsi_lun lun;            /* FCP LUN (BE). */
 902
 903        uint32_t control_flags;         /* Control Flags. */
 904#define TCF_NOTMCMD_TO_TARGET   BIT_31
 905#define TCF_LUN_RESET           BIT_4
 906#define TCF_ABORT_TASK_SET      BIT_3
 907#define TCF_CLEAR_TASK_SET      BIT_2
 908#define TCF_TARGET_RESET        BIT_1
 909#define TCF_CLEAR_ACA           BIT_0
 910
 911        uint8_t reserved_2[20];
 912
 913        uint8_t port_id[3];             /* PortID of destination port. */
 914        uint8_t vp_index;
 915
 916        uint8_t reserved_3[12];
 917};
 918
 919#define ABORT_IOCB_TYPE 0x33
 920struct abort_entry_24xx {
 921        uint8_t entry_type;             /* Entry type. */
 922        uint8_t entry_count;            /* Entry count. */
 923        uint8_t handle_count;           /* Handle count. */
 924        uint8_t entry_status;           /* Entry Status. */
 925
 926        uint32_t handle;                /* System handle. */
 927
 928        uint16_t nport_handle;          /* N_PORT handle. */
 929                                        /* or Completion status. */
 930
 931        uint16_t options;               /* Options. */
 932#define AOF_NO_ABTS             BIT_0   /* Do not send any ABTS. */
 933
 934        uint32_t handle_to_abort;       /* System handle to abort. */
 935
 936        uint16_t req_que_no;
 937        uint8_t reserved_1[30];
 938
 939        uint8_t port_id[3];             /* PortID of destination port. */
 940        uint8_t vp_index;
 941
 942        uint8_t reserved_2[12];
 943};
 944
 945/*
 946 * ISP I/O Register Set structure definitions.
 947 */
 948struct device_reg_24xx {
 949        uint32_t flash_addr;            /* Flash/NVRAM BIOS address. */
 950#define FARX_DATA_FLAG  BIT_31
 951#define FARX_ACCESS_FLASH_CONF  0x7FFD0000
 952#define FARX_ACCESS_FLASH_DATA  0x7FF00000
 953#define FARX_ACCESS_NVRAM_CONF  0x7FFF0000
 954#define FARX_ACCESS_NVRAM_DATA  0x7FFE0000
 955
 956#define FA_NVRAM_FUNC0_ADDR     0x80
 957#define FA_NVRAM_FUNC1_ADDR     0x180
 958
 959#define FA_NVRAM_VPD_SIZE       0x200
 960#define FA_NVRAM_VPD0_ADDR      0x00
 961#define FA_NVRAM_VPD1_ADDR      0x100
 962
 963#define FA_BOOT_CODE_ADDR       0x00000
 964                                        /*
 965                                         * RISC code begins at offset 512KB
 966                                         * within flash. Consisting of two
 967                                         * contiguous RISC code segments.
 968                                         */
 969#define FA_RISC_CODE_ADDR       0x20000
 970#define FA_RISC_CODE_SEGMENTS   2
 971
 972#define FA_FLASH_DESCR_ADDR_24  0x11000
 973#define FA_FLASH_LAYOUT_ADDR_24 0x11400
 974#define FA_NPIV_CONF0_ADDR_24   0x16000
 975#define FA_NPIV_CONF1_ADDR_24   0x17000
 976
 977#define FA_FW_AREA_ADDR         0x40000
 978#define FA_VPD_NVRAM_ADDR       0x48000
 979#define FA_FEATURE_ADDR         0x4C000
 980#define FA_FLASH_DESCR_ADDR     0x50000
 981#define FA_FLASH_LAYOUT_ADDR    0x50400
 982#define FA_HW_EVENT0_ADDR       0x54000
 983#define FA_HW_EVENT1_ADDR       0x54400
 984#define FA_HW_EVENT_SIZE        0x200
 985#define FA_HW_EVENT_ENTRY_SIZE  4
 986#define FA_NPIV_CONF0_ADDR      0x5C000
 987#define FA_NPIV_CONF1_ADDR      0x5D000
 988#define FA_FCP_PRIO0_ADDR       0x10000
 989#define FA_FCP_PRIO1_ADDR       0x12000
 990
 991/*
 992 * Flash Error Log Event Codes.
 993 */
 994#define HW_EVENT_RESET_ERR      0xF00B
 995#define HW_EVENT_ISP_ERR        0xF020
 996#define HW_EVENT_PARITY_ERR     0xF022
 997#define HW_EVENT_NVRAM_CHKSUM_ERR       0xF023
 998#define HW_EVENT_FLASH_FW_ERR   0xF024
 999
1000        uint32_t flash_data;            /* Flash/NVRAM BIOS data. */

1001
1002        uint32_t ctrl_status;           /* Control/Status. */
1003#define CSRX_FLASH_ACCESS_ERROR BIT_18  /* Flash/NVRAM Access Error. */
1004#define CSRX_DMA_ACTIVE         BIT_17  /* DMA Active status. */
1005#define CSRX_DMA_SHUTDOWN       BIT_16  /* DMA Shutdown control status. */
1006#define CSRX_FUNCTION           BIT_15  /* Function number. */
1007                                        /* PCI-X Bus Mode. */
1008#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
1009#define PBM_PCI_33MHZ           (0 << 8)
1010#define PBM_PCIX_M1_66MHZ       (1 << 8)
1011#define PBM_PCIX_M1_100MHZ      (2 << 8)
1012#define PBM_PCIX_M1_133MHZ      (3 << 8)
1013#define PBM_PCIX_M2_66MHZ       (5 << 8)
1014#define PBM_PCIX_M2_100MHZ      (6 << 8)
1015#define PBM_PCIX_M2_133MHZ      (7 << 8)
1016#define PBM_PCI_66MHZ           (8 << 8)
1017                                        /* Max Write Burst byte count. */
1018#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
1019#define MWB_512_BYTES           (0 << 4)
1020#define MWB_1024_BYTES          (1 << 4)
1021#define MWB_2048_BYTES          (2 << 4)
1022#define MWB_4096_BYTES          (3 << 4)
1023
1024#define CSRX_64BIT_SLOT         BIT_2   /* PCI 64-Bit Bus Slot. */
1025#define CSRX_FLASH_ENABLE       BIT_1   /* Flash BIOS Read/Write enable. */
1026#define CSRX_ISP_SOFT_RESET     BIT_0   /* ISP soft reset. */
1027
1028        uint32_t ictrl;                 /* Interrupt control. */
1029#define ICRX_EN_RISC_INT        BIT_3   /* Enable RISC interrupts on PCI. */
1030
1031        uint32_t istatus;               /* Interrupt status. */
1032#define ISRX_RISC_INT           BIT_3   /* RISC interrupt. */
1033
1034        uint32_t unused_1[2];           /* Gap. */
1035
1036                                        /* Request Queue. */
1037        uint32_t req_q_in;              /*  In-Pointer. */
1038        uint32_t req_q_out;             /*  Out-Pointer. */
1039                                        /* Response Queue. */
1040        uint32_t rsp_q_in;              /*  In-Pointer. */
1041        uint32_t rsp_q_out;             /*  Out-Pointer. */
1042                                        /* Priority Request Queue. */
1043        uint32_t preq_q_in;             /*  In-Pointer. */
1044        uint32_t preq_q_out;            /*  Out-Pointer. */
1045
1046        uint32_t unused_2[2];           /* Gap. */
1047
1048                                        /* ATIO Queue. */
1049        uint32_t atio_q_in;             /*  In-Pointer. */
1050        uint32_t atio_q_out;            /*  Out-Pointer. */
1051
1052        uint32_t host_status;
1053#define HSRX_RISC_INT           BIT_15  /* RISC to Host interrupt. */
1054#define HSRX_RISC_PAUSED        BIT_8   /* RISC Paused. */
1055
1056        uint32_t hccr;                  /* Host command & control register. */
1057                                        /* HCCR statuses. */
1058#define HCCRX_HOST_INT          BIT_6   /* Host to RISC interrupt bit. */
1059#define HCCRX_RISC_RESET        BIT_5   /* RISC Reset mode bit. */
1060                                        /* HCCR commands. */
1061                                        /* NOOP. */
1062#define HCCRX_NOOP              0x00000000
1063                                        /* Set RISC Reset. */
1064#define HCCRX_SET_RISC_RESET    0x10000000
1065                                        /* Clear RISC Reset. */
1066#define HCCRX_CLR_RISC_RESET    0x20000000
1067                                        /* Set RISC Pause. */
1068#define HCCRX_SET_RISC_PAUSE    0x30000000
1069                                        /* Releases RISC Pause. */
1070#define HCCRX_REL_RISC_PAUSE    0x40000000
1071                                        /* Set HOST to RISC interrupt. */
1072#define HCCRX_SET_HOST_INT      0x50000000
1073                                        /* Clear HOST to RISC interrupt. */
1074#define HCCRX_CLR_HOST_INT      0x60000000
1075                                        /* Clear RISC to PCI interrupt. */
1076#define HCCRX_CLR_RISC_INT      0xA0000000
1077
1078        uint32_t gpiod;                 /* GPIO Data register. */
1079
1080                                        /* LED update mask. */
1081#define GPDX_LED_UPDATE_MASK    (BIT_20|BIT_19|BIT_18)
1082                                        /* Data update mask. */
1083#define GPDX_DATA_UPDATE_MASK   (BIT_17|BIT_16)
1084                                        /* Data update mask. */
1085#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1086                                        /* LED control mask. */
1087#define GPDX_LED_COLOR_MASK     (BIT_4|BIT_3|BIT_2)
1088                                        /* LED bit values. Color names as
1089                                         * referenced in fw spec.
1090                                         */
1091#define GPDX_LED_YELLOW_ON      BIT_2
1092#define GPDX_LED_GREEN_ON       BIT_3
1093#define GPDX_LED_AMBER_ON       BIT_4
1094                                        /* Data in/out. */
1095#define GPDX_DATA_INOUT         (BIT_1|BIT_0)
1096
1097        uint32_t gpioe;                 /* GPIO Enable register. */
1098                                        /* Enable update mask. */
1099#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1100                                        /* Enable update mask. */
1101#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1102                                        /* Enable. */
1103#define GPEX_ENABLE             (BIT_1|BIT_0)
1104
1105        uint32_t iobase_addr;           /* I/O Bus Base Address register. */
1106
1107        uint32_t unused_3[10];          /* Gap. */
1108
1109        uint16_t mailbox0;
1110        uint16_t mailbox1;
1111        uint16_t mailbox2;
1112        uint16_t mailbox3;
1113        uint16_t mailbox4;
1114        uint16_t mailbox5;
1115        uint16_t mailbox6;
1116        uint16_t mailbox7;
1117        uint16_t mailbox8;
1118        uint16_t mailbox9;
1119        uint16_t mailbox10;
1120        uint16_t mailbox11;
1121        uint16_t mailbox12;
1122        uint16_t mailbox13;
1123        uint16_t mailbox14;
1124        uint16_t mailbox15;
1125        uint16_t mailbox16;
1126        uint16_t mailbox17;
1127        uint16_t mailbox18;
1128        uint16_t mailbox19;
1129        uint16_t mailbox20;
1130        uint16_t mailbox21;
1131        uint16_t mailbox22;
1132        uint16_t mailbox23;
1133        uint16_t mailbox24;
1134        uint16_t mailbox25;
1135        uint16_t mailbox26;
1136        uint16_t mailbox27;
1137        uint16_t mailbox28;
1138        uint16_t mailbox29;
1139        uint16_t mailbox30;
1140        uint16_t mailbox31;
1141
1142        uint32_t iobase_window;
1143        uint32_t iobase_c4;
1144        uint32_t iobase_c8;
1145        uint32_t unused_4_1[6];         /* Gap. */
1146        uint32_t iobase_q;
1147        uint32_t unused_5[2];           /* Gap. */
1148        uint32_t iobase_select;
1149        uint32_t unused_6[2];           /* Gap. */
1150        uint32_t iobase_sdata;
1151};
1152/* RISC-RISC semaphore register PCI offet */
1153#define RISC_REGISTER_BASE_OFFSET       0x7010
1154#define RISC_REGISTER_WINDOW_OFFET      0x6
1155
1156/* RISC-RISC semaphore/flag register (risc address 0x7016) */
1157
1158#define RISC_SEMAPHORE          0x1UL
1159#define RISC_SEMAPHORE_WE       (RISC_SEMAPHORE << 16)
1160#define RISC_SEMAPHORE_CLR      (RISC_SEMAPHORE_WE | 0x0UL)
1161#define RISC_SEMAPHORE_SET      (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1162
1163#define RISC_SEMAPHORE_FORCE            0x8000UL
1164#define RISC_SEMAPHORE_FORCE_WE         (RISC_SEMAPHORE_FORCE << 16)
1165#define RISC_SEMAPHORE_FORCE_CLR        (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1166#define RISC_SEMAPHORE_FORCE_SET        \
1167                (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1168
1169/* RISC semaphore timeouts (ms) */
1170#define TIMEOUT_SEMAPHORE               2500
1171#define TIMEOUT_SEMAPHORE_FORCE         2000
1172#define TIMEOUT_TOTAL_ELAPSED           4500
1173
1174/* Trace Control *************************************************************/
1175
1176#define TC_AEN_DISABLE          0
1177
1178#define TC_EFT_ENABLE           4
1179#define TC_EFT_DISABLE          5
1180
1181#define TC_FCE_ENABLE           8
1182#define TC_FCE_OPTIONS          0
1183#define TC_FCE_DEFAULT_RX_SIZE  2112
1184#define TC_FCE_DEFAULT_TX_SIZE  2112
1185#define TC_FCE_DISABLE          9
1186#define TC_FCE_DISABLE_TRACE    BIT_0
1187
1188/* MID Support ***************************************************************/
1189
1190#define MIN_MULTI_ID_FABRIC     64      /* Must be power-of-2. */
1191#define MAX_MULTI_ID_FABRIC     256     /* ... */
1192
1193struct mid_conf_entry_24xx {
1194        uint16_t reserved_1;
1195
1196        /*
1197         * BIT 0  = Enable Hard Loop Id
1198         * BIT 1  = Acquire Loop ID in LIPA
1199         * BIT 2  = ID not Acquired
1200         * BIT 3  = Enable VP
1201         * BIT 4  = Enable Initiator Mode
1202         * BIT 5  = Disable Target Mode
1203         * BIT 6-7 = Reserved
1204         */
1205        uint8_t options;
1206
1207        uint8_t hard_address;
1208
1209        uint8_t port_name[WWN_SIZE];
1210        uint8_t node_name[WWN_SIZE];
1211};
1212
1213struct mid_init_cb_24xx {
1214        struct init_cb_24xx init_cb;
1215
1216        uint16_t count;
1217        uint16_t options;
1218
1219        struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1220};
1221
1222
1223struct mid_db_entry_24xx {
1224        uint16_t status;
1225#define MDBS_NON_PARTIC         BIT_3
1226#define MDBS_ID_ACQUIRED        BIT_1
1227#define MDBS_ENABLED            BIT_0
1228
1229        uint8_t options;
1230        uint8_t hard_address;
1231
1232        uint8_t port_name[WWN_SIZE];
1233        uint8_t node_name[WWN_SIZE];
1234
1235        uint8_t port_id[3];
1236        uint8_t reserved_1;
1237};
1238
1239/*
1240 * Virtual Port Control IOCB
1241 */
1242#define VP_CTRL_IOCB_TYPE       0x30    /* Virtual Port Control entry. */
1243struct vp_ctrl_entry_24xx {
1244        uint8_t entry_type;             /* Entry type. */
1245        uint8_t entry_count;            /* Entry count. */
1246        uint8_t sys_define;             /* System defined. */
1247        uint8_t entry_status;           /* Entry Status. */
1248
1249        uint32_t handle;                /* System handle. */
1250
1251        uint16_t vp_idx_failed;
1252
1253        uint16_t comp_status;           /* Completion status. */
1254#define CS_VCE_IOCB_ERROR       0x01    /* Error processing IOCB */
1255#define CS_VCE_ACQ_ID_ERROR     0x02    /* Error while acquireing ID. */
1256#define CS_VCE_BUSY             0x05    /* Firmware not ready to accept cmd. */
1257
1258        uint16_t command;
1259#define VCE_COMMAND_ENABLE_VPS  0x00    /* Enable VPs. */
1260#define VCE_COMMAND_DISABLE_VPS 0x08    /* Disable VPs. */
1261#define VCE_COMMAND_DISABLE_VPS_REINIT  0x09 /* Disable VPs and reinit link. */
1262#define VCE_COMMAND_DISABLE_VPS_LOGO    0x0a /* Disable VPs and LOGO ports. */
1263#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL        0x0b /* Disable VPs and LOGO ports. */
1264
1265        uint16_t vp_count;
1266
1267        uint8_t vp_idx_map[16];
1268        uint16_t flags;
1269        uint16_t id;
1270        uint16_t reserved_4;
1271        uint16_t hopct;
1272        uint8_t reserved_5[24];
1273};
1274
1275/*
1276 * Modify Virtual Port Configuration IOCB
1277 */
1278#define VP_CONFIG_IOCB_TYPE     0x31    /* Virtual Port Config entry. */
1279struct vp_config_entry_24xx {
1280        uint8_t entry_type;             /* Entry type. */
1281        uint8_t entry_count;            /* Entry count. */
1282        uint8_t handle_count;
1283        uint8_t entry_status;           /* Entry Status. */
1284
1285        uint32_t handle;                /* System handle. */
1286
1287        uint16_t flags;
1288#define CS_VF_BIND_VPORTS_TO_VF         BIT_0
1289#define CS_VF_SET_QOS_OF_VPORTS         BIT_1
1290#define CS_VF_SET_HOPS_OF_VPORTS        BIT_2
1291
1292        uint16_t comp_status;           /* Completion status. */
1293#define CS_VCT_STS_ERROR        0x01    /* Specified VPs were not disabled. */
1294#define CS_VCT_CNT_ERROR        0x02    /* Invalid VP count. */
1295#define CS_VCT_ERROR            0x03    /* Unknown error. */
1296#define CS_VCT_IDX_ERROR        0x02    /* Invalid VP index. */
1297#define CS_VCT_BUSY             0x05    /* Firmware not ready to accept cmd. */
1298
1299        uint8_t command;
1300#define VCT_COMMAND_MOD_VPS     0x00    /* Modify VP configurations. */
1301#define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1302
1303        uint8_t vp_count;
1304
1305        uint8_t vp_index1;
1306        uint8_t vp_index2;
1307
1308        uint8_t options_idx1;
1309        uint8_t hard_address_idx1;
1310        uint16_t reserved_vp1;
1311        uint8_t port_name_idx1[WWN_SIZE];
1312        uint8_t node_name_idx1[WWN_SIZE];
1313
1314        uint8_t options_idx2;
1315        uint8_t hard_address_idx2;
1316        uint16_t reserved_vp2;
1317        uint8_t port_name_idx2[WWN_SIZE];
1318        uint8_t node_name_idx2[WWN_SIZE];
1319        uint16_t id;
1320        uint16_t reserved_4;
1321        uint16_t hopct;
1322        uint8_t reserved_5[2];
1323};
1324
1325#define VP_RPT_ID_IOCB_TYPE     0x32    /* Report ID Acquisition entry. */
1326enum VP_STATUS {
1327        VP_STAT_COMPL,
1328        VP_STAT_FAIL,
1329        VP_STAT_ID_CHG,
1330        VP_STAT_SNS_TO,                         /* timeout */
1331        VP_STAT_SNS_RJT,
1332        VP_STAT_SCR_TO,                         /* timeout */
1333        VP_STAT_SCR_RJT,
1334};
1335
1336enum VP_FLAGS {
1337        VP_FLAGS_CON_FLOOP = 1,
1338        VP_FLAGS_CON_P2P = 2,
1339        VP_FLAGS_CON_FABRIC = 3,
1340        VP_FLAGS_NAME_VALID = BIT_5,
1341};
1342
1343struct vp_rpt_id_entry_24xx {
1344        uint8_t entry_type;             /* Entry type. */
1345        uint8_t entry_count;            /* Entry count. */
1346        uint8_t sys_define;             /* System defined. */
1347        uint8_t entry_status;           /* Entry Status. */
1348        uint32_t resv1;
1349        uint8_t vp_acquired;
1350        uint8_t vp_setup;
1351        uint8_t vp_idx;         /* Format 0=reserved */
1352        uint8_t vp_status;      /* Format 0=reserved */
1353
1354        uint8_t port_id[3];
1355        uint8_t format;
1356        union {
1357                struct {
1358                        /* format 0 loop */
1359                        uint8_t vp_idx_map[16];
1360                        uint8_t reserved_4[32];
1361                } f0;
1362                struct {
1363                        /* format 1 fabric */
1364                        uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1365                        uint8_t flags;
1366#define TOPO_MASK  0xE
1367#define TOPO_FL    0x2
1368#define TOPO_N2N   0x4
1369#define TOPO_F     0x6
1370
1371                        uint16_t fip_flags;
1372                        uint8_t rsv2[12];
1373
1374                        uint8_t ls_rjt_vendor;
1375                        uint8_t ls_rjt_explanation;
1376                        uint8_t ls_rjt_reason;
1377                        uint8_t rsv3[5];
1378
1379                        uint8_t port_name[8];
1380                        uint8_t node_name[8];
1381                        uint16_t bbcr;
1382                        uint8_t reserved_5[6];
1383                } f1;
1384                struct { /* format 2: N2N direct connect */
1385                    uint8_t vpstat1_subcode;
1386                    uint8_t flags;
1387                    uint16_t rsv6;
1388                    uint8_t rsv2[12];
1389
1390                    uint8_t ls_rjt_vendor;
1391                    uint8_t ls_rjt_explanation;
1392                    uint8_t ls_rjt_reason;
1393                    uint8_t rsv3[5];
1394
1395                    uint8_t port_name[8];
1396                    uint8_t node_name[8];
1397                    uint8_t remote_nport_id[4];
1398                    uint32_t reserved_5;
1399                } f2;
1400        } u;
1401};
1402
1403#define VF_EVFP_IOCB_TYPE       0x26    /* Exchange Virtual Fabric Parameters entry. */
1404struct vf_evfp_entry_24xx {
1405        uint8_t entry_type;             /* Entry type. */
1406        uint8_t entry_count;            /* Entry count. */
1407        uint8_t sys_define;             /* System defined. */
1408        uint8_t entry_status;           /* Entry Status. */
1409
1410        uint32_t handle;                /* System handle. */
1411        uint16_t comp_status;           /* Completion status. */
1412        uint16_t timeout;               /* timeout */
1413        uint16_t adim_tagging_mode;
1414
1415        uint16_t vfport_id;
1416        uint32_t exch_addr;
1417
1418        uint16_t nport_handle;          /* N_PORT handle. */
1419        uint16_t control_flags;
1420        uint32_t io_parameter_0;
1421        uint32_t io_parameter_1;
1422        __le64   tx_address __packed;   /* Data segment 0 address. */
1423        uint32_t tx_len;                /* Data segment 0 length. */
1424        __le64   rx_address __packed;   /* Data segment 1 address. */
1425        uint32_t rx_len;                /* Data segment 1 length. */
1426};
1427
1428/* END MID Support ***********************************************************/
1429
1430/* Flash Description Table ***************************************************/
1431
1432struct qla_fdt_layout {
1433        uint8_t sig[4];
1434        uint16_t version;
1435        uint16_t len;
1436        uint16_t checksum;
1437        uint8_t unused1[2];
1438        uint8_t model[16];
1439        uint16_t man_id;
1440        uint16_t id;
1441        uint8_t flags;
1442        uint8_t erase_cmd;
1443        uint8_t alt_erase_cmd;
1444        uint8_t wrt_enable_cmd;
1445        uint8_t wrt_enable_bits;
1446        uint8_t wrt_sts_reg_cmd;
1447        uint8_t unprotect_sec_cmd;
1448        uint8_t read_man_id_cmd;
1449        uint32_t block_size;
1450        uint32_t alt_block_size;
1451        uint32_t flash_size;
1452        uint32_t wrt_enable_data;
1453        uint8_t read_id_addr_len;
1454        uint8_t wrt_disable_bits;
1455        uint8_t read_dev_id_len;
1456        uint8_t chip_erase_cmd;
1457        uint16_t read_timeout;
1458        uint8_t protect_sec_cmd;
1459        uint8_t unused2[65];
1460};
1461
1462/* Flash Layout Table ********************************************************/
1463
1464struct qla_flt_location {
1465        uint8_t sig[4];
1466        uint16_t start_lo;
1467        uint16_t start_hi;
1468        uint8_t version;
1469        uint8_t unused[5];
1470        uint16_t checksum;
1471};
1472
1473struct qla_flt_header {
1474        uint16_t version;
1475        uint16_t length;
1476        uint16_t checksum;
1477        uint16_t unused;
1478};
1479
1480#define FLT_REG_FW              0x01
1481#define FLT_REG_BOOT_CODE       0x07
1482#define FLT_REG_VPD_0           0x14
1483#define FLT_REG_NVRAM_0         0x15
1484#define FLT_REG_VPD_1           0x16
1485#define FLT_REG_NVRAM_1         0x17
1486#define FLT_REG_VPD_2           0xD4
1487#define FLT_REG_NVRAM_2         0xD5
1488#define FLT_REG_VPD_3           0xD6
1489#define FLT_REG_NVRAM_3         0xD7
1490#define FLT_REG_FDT             0x1a
1491#define FLT_REG_FLT             0x1c
1492#define FLT_REG_HW_EVENT_0      0x1d
1493#define FLT_REG_HW_EVENT_1      0x1f
1494#define FLT_REG_NPIV_CONF_0     0x29
1495#define FLT_REG_NPIV_CONF_1     0x2a
1496#define FLT_REG_GOLD_FW         0x2f
1497#define FLT_REG_FCP_PRIO_0      0x87
1498#define FLT_REG_FCP_PRIO_1      0x88
1499#define FLT_REG_CNA_FW          0x97
1500#define FLT_REG_BOOT_CODE_8044  0xA2
1501#define FLT_REG_FCOE_FW         0xA4
1502#define FLT_REG_FCOE_NVRAM_0    0xAA
1503#define FLT_REG_FCOE_NVRAM_1    0xAC
1504
1505/* 27xx */
1506#define FLT_REG_IMG_PRI_27XX    0x95
1507#define FLT_REG_IMG_SEC_27XX    0x96
1508#define FLT_REG_FW_SEC_27XX     0x02
1509#define FLT_REG_BOOTLOAD_SEC_27XX       0x9
1510#define FLT_REG_VPD_SEC_27XX_0  0x50
1511#define FLT_REG_VPD_SEC_27XX_1  0x52
1512#define FLT_REG_VPD_SEC_27XX_2  0xD8
1513#define FLT_REG_VPD_SEC_27XX_3  0xDA
1514
1515/* 28xx */
1516#define FLT_REG_AUX_IMG_PRI_28XX        0x125
1517#define FLT_REG_AUX_IMG_SEC_28XX        0x126
1518#define FLT_REG_VPD_SEC_28XX_0          0x10C
1519#define FLT_REG_VPD_SEC_28XX_1          0x10E
1520#define FLT_REG_VPD_SEC_28XX_2          0x110
1521#define FLT_REG_VPD_SEC_28XX_3          0x112
1522#define FLT_REG_NVRAM_SEC_28XX_0        0x10D
1523#define FLT_REG_NVRAM_SEC_28XX_1        0x10F
1524#define FLT_REG_NVRAM_SEC_28XX_2        0x111
1525#define FLT_REG_NVRAM_SEC_28XX_3        0x113
1526
1527struct qla_flt_region {
1528        uint16_t code;
1529        uint8_t attribute;
1530        uint8_t reserved;
1531        uint32_t size;
1532        uint32_t start;
1533        uint32_t end;
1534};
1535
1536#define FLT_REGION_SIZE         16
1537#define FLT_MAX_REGIONS         0xFF
1538#define FLT_REGIONS_SIZE        (FLT_REGION_SIZE * FLT_MAX_REGIONS)
1539
1540/* Flash NPIV Configuration Table ********************************************/
1541
1542struct qla_npiv_header {
1543        uint8_t sig[2];
1544        uint16_t version;
1545        uint16_t entries;
1546        uint16_t unused[4];
1547        uint16_t checksum;
1548};
1549
1550struct qla_npiv_entry {
1551        uint16_t flags;
1552        uint16_t vf_id;
1553        uint8_t q_qos;
1554        uint8_t f_qos;
1555        uint16_t unused1;
1556        uint8_t port_name[WWN_SIZE];
1557        uint8_t node_name[WWN_SIZE];
1558};
1559
1560/* 84XX Support **************************************************************/
1561
1562#define MBA_ISP84XX_ALERT       0x800f  /* Alert Notification. */
1563#define A84_PANIC_RECOVERY      0x1
1564#define A84_OP_LOGIN_COMPLETE   0x2
1565#define A84_DIAG_LOGIN_COMPLETE 0x3
1566#define A84_GOLD_LOGIN_COMPLETE 0x4
1567
1568#define MBC_ISP84XX_RESET       0x3a    /* Reset. */
1569
1570#define FSTATE_REMOTE_FC_DOWN   BIT_0
1571#define FSTATE_NSL_LINK_DOWN    BIT_1
1572#define FSTATE_IS_DIAG_FW       BIT_2
1573#define FSTATE_LOGGED_IN        BIT_3
1574#define FSTATE_WAITING_FOR_VERIFY       BIT_4
1575
1576#define VERIFY_CHIP_IOCB_TYPE   0x1B
1577struct verify_chip_entry_84xx {
1578        uint8_t entry_type;
1579        uint8_t entry_count;
1580        uint8_t sys_defined;
1581        uint8_t entry_status;
1582
1583        uint32_t handle;
1584
1585        uint16_t options;
1586#define VCO_DONT_UPDATE_FW      BIT_0
1587#define VCO_FORCE_UPDATE        BIT_1
1588#define VCO_DONT_RESET_UPDATE   BIT_2
1589#define VCO_DIAG_FW             BIT_3
1590#define VCO_END_OF_DATA         BIT_14
1591#define VCO_ENABLE_DSD          BIT_15
1592
1593        uint16_t reserved_1;
1594
1595        uint16_t data_seg_cnt;
1596        uint16_t reserved_2[3];
1597
1598        uint32_t fw_ver;
1599        uint32_t exchange_address;
1600
1601        uint32_t reserved_3[3];
1602        uint32_t fw_size;
1603        uint32_t fw_seq_size;
1604        uint32_t relative_offset;
1605
1606        struct dsd64 dsd;
1607};
1608
1609struct verify_chip_rsp_84xx {
1610        uint8_t entry_type;
1611        uint8_t entry_count;
1612        uint8_t sys_defined;
1613        uint8_t entry_status;
1614
1615        uint32_t handle;
1616
1617        uint16_t comp_status;
1618#define CS_VCS_CHIP_FAILURE     0x3
1619#define CS_VCS_BAD_EXCHANGE     0x8
1620#define CS_VCS_SEQ_COMPLETEi    0x40
1621
1622        uint16_t failure_code;
1623#define VFC_CHECKSUM_ERROR      0x1
1624#define VFC_INVALID_LEN         0x2
1625#define VFC_ALREADY_IN_PROGRESS 0x8
1626
1627        uint16_t reserved_1[4];
1628
1629        uint32_t fw_ver;
1630        uint32_t exchange_address;
1631
1632        uint32_t reserved_2[6];
1633};
1634
1635#define ACCESS_CHIP_IOCB_TYPE   0x2B
1636struct access_chip_84xx {
1637        uint8_t entry_type;
1638        uint8_t entry_count;
1639        uint8_t sys_defined;
1640        uint8_t entry_status;
1641
1642        uint32_t handle;
1643
1644        uint16_t options;
1645#define ACO_DUMP_MEMORY         0x0
1646#define ACO_LOAD_MEMORY         0x1
1647#define ACO_CHANGE_CONFIG_PARAM 0x2
1648#define ACO_REQUEST_INFO        0x3
1649
1650        uint16_t reserved1;
1651
1652        uint16_t dseg_count;
1653        uint16_t reserved2[3];
1654
1655        uint32_t parameter1;
1656        uint32_t parameter2;
1657        uint32_t parameter3;
1658
1659        uint32_t reserved3[3];
1660        uint32_t total_byte_cnt;
1661        uint32_t reserved4;
1662
1663        struct dsd64 dsd;
1664};
1665
1666struct access_chip_rsp_84xx {
1667        uint8_t entry_type;
1668        uint8_t entry_count;
1669        uint8_t sys_defined;
1670        uint8_t entry_status;
1671
1672        uint32_t handle;
1673
1674        uint16_t comp_status;
1675        uint16_t failure_code;
1676        uint32_t residual_count;
1677
1678        uint32_t reserved[12];
1679};
1680
1681/* 81XX Support **************************************************************/
1682
1683#define MBA_DCBX_START          0x8016
1684#define MBA_DCBX_COMPLETE       0x8030
1685#define MBA_FCF_CONF_ERR        0x8031
1686#define MBA_DCBX_PARAM_UPDATE   0x8032
1687#define MBA_IDC_COMPLETE        0x8100
1688#define MBA_IDC_NOTIFY          0x8101
1689#define MBA_IDC_TIME_EXT        0x8102
1690
1691#define MBC_IDC_ACK             0x101
1692#define MBC_RESTART_MPI_FW      0x3d
1693#define MBC_FLASH_ACCESS_CTRL   0x3e    /* Control flash access. */
1694#define MBC_GET_XGMAC_STATS     0x7a
1695#define MBC_GET_DCBX_PARAMS     0x51
1696
1697/*
1698 * ISP83xx mailbox commands
1699 */
1700#define MBC_WRITE_REMOTE_REG            0x0001 /* Write remote register */
1701#define MBC_READ_REMOTE_REG             0x0009 /* Read remote register */
1702#define MBC_RESTART_NIC_FIRMWARE        0x003d /* Restart NIC firmware */
1703#define MBC_SET_ACCESS_CONTROL          0x003e /* Access control command */
1704
1705/* Flash access control option field bit definitions */
1706#define FAC_OPT_FORCE_SEMAPHORE         BIT_15
1707#define FAC_OPT_REQUESTOR_ID            BIT_14
1708#define FAC_OPT_CMD_SUBCODE             0xff
1709
1710/* Flash access control command subcodes */
1711#define FAC_OPT_CMD_WRITE_PROTECT       0x00
1712#define FAC_OPT_CMD_WRITE_ENABLE        0x01
1713#define FAC_OPT_CMD_ERASE_SECTOR        0x02
1714#define FAC_OPT_CMD_LOCK_SEMAPHORE      0x03
1715#define FAC_OPT_CMD_UNLOCK_SEMAPHORE    0x04
1716#define FAC_OPT_CMD_GET_SECTOR_SIZE     0x05
1717
1718/* enhanced features bit definitions */
1719#define NEF_LR_DIST_ENABLE      BIT_0
1720
1721/* LR Distance bit positions */
1722#define LR_DIST_NV_POS          2
1723#define LR_DIST_FW_POS          12
1724#define LR_DIST_FW_SHIFT        (LR_DIST_FW_POS - LR_DIST_NV_POS)
1725#define LR_DIST_FW_FIELD(x)     ((x) << LR_DIST_FW_SHIFT & 0xf000)
1726
1727/* FAC semaphore defines */
1728#define FAC_SEMAPHORE_UNLOCK    0
1729#define FAC_SEMAPHORE_LOCK      1
1730
1731struct nvram_81xx {
1732        /* NVRAM header. */
1733        uint8_t id[4];
1734        uint16_t nvram_version;
1735        uint16_t reserved_0;
1736
1737        /* Firmware Initialization Control Block. */
1738        uint16_t version;
1739        uint16_t reserved_1;
1740        uint16_t frame_payload_size;
1741        uint16_t execution_throttle;
1742        uint16_t exchange_count;
1743        uint16_t reserved_2;
1744
1745        uint8_t port_name[WWN_SIZE];
1746        uint8_t node_name[WWN_SIZE];
1747
1748        uint16_t login_retry_count;
1749        uint16_t reserved_3;
1750        uint16_t interrupt_delay_timer;
1751        uint16_t login_timeout;
1752
1753        uint32_t firmware_options_1;
1754        uint32_t firmware_options_2;
1755        uint32_t firmware_options_3;
1756
1757        uint16_t reserved_4[4];
1758
1759        /* Offset 64. */
1760        uint8_t enode_mac[6];
1761        uint16_t reserved_5[5];
1762
1763        /* Offset 80. */
1764        uint16_t reserved_6[24];
1765
1766        /* Offset 128. */
1767        uint16_t ex_version;
1768        uint8_t prio_fcf_matching_flags;
1769        uint8_t reserved_6_1[3];
1770        uint16_t pri_fcf_vlan_id;
1771        uint8_t pri_fcf_fabric_name[8];
1772        uint16_t reserved_6_2[7];
1773        uint8_t spma_mac_addr[6];
1774        uint16_t reserved_6_3[14];
1775
1776        /* Offset 192. */
1777        uint8_t min_supported_speed;
1778        uint8_t reserved_7_0;
1779        uint16_t reserved_7[31];
1780
1781        /*
1782         * BIT 0  = Enable spinup delay
1783         * BIT 1  = Disable BIOS
1784         * BIT 2  = Enable Memory Map BIOS
1785         * BIT 3  = Enable Selectable Boot
1786         * BIT 4  = Disable RISC code load
1787         * BIT 5  = Disable Serdes
1788         * BIT 6  = Opt boot mode
1789         * BIT 7  = Interrupt enable
1790         *
1791         * BIT 8  = EV Control enable
1792         * BIT 9  = Enable lip reset
1793         * BIT 10 = Enable lip full login
1794         * BIT 11 = Enable target reset
1795         * BIT 12 = Stop firmware
1796         * BIT 13 = Enable nodename option
1797         * BIT 14 = Default WWPN valid
1798         * BIT 15 = Enable alternate WWN
1799         *
1800         * BIT 16 = CLP LUN string
1801         * BIT 17 = CLP Target string
1802         * BIT 18 = CLP BIOS enable string
1803         * BIT 19 = CLP Serdes string
1804         * BIT 20 = CLP WWPN string
1805         * BIT 21 = CLP WWNN string
1806         * BIT 22 =
1807         * BIT 23 =
1808         * BIT 24 = Keep WWPN
1809         * BIT 25 = Temp WWPN
1810         * BIT 26-31 =
1811         */
1812        uint32_t host_p;
1813
1814        uint8_t alternate_port_name[WWN_SIZE];
1815        uint8_t alternate_node_name[WWN_SIZE];
1816
1817        uint8_t boot_port_name[WWN_SIZE];
1818        uint16_t boot_lun_number;
1819        uint16_t reserved_8;
1820
1821        uint8_t alt1_boot_port_name[WWN_SIZE];
1822        uint16_t alt1_boot_lun_number;
1823        uint16_t reserved_9;
1824
1825        uint8_t alt2_boot_port_name[WWN_SIZE];
1826        uint16_t alt2_boot_lun_number;
1827        uint16_t reserved_10;
1828
1829        uint8_t alt3_boot_port_name[WWN_SIZE];
1830        uint16_t alt3_boot_lun_number;
1831        uint16_t reserved_11;
1832
1833        /*
1834         * BIT 0 = Selective Login
1835         * BIT 1 = Alt-Boot Enable
1836         * BIT 2 = Reserved
1837         * BIT 3 = Boot Order List
1838         * BIT 4 = Reserved
1839         * BIT 5 = Selective LUN
1840         * BIT 6 = Reserved
1841         * BIT 7-31 =
1842         */
1843        uint32_t efi_parameters;
1844
1845        uint8_t reset_delay;
1846        uint8_t reserved_12;
1847        uint16_t reserved_13;
1848
1849        uint16_t boot_id_number;
1850        uint16_t reserved_14;
1851
1852        uint16_t max_luns_per_target;
1853        uint16_t reserved_15;
1854
1855        uint16_t port_down_retry_count;
1856        uint16_t link_down_timeout;
1857
1858        /* FCode parameters. */
1859        uint16_t fcode_parameter;
1860
1861        uint16_t reserved_16[3];
1862
1863        /* Offset 352. */
1864        uint8_t reserved_17[4];
1865        uint16_t reserved_18[5];
1866        uint8_t reserved_19[2];
1867        uint16_t reserved_20[8];
1868
1869        /* Offset 384. */
1870        uint8_t reserved_21[16];
1871        uint16_t reserved_22[3];
1872
1873        /* Offset 406 (0x196) Enhanced Features
1874         * BIT 0    = Extended BB credits for LR
1875         * BIT 1    = Virtual Fabric Enable
1876         * BIT 2-5  = Distance Support if BIT 0 is on
1877         * BIT 6-15 = Unused
1878         */
1879        uint16_t enhanced_features;
1880        uint16_t reserved_24[4];
1881
1882        /* Offset 416. */
1883        uint16_t reserved_25[32];
1884
1885        /* Offset 480. */
1886        uint8_t model_name[16];
1887
1888        /* Offset 496. */
1889        uint16_t feature_mask_l;
1890        uint16_t feature_mask_h;
1891        uint16_t reserved_26[2];
1892
1893        uint16_t subsystem_vendor_id;
1894        uint16_t subsystem_device_id;
1895
1896        uint32_t checksum;
1897};
1898
1899/*
1900 * ISP Initialization Control Block.
1901 * Little endian except where noted.
1902 */
1903#define ICB_VERSION 1
1904struct init_cb_81xx {
1905        uint16_t version;
1906        uint16_t reserved_1;
1907
1908        uint16_t frame_payload_size;
1909        uint16_t execution_throttle;
1910        uint16_t exchange_count;
1911
1912        uint16_t reserved_2;
1913
1914        uint8_t port_name[WWN_SIZE];            /* Big endian. */
1915        uint8_t node_name[WWN_SIZE];            /* Big endian. */
1916
1917        uint16_t response_q_inpointer;
1918        uint16_t request_q_outpointer;
1919
1920        uint16_t login_retry_count;
1921
1922        uint16_t prio_request_q_outpointer;
1923
1924        uint16_t response_q_length;
1925        uint16_t request_q_length;
1926
1927        uint16_t reserved_3;
1928
1929        uint16_t prio_request_q_length;
1930
1931        __le64   request_q_address __packed;
1932        __le64   response_q_address __packed;
1933        __le64   prio_request_q_address __packed;
1934
1935        uint8_t reserved_4[8];
1936
1937        uint16_t atio_q_inpointer;
1938        uint16_t atio_q_length;
1939        __le64   atio_q_address __packed;
1940
1941        uint16_t interrupt_delay_timer;         /* 100us increments. */
1942        uint16_t login_timeout;
1943
1944        /*
1945         * BIT 0-3 = Reserved
1946         * BIT 4  = Enable Target Mode
1947         * BIT 5  = Disable Initiator Mode
1948         * BIT 6  = Reserved
1949         * BIT 7  = Reserved
1950         *
1951         * BIT 8-13 = Reserved
1952         * BIT 14 = Node Name Option
1953         * BIT 15-31 = Reserved
1954         */
1955        uint32_t firmware_options_1;
1956
1957        /*
1958         * BIT 0  = Operation Mode bit 0
1959         * BIT 1  = Operation Mode bit 1
1960         * BIT 2  = Operation Mode bit 2
1961         * BIT 3  = Operation Mode bit 3
1962         * BIT 4-7 = Reserved
1963         *
1964         * BIT 8  = Enable Class 2
1965         * BIT 9  = Enable ACK0
1966         * BIT 10 = Reserved
1967         * BIT 11 = Enable FC-SP Security
1968         * BIT 12 = FC Tape Enable
1969         * BIT 13 = Reserved
1970         * BIT 14 = Enable Target PRLI Control
1971         * BIT 15-31 = Reserved
1972         */
1973        uint32_t firmware_options_2;
1974
1975        /*
1976         * BIT 0-3 = Reserved
1977         * BIT 4  = FCP RSP Payload bit 0
1978         * BIT 5  = FCP RSP Payload bit 1
1979         * BIT 6  = Enable Receive Out-of-Order data frame handling
1980         * BIT 7  = Reserved
1981         *
1982         * BIT 8  = Reserved
1983         * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
1984         * BIT 10-16 = Reserved
1985         * BIT 17 = Enable multiple FCFs
1986         * BIT 18-20 = MAC addressing mode
1987         * BIT 21-25 = Ethernet data rate
1988         * BIT 26 = Enable ethernet header rx IOCB for ATIO q
1989         * BIT 27 = Enable ethernet header rx IOCB for response q
1990         * BIT 28 = SPMA selection bit 0
1991         * BIT 28 = SPMA selection bit 1
1992         * BIT 30-31 = Reserved
1993         */
1994        uint32_t firmware_options_3;
1995
1996        uint8_t  reserved_5[8];
1997
1998        uint8_t enode_mac[6];
1999
2000        uint8_t reserved_6[10];

2001};
2002
2003struct mid_init_cb_81xx {
2004        struct init_cb_81xx init_cb;
2005
2006        uint16_t count;
2007        uint16_t options;
2008
2009        struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
2010};
2011
2012struct ex_init_cb_81xx {
2013        uint16_t ex_version;
2014        uint8_t prio_fcf_matching_flags;
2015        uint8_t reserved_1[3];
2016        uint16_t pri_fcf_vlan_id;
2017        uint8_t pri_fcf_fabric_name[8];
2018        uint16_t reserved_2[7];
2019        uint8_t spma_mac_addr[6];
2020        uint16_t reserved_3[14];
2021};
2022
2023#define FARX_ACCESS_FLASH_CONF_81XX     0x7FFD0000
2024#define FARX_ACCESS_FLASH_DATA_81XX     0x7F800000
2025#define FARX_ACCESS_FLASH_CONF_28XX     0x7FFD0000
2026#define FARX_ACCESS_FLASH_DATA_28XX     0x7F7D0000
2027
2028/* FCP priority config defines *************************************/
2029/* operations */
2030#define QLFC_FCP_PRIO_DISABLE           0x0
2031#define QLFC_FCP_PRIO_ENABLE            0x1
2032#define QLFC_FCP_PRIO_GET_CONFIG        0x2
2033#define QLFC_FCP_PRIO_SET_CONFIG        0x3
2034
2035struct qla_fcp_prio_entry {
2036        uint16_t flags;         /* Describes parameter(s) in FCP        */
2037        /* priority entry that are valid        */
2038#define FCP_PRIO_ENTRY_VALID            0x1
2039#define FCP_PRIO_ENTRY_TAG_VALID        0x2
2040#define FCP_PRIO_ENTRY_SPID_VALID       0x4
2041#define FCP_PRIO_ENTRY_DPID_VALID       0x8
2042#define FCP_PRIO_ENTRY_LUNB_VALID       0x10
2043#define FCP_PRIO_ENTRY_LUNE_VALID       0x20
2044#define FCP_PRIO_ENTRY_SWWN_VALID       0x40
2045#define FCP_PRIO_ENTRY_DWWN_VALID       0x80
2046        uint8_t  tag;           /* Priority value                   */
2047        uint8_t  reserved;      /* Reserved for future use          */
2048        uint32_t src_pid;       /* Src port id. high order byte     */
2049                                /* unused; -1 (wild card)           */
2050        uint32_t dst_pid;       /* Src port id. high order byte     */
2051        /* unused; -1 (wild card)           */
2052        uint16_t lun_beg;       /* 1st lun num of lun range.        */
2053                                /* -1 (wild card)                   */
2054        uint16_t lun_end;       /* 2nd lun num of lun range.        */
2055                                /* -1 (wild card)                   */
2056        uint8_t  src_wwpn[8];   /* Source WWPN: -1 (wild card)      */
2057        uint8_t  dst_wwpn[8];   /* Destination WWPN: -1 (wild card) */
2058};
2059
2060struct qla_fcp_prio_cfg {
2061        uint8_t  signature[4];  /* "HQOS" signature of config data  */
2062        uint16_t version;       /* 1: Initial version               */
2063        uint16_t length;        /* config data size in num bytes    */
2064        uint16_t checksum;      /* config data bytes checksum       */
2065        uint16_t num_entries;   /* Number of entries                */
2066        uint16_t size_of_entry; /* Size of each entry in num bytes  */
2067        uint8_t  attributes;    /* enable/disable, persistence      */
2068#define FCP_PRIO_ATTR_DISABLE   0x0
2069#define FCP_PRIO_ATTR_ENABLE    0x1
2070#define FCP_PRIO_ATTR_PERSIST   0x2
2071        uint8_t  reserved;      /* Reserved for future use          */
2072#define FCP_PRIO_CFG_HDR_SIZE   0x10
2073        struct qla_fcp_prio_entry entry[1];     /* fcp priority entries  */
2074#define FCP_PRIO_CFG_ENTRY_SIZE 0x20
2075};
2076
2077#define FCP_PRIO_CFG_SIZE       (32*1024) /* fcp prio data per port*/
2078
2079/* 25XX Support ****************************************************/
2080#define FA_FCP_PRIO0_ADDR_25    0x3C000
2081#define FA_FCP_PRIO1_ADDR_25    0x3E000
2082
2083/* 81XX Flash locations -- occupies second 2MB region. */
2084#define FA_BOOT_CODE_ADDR_81    0x80000
2085#define FA_RISC_CODE_ADDR_81    0xA0000
2086#define FA_FW_AREA_ADDR_81      0xC0000
2087#define FA_VPD_NVRAM_ADDR_81    0xD0000
2088#define FA_VPD0_ADDR_81         0xD0000
2089#define FA_VPD1_ADDR_81         0xD0400
2090#define FA_NVRAM0_ADDR_81       0xD0080
2091#define FA_NVRAM1_ADDR_81       0xD0180
2092#define FA_FEATURE_ADDR_81      0xD4000
2093#define FA_FLASH_DESCR_ADDR_81  0xD8000
2094#define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2095#define FA_HW_EVENT0_ADDR_81    0xDC000
2096#define FA_HW_EVENT1_ADDR_81    0xDC400
2097#define FA_NPIV_CONF0_ADDR_81   0xD1000
2098#define FA_NPIV_CONF1_ADDR_81   0xD2000
2099
2100/* 83XX Flash locations -- occupies second 8MB region. */
2101#define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
2102#define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
2103
2104#endif
2105