1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8#ifndef __QLA_DMP27_H__ 9#define __QLA_DMP27_H__ 10 11#define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr) 12 13struct __packed qla27xx_fwdt_template { 14 __le32 template_type; 15 __le32 entry_offset; 16 uint32_t template_size; 17 uint32_t count; /* borrow field for running/residual count */ 18 19 __le32 entry_count; 20 uint32_t template_version; 21 uint32_t capture_timestamp; 22 uint32_t template_checksum; 23 24 uint32_t reserved_2; 25 uint32_t driver_info[3]; 26 27 uint32_t saved_state[16]; 28 29 uint32_t reserved_3[8]; 30 uint32_t firmware_version[5]; 31}; 32 33#define TEMPLATE_TYPE_FWDUMP 99 34 35#define ENTRY_TYPE_NOP 0 36#define ENTRY_TYPE_TMP_END 255 37#define ENTRY_TYPE_RD_IOB_T1 256 38#define ENTRY_TYPE_WR_IOB_T1 257 39#define ENTRY_TYPE_RD_IOB_T2 258 40#define ENTRY_TYPE_WR_IOB_T2 259 41#define ENTRY_TYPE_RD_PCI 260 42#define ENTRY_TYPE_WR_PCI 261 43#define ENTRY_TYPE_RD_RAM 262 44#define ENTRY_TYPE_GET_QUEUE 263 45#define ENTRY_TYPE_GET_FCE 264 46#define ENTRY_TYPE_PSE_RISC 265 47#define ENTRY_TYPE_RST_RISC 266 48#define ENTRY_TYPE_DIS_INTR 267 49#define ENTRY_TYPE_GET_HBUF 268 50#define ENTRY_TYPE_SCRATCH 269 51#define ENTRY_TYPE_RDREMREG 270 52#define ENTRY_TYPE_WRREMREG 271 53#define ENTRY_TYPE_RDREMRAM 272 54#define ENTRY_TYPE_PCICFG 273 55#define ENTRY_TYPE_GET_SHADOW 274 56#define ENTRY_TYPE_WRITE_BUF 275 57#define ENTRY_TYPE_CONDITIONAL 276 58#define ENTRY_TYPE_RDPEPREG 277 59#define ENTRY_TYPE_WRPEPREG 278 60 61#define CAPTURE_FLAG_PHYS_ONLY BIT_0 62#define CAPTURE_FLAG_PHYS_VIRT BIT_1 63 64#define DRIVER_FLAG_SKIP_ENTRY BIT_7 65 66struct __packed qla27xx_fwdt_entry { 67 struct __packed { 68 __le32 type; 69 __le32 size; 70 uint32_t reserved_1; 71 72 uint8_t capture_flags; 73 uint8_t reserved_2[2]; 74 uint8_t driver_flags; 75 } hdr; 76 union __packed { 77 struct __packed { 78 } t0; 79 80 struct __packed { 81 } t255; 82 83 struct __packed { 84 __le32 base_addr; 85 uint8_t reg_width; 86 __le16 reg_count; 87 uint8_t pci_offset; 88 } t256; 89 90 struct __packed { 91 __le32 base_addr; 92 __le32 write_data; 93 uint8_t pci_offset; 94 uint8_t reserved[3]; 95 } t257; 96 97 struct __packed { 98 __le32 base_addr; 99 uint8_t reg_width; 100 __le16 reg_count; 101 uint8_t pci_offset; 102 uint8_t banksel_offset; 103 uint8_t reserved[3]; 104 __le32 bank; 105 } t258; 106 107 struct __packed { 108 __le32 base_addr; 109 __le32 write_data; 110 uint8_t reserved[2]; 111 uint8_t pci_offset; 112 uint8_t banksel_offset; 113 __le32 bank; 114 } t259; 115 116 struct __packed { 117 uint8_t pci_offset; 118 uint8_t reserved[3]; 119 } t260; 120 121 struct __packed { 122 uint8_t pci_offset; 123 uint8_t reserved[3]; 124 __le32 write_data; 125 } t261; 126 127 struct __packed { 128 uint8_t ram_area; 129 uint8_t reserved[3]; 130 __le32 start_addr; 131 __le32 end_addr; 132 } t262; 133 134 struct __packed { 135 uint32_t num_queues; 136 uint8_t queue_type; 137 uint8_t reserved[3]; 138 } t263; 139 140 struct __packed { 141 uint32_t fce_trace_size; 142 uint64_t write_pointer; 143 uint64_t base_pointer; 144 uint32_t fce_enable_mb0; 145 uint32_t fce_enable_mb2; 146 uint32_t fce_enable_mb3; 147 uint32_t fce_enable_mb4; 148 uint32_t fce_enable_mb5; 149 uint32_t fce_enable_mb6; 150 } t264; 151 152 struct __packed { 153 } t265; 154 155 struct __packed { 156 } t266; 157 158 struct __packed { 159 uint8_t pci_offset; 160 uint8_t reserved[3]; 161 __le32 data; 162 } t267; 163 164 struct __packed { 165 uint8_t buf_type; 166 uint8_t reserved[3]; 167 uint32_t buf_size; 168 uint64_t start_addr; 169 } t268; 170 171 struct __packed { 172 uint32_t scratch_size; 173 } t269; 174 175 struct __packed { 176 __le32 addr; 177 __le32 count; 178 } t270; 179 180 struct __packed { 181 __le32 addr; 182 __le32 data; 183 } t271; 184 185 struct __packed { 186 __le32 addr; 187 __le32 count; 188 } t272; 189 190 struct __packed { 191 __le32 addr; 192 __le32 count; 193 } t273; 194 195 struct __packed { 196 uint32_t num_queues; 197 uint8_t queue_type; 198 uint8_t reserved[3]; 199 } t274; 200 201 struct __packed { 202 __le32 length; 203 uint8_t buffer[]; 204 } t275; 205 206 struct __packed { 207 __le32 cond1; 208 __le32 cond2; 209 } t276; 210 211 struct __packed { 212 __le32 cmd_addr; 213 __le32 wr_cmd_data; 214 __le32 data_addr; 215 } t277; 216 217 struct __packed { 218 __le32 cmd_addr; 219 __le32 wr_cmd_data; 220 __le32 data_addr; 221 __le32 wr_data; 222 } t278; 223 }; 224}; 225 226#define T262_RAM_AREA_CRITICAL_RAM 1 227#define T262_RAM_AREA_EXTERNAL_RAM 2 228#define T262_RAM_AREA_SHARED_RAM 3 229#define T262_RAM_AREA_DDR_RAM 4 230#define T262_RAM_AREA_MISC 5 231 232#define T263_QUEUE_TYPE_REQ 1 233#define T263_QUEUE_TYPE_RSP 2 234#define T263_QUEUE_TYPE_ATIO 3 235 236#define T268_BUF_TYPE_EXTD_TRACE 1 237#define T268_BUF_TYPE_EXCH_BUFOFF 2 238#define T268_BUF_TYPE_EXTD_LOGIN 3 239#define T268_BUF_TYPE_REQ_MIRROR 4 240#define T268_BUF_TYPE_RSP_MIRROR 5 241 242#define T274_QUEUE_TYPE_REQ_SHAD 1 243#define T274_QUEUE_TYPE_RSP_SHAD 2 244#define T274_QUEUE_TYPE_ATIO_SHAD 3 245 246#endif 247