1
2
3
4
5
6
7
8
9
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/spi_bitbang.h>
19#include <linux/bitops.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/platform_data/spi-ath79.h>
23
24#define DRV_NAME "ath79-spi"
25
26#define ATH79_SPI_RRW_DELAY_FACTOR 12000
27#define MHZ (1000 * 1000)
28
29#define AR71XX_SPI_REG_FS 0x00
30#define AR71XX_SPI_REG_CTRL 0x04
31#define AR71XX_SPI_REG_IOC 0x08
32#define AR71XX_SPI_REG_RDS 0x0c
33
34#define AR71XX_SPI_FS_GPIO BIT(0)
35
36#define AR71XX_SPI_IOC_DO BIT(0)
37#define AR71XX_SPI_IOC_CLK BIT(8)
38#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
39
40struct ath79_spi {
41 struct spi_bitbang bitbang;
42 u32 ioc_base;
43 u32 reg_ctrl;
44 void __iomem *base;
45 struct clk *clk;
46 unsigned int rrw_delay;
47};
48
49static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
50{
51 return ioread32(sp->base + reg);
52}
53
54static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
55{
56 iowrite32(val, sp->base + reg);
57}
58
59static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
60{
61 return spi_master_get_devdata(spi->master);
62}
63
64static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
65{
66 if (nsecs > sp->rrw_delay)
67 ndelay(nsecs - sp->rrw_delay);
68}
69
70static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
71{
72 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
73 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
74 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
75
76 if (cs_high)
77 sp->ioc_base |= cs_bit;
78 else
79 sp->ioc_base &= ~cs_bit;
80
81 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
82}
83
84static void ath79_spi_enable(struct ath79_spi *sp)
85{
86
87 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
88
89
90 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
91 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
92
93
94 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
95
96
97 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
98}
99
100static void ath79_spi_disable(struct ath79_spi *sp)
101{
102
103 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
104
105 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
106}
107
108static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
109 u32 word, u8 bits, unsigned flags)
110{
111 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
112 u32 ioc = sp->ioc_base;
113
114
115 for (word <<= (32 - bits); likely(bits); bits--) {
116 u32 out;
117
118 if (word & (1 << 31))
119 out = ioc | AR71XX_SPI_IOC_DO;
120 else
121 out = ioc & ~AR71XX_SPI_IOC_DO;
122
123
124 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
125 ath79_spi_delay(sp, nsecs);
126 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
127 ath79_spi_delay(sp, nsecs);
128 if (bits == 1)
129 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
130
131 word <<= 1;
132 }
133
134 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
135}
136
137static int ath79_spi_probe(struct platform_device *pdev)
138{
139 struct spi_master *master;
140 struct ath79_spi *sp;
141 struct ath79_spi_platform_data *pdata;
142 struct resource *r;
143 unsigned long rate;
144 int ret;
145
146 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
147 if (master == NULL) {
148 dev_err(&pdev->dev, "failed to allocate spi master\n");
149 return -ENOMEM;
150 }
151
152 sp = spi_master_get_devdata(master);
153 master->dev.of_node = pdev->dev.of_node;
154 platform_set_drvdata(pdev, sp);
155
156 pdata = dev_get_platdata(&pdev->dev);
157
158 master->use_gpio_descriptors = true;
159 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
160 master->setup = spi_bitbang_setup;
161 master->cleanup = spi_bitbang_cleanup;
162 if (pdata) {
163 master->bus_num = pdata->bus_num;
164 master->num_chipselect = pdata->num_chipselect;
165 }
166
167 sp->bitbang.master = master;
168 sp->bitbang.chipselect = ath79_spi_chipselect;
169 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
170 sp->bitbang.flags = SPI_CS_HIGH;
171
172 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
173 sp->base = devm_ioremap_resource(&pdev->dev, r);
174 if (IS_ERR(sp->base)) {
175 ret = PTR_ERR(sp->base);
176 goto err_put_master;
177 }
178
179 sp->clk = devm_clk_get(&pdev->dev, "ahb");
180 if (IS_ERR(sp->clk)) {
181 ret = PTR_ERR(sp->clk);
182 goto err_put_master;
183 }
184
185 ret = clk_prepare_enable(sp->clk);
186 if (ret)
187 goto err_put_master;
188
189 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
190 if (!rate) {
191 ret = -EINVAL;
192 goto err_clk_disable;
193 }
194
195 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
196 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
197 sp->rrw_delay);
198
199 ath79_spi_enable(sp);
200 ret = spi_bitbang_start(&sp->bitbang);
201 if (ret)
202 goto err_disable;
203
204 return 0;
205
206err_disable:
207 ath79_spi_disable(sp);
208err_clk_disable:
209 clk_disable_unprepare(sp->clk);
210err_put_master:
211 spi_master_put(sp->bitbang.master);
212
213 return ret;
214}
215
216static int ath79_spi_remove(struct platform_device *pdev)
217{
218 struct ath79_spi *sp = platform_get_drvdata(pdev);
219
220 spi_bitbang_stop(&sp->bitbang);
221 ath79_spi_disable(sp);
222 clk_disable_unprepare(sp->clk);
223 spi_master_put(sp->bitbang.master);
224
225 return 0;
226}
227
228static void ath79_spi_shutdown(struct platform_device *pdev)
229{
230 ath79_spi_remove(pdev);
231}
232
233static const struct of_device_id ath79_spi_of_match[] = {
234 { .compatible = "qca,ar7100-spi", },
235 { },
236};
237MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
238
239static struct platform_driver ath79_spi_driver = {
240 .probe = ath79_spi_probe,
241 .remove = ath79_spi_remove,
242 .shutdown = ath79_spi_shutdown,
243 .driver = {
244 .name = DRV_NAME,
245 .of_match_table = ath79_spi_of_match,
246 },
247};
248module_platform_driver(ath79_spi_driver);
249
250MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
251MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
252MODULE_LICENSE("GPL v2");
253MODULE_ALIAS("platform:" DRV_NAME);
254
