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10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21#include <linux/mutex.h>
22#include <linux/of.h>
23
24#define HSSPI_GLOBAL_CTRL_REG 0x0
25#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
26#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
27#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
28#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
29#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
30#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
31#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
32
33#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
34
35#define HSSPI_INT_STATUS_REG 0x8
36#define HSSPI_INT_STATUS_MASKED_REG 0xc
37#define HSSPI_INT_MASK_REG 0x10
38
39#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
40#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
41#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
42#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
43#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
44
45#define HSSPI_INT_CLEAR_ALL 0xff001f1f
46
47#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
48#define PINGPONG_CMD_COMMAND_MASK 0xf
49#define PINGPONG_COMMAND_NOOP 0
50#define PINGPONG_COMMAND_START_NOW 1
51#define PINGPONG_COMMAND_START_TRIGGER 2
52#define PINGPONG_COMMAND_HALT 3
53#define PINGPONG_COMMAND_FLUSH 4
54#define PINGPONG_CMD_PROFILE_SHIFT 8
55#define PINGPONG_CMD_SS_SHIFT 12
56
57#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
58
59#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
60#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
61#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
62#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
63
64#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
65#define SIGNAL_CTRL_LATCH_RISING BIT(12)
66#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
67#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
68
69#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
70#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
71#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
72#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
73#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
74#define MODE_CTRL_MODE_3WIRE BIT(20)
75#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
76
77#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
78
79
80#define HSSPI_OP_MULTIBIT BIT(11)
81#define HSSPI_OP_CODE_SHIFT 13
82#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
83#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
84#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
85#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
86#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
87
88#define HSSPI_BUFFER_LEN 512
89#define HSSPI_OPCODE_LEN 2
90
91#define HSSPI_MAX_PREPEND_LEN 15
92
93#define HSSPI_MAX_SYNC_CLOCK 30000000
94
95#define HSSPI_SPI_MAX_CS 8
96#define HSSPI_BUS_NUM 1
97
98struct bcm63xx_hsspi {
99 struct completion done;
100 struct mutex bus_mutex;
101
102 struct platform_device *pdev;
103 struct clk *clk;
104 struct clk *pll_clk;
105 void __iomem *regs;
106 u8 __iomem *fifo;
107
108 u32 speed_hz;
109 u8 cs_polarity;
110};
111
112static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
113 bool active)
114{
115 u32 reg;
116
117 mutex_lock(&bs->bus_mutex);
118 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
119
120 reg &= ~BIT(cs);
121 if (active == !(bs->cs_polarity & BIT(cs)))
122 reg |= BIT(cs);
123
124 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
125 mutex_unlock(&bs->bus_mutex);
126}
127
128static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
129 struct spi_device *spi, int hz)
130{
131 unsigned int profile = spi->chip_select;
132 u32 reg;
133
134 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
135 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
136 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
137
138 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
139 if (hz > HSSPI_MAX_SYNC_CLOCK)
140 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
141 else
142 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
143 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
144
145 mutex_lock(&bs->bus_mutex);
146
147 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
148 reg &= ~GLOBAL_CTRL_CLK_POLARITY;
149 if (spi->mode & SPI_CPOL)
150 reg |= GLOBAL_CTRL_CLK_POLARITY;
151 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
152 mutex_unlock(&bs->bus_mutex);
153}
154
155static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
156{
157 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
158 unsigned int chip_select = spi->chip_select;
159 u16 opcode = 0;
160 int pending = t->len;
161 int step_size = HSSPI_BUFFER_LEN;
162 const u8 *tx = t->tx_buf;
163 u8 *rx = t->rx_buf;
164
165 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
166 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
167
168 if (tx && rx)
169 opcode = HSSPI_OP_READ_WRITE;
170 else if (tx)
171 opcode = HSSPI_OP_WRITE;
172 else if (rx)
173 opcode = HSSPI_OP_READ;
174
175 if (opcode != HSSPI_OP_READ)
176 step_size -= HSSPI_OPCODE_LEN;
177
178 if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
179 (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
180 opcode |= HSSPI_OP_MULTIBIT;
181
182 __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
183 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
184 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
185
186 while (pending > 0) {
187 int curr_step = min_t(int, step_size, pending);
188
189 reinit_completion(&bs->done);
190 if (tx) {
191 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
192 tx += curr_step;
193 }
194
195 __raw_writew(opcode | curr_step, bs->fifo);
196
197
198 __raw_writel(HSSPI_PINGx_CMD_DONE(0),
199 bs->regs + HSSPI_INT_MASK_REG);
200
201
202 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
203 chip_select << PINGPONG_CMD_PROFILE_SHIFT |
204 PINGPONG_COMMAND_START_NOW,
205 bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
206
207 if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
208 dev_err(&bs->pdev->dev, "transfer timed out!\n");
209 return -ETIMEDOUT;
210 }
211
212 if (rx) {
213 memcpy_fromio(rx, bs->fifo, curr_step);
214 rx += curr_step;
215 }
216
217 pending -= curr_step;
218 }
219
220 return 0;
221}
222
223static int bcm63xx_hsspi_setup(struct spi_device *spi)
224{
225 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
226 u32 reg;
227
228 reg = __raw_readl(bs->regs +
229 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
230 reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
231 if (spi->mode & SPI_CPHA)
232 reg |= SIGNAL_CTRL_LAUNCH_RISING;
233 else
234 reg |= SIGNAL_CTRL_LATCH_RISING;
235 __raw_writel(reg, bs->regs +
236 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
237
238 mutex_lock(&bs->bus_mutex);
239 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
240
241
242 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
243 if (spi->mode & SPI_CS_HIGH)
244 reg |= BIT(spi->chip_select);
245 else
246 reg &= ~BIT(spi->chip_select);
247 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
248 }
249
250 if (spi->mode & SPI_CS_HIGH)
251 bs->cs_polarity |= BIT(spi->chip_select);
252 else
253 bs->cs_polarity &= ~BIT(spi->chip_select);
254
255 mutex_unlock(&bs->bus_mutex);
256
257 return 0;
258}
259
260static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
261 struct spi_message *msg)
262{
263 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
264 struct spi_transfer *t;
265 struct spi_device *spi = msg->spi;
266 int status = -EINVAL;
267 int dummy_cs;
268 u32 reg;
269
270
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273
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275
276
277
278
279
280
281
282
283
284 dummy_cs = !spi->chip_select;
285 bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
286
287 list_for_each_entry(t, &msg->transfers, transfer_list) {
288 status = bcm63xx_hsspi_do_txrx(spi, t);
289 if (status)
290 break;
291
292 msg->actual_length += t->len;
293
294 if (t->delay_usecs)
295 udelay(t->delay_usecs);
296
297 if (t->cs_change)
298 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
299 }
300
301 mutex_lock(&bs->bus_mutex);
302 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
303 reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
304 reg |= bs->cs_polarity;
305 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
306 mutex_unlock(&bs->bus_mutex);
307
308 msg->status = status;
309 spi_finalize_current_message(master);
310
311 return 0;
312}
313
314static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
315{
316 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
317
318 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
319 return IRQ_NONE;
320
321 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
322 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
323
324 complete(&bs->done);
325
326 return IRQ_HANDLED;
327}
328
329static int bcm63xx_hsspi_probe(struct platform_device *pdev)
330{
331 struct spi_master *master;
332 struct bcm63xx_hsspi *bs;
333 struct resource *res_mem;
334 void __iomem *regs;
335 struct device *dev = &pdev->dev;
336 struct clk *clk, *pll_clk = NULL;
337 int irq, ret;
338 u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
339
340 irq = platform_get_irq(pdev, 0);
341 if (irq < 0) {
342 dev_err(dev, "no irq: %d\n", irq);
343 return irq;
344 }
345
346 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
347 regs = devm_ioremap_resource(dev, res_mem);
348 if (IS_ERR(regs))
349 return PTR_ERR(regs);
350
351 clk = devm_clk_get(dev, "hsspi");
352
353 if (IS_ERR(clk))
354 return PTR_ERR(clk);
355
356 ret = clk_prepare_enable(clk);
357 if (ret)
358 return ret;
359
360 rate = clk_get_rate(clk);
361 if (!rate) {
362 pll_clk = devm_clk_get(dev, "pll");
363
364 if (IS_ERR(pll_clk)) {
365 ret = PTR_ERR(pll_clk);
366 goto out_disable_clk;
367 }
368
369 ret = clk_prepare_enable(pll_clk);
370 if (ret)
371 goto out_disable_clk;
372
373 rate = clk_get_rate(pll_clk);
374 clk_disable_unprepare(pll_clk);
375 if (!rate) {
376 ret = -EINVAL;
377 goto out_disable_pll_clk;
378 }
379 }
380
381 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
382 if (!master) {
383 ret = -ENOMEM;
384 goto out_disable_pll_clk;
385 }
386
387 bs = spi_master_get_devdata(master);
388 bs->pdev = pdev;
389 bs->clk = clk;
390 bs->pll_clk = pll_clk;
391 bs->regs = regs;
392 bs->speed_hz = rate;
393 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
394
395 mutex_init(&bs->bus_mutex);
396 init_completion(&bs->done);
397
398 master->dev.of_node = dev->of_node;
399 if (!dev->of_node)
400 master->bus_num = HSSPI_BUS_NUM;
401
402 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
403 if (num_cs > 8) {
404 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
405 num_cs);
406 num_cs = HSSPI_SPI_MAX_CS;
407 }
408 master->num_chipselect = num_cs;
409 master->setup = bcm63xx_hsspi_setup;
410 master->transfer_one_message = bcm63xx_hsspi_transfer_one;
411 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
412 SPI_RX_DUAL | SPI_TX_DUAL;
413 master->bits_per_word_mask = SPI_BPW_MASK(8);
414 master->auto_runtime_pm = true;
415
416 platform_set_drvdata(pdev, master);
417
418
419 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
420
421
422 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
423
424
425 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
426 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
427 __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
428 bs->regs + HSSPI_GLOBAL_CTRL_REG);
429
430 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
431 pdev->name, bs);
432
433 if (ret)
434 goto out_put_master;
435
436
437 ret = devm_spi_register_master(dev, master);
438 if (ret)
439 goto out_put_master;
440
441 return 0;
442
443out_put_master:
444 spi_master_put(master);
445out_disable_pll_clk:
446 clk_disable_unprepare(pll_clk);
447out_disable_clk:
448 clk_disable_unprepare(clk);
449 return ret;
450}
451
452
453static int bcm63xx_hsspi_remove(struct platform_device *pdev)
454{
455 struct spi_master *master = platform_get_drvdata(pdev);
456 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
457
458
459 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
460 clk_disable_unprepare(bs->pll_clk);
461 clk_disable_unprepare(bs->clk);
462
463 return 0;
464}
465
466#ifdef CONFIG_PM_SLEEP
467static int bcm63xx_hsspi_suspend(struct device *dev)
468{
469 struct spi_master *master = dev_get_drvdata(dev);
470 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
471
472 spi_master_suspend(master);
473 clk_disable_unprepare(bs->pll_clk);
474 clk_disable_unprepare(bs->clk);
475
476 return 0;
477}
478
479static int bcm63xx_hsspi_resume(struct device *dev)
480{
481 struct spi_master *master = dev_get_drvdata(dev);
482 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
483 int ret;
484
485 ret = clk_prepare_enable(bs->clk);
486 if (ret)
487 return ret;
488
489 if (bs->pll_clk) {
490 ret = clk_prepare_enable(bs->pll_clk);
491 if (ret)
492 return ret;
493 }
494
495 spi_master_resume(master);
496
497 return 0;
498}
499#endif
500
501static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
502 bcm63xx_hsspi_resume);
503
504static const struct of_device_id bcm63xx_hsspi_of_match[] = {
505 { .compatible = "brcm,bcm6328-hsspi", },
506 { },
507};
508MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
509
510static struct platform_driver bcm63xx_hsspi_driver = {
511 .driver = {
512 .name = "bcm63xx-hsspi",
513 .pm = &bcm63xx_hsspi_pm_ops,
514 .of_match_table = bcm63xx_hsspi_of_match,
515 },
516 .probe = bcm63xx_hsspi_probe,
517 .remove = bcm63xx_hsspi_remove,
518};
519
520module_platform_driver(bcm63xx_hsspi_driver);
521
522MODULE_ALIAS("platform:bcm63xx_hsspi");
523MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
524MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
525MODULE_LICENSE("GPL");
526
