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10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/spi/spi.h>
21
22
23#define CDNS_SPI_NAME "cdns-spi"
24
25
26#define CDNS_SPI_CR 0x00
27#define CDNS_SPI_ISR 0x04
28#define CDNS_SPI_IER 0x08
29#define CDNS_SPI_IDR 0x0c
30#define CDNS_SPI_IMR 0x10
31#define CDNS_SPI_ER 0x14
32#define CDNS_SPI_DR 0x18
33#define CDNS_SPI_TXD 0x1C
34#define CDNS_SPI_RXD 0x20
35#define CDNS_SPI_SICR 0x24
36#define CDNS_SPI_THLD 0x28
37
38#define SPI_AUTOSUSPEND_TIMEOUT 3000
39
40
41
42
43
44
45#define CDNS_SPI_CR_MANSTRT 0x00010000
46#define CDNS_SPI_CR_CPHA 0x00000004
47#define CDNS_SPI_CR_CPOL 0x00000002
48#define CDNS_SPI_CR_SSCTRL 0x00003C00
49#define CDNS_SPI_CR_PERI_SEL 0x00000200
50#define CDNS_SPI_CR_BAUD_DIV 0x00000038
51#define CDNS_SPI_CR_MSTREN 0x00000001
52#define CDNS_SPI_CR_MANSTRTEN 0x00008000
53#define CDNS_SPI_CR_SSFORCE 0x00004000
54#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008
55#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
56 CDNS_SPI_CR_SSCTRL | \
57 CDNS_SPI_CR_SSFORCE | \
58 CDNS_SPI_CR_BAUD_DIV_4)
59
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64
65
66
67#define CDNS_SPI_BAUD_DIV_MAX 7
68#define CDNS_SPI_BAUD_DIV_MIN 1
69#define CDNS_SPI_BAUD_DIV_SHIFT 3
70#define CDNS_SPI_SS_SHIFT 10
71#define CDNS_SPI_SS0 0x1
72
73
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75
76
77
78
79#define CDNS_SPI_IXR_TXOW 0x00000004
80#define CDNS_SPI_IXR_MODF 0x00000002
81#define CDNS_SPI_IXR_RXNEMTY 0x00000010
82#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
83 CDNS_SPI_IXR_MODF)
84#define CDNS_SPI_IXR_TXFULL 0x00000008
85#define CDNS_SPI_IXR_ALL 0x0000007F
86
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88
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90
91
92#define CDNS_SPI_ER_ENABLE 0x00000001
93#define CDNS_SPI_ER_DISABLE 0x0
94
95
96#define CDNS_SPI_FIFO_DEPTH 128
97
98
99#define CDNS_SPI_DEFAULT_NUM_CS 4
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112
113
114struct cdns_spi {
115 void __iomem *regs;
116 struct clk *ref_clk;
117 struct clk *pclk;
118 u32 speed_hz;
119 const u8 *txbuf;
120 u8 *rxbuf;
121 int tx_bytes;
122 int rx_bytes;
123 u8 dev_busy;
124 u32 is_decoded_cs;
125};
126
127
128static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
129{
130 return readl_relaxed(xspi->regs + offset);
131}
132
133static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
134{
135 writel_relaxed(val, xspi->regs + offset);
136}
137
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147
148
149static void cdns_spi_init_hw(struct cdns_spi *xspi)
150{
151 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
152
153 if (xspi->is_decoded_cs)
154 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
155
156 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
157 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
158
159
160 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
161 cdns_spi_read(xspi, CDNS_SPI_RXD);
162
163 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
164 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
165 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
166}
167
168
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170
171
172
173static void cdns_spi_chipselect(struct spi_device *spi, bool enable)
174{
175 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
176 u32 ctrl_reg;
177
178 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
179
180 if (!enable) {
181
182 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
183 } else {
184
185 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
186 if (!(xspi->is_decoded_cs))
187 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
188 CDNS_SPI_SS_SHIFT) &
189 CDNS_SPI_CR_SSCTRL;
190 else
191 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
192 CDNS_SPI_CR_SSCTRL;
193 }
194
195 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
196}
197
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203
204static void cdns_spi_config_clock_mode(struct spi_device *spi)
205{
206 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
207 u32 ctrl_reg, new_ctrl_reg;
208
209 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
210 ctrl_reg = new_ctrl_reg;
211
212
213 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
214 if (spi->mode & SPI_CPHA)
215 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
216 if (spi->mode & SPI_CPOL)
217 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
218
219 if (new_ctrl_reg != ctrl_reg) {
220
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224
225
226 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
227 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
228 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
229 }
230}
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245
246static void cdns_spi_config_clock_freq(struct spi_device *spi,
247 struct spi_transfer *transfer)
248{
249 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
250 u32 ctrl_reg, baud_rate_val;
251 unsigned long frequency;
252
253 frequency = clk_get_rate(xspi->ref_clk);
254
255 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
256
257
258 if (xspi->speed_hz != transfer->speed_hz) {
259
260 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
261 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
262 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
263 baud_rate_val++;
264
265 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
266 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
267
268 xspi->speed_hz = frequency / (2 << baud_rate_val);
269 }
270 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
271}
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283
284static int cdns_spi_setup_transfer(struct spi_device *spi,
285 struct spi_transfer *transfer)
286{
287 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
288
289 cdns_spi_config_clock_freq(spi, transfer);
290
291 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
292 __func__, spi->mode, spi->bits_per_word,
293 xspi->speed_hz);
294
295 return 0;
296}
297
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299
300
301
302static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
303{
304 unsigned long trans_cnt = 0;
305
306 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
307 (xspi->tx_bytes > 0)) {
308
309
310
311
312 if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
313 CDNS_SPI_IXR_TXFULL)
314 udelay(10);
315
316 if (xspi->txbuf)
317 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
318 else
319 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
320
321 xspi->tx_bytes--;
322 trans_cnt++;
323 }
324}
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339
340static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
341{
342 struct spi_master *master = dev_id;
343 struct cdns_spi *xspi = spi_master_get_devdata(master);
344 u32 intr_status, status;
345
346 status = IRQ_NONE;
347 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
348 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
349
350 if (intr_status & CDNS_SPI_IXR_MODF) {
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355 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
356 spi_finalize_current_transfer(master);
357 status = IRQ_HANDLED;
358 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
359 unsigned long trans_cnt;
360
361 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
362
363
364 while (trans_cnt) {
365 u8 data;
366
367 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
368 if (xspi->rxbuf)
369 *xspi->rxbuf++ = data;
370
371 xspi->rx_bytes--;
372 trans_cnt--;
373 }
374
375 if (xspi->tx_bytes) {
376
377 cdns_spi_fill_tx_fifo(xspi);
378 } else {
379
380 cdns_spi_write(xspi, CDNS_SPI_IDR,
381 CDNS_SPI_IXR_DEFAULT);
382 spi_finalize_current_transfer(master);
383 }
384 status = IRQ_HANDLED;
385 }
386
387 return status;
388}
389
390static int cdns_prepare_message(struct spi_master *master,
391 struct spi_message *msg)
392{
393 cdns_spi_config_clock_mode(msg->spi);
394 return 0;
395}
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408
409static int cdns_transfer_one(struct spi_master *master,
410 struct spi_device *spi,
411 struct spi_transfer *transfer)
412{
413 struct cdns_spi *xspi = spi_master_get_devdata(master);
414
415 xspi->txbuf = transfer->tx_buf;
416 xspi->rxbuf = transfer->rx_buf;
417 xspi->tx_bytes = transfer->len;
418 xspi->rx_bytes = transfer->len;
419
420 cdns_spi_setup_transfer(spi, transfer);
421
422 cdns_spi_fill_tx_fifo(xspi);
423
424 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
425 return transfer->len;
426}
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436
437static int cdns_prepare_transfer_hardware(struct spi_master *master)
438{
439 struct cdns_spi *xspi = spi_master_get_devdata(master);
440
441 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
442
443 return 0;
444}
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454
455static int cdns_unprepare_transfer_hardware(struct spi_master *master)
456{
457 struct cdns_spi *xspi = spi_master_get_devdata(master);
458
459 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
460
461 return 0;
462}
463
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470
471
472static int cdns_spi_probe(struct platform_device *pdev)
473{
474 int ret = 0, irq;
475 struct spi_master *master;
476 struct cdns_spi *xspi;
477 struct resource *res;
478 u32 num_cs;
479
480 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
481 if (!master)
482 return -ENOMEM;
483
484 xspi = spi_master_get_devdata(master);
485 master->dev.of_node = pdev->dev.of_node;
486 platform_set_drvdata(pdev, master);
487
488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
490 if (IS_ERR(xspi->regs)) {
491 ret = PTR_ERR(xspi->regs);
492 goto remove_master;
493 }
494
495 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
496 if (IS_ERR(xspi->pclk)) {
497 dev_err(&pdev->dev, "pclk clock not found.\n");
498 ret = PTR_ERR(xspi->pclk);
499 goto remove_master;
500 }
501
502 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
503 if (IS_ERR(xspi->ref_clk)) {
504 dev_err(&pdev->dev, "ref_clk clock not found.\n");
505 ret = PTR_ERR(xspi->ref_clk);
506 goto remove_master;
507 }
508
509 ret = clk_prepare_enable(xspi->pclk);
510 if (ret) {
511 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
512 goto remove_master;
513 }
514
515 ret = clk_prepare_enable(xspi->ref_clk);
516 if (ret) {
517 dev_err(&pdev->dev, "Unable to enable device clock.\n");
518 goto clk_dis_apb;
519 }
520
521 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
522 if (ret < 0)
523 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
524 else
525 master->num_chipselect = num_cs;
526
527 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
528 &xspi->is_decoded_cs);
529 if (ret < 0)
530 xspi->is_decoded_cs = 0;
531
532
533 cdns_spi_init_hw(xspi);
534
535 pm_runtime_set_active(&pdev->dev);
536 pm_runtime_enable(&pdev->dev);
537 pm_runtime_use_autosuspend(&pdev->dev);
538 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
539
540 irq = platform_get_irq(pdev, 0);
541 if (irq <= 0) {
542 ret = -ENXIO;
543 dev_err(&pdev->dev, "irq number is invalid\n");
544 goto clk_dis_all;
545 }
546
547 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
548 0, pdev->name, master);
549 if (ret != 0) {
550 ret = -ENXIO;
551 dev_err(&pdev->dev, "request_irq failed\n");
552 goto clk_dis_all;
553 }
554
555 master->use_gpio_descriptors = true;
556 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
557 master->prepare_message = cdns_prepare_message;
558 master->transfer_one = cdns_transfer_one;
559 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
560 master->set_cs = cdns_spi_chipselect;
561 master->auto_runtime_pm = true;
562 master->mode_bits = SPI_CPOL | SPI_CPHA;
563
564
565 master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
566 xspi->speed_hz = master->max_speed_hz;
567
568 master->bits_per_word_mask = SPI_BPW_MASK(8);
569
570 ret = spi_register_master(master);
571 if (ret) {
572 dev_err(&pdev->dev, "spi_register_master failed\n");
573 goto clk_dis_all;
574 }
575
576 return ret;
577
578clk_dis_all:
579 pm_runtime_set_suspended(&pdev->dev);
580 pm_runtime_disable(&pdev->dev);
581 clk_disable_unprepare(xspi->ref_clk);
582clk_dis_apb:
583 clk_disable_unprepare(xspi->pclk);
584remove_master:
585 spi_master_put(master);
586 return ret;
587}
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598
599static int cdns_spi_remove(struct platform_device *pdev)
600{
601 struct spi_master *master = platform_get_drvdata(pdev);
602 struct cdns_spi *xspi = spi_master_get_devdata(master);
603
604 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
605
606 clk_disable_unprepare(xspi->ref_clk);
607 clk_disable_unprepare(xspi->pclk);
608 pm_runtime_set_suspended(&pdev->dev);
609 pm_runtime_disable(&pdev->dev);
610
611 spi_unregister_master(master);
612
613 return 0;
614}
615
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619
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621
622
623
624
625static int __maybe_unused cdns_spi_suspend(struct device *dev)
626{
627 struct spi_master *master = dev_get_drvdata(dev);
628
629 return spi_master_suspend(master);
630}
631
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635
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638
639
640static int __maybe_unused cdns_spi_resume(struct device *dev)
641{
642 struct spi_master *master = dev_get_drvdata(dev);
643 struct cdns_spi *xspi = spi_master_get_devdata(master);
644
645 cdns_spi_init_hw(xspi);
646 return spi_master_resume(master);
647}
648
649
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652
653
654
655
656
657static int __maybe_unused cnds_runtime_resume(struct device *dev)
658{
659 struct spi_master *master = dev_get_drvdata(dev);
660 struct cdns_spi *xspi = spi_master_get_devdata(master);
661 int ret;
662
663 ret = clk_prepare_enable(xspi->pclk);
664 if (ret) {
665 dev_err(dev, "Cannot enable APB clock.\n");
666 return ret;
667 }
668
669 ret = clk_prepare_enable(xspi->ref_clk);
670 if (ret) {
671 dev_err(dev, "Cannot enable device clock.\n");
672 clk_disable_unprepare(xspi->pclk);
673 return ret;
674 }
675 return 0;
676}
677
678
679
680
681
682
683
684
685
686static int __maybe_unused cnds_runtime_suspend(struct device *dev)
687{
688 struct spi_master *master = dev_get_drvdata(dev);
689 struct cdns_spi *xspi = spi_master_get_devdata(master);
690
691 clk_disable_unprepare(xspi->ref_clk);
692 clk_disable_unprepare(xspi->pclk);
693
694 return 0;
695}
696
697static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
698 SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
699 cnds_runtime_resume, NULL)
700 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
701};
702
703static const struct of_device_id cdns_spi_of_match[] = {
704 { .compatible = "xlnx,zynq-spi-r1p6" },
705 { .compatible = "cdns,spi-r1p6" },
706 { }
707};
708MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
709
710
711static struct platform_driver cdns_spi_driver = {
712 .probe = cdns_spi_probe,
713 .remove = cdns_spi_remove,
714 .driver = {
715 .name = CDNS_SPI_NAME,
716 .of_match_table = cdns_spi_of_match,
717 .pm = &cdns_spi_dev_pm_ops,
718 },
719};
720
721module_platform_driver(cdns_spi_driver);
722
723MODULE_AUTHOR("Xilinx, Inc.");
724MODULE_DESCRIPTION("Cadence SPI driver");
725MODULE_LICENSE("GPL");
726