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6
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/clk.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/interrupt.h>
14#include <linux/sched.h>
15#include <linux/completion.h>
16#include <linux/spinlock.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/pm_runtime.h>
20#include <linux/spi/spi.h>
21
22#ifdef CONFIG_LANTIQ
23#include <lantiq_soc.h>
24#endif
25
26#define LTQ_SPI_RX_IRQ_NAME "spi_rx"
27#define LTQ_SPI_TX_IRQ_NAME "spi_tx"
28#define LTQ_SPI_ERR_IRQ_NAME "spi_err"
29#define LTQ_SPI_FRM_IRQ_NAME "spi_frm"
30
31#define LTQ_SPI_CLC 0x00
32#define LTQ_SPI_PISEL 0x04
33#define LTQ_SPI_ID 0x08
34#define LTQ_SPI_CON 0x10
35#define LTQ_SPI_STAT 0x14
36#define LTQ_SPI_WHBSTATE 0x18
37#define LTQ_SPI_TB 0x20
38#define LTQ_SPI_RB 0x24
39#define LTQ_SPI_RXFCON 0x30
40#define LTQ_SPI_TXFCON 0x34
41#define LTQ_SPI_FSTAT 0x38
42#define LTQ_SPI_BRT 0x40
43#define LTQ_SPI_BRSTAT 0x44
44#define LTQ_SPI_SFCON 0x60
45#define LTQ_SPI_SFSTAT 0x64
46#define LTQ_SPI_GPOCON 0x70
47#define LTQ_SPI_GPOSTAT 0x74
48#define LTQ_SPI_FPGO 0x78
49#define LTQ_SPI_RXREQ 0x80
50#define LTQ_SPI_RXCNT 0x84
51#define LTQ_SPI_DMACON 0xec
52#define LTQ_SPI_IRNEN 0xf4
53#define LTQ_SPI_IRNICR 0xf8
54#define LTQ_SPI_IRNCR 0xfc
55
56#define LTQ_SPI_CLC_SMC_S 16
57#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
58#define LTQ_SPI_CLC_RMC_S 8
59#define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S)
60#define LTQ_SPI_CLC_DISS BIT(1)
61#define LTQ_SPI_CLC_DISR BIT(0)
62
63#define LTQ_SPI_ID_TXFS_S 24
64#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S)
65#define LTQ_SPI_ID_RXFS_S 16
66#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S)
67#define LTQ_SPI_ID_MOD_S 8
68#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
69#define LTQ_SPI_ID_CFG_S 5
70#define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S)
71#define LTQ_SPI_ID_REV_M 0x1F
72
73#define LTQ_SPI_CON_BM_S 16
74#define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S)
75#define LTQ_SPI_CON_EM BIT(24)
76#define LTQ_SPI_CON_IDLE BIT(23)
77#define LTQ_SPI_CON_ENBV BIT(22)
78#define LTQ_SPI_CON_RUEN BIT(12)
79#define LTQ_SPI_CON_TUEN BIT(11)
80#define LTQ_SPI_CON_AEN BIT(10)
81#define LTQ_SPI_CON_REN BIT(9)
82#define LTQ_SPI_CON_TEN BIT(8)
83#define LTQ_SPI_CON_LB BIT(7)
84#define LTQ_SPI_CON_PO BIT(6)
85#define LTQ_SPI_CON_PH BIT(5)
86#define LTQ_SPI_CON_HB BIT(4)
87#define LTQ_SPI_CON_RXOFF BIT(1)
88#define LTQ_SPI_CON_TXOFF BIT(0)
89
90#define LTQ_SPI_STAT_RXBV_S 28
91#define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S)
92#define LTQ_SPI_STAT_BSY BIT(13)
93#define LTQ_SPI_STAT_RUE BIT(12)
94#define LTQ_SPI_STAT_TUE BIT(11)
95#define LTQ_SPI_STAT_AE BIT(10)
96#define LTQ_SPI_STAT_RE BIT(9)
97#define LTQ_SPI_STAT_TE BIT(8)
98#define LTQ_SPI_STAT_ME BIT(7)
99#define LTQ_SPI_STAT_MS BIT(1)
100#define LTQ_SPI_STAT_EN BIT(0)
101#define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
102 LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
103 LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)
104
105#define LTQ_SPI_WHBSTATE_SETTUE BIT(15)
106#define LTQ_SPI_WHBSTATE_SETAE BIT(14)
107#define LTQ_SPI_WHBSTATE_SETRE BIT(13)
108#define LTQ_SPI_WHBSTATE_SETTE BIT(12)
109#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11)
110#define LTQ_SPI_WHBSTATE_CLRAE BIT(10)
111#define LTQ_SPI_WHBSTATE_CLRRE BIT(9)
112#define LTQ_SPI_WHBSTATE_CLRTE BIT(8)
113#define LTQ_SPI_WHBSTATE_SETME BIT(7)
114#define LTQ_SPI_WHBSTATE_CLRME BIT(6)
115#define LTQ_SPI_WHBSTATE_SETRUE BIT(5)
116#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4)
117#define LTQ_SPI_WHBSTATE_SETMS BIT(3)
118#define LTQ_SPI_WHBSTATE_CLRMS BIT(2)
119#define LTQ_SPI_WHBSTATE_SETEN BIT(1)
120#define LTQ_SPI_WHBSTATE_CLREN BIT(0)
121#define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \
122 LTQ_SPI_WHBSTATE_CLRME | \
123 LTQ_SPI_WHBSTATE_CLRTE | \
124 LTQ_SPI_WHBSTATE_CLRRE | \
125 LTQ_SPI_WHBSTATE_CLRAE | \
126 LTQ_SPI_WHBSTATE_CLRTUE)
127
128#define LTQ_SPI_RXFCON_RXFITL_S 8
129#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S)
130#define LTQ_SPI_RXFCON_RXFLU BIT(1)
131#define LTQ_SPI_RXFCON_RXFEN BIT(0)
132
133#define LTQ_SPI_TXFCON_TXFITL_S 8
134#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S)
135#define LTQ_SPI_TXFCON_TXFLU BIT(1)
136#define LTQ_SPI_TXFCON_TXFEN BIT(0)
137
138#define LTQ_SPI_FSTAT_RXFFL_S 0
139#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S)
140#define LTQ_SPI_FSTAT_TXFFL_S 8
141#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S)
142
143#define LTQ_SPI_GPOCON_ISCSBN_S 8
144#define LTQ_SPI_GPOCON_INVOUTN_S 0
145
146#define LTQ_SPI_FGPO_SETOUTN_S 8
147#define LTQ_SPI_FGPO_CLROUTN_S 0
148
149#define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF
150#define LTQ_SPI_RXCNT_TODO_M 0xFFFF
151
152#define LTQ_SPI_IRNEN_TFI BIT(4)
153#define LTQ_SPI_IRNEN_F BIT(3)
154#define LTQ_SPI_IRNEN_E BIT(2)
155#define LTQ_SPI_IRNEN_T_XWAY BIT(1)
156#define LTQ_SPI_IRNEN_R_XWAY BIT(0)
157#define LTQ_SPI_IRNEN_R_XRX BIT(1)
158#define LTQ_SPI_IRNEN_T_XRX BIT(0)
159#define LTQ_SPI_IRNEN_ALL 0x1F
160
161struct lantiq_ssc_hwcfg {
162 unsigned int irnen_r;
163 unsigned int irnen_t;
164};
165
166struct lantiq_ssc_spi {
167 struct spi_master *master;
168 struct device *dev;
169 void __iomem *regbase;
170 struct clk *spi_clk;
171 struct clk *fpi_clk;
172 const struct lantiq_ssc_hwcfg *hwcfg;
173
174 spinlock_t lock;
175 struct workqueue_struct *wq;
176 struct work_struct work;
177
178 const u8 *tx;
179 u8 *rx;
180 unsigned int tx_todo;
181 unsigned int rx_todo;
182 unsigned int bits_per_word;
183 unsigned int speed_hz;
184 unsigned int tx_fifo_size;
185 unsigned int rx_fifo_size;
186 unsigned int base_cs;
187};
188
189static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
190{
191 return __raw_readl(spi->regbase + reg);
192}
193
194static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
195 u32 reg)
196{
197 __raw_writel(val, spi->regbase + reg);
198}
199
200static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
201 u32 set, u32 reg)
202{
203 u32 val = __raw_readl(spi->regbase + reg);
204
205 val &= ~clr;
206 val |= set;
207 __raw_writel(val, spi->regbase + reg);
208}
209
210static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
211{
212 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
213
214 return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
215}
216
217static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
218{
219 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
220
221 return fstat & LTQ_SPI_FSTAT_RXFFL_M;
222}
223
224static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
225{
226 return spi->tx_fifo_size - tx_fifo_level(spi);
227}
228
229static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
230{
231 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
232
233 val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
234 lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
235}
236
237static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
238{
239 u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S;
240
241 val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
242 lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
243}
244
245static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
246{
247 lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
248}
249
250static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
251{
252 lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
253}
254
255static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
256{
257 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
258}
259
260static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
261{
262 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
263}
264
265static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
266 unsigned int max_speed_hz)
267{
268 u32 spi_clk, brt;
269
270
271
272
273
274
275
276
277
278 spi_clk = clk_get_rate(spi->fpi_clk) / 2;
279
280 if (max_speed_hz > spi_clk)
281 brt = 0;
282 else
283 brt = spi_clk / max_speed_hz - 1;
284
285 if (brt > 0xFFFF)
286 brt = 0xFFFF;
287
288 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
289 spi_clk, max_speed_hz, brt);
290
291 lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
292}
293
294static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
295 unsigned int bits_per_word)
296{
297 u32 bm;
298
299
300 bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S;
301
302 lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
303}
304
305static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
306 unsigned int mode)
307{
308 u32 con_set = 0, con_clr = 0;
309
310
311
312
313
314
315
316
317
318 if (mode & SPI_CPHA)
319 con_clr |= LTQ_SPI_CON_PH;
320 else
321 con_set |= LTQ_SPI_CON_PH;
322
323 if (mode & SPI_CPOL)
324 con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
325 else
326 con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
327
328
329 if (mode & SPI_LSB_FIRST)
330 con_clr |= LTQ_SPI_CON_HB;
331 else
332 con_set |= LTQ_SPI_CON_HB;
333
334
335 if (mode & SPI_LOOP)
336 con_set |= LTQ_SPI_CON_LB;
337 else
338 con_clr |= LTQ_SPI_CON_LB;
339
340 lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
341}
342
343static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
344{
345 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
346
347
348
349
350
351 lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
352
353
354 hw_enter_config_mode(spi);
355
356
357 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
358
359
360 lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
361 LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
362 LTQ_SPI_CON_RXOFF, LTQ_SPI_CON);
363
364
365 hw_setup_bits_per_word(spi, spi->bits_per_word);
366 hw_setup_clock_mode(spi, SPI_MODE_0);
367
368
369 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
370 LTQ_SPI_WHBSTATE_CLR_ERRORS,
371 LTQ_SPI_WHBSTATE);
372
373
374 lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
375 lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
376
377
378 rx_fifo_reset(spi);
379 tx_fifo_reset(spi);
380
381
382 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
383 LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
384}
385
386static int lantiq_ssc_setup(struct spi_device *spidev)
387{
388 struct spi_master *master = spidev->master;
389 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
390 unsigned int cs = spidev->chip_select;
391 u32 gpocon;
392
393
394 if (gpio_is_valid(spidev->cs_gpio))
395 return 0;
396
397 dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
398
399 if (cs < spi->base_cs) {
400 dev_err(spi->dev,
401 "chipselect %i too small (min %i)\n", cs, spi->base_cs);
402 return -EINVAL;
403 }
404
405
406 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
407
408
409 if (spidev->mode & SPI_CS_HIGH)
410 gpocon |= 1 << (cs - spi->base_cs);
411
412 lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
413
414 return 0;
415}
416
417static int lantiq_ssc_prepare_message(struct spi_master *master,
418 struct spi_message *message)
419{
420 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
421
422 hw_enter_config_mode(spi);
423 hw_setup_clock_mode(spi, message->spi->mode);
424 hw_enter_active_mode(spi);
425
426 return 0;
427}
428
429static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
430 struct spi_device *spidev, struct spi_transfer *t)
431{
432 unsigned int speed_hz = t->speed_hz;
433 unsigned int bits_per_word = t->bits_per_word;
434 u32 con;
435
436 if (bits_per_word != spi->bits_per_word ||
437 speed_hz != spi->speed_hz) {
438 hw_enter_config_mode(spi);
439 hw_setup_speed_hz(spi, speed_hz);
440 hw_setup_bits_per_word(spi, bits_per_word);
441 hw_enter_active_mode(spi);
442
443 spi->speed_hz = speed_hz;
444 spi->bits_per_word = bits_per_word;
445 }
446
447
448 con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
449 if (t->tx_buf)
450 con &= ~LTQ_SPI_CON_TXOFF;
451 else
452 con |= LTQ_SPI_CON_TXOFF;
453
454 if (t->rx_buf)
455 con &= ~LTQ_SPI_CON_RXOFF;
456 else
457 con |= LTQ_SPI_CON_RXOFF;
458
459 lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
460}
461
462static int lantiq_ssc_unprepare_message(struct spi_master *master,
463 struct spi_message *message)
464{
465 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
466
467 flush_workqueue(spi->wq);
468
469
470 lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
471 LTQ_SPI_CON);
472
473 return 0;
474}
475
476static void tx_fifo_write(struct lantiq_ssc_spi *spi)
477{
478 const u8 *tx8;
479 const u16 *tx16;
480 const u32 *tx32;
481 u32 data;
482 unsigned int tx_free = tx_fifo_free(spi);
483
484 while (spi->tx_todo && tx_free) {
485 switch (spi->bits_per_word) {
486 case 2 ... 8:
487 tx8 = spi->tx;
488 data = *tx8;
489 spi->tx_todo--;
490 spi->tx++;
491 break;
492 case 16:
493 tx16 = (u16 *) spi->tx;
494 data = *tx16;
495 spi->tx_todo -= 2;
496 spi->tx += 2;
497 break;
498 case 32:
499 tx32 = (u32 *) spi->tx;
500 data = *tx32;
501 spi->tx_todo -= 4;
502 spi->tx += 4;
503 break;
504 default:
505 WARN_ON(1);
506 data = 0;
507 break;
508 }
509
510 lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
511 tx_free--;
512 }
513}
514
515static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
516{
517 u8 *rx8;
518 u16 *rx16;
519 u32 *rx32;
520 u32 data;
521 unsigned int rx_fill = rx_fifo_level(spi);
522
523 while (rx_fill) {
524 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
525
526 switch (spi->bits_per_word) {
527 case 2 ... 8:
528 rx8 = spi->rx;
529 *rx8 = data;
530 spi->rx_todo--;
531 spi->rx++;
532 break;
533 case 16:
534 rx16 = (u16 *) spi->rx;
535 *rx16 = data;
536 spi->rx_todo -= 2;
537 spi->rx += 2;
538 break;
539 case 32:
540 rx32 = (u32 *) spi->rx;
541 *rx32 = data;
542 spi->rx_todo -= 4;
543 spi->rx += 4;
544 break;
545 default:
546 WARN_ON(1);
547 break;
548 }
549
550 rx_fill--;
551 }
552}
553
554static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
555{
556 u32 data, *rx32;
557 u8 *rx8;
558 unsigned int rxbv, shift;
559 unsigned int rx_fill = rx_fifo_level(spi);
560
561
562
563
564
565
566
567
568 while (rx_fill) {
569 if (spi->rx_todo < 4) {
570 rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
571 LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;
572 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
573
574 shift = (rxbv - 1) * 8;
575 rx8 = spi->rx;
576
577 while (rxbv) {
578 *rx8++ = (data >> shift) & 0xFF;
579 rxbv--;
580 shift -= 8;
581 spi->rx_todo--;
582 spi->rx++;
583 }
584 } else {
585 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
586 rx32 = (u32 *) spi->rx;
587
588 *rx32++ = data;
589 spi->rx_todo -= 4;
590 spi->rx += 4;
591 }
592 rx_fill--;
593 }
594}
595
596static void rx_request(struct lantiq_ssc_spi *spi)
597{
598 unsigned int rxreq, rxreq_max;
599
600
601
602
603
604
605 rxreq = spi->rx_todo;
606 rxreq_max = spi->rx_fifo_size * 4;
607 if (rxreq > rxreq_max)
608 rxreq = rxreq_max;
609
610 lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
611}
612
613static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
614{
615 struct lantiq_ssc_spi *spi = data;
616
617 if (spi->tx) {
618 if (spi->rx && spi->rx_todo)
619 rx_fifo_read_full_duplex(spi);
620
621 if (spi->tx_todo)
622 tx_fifo_write(spi);
623 else if (!tx_fifo_level(spi))
624 goto completed;
625 } else if (spi->rx) {
626 if (spi->rx_todo) {
627 rx_fifo_read_half_duplex(spi);
628
629 if (spi->rx_todo)
630 rx_request(spi);
631 else
632 goto completed;
633 } else {
634 goto completed;
635 }
636 }
637
638 return IRQ_HANDLED;
639
640completed:
641 queue_work(spi->wq, &spi->work);
642
643 return IRQ_HANDLED;
644}
645
646static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
647{
648 struct lantiq_ssc_spi *spi = data;
649 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
650
651 if (!(stat & LTQ_SPI_STAT_ERRORS))
652 return IRQ_NONE;
653
654 if (stat & LTQ_SPI_STAT_RUE)
655 dev_err(spi->dev, "receive underflow error\n");
656 if (stat & LTQ_SPI_STAT_TUE)
657 dev_err(spi->dev, "transmit underflow error\n");
658 if (stat & LTQ_SPI_STAT_AE)
659 dev_err(spi->dev, "abort error\n");
660 if (stat & LTQ_SPI_STAT_RE)
661 dev_err(spi->dev, "receive overflow error\n");
662 if (stat & LTQ_SPI_STAT_TE)
663 dev_err(spi->dev, "transmit overflow error\n");
664 if (stat & LTQ_SPI_STAT_ME)
665 dev_err(spi->dev, "mode error\n");
666
667
668 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
669
670
671 if (spi->master->cur_msg)
672 spi->master->cur_msg->status = -EIO;
673 queue_work(spi->wq, &spi->work);
674
675 return IRQ_HANDLED;
676}
677
678static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
679 struct spi_transfer *t)
680{
681 unsigned long flags;
682
683 spin_lock_irqsave(&spi->lock, flags);
684
685 spi->tx = t->tx_buf;
686 spi->rx = t->rx_buf;
687
688 if (t->tx_buf) {
689 spi->tx_todo = t->len;
690
691
692 tx_fifo_write(spi);
693 }
694
695 if (spi->rx) {
696 spi->rx_todo = t->len;
697
698
699 if (!spi->tx)
700 rx_request(spi);
701 }
702
703 spin_unlock_irqrestore(&spi->lock, flags);
704
705 return t->len;
706}
707
708
709
710
711
712
713
714
715static void lantiq_ssc_bussy_work(struct work_struct *work)
716{
717 struct lantiq_ssc_spi *spi;
718 unsigned long long timeout = 8LL * 1000LL;
719 unsigned long end;
720
721 spi = container_of(work, typeof(*spi), work);
722
723 do_div(timeout, spi->speed_hz);
724 timeout += timeout + 100;
725
726 end = jiffies + msecs_to_jiffies(timeout);
727 do {
728 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
729
730 if (!(stat & LTQ_SPI_STAT_BSY)) {
731 spi_finalize_current_transfer(spi->master);
732 return;
733 }
734
735 cond_resched();
736 } while (!time_after_eq(jiffies, end));
737
738 if (spi->master->cur_msg)
739 spi->master->cur_msg->status = -EIO;
740 spi_finalize_current_transfer(spi->master);
741}
742
743static void lantiq_ssc_handle_err(struct spi_master *master,
744 struct spi_message *message)
745{
746 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
747
748
749 rx_fifo_flush(spi);
750 tx_fifo_flush(spi);
751}
752
753static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
754{
755 struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
756 unsigned int cs = spidev->chip_select;
757 u32 fgpo;
758
759 if (!!(spidev->mode & SPI_CS_HIGH) == enable)
760 fgpo = (1 << (cs - spi->base_cs));
761 else
762 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
763
764 lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
765}
766
767static int lantiq_ssc_transfer_one(struct spi_master *master,
768 struct spi_device *spidev,
769 struct spi_transfer *t)
770{
771 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
772
773 hw_setup_transfer(spi, spidev, t);
774
775 return transfer_start(spi, spidev, t);
776}
777
778static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
779 .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
780 .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
781};
782
783static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
784 .irnen_r = LTQ_SPI_IRNEN_R_XRX,
785 .irnen_t = LTQ_SPI_IRNEN_T_XRX,
786};
787
788static const struct of_device_id lantiq_ssc_match[] = {
789 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
790 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
791 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
792 {},
793};
794MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
795
796static int lantiq_ssc_probe(struct platform_device *pdev)
797{
798 struct device *dev = &pdev->dev;
799 struct spi_master *master;
800 struct resource *res;
801 struct lantiq_ssc_spi *spi;
802 const struct lantiq_ssc_hwcfg *hwcfg;
803 const struct of_device_id *match;
804 int err, rx_irq, tx_irq, err_irq;
805 u32 id, supports_dma, revision;
806 unsigned int num_cs;
807
808 match = of_match_device(lantiq_ssc_match, dev);
809 if (!match) {
810 dev_err(dev, "no device match\n");
811 return -EINVAL;
812 }
813 hwcfg = match->data;
814
815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
816 if (!res) {
817 dev_err(dev, "failed to get resources\n");
818 return -ENXIO;
819 }
820
821 rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
822 if (rx_irq < 0) {
823 dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME);
824 return -ENXIO;
825 }
826
827 tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
828 if (tx_irq < 0) {
829 dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME);
830 return -ENXIO;
831 }
832
833 err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
834 if (err_irq < 0) {
835 dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME);
836 return -ENXIO;
837 }
838
839 master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
840 if (!master)
841 return -ENOMEM;
842
843 spi = spi_master_get_devdata(master);
844 spi->master = master;
845 spi->dev = dev;
846 spi->hwcfg = hwcfg;
847 platform_set_drvdata(pdev, spi);
848
849 spi->regbase = devm_ioremap_resource(dev, res);
850 if (IS_ERR(spi->regbase)) {
851 err = PTR_ERR(spi->regbase);
852 goto err_master_put;
853 }
854
855 err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
856 0, LTQ_SPI_RX_IRQ_NAME, spi);
857 if (err)
858 goto err_master_put;
859
860 err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
861 0, LTQ_SPI_TX_IRQ_NAME, spi);
862 if (err)
863 goto err_master_put;
864
865 err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
866 0, LTQ_SPI_ERR_IRQ_NAME, spi);
867 if (err)
868 goto err_master_put;
869
870 spi->spi_clk = devm_clk_get(dev, "gate");
871 if (IS_ERR(spi->spi_clk)) {
872 err = PTR_ERR(spi->spi_clk);
873 goto err_master_put;
874 }
875 err = clk_prepare_enable(spi->spi_clk);
876 if (err)
877 goto err_master_put;
878
879
880
881
882
883#if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
884 spi->fpi_clk = clk_get_fpi();
885#else
886 spi->fpi_clk = clk_get(dev, "freq");
887#endif
888 if (IS_ERR(spi->fpi_clk)) {
889 err = PTR_ERR(spi->fpi_clk);
890 goto err_clk_disable;
891 }
892
893 num_cs = 8;
894 of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
895
896 spi->base_cs = 1;
897 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
898
899 spin_lock_init(&spi->lock);
900 spi->bits_per_word = 8;
901 spi->speed_hz = 0;
902
903 master->dev.of_node = pdev->dev.of_node;
904 master->num_chipselect = num_cs;
905 master->setup = lantiq_ssc_setup;
906 master->set_cs = lantiq_ssc_set_cs;
907 master->handle_err = lantiq_ssc_handle_err;
908 master->prepare_message = lantiq_ssc_prepare_message;
909 master->unprepare_message = lantiq_ssc_unprepare_message;
910 master->transfer_one = lantiq_ssc_transfer_one;
911 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
912 SPI_LOOP;
913 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
914 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
915
916 spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);
917 if (!spi->wq) {
918 err = -ENOMEM;
919 goto err_clk_put;
920 }
921 INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
922
923 id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
924 spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
925 spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
926 supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
927 revision = id & LTQ_SPI_ID_REV_M;
928
929 lantiq_ssc_hw_init(spi);
930
931 dev_info(dev,
932 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
933 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
934
935 err = devm_spi_register_master(dev, master);
936 if (err) {
937 dev_err(dev, "failed to register spi_master\n");
938 goto err_wq_destroy;
939 }
940
941 return 0;
942
943err_wq_destroy:
944 destroy_workqueue(spi->wq);
945err_clk_put:
946 clk_put(spi->fpi_clk);
947err_clk_disable:
948 clk_disable_unprepare(spi->spi_clk);
949err_master_put:
950 spi_master_put(master);
951
952 return err;
953}
954
955static int lantiq_ssc_remove(struct platform_device *pdev)
956{
957 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
958
959 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
960 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
961 rx_fifo_flush(spi);
962 tx_fifo_flush(spi);
963 hw_enter_config_mode(spi);
964
965 destroy_workqueue(spi->wq);
966 clk_disable_unprepare(spi->spi_clk);
967 clk_put(spi->fpi_clk);
968
969 return 0;
970}
971
972static struct platform_driver lantiq_ssc_driver = {
973 .probe = lantiq_ssc_probe,
974 .remove = lantiq_ssc_remove,
975 .driver = {
976 .name = "spi-lantiq-ssc",
977 .of_match_table = lantiq_ssc_match,
978 },
979};
980module_platform_driver(lantiq_ssc_driver);
981
982MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
983MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
984MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
985MODULE_LICENSE("GPL");
986MODULE_ALIAS("platform:spi-lantiq-ssc");
987