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6
7#include <linux/clk.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_gpio.h>
16#include <linux/platform_device.h>
17#include <linux/platform_data/spi-mt65xx.h>
18#include <linux/pm_runtime.h>
19#include <linux/spi/spi.h>
20
21#define SPI_CFG0_REG 0x0000
22#define SPI_CFG1_REG 0x0004
23#define SPI_TX_SRC_REG 0x0008
24#define SPI_RX_DST_REG 0x000c
25#define SPI_TX_DATA_REG 0x0010
26#define SPI_RX_DATA_REG 0x0014
27#define SPI_CMD_REG 0x0018
28#define SPI_STATUS0_REG 0x001c
29#define SPI_PAD_SEL_REG 0x0024
30#define SPI_CFG2_REG 0x0028
31
32#define SPI_CFG0_SCK_HIGH_OFFSET 0
33#define SPI_CFG0_SCK_LOW_OFFSET 8
34#define SPI_CFG0_CS_HOLD_OFFSET 16
35#define SPI_CFG0_CS_SETUP_OFFSET 24
36#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
37#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
38#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
39
40#define SPI_CFG1_CS_IDLE_OFFSET 0
41#define SPI_CFG1_PACKET_LOOP_OFFSET 8
42#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
43#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
44
45#define SPI_CFG1_CS_IDLE_MASK 0xff
46#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
47#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
48
49#define SPI_CMD_ACT BIT(0)
50#define SPI_CMD_RESUME BIT(1)
51#define SPI_CMD_RST BIT(2)
52#define SPI_CMD_PAUSE_EN BIT(4)
53#define SPI_CMD_DEASSERT BIT(5)
54#define SPI_CMD_SAMPLE_SEL BIT(6)
55#define SPI_CMD_CS_POL BIT(7)
56#define SPI_CMD_CPHA BIT(8)
57#define SPI_CMD_CPOL BIT(9)
58#define SPI_CMD_RX_DMA BIT(10)
59#define SPI_CMD_TX_DMA BIT(11)
60#define SPI_CMD_TXMSBF BIT(12)
61#define SPI_CMD_RXMSBF BIT(13)
62#define SPI_CMD_RX_ENDIAN BIT(14)
63#define SPI_CMD_TX_ENDIAN BIT(15)
64#define SPI_CMD_FINISH_IE BIT(16)
65#define SPI_CMD_PAUSE_IE BIT(17)
66
67#define MT8173_SPI_MAX_PAD_SEL 3
68
69#define MTK_SPI_PAUSE_INT_STATUS 0x2
70
71#define MTK_SPI_IDLE 0
72#define MTK_SPI_PAUSED 1
73
74#define MTK_SPI_MAX_FIFO_SIZE 32U
75#define MTK_SPI_PACKET_SIZE 1024
76
77struct mtk_spi_compatible {
78 bool need_pad_sel;
79
80 bool must_tx;
81
82 bool enhance_timing;
83};
84
85struct mtk_spi {
86 void __iomem *base;
87 u32 state;
88 int pad_num;
89 u32 *pad_sel;
90 struct clk *parent_clk, *sel_clk, *spi_clk;
91 struct spi_transfer *cur_transfer;
92 u32 xfer_len;
93 u32 num_xfered;
94 struct scatterlist *tx_sgl, *rx_sgl;
95 u32 tx_sgl_len, rx_sgl_len;
96 const struct mtk_spi_compatible *dev_comp;
97};
98
99static const struct mtk_spi_compatible mtk_common_compat;
100
101static const struct mtk_spi_compatible mt2712_compat = {
102 .must_tx = true,
103};
104
105static const struct mtk_spi_compatible mt7622_compat = {
106 .must_tx = true,
107 .enhance_timing = true,
108};
109
110static const struct mtk_spi_compatible mt8173_compat = {
111 .need_pad_sel = true,
112 .must_tx = true,
113};
114
115static const struct mtk_spi_compatible mt8183_compat = {
116 .need_pad_sel = true,
117 .must_tx = true,
118 .enhance_timing = true,
119};
120
121
122
123
124
125static const struct mtk_chip_config mtk_default_chip_info = {
126 .cs_pol = 0,
127 .sample_sel = 0,
128};
129
130static const struct of_device_id mtk_spi_of_match[] = {
131 { .compatible = "mediatek,mt2701-spi",
132 .data = (void *)&mtk_common_compat,
133 },
134 { .compatible = "mediatek,mt2712-spi",
135 .data = (void *)&mt2712_compat,
136 },
137 { .compatible = "mediatek,mt6589-spi",
138 .data = (void *)&mtk_common_compat,
139 },
140 { .compatible = "mediatek,mt7622-spi",
141 .data = (void *)&mt7622_compat,
142 },
143 { .compatible = "mediatek,mt7629-spi",
144 .data = (void *)&mt7622_compat,
145 },
146 { .compatible = "mediatek,mt8135-spi",
147 .data = (void *)&mtk_common_compat,
148 },
149 { .compatible = "mediatek,mt8173-spi",
150 .data = (void *)&mt8173_compat,
151 },
152 { .compatible = "mediatek,mt8183-spi",
153 .data = (void *)&mt8183_compat,
154 },
155 {}
156};
157MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
158
159static void mtk_spi_reset(struct mtk_spi *mdata)
160{
161 u32 reg_val;
162
163
164 reg_val = readl(mdata->base + SPI_CMD_REG);
165 reg_val |= SPI_CMD_RST;
166 writel(reg_val, mdata->base + SPI_CMD_REG);
167
168 reg_val = readl(mdata->base + SPI_CMD_REG);
169 reg_val &= ~SPI_CMD_RST;
170 writel(reg_val, mdata->base + SPI_CMD_REG);
171}
172
173static int mtk_spi_prepare_message(struct spi_master *master,
174 struct spi_message *msg)
175{
176 u16 cpha, cpol;
177 u32 reg_val;
178 struct spi_device *spi = msg->spi;
179 struct mtk_chip_config *chip_config = spi->controller_data;
180 struct mtk_spi *mdata = spi_master_get_devdata(master);
181
182 cpha = spi->mode & SPI_CPHA ? 1 : 0;
183 cpol = spi->mode & SPI_CPOL ? 1 : 0;
184
185 reg_val = readl(mdata->base + SPI_CMD_REG);
186 if (cpha)
187 reg_val |= SPI_CMD_CPHA;
188 else
189 reg_val &= ~SPI_CMD_CPHA;
190 if (cpol)
191 reg_val |= SPI_CMD_CPOL;
192 else
193 reg_val &= ~SPI_CMD_CPOL;
194
195
196 if (spi->mode & SPI_LSB_FIRST) {
197 reg_val &= ~SPI_CMD_TXMSBF;
198 reg_val &= ~SPI_CMD_RXMSBF;
199 } else {
200 reg_val |= SPI_CMD_TXMSBF;
201 reg_val |= SPI_CMD_RXMSBF;
202 }
203
204
205#ifdef __LITTLE_ENDIAN
206 reg_val &= ~SPI_CMD_TX_ENDIAN;
207 reg_val &= ~SPI_CMD_RX_ENDIAN;
208#else
209 reg_val |= SPI_CMD_TX_ENDIAN;
210 reg_val |= SPI_CMD_RX_ENDIAN;
211#endif
212
213 if (mdata->dev_comp->enhance_timing) {
214 if (chip_config->cs_pol)
215 reg_val |= SPI_CMD_CS_POL;
216 else
217 reg_val &= ~SPI_CMD_CS_POL;
218 if (chip_config->sample_sel)
219 reg_val |= SPI_CMD_SAMPLE_SEL;
220 else
221 reg_val &= ~SPI_CMD_SAMPLE_SEL;
222 }
223
224
225 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
226
227
228 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
229
230
231 reg_val &= ~SPI_CMD_DEASSERT;
232
233 writel(reg_val, mdata->base + SPI_CMD_REG);
234
235
236 if (mdata->dev_comp->need_pad_sel)
237 writel(mdata->pad_sel[spi->chip_select],
238 mdata->base + SPI_PAD_SEL_REG);
239
240 return 0;
241}
242
243static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
244{
245 u32 reg_val;
246 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
247
248 reg_val = readl(mdata->base + SPI_CMD_REG);
249 if (!enable) {
250 reg_val |= SPI_CMD_PAUSE_EN;
251 writel(reg_val, mdata->base + SPI_CMD_REG);
252 } else {
253 reg_val &= ~SPI_CMD_PAUSE_EN;
254 writel(reg_val, mdata->base + SPI_CMD_REG);
255 mdata->state = MTK_SPI_IDLE;
256 mtk_spi_reset(mdata);
257 }
258}
259
260static void mtk_spi_prepare_transfer(struct spi_master *master,
261 struct spi_transfer *xfer)
262{
263 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
264 struct mtk_spi *mdata = spi_master_get_devdata(master);
265
266 spi_clk_hz = clk_get_rate(mdata->spi_clk);
267 if (xfer->speed_hz < spi_clk_hz / 2)
268 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
269 else
270 div = 1;
271
272 sck_time = (div + 1) / 2;
273 cs_time = sck_time * 2;
274
275 if (mdata->dev_comp->enhance_timing) {
276 reg_val |= (((sck_time - 1) & 0xffff)
277 << SPI_CFG0_SCK_HIGH_OFFSET);
278 reg_val |= (((sck_time - 1) & 0xffff)
279 << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
280 writel(reg_val, mdata->base + SPI_CFG2_REG);
281 reg_val |= (((cs_time - 1) & 0xffff)
282 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
283 reg_val |= (((cs_time - 1) & 0xffff)
284 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
285 writel(reg_val, mdata->base + SPI_CFG0_REG);
286 } else {
287 reg_val |= (((sck_time - 1) & 0xff)
288 << SPI_CFG0_SCK_HIGH_OFFSET);
289 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
290 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
291 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
292 writel(reg_val, mdata->base + SPI_CFG0_REG);
293 }
294
295 reg_val = readl(mdata->base + SPI_CFG1_REG);
296 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
297 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
298 writel(reg_val, mdata->base + SPI_CFG1_REG);
299}
300
301static void mtk_spi_setup_packet(struct spi_master *master)
302{
303 u32 packet_size, packet_loop, reg_val;
304 struct mtk_spi *mdata = spi_master_get_devdata(master);
305
306 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
307 packet_loop = mdata->xfer_len / packet_size;
308
309 reg_val = readl(mdata->base + SPI_CFG1_REG);
310 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
311 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
312 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
313 writel(reg_val, mdata->base + SPI_CFG1_REG);
314}
315
316static void mtk_spi_enable_transfer(struct spi_master *master)
317{
318 u32 cmd;
319 struct mtk_spi *mdata = spi_master_get_devdata(master);
320
321 cmd = readl(mdata->base + SPI_CMD_REG);
322 if (mdata->state == MTK_SPI_IDLE)
323 cmd |= SPI_CMD_ACT;
324 else
325 cmd |= SPI_CMD_RESUME;
326 writel(cmd, mdata->base + SPI_CMD_REG);
327}
328
329static int mtk_spi_get_mult_delta(u32 xfer_len)
330{
331 u32 mult_delta;
332
333 if (xfer_len > MTK_SPI_PACKET_SIZE)
334 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
335 else
336 mult_delta = 0;
337
338 return mult_delta;
339}
340
341static void mtk_spi_update_mdata_len(struct spi_master *master)
342{
343 int mult_delta;
344 struct mtk_spi *mdata = spi_master_get_devdata(master);
345
346 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
347 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
348 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
349 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
350 mdata->rx_sgl_len = mult_delta;
351 mdata->tx_sgl_len -= mdata->xfer_len;
352 } else {
353 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
354 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
355 mdata->tx_sgl_len = mult_delta;
356 mdata->rx_sgl_len -= mdata->xfer_len;
357 }
358 } else if (mdata->tx_sgl_len) {
359 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
360 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
361 mdata->tx_sgl_len = mult_delta;
362 } else if (mdata->rx_sgl_len) {
363 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
364 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
365 mdata->rx_sgl_len = mult_delta;
366 }
367}
368
369static void mtk_spi_setup_dma_addr(struct spi_master *master,
370 struct spi_transfer *xfer)
371{
372 struct mtk_spi *mdata = spi_master_get_devdata(master);
373
374 if (mdata->tx_sgl)
375 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
376 if (mdata->rx_sgl)
377 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
378}
379
380static int mtk_spi_fifo_transfer(struct spi_master *master,
381 struct spi_device *spi,
382 struct spi_transfer *xfer)
383{
384 int cnt, remainder;
385 u32 reg_val;
386 struct mtk_spi *mdata = spi_master_get_devdata(master);
387
388 mdata->cur_transfer = xfer;
389 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
390 mdata->num_xfered = 0;
391 mtk_spi_prepare_transfer(master, xfer);
392 mtk_spi_setup_packet(master);
393
394 cnt = xfer->len / 4;
395 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
396
397 remainder = xfer->len % 4;
398 if (remainder > 0) {
399 reg_val = 0;
400 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
401 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
402 }
403
404 mtk_spi_enable_transfer(master);
405
406 return 1;
407}
408
409static int mtk_spi_dma_transfer(struct spi_master *master,
410 struct spi_device *spi,
411 struct spi_transfer *xfer)
412{
413 int cmd;
414 struct mtk_spi *mdata = spi_master_get_devdata(master);
415
416 mdata->tx_sgl = NULL;
417 mdata->rx_sgl = NULL;
418 mdata->tx_sgl_len = 0;
419 mdata->rx_sgl_len = 0;
420 mdata->cur_transfer = xfer;
421 mdata->num_xfered = 0;
422
423 mtk_spi_prepare_transfer(master, xfer);
424
425 cmd = readl(mdata->base + SPI_CMD_REG);
426 if (xfer->tx_buf)
427 cmd |= SPI_CMD_TX_DMA;
428 if (xfer->rx_buf)
429 cmd |= SPI_CMD_RX_DMA;
430 writel(cmd, mdata->base + SPI_CMD_REG);
431
432 if (xfer->tx_buf)
433 mdata->tx_sgl = xfer->tx_sg.sgl;
434 if (xfer->rx_buf)
435 mdata->rx_sgl = xfer->rx_sg.sgl;
436
437 if (mdata->tx_sgl) {
438 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
439 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
440 }
441 if (mdata->rx_sgl) {
442 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
443 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
444 }
445
446 mtk_spi_update_mdata_len(master);
447 mtk_spi_setup_packet(master);
448 mtk_spi_setup_dma_addr(master, xfer);
449 mtk_spi_enable_transfer(master);
450
451 return 1;
452}
453
454static int mtk_spi_transfer_one(struct spi_master *master,
455 struct spi_device *spi,
456 struct spi_transfer *xfer)
457{
458 if (master->can_dma(master, spi, xfer))
459 return mtk_spi_dma_transfer(master, spi, xfer);
460 else
461 return mtk_spi_fifo_transfer(master, spi, xfer);
462}
463
464static bool mtk_spi_can_dma(struct spi_master *master,
465 struct spi_device *spi,
466 struct spi_transfer *xfer)
467{
468
469 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
470 (unsigned long)xfer->tx_buf % 4 == 0 &&
471 (unsigned long)xfer->rx_buf % 4 == 0);
472}
473
474static int mtk_spi_setup(struct spi_device *spi)
475{
476 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
477
478 if (!spi->controller_data)
479 spi->controller_data = (void *)&mtk_default_chip_info;
480
481 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
482 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
483
484 return 0;
485}
486
487static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
488{
489 u32 cmd, reg_val, cnt, remainder, len;
490 struct spi_master *master = dev_id;
491 struct mtk_spi *mdata = spi_master_get_devdata(master);
492 struct spi_transfer *trans = mdata->cur_transfer;
493
494 reg_val = readl(mdata->base + SPI_STATUS0_REG);
495 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
496 mdata->state = MTK_SPI_PAUSED;
497 else
498 mdata->state = MTK_SPI_IDLE;
499
500 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
501 if (trans->rx_buf) {
502 cnt = mdata->xfer_len / 4;
503 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
504 trans->rx_buf + mdata->num_xfered, cnt);
505 remainder = mdata->xfer_len % 4;
506 if (remainder > 0) {
507 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
508 memcpy(trans->rx_buf +
509 mdata->num_xfered +
510 (cnt * 4),
511 ®_val,
512 remainder);
513 }
514 }
515
516 mdata->num_xfered += mdata->xfer_len;
517 if (mdata->num_xfered == trans->len) {
518 spi_finalize_current_transfer(master);
519 return IRQ_HANDLED;
520 }
521
522 len = trans->len - mdata->num_xfered;
523 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
524 mtk_spi_setup_packet(master);
525
526 cnt = mdata->xfer_len / 4;
527 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
528 trans->tx_buf + mdata->num_xfered, cnt);
529
530 remainder = mdata->xfer_len % 4;
531 if (remainder > 0) {
532 reg_val = 0;
533 memcpy(®_val,
534 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
535 remainder);
536 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
537 }
538
539 mtk_spi_enable_transfer(master);
540
541 return IRQ_HANDLED;
542 }
543
544 if (mdata->tx_sgl)
545 trans->tx_dma += mdata->xfer_len;
546 if (mdata->rx_sgl)
547 trans->rx_dma += mdata->xfer_len;
548
549 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
550 mdata->tx_sgl = sg_next(mdata->tx_sgl);
551 if (mdata->tx_sgl) {
552 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
553 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
554 }
555 }
556 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
557 mdata->rx_sgl = sg_next(mdata->rx_sgl);
558 if (mdata->rx_sgl) {
559 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
560 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
561 }
562 }
563
564 if (!mdata->tx_sgl && !mdata->rx_sgl) {
565
566 cmd = readl(mdata->base + SPI_CMD_REG);
567 cmd &= ~SPI_CMD_TX_DMA;
568 cmd &= ~SPI_CMD_RX_DMA;
569 writel(cmd, mdata->base + SPI_CMD_REG);
570
571 spi_finalize_current_transfer(master);
572 return IRQ_HANDLED;
573 }
574
575 mtk_spi_update_mdata_len(master);
576 mtk_spi_setup_packet(master);
577 mtk_spi_setup_dma_addr(master, trans);
578 mtk_spi_enable_transfer(master);
579
580 return IRQ_HANDLED;
581}
582
583static int mtk_spi_probe(struct platform_device *pdev)
584{
585 struct spi_master *master;
586 struct mtk_spi *mdata;
587 const struct of_device_id *of_id;
588 struct resource *res;
589 int i, irq, ret;
590
591 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
592 if (!master) {
593 dev_err(&pdev->dev, "failed to alloc spi master\n");
594 return -ENOMEM;
595 }
596
597 master->auto_runtime_pm = true;
598 master->dev.of_node = pdev->dev.of_node;
599 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
600
601 master->set_cs = mtk_spi_set_cs;
602 master->prepare_message = mtk_spi_prepare_message;
603 master->transfer_one = mtk_spi_transfer_one;
604 master->can_dma = mtk_spi_can_dma;
605 master->setup = mtk_spi_setup;
606
607 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
608 if (!of_id) {
609 dev_err(&pdev->dev, "failed to probe of_node\n");
610 ret = -EINVAL;
611 goto err_put_master;
612 }
613
614 mdata = spi_master_get_devdata(master);
615 mdata->dev_comp = of_id->data;
616 if (mdata->dev_comp->must_tx)
617 master->flags = SPI_MASTER_MUST_TX;
618
619 if (mdata->dev_comp->need_pad_sel) {
620 mdata->pad_num = of_property_count_u32_elems(
621 pdev->dev.of_node,
622 "mediatek,pad-select");
623 if (mdata->pad_num < 0) {
624 dev_err(&pdev->dev,
625 "No 'mediatek,pad-select' property\n");
626 ret = -EINVAL;
627 goto err_put_master;
628 }
629
630 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
631 sizeof(u32), GFP_KERNEL);
632 if (!mdata->pad_sel) {
633 ret = -ENOMEM;
634 goto err_put_master;
635 }
636
637 for (i = 0; i < mdata->pad_num; i++) {
638 of_property_read_u32_index(pdev->dev.of_node,
639 "mediatek,pad-select",
640 i, &mdata->pad_sel[i]);
641 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
642 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
643 i, mdata->pad_sel[i]);
644 ret = -EINVAL;
645 goto err_put_master;
646 }
647 }
648 }
649
650 platform_set_drvdata(pdev, master);
651
652 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
653 if (!res) {
654 ret = -ENODEV;
655 dev_err(&pdev->dev, "failed to determine base address\n");
656 goto err_put_master;
657 }
658
659 mdata->base = devm_ioremap_resource(&pdev->dev, res);
660 if (IS_ERR(mdata->base)) {
661 ret = PTR_ERR(mdata->base);
662 goto err_put_master;
663 }
664
665 irq = platform_get_irq(pdev, 0);
666 if (irq < 0) {
667 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
668 ret = irq;
669 goto err_put_master;
670 }
671
672 if (!pdev->dev.dma_mask)
673 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
674
675 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
676 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
677 if (ret) {
678 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
679 goto err_put_master;
680 }
681
682 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
683 if (IS_ERR(mdata->parent_clk)) {
684 ret = PTR_ERR(mdata->parent_clk);
685 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
686 goto err_put_master;
687 }
688
689 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
690 if (IS_ERR(mdata->sel_clk)) {
691 ret = PTR_ERR(mdata->sel_clk);
692 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
693 goto err_put_master;
694 }
695
696 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
697 if (IS_ERR(mdata->spi_clk)) {
698 ret = PTR_ERR(mdata->spi_clk);
699 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
700 goto err_put_master;
701 }
702
703 ret = clk_prepare_enable(mdata->spi_clk);
704 if (ret < 0) {
705 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
706 goto err_put_master;
707 }
708
709 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
710 if (ret < 0) {
711 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
712 clk_disable_unprepare(mdata->spi_clk);
713 goto err_put_master;
714 }
715
716 clk_disable_unprepare(mdata->spi_clk);
717
718 pm_runtime_enable(&pdev->dev);
719
720 ret = devm_spi_register_master(&pdev->dev, master);
721 if (ret) {
722 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
723 goto err_disable_runtime_pm;
724 }
725
726 if (mdata->dev_comp->need_pad_sel) {
727 if (mdata->pad_num != master->num_chipselect) {
728 dev_err(&pdev->dev,
729 "pad_num does not match num_chipselect(%d != %d)\n",
730 mdata->pad_num, master->num_chipselect);
731 ret = -EINVAL;
732 goto err_disable_runtime_pm;
733 }
734
735 if (!master->cs_gpios && master->num_chipselect > 1) {
736 dev_err(&pdev->dev,
737 "cs_gpios not specified and num_chipselect > 1\n");
738 ret = -EINVAL;
739 goto err_disable_runtime_pm;
740 }
741
742 if (master->cs_gpios) {
743 for (i = 0; i < master->num_chipselect; i++) {
744 ret = devm_gpio_request(&pdev->dev,
745 master->cs_gpios[i],
746 dev_name(&pdev->dev));
747 if (ret) {
748 dev_err(&pdev->dev,
749 "can't get CS GPIO %i\n", i);
750 goto err_disable_runtime_pm;
751 }
752 }
753 }
754 }
755
756 return 0;
757
758err_disable_runtime_pm:
759 pm_runtime_disable(&pdev->dev);
760err_put_master:
761 spi_master_put(master);
762
763 return ret;
764}
765
766static int mtk_spi_remove(struct platform_device *pdev)
767{
768 struct spi_master *master = platform_get_drvdata(pdev);
769 struct mtk_spi *mdata = spi_master_get_devdata(master);
770
771 pm_runtime_disable(&pdev->dev);
772
773 mtk_spi_reset(mdata);
774
775 return 0;
776}
777
778#ifdef CONFIG_PM_SLEEP
779static int mtk_spi_suspend(struct device *dev)
780{
781 int ret;
782 struct spi_master *master = dev_get_drvdata(dev);
783 struct mtk_spi *mdata = spi_master_get_devdata(master);
784
785 ret = spi_master_suspend(master);
786 if (ret)
787 return ret;
788
789 if (!pm_runtime_suspended(dev))
790 clk_disable_unprepare(mdata->spi_clk);
791
792 return ret;
793}
794
795static int mtk_spi_resume(struct device *dev)
796{
797 int ret;
798 struct spi_master *master = dev_get_drvdata(dev);
799 struct mtk_spi *mdata = spi_master_get_devdata(master);
800
801 if (!pm_runtime_suspended(dev)) {
802 ret = clk_prepare_enable(mdata->spi_clk);
803 if (ret < 0) {
804 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
805 return ret;
806 }
807 }
808
809 ret = spi_master_resume(master);
810 if (ret < 0)
811 clk_disable_unprepare(mdata->spi_clk);
812
813 return ret;
814}
815#endif
816
817#ifdef CONFIG_PM
818static int mtk_spi_runtime_suspend(struct device *dev)
819{
820 struct spi_master *master = dev_get_drvdata(dev);
821 struct mtk_spi *mdata = spi_master_get_devdata(master);
822
823 clk_disable_unprepare(mdata->spi_clk);
824
825 return 0;
826}
827
828static int mtk_spi_runtime_resume(struct device *dev)
829{
830 struct spi_master *master = dev_get_drvdata(dev);
831 struct mtk_spi *mdata = spi_master_get_devdata(master);
832 int ret;
833
834 ret = clk_prepare_enable(mdata->spi_clk);
835 if (ret < 0) {
836 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
837 return ret;
838 }
839
840 return 0;
841}
842#endif
843
844static const struct dev_pm_ops mtk_spi_pm = {
845 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
846 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
847 mtk_spi_runtime_resume, NULL)
848};
849
850static struct platform_driver mtk_spi_driver = {
851 .driver = {
852 .name = "mtk-spi",
853 .pm = &mtk_spi_pm,
854 .of_match_table = mtk_spi_of_match,
855 },
856 .probe = mtk_spi_probe,
857 .remove = mtk_spi_remove,
858};
859
860module_platform_driver(mtk_spi_driver);
861
862MODULE_DESCRIPTION("MTK SPI Controller driver");
863MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
864MODULE_LICENSE("GPL v2");
865MODULE_ALIAS("platform:mtk-spi");
866
