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8#include <linux/spinlock.h>
9#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18
19#include <linux/spi/spi.h>
20#include <linux/spi/spi_bitbang.h>
21#include <linux/spi/s3c24xx.h>
22#include <linux/module.h>
23
24#include <plat/regs-spi.h>
25
26#include <asm/fiq.h>
27
28#include "spi-s3c24xx-fiq.h"
29
30
31
32
33
34
35
36
37struct s3c24xx_spi_devstate {
38 unsigned int hz;
39 unsigned int mode;
40 u8 spcon;
41 u8 sppre;
42};
43
44enum spi_fiq_mode {
45 FIQ_MODE_NONE = 0,
46 FIQ_MODE_TX = 1,
47 FIQ_MODE_RX = 2,
48 FIQ_MODE_TXRX = 3,
49};
50
51struct s3c24xx_spi {
52
53 struct spi_bitbang bitbang;
54 struct completion done;
55
56 void __iomem *regs;
57 int irq;
58 int len;
59 int count;
60
61 struct fiq_handler fiq_handler;
62 enum spi_fiq_mode fiq_mode;
63 unsigned char fiq_inuse;
64 unsigned char fiq_claimed;
65
66 void (*set_cs)(struct s3c2410_spi_info *spi,
67 int cs, int pol);
68
69
70 const unsigned char *tx;
71 unsigned char *rx;
72
73 struct clk *clk;
74 struct spi_master *master;
75 struct spi_device *curdev;
76 struct device *dev;
77 struct s3c2410_spi_info *pdata;
78};
79
80#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
81#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
82
83static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
84{
85 return spi_master_get_devdata(sdev->master);
86}
87
88static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
89{
90 gpio_set_value(spi->pin_cs, pol);
91}
92
93static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
94{
95 struct s3c24xx_spi_devstate *cs = spi->controller_state;
96 struct s3c24xx_spi *hw = to_hw(spi);
97 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
98
99
100
101 switch (value) {
102 case BITBANG_CS_INACTIVE:
103 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
104 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
105 break;
106
107 case BITBANG_CS_ACTIVE:
108 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
109 hw->regs + S3C2410_SPCON);
110 hw->set_cs(hw->pdata, spi->chip_select, cspol);
111 break;
112 }
113}
114
115static int s3c24xx_spi_update_state(struct spi_device *spi,
116 struct spi_transfer *t)
117{
118 struct s3c24xx_spi *hw = to_hw(spi);
119 struct s3c24xx_spi_devstate *cs = spi->controller_state;
120 unsigned int hz;
121 unsigned int div;
122 unsigned long clk;
123
124 hz = t ? t->speed_hz : spi->max_speed_hz;
125
126 if (!hz)
127 hz = spi->max_speed_hz;
128
129 if (spi->mode != cs->mode) {
130 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
131
132 if (spi->mode & SPI_CPHA)
133 spcon |= S3C2410_SPCON_CPHA_FMTB;
134
135 if (spi->mode & SPI_CPOL)
136 spcon |= S3C2410_SPCON_CPOL_HIGH;
137
138 cs->mode = spi->mode;
139 cs->spcon = spcon;
140 }
141
142 if (cs->hz != hz) {
143 clk = clk_get_rate(hw->clk);
144 div = DIV_ROUND_UP(clk, hz * 2) - 1;
145
146 if (div > 255)
147 div = 255;
148
149 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
150 div, hz, clk / (2 * (div + 1)));
151
152 cs->hz = hz;
153 cs->sppre = div;
154 }
155
156 return 0;
157}
158
159static int s3c24xx_spi_setupxfer(struct spi_device *spi,
160 struct spi_transfer *t)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 ret = s3c24xx_spi_update_state(spi, t);
167 if (!ret)
168 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
169
170 return ret;
171}
172
173static int s3c24xx_spi_setup(struct spi_device *spi)
174{
175 struct s3c24xx_spi_devstate *cs = spi->controller_state;
176 struct s3c24xx_spi *hw = to_hw(spi);
177 int ret;
178
179
180 if (!cs) {
181 cs = devm_kzalloc(&spi->dev,
182 sizeof(struct s3c24xx_spi_devstate),
183 GFP_KERNEL);
184 if (!cs)
185 return -ENOMEM;
186
187 cs->spcon = SPCON_DEFAULT;
188 cs->hz = -1;
189 spi->controller_state = cs;
190 }
191
192
193 ret = s3c24xx_spi_update_state(spi, NULL);
194 if (ret)
195 return ret;
196
197 mutex_lock(&hw->bitbang.lock);
198 if (!hw->bitbang.busy) {
199 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
200
201 }
202 mutex_unlock(&hw->bitbang.lock);
203
204 return 0;
205}
206
207static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
208{
209 return hw->tx ? hw->tx[count] : 0;
210}
211
212#ifdef CONFIG_SPI_S3C24XX_FIQ
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225
226
227struct spi_fiq_code {
228 u32 length;
229 u32 ack_offset;
230 u8 data[0];
231};
232
233extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
234extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
235extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
236
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240
241
242
243static inline u32 ack_bit(unsigned int irq)
244{
245 return 1 << (irq - IRQ_EINT0);
246}
247
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256
257
258
259static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
260{
261 struct pt_regs regs;
262 enum spi_fiq_mode mode;
263 struct spi_fiq_code *code;
264 int ret;
265
266 if (!hw->fiq_claimed) {
267
268
269
270 ret = claim_fiq(&hw->fiq_handler);
271 if (ret)
272 return;
273 }
274
275 if (hw->tx && !hw->rx)
276 mode = FIQ_MODE_TX;
277 else if (hw->rx && !hw->tx)
278 mode = FIQ_MODE_RX;
279 else
280 mode = FIQ_MODE_TXRX;
281
282 regs.uregs[fiq_rspi] = (long)hw->regs;
283 regs.uregs[fiq_rrx] = (long)hw->rx;
284 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
285 regs.uregs[fiq_rcount] = hw->len - 1;
286 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
287
288 set_fiq_regs(®s);
289
290 if (hw->fiq_mode != mode) {
291 u32 *ack_ptr;
292
293 hw->fiq_mode = mode;
294
295 switch (mode) {
296 case FIQ_MODE_TX:
297 code = &s3c24xx_spi_fiq_tx;
298 break;
299 case FIQ_MODE_RX:
300 code = &s3c24xx_spi_fiq_rx;
301 break;
302 case FIQ_MODE_TXRX:
303 code = &s3c24xx_spi_fiq_txrx;
304 break;
305 default:
306 code = NULL;
307 }
308
309 BUG_ON(!code);
310
311 ack_ptr = (u32 *)&code->data[code->ack_offset];
312 *ack_ptr = ack_bit(hw->irq);
313
314 set_fiq_handler(&code->data, code->length);
315 }
316
317 s3c24xx_set_fiq(hw->irq, true);
318
319 hw->fiq_mode = mode;
320 hw->fiq_inuse = 1;
321}
322
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328
329
330
331
332static int s3c24xx_spi_fiqop(void *pw, int release)
333{
334 struct s3c24xx_spi *hw = pw;
335 int ret = 0;
336
337 if (release) {
338 if (hw->fiq_inuse)
339 ret = -EBUSY;
340
341
342
343
344 hw->fiq_mode = FIQ_MODE_NONE;
345 hw->fiq_claimed = 0;
346 } else {
347 hw->fiq_claimed = 1;
348 }
349
350 return ret;
351}
352
353
354
355
356
357
358
359static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
360{
361 hw->fiq_handler.dev_id = hw;
362 hw->fiq_handler.name = dev_name(hw->dev);
363 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
364}
365
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372
373static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
374{
375 return hw->pdata->use_fiq;
376}
377
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382
383
384
385static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
386{
387 return spi->fiq_inuse;
388}
389#else
390
391static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
392static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
393static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
394static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
395
396#endif
397
398static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
399{
400 struct s3c24xx_spi *hw = to_hw(spi);
401
402 hw->tx = t->tx_buf;
403 hw->rx = t->rx_buf;
404 hw->len = t->len;
405 hw->count = 0;
406
407 init_completion(&hw->done);
408
409 hw->fiq_inuse = 0;
410 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
411 s3c24xx_spi_tryfiq(hw);
412
413
414 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
415
416 wait_for_completion(&hw->done);
417 return hw->count;
418}
419
420static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
421{
422 struct s3c24xx_spi *hw = dev;
423 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
424 unsigned int count = hw->count;
425
426 if (spsta & S3C2410_SPSTA_DCOL) {
427 dev_dbg(hw->dev, "data-collision\n");
428 complete(&hw->done);
429 goto irq_done;
430 }
431
432 if (!(spsta & S3C2410_SPSTA_READY)) {
433 dev_dbg(hw->dev, "spi not ready for tx?\n");
434 complete(&hw->done);
435 goto irq_done;
436 }
437
438 if (!s3c24xx_spi_usingfiq(hw)) {
439 hw->count++;
440
441 if (hw->rx)
442 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
443
444 count++;
445
446 if (count < hw->len)
447 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
448 else
449 complete(&hw->done);
450 } else {
451 hw->count = hw->len;
452 hw->fiq_inuse = 0;
453
454 if (hw->rx)
455 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
456
457 complete(&hw->done);
458 }
459
460 irq_done:
461 return IRQ_HANDLED;
462}
463
464static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
465{
466
467
468 clk_enable(hw->clk);
469
470
471
472 writeb(0xff, hw->regs + S3C2410_SPPRE);
473 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
474 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
475
476 if (hw->pdata) {
477 if (hw->set_cs == s3c24xx_spi_gpiocs)
478 gpio_direction_output(hw->pdata->pin_cs, 1);
479
480 if (hw->pdata->gpio_setup)
481 hw->pdata->gpio_setup(hw->pdata, 1);
482 }
483}
484
485static int s3c24xx_spi_probe(struct platform_device *pdev)
486{
487 struct s3c2410_spi_info *pdata;
488 struct s3c24xx_spi *hw;
489 struct spi_master *master;
490 struct resource *res;
491 int err = 0;
492
493 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
494 if (master == NULL) {
495 dev_err(&pdev->dev, "No memory for spi_master\n");
496 return -ENOMEM;
497 }
498
499 hw = spi_master_get_devdata(master);
500
501 hw->master = master;
502 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
503 hw->dev = &pdev->dev;
504
505 if (pdata == NULL) {
506 dev_err(&pdev->dev, "No platform data supplied\n");
507 err = -ENOENT;
508 goto err_no_pdata;
509 }
510
511 platform_set_drvdata(pdev, hw);
512 init_completion(&hw->done);
513
514
515
516 s3c24xx_spi_initfiq(hw);
517
518
519
520
521 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
522
523 master->num_chipselect = hw->pdata->num_cs;
524 master->bus_num = pdata->bus_num;
525 master->bits_per_word_mask = SPI_BPW_MASK(8);
526
527
528
529 hw->bitbang.master = hw->master;
530 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
531 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
532 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
533
534 hw->master->setup = s3c24xx_spi_setup;
535
536 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
537
538
539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
540 hw->regs = devm_ioremap_resource(&pdev->dev, res);
541 if (IS_ERR(hw->regs)) {
542 err = PTR_ERR(hw->regs);
543 goto err_no_pdata;
544 }
545
546 hw->irq = platform_get_irq(pdev, 0);
547 if (hw->irq < 0) {
548 dev_err(&pdev->dev, "No IRQ specified\n");
549 err = -ENOENT;
550 goto err_no_pdata;
551 }
552
553 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
554 pdev->name, hw);
555 if (err) {
556 dev_err(&pdev->dev, "Cannot claim IRQ\n");
557 goto err_no_pdata;
558 }
559
560 hw->clk = devm_clk_get(&pdev->dev, "spi");
561 if (IS_ERR(hw->clk)) {
562 dev_err(&pdev->dev, "No clock for device\n");
563 err = PTR_ERR(hw->clk);
564 goto err_no_pdata;
565 }
566
567
568
569 if (!pdata->set_cs) {
570 if (pdata->pin_cs < 0) {
571 dev_err(&pdev->dev, "No chipselect pin\n");
572 err = -EINVAL;
573 goto err_register;
574 }
575
576 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
577 dev_name(&pdev->dev));
578 if (err) {
579 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
580 goto err_register;
581 }
582
583 hw->set_cs = s3c24xx_spi_gpiocs;
584 gpio_direction_output(pdata->pin_cs, 1);
585 } else
586 hw->set_cs = pdata->set_cs;
587
588 s3c24xx_spi_initialsetup(hw);
589
590
591
592 err = spi_bitbang_start(&hw->bitbang);
593 if (err) {
594 dev_err(&pdev->dev, "Failed to register SPI master\n");
595 goto err_register;
596 }
597
598 return 0;
599
600 err_register:
601 clk_disable(hw->clk);
602
603 err_no_pdata:
604 spi_master_put(hw->master);
605 return err;
606}
607
608static int s3c24xx_spi_remove(struct platform_device *dev)
609{
610 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
611
612 spi_bitbang_stop(&hw->bitbang);
613 clk_disable(hw->clk);
614 spi_master_put(hw->master);
615 return 0;
616}
617
618
619#ifdef CONFIG_PM
620
621static int s3c24xx_spi_suspend(struct device *dev)
622{
623 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
624 int ret;
625
626 ret = spi_master_suspend(hw->master);
627 if (ret)
628 return ret;
629
630 if (hw->pdata && hw->pdata->gpio_setup)
631 hw->pdata->gpio_setup(hw->pdata, 0);
632
633 clk_disable(hw->clk);
634 return 0;
635}
636
637static int s3c24xx_spi_resume(struct device *dev)
638{
639 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
640
641 s3c24xx_spi_initialsetup(hw);
642 return spi_master_resume(hw->master);
643}
644
645static const struct dev_pm_ops s3c24xx_spi_pmops = {
646 .suspend = s3c24xx_spi_suspend,
647 .resume = s3c24xx_spi_resume,
648};
649
650#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
651#else
652#define S3C24XX_SPI_PMOPS NULL
653#endif
654
655MODULE_ALIAS("platform:s3c2410-spi");
656static struct platform_driver s3c24xx_spi_driver = {
657 .probe = s3c24xx_spi_probe,
658 .remove = s3c24xx_spi_remove,
659 .driver = {
660 .name = "s3c2410-spi",
661 .pm = S3C24XX_SPI_PMOPS,
662 },
663};
664module_platform_driver(s3c24xx_spi_driver);
665
666MODULE_DESCRIPTION("S3C24XX SPI Driver");
667MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
668MODULE_LICENSE("GPL");
669