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19#ifndef _DAVINCI_VPFE_DM365_IPIPEIF_H
20#define _DAVINCI_VPFE_DM365_IPIPEIF_H
21
22#include <linux/platform_device.h>
23
24#include <media/davinci/vpss.h>
25#include <media/v4l2-ctrls.h>
26#include <media/v4l2-subdev.h>
27
28#include "dm365_ipipeif_user.h"
29#include "vpfe_video.h"
30
31
32enum ipipeif_data_shift {
33 IPIPEIF_BITS15_2 = 0,
34 IPIPEIF_BITS14_1 = 1,
35 IPIPEIF_BITS13_0 = 2,
36 IPIPEIF_BITS12_0 = 3,
37 IPIPEIF_BITS11_0 = 4,
38 IPIPEIF_BITS10_0 = 5,
39 IPIPEIF_BITS9_0 = 6,
40};
41
42enum ipipeif_clkdiv {
43 IPIPEIF_DIVIDE_HALF = 0,
44 IPIPEIF_DIVIDE_THIRD = 1,
45 IPIPEIF_DIVIDE_FOURTH = 2,
46 IPIPEIF_DIVIDE_FIFTH = 3,
47 IPIPEIF_DIVIDE_SIXTH = 4,
48 IPIPEIF_DIVIDE_EIGHTH = 5,
49 IPIPEIF_DIVIDE_SIXTEENTH = 6,
50 IPIPEIF_DIVIDE_THIRTY = 7,
51};
52
53enum ipipeif_pack_mode {
54 IPIPEIF_PACK_16_BIT = 0,
55 IPIPEIF_PACK_8_BIT = 1,
56};
57
58enum ipipeif_5_1_pack_mode {
59 IPIPEIF_5_1_PACK_16_BIT = 0,
60 IPIPEIF_5_1_PACK_8_BIT = 1,
61 IPIPEIF_5_1_PACK_8_BIT_A_LAW = 2,
62 IPIPEIF_5_1_PACK_12_BIT = 3
63};
64
65enum ipipeif_input_source {
66 IPIPEIF_CCDC = 0,
67 IPIPEIF_SDRAM_RAW = 1,
68 IPIPEIF_CCDC_DARKFM = 2,
69 IPIPEIF_SDRAM_YUV = 3,
70};
71
72enum ipipeif_ialaw {
73 IPIPEIF_ALAW_OFF = 0,
74 IPIPEIF_ALAW_ON = 1,
75};
76
77enum ipipeif_input_src1 {
78 IPIPEIF_SRC1_PARALLEL_PORT = 0,
79 IPIPEIF_SRC1_SDRAM_RAW = 1,
80 IPIPEIF_SRC1_ISIF_DARKFM = 2,
81 IPIPEIF_SRC1_SDRAM_YUV = 3,
82};
83
84enum ipipeif_dfs_dir {
85 IPIPEIF_PORT_MINUS_SDRAM = 0,
86 IPIPEIF_SDRAM_MINUS_PORT = 1,
87};
88
89enum ipipeif_chroma_phase {
90 IPIPEIF_CBCR_Y = 0,
91 IPIPEIF_Y_CBCR = 1,
92};
93
94enum ipipeif_dpcm_type {
95 IPIPEIF_DPCM_8BIT_10BIT = 0,
96 IPIPEIF_DPCM_8BIT_12BIT = 1,
97};
98
99
100enum ipipeif_5_1_data_shift {
101 IPIPEIF_5_1_BITS11_0 = 0,
102 IPIPEIF_5_1_BITS10_0 = 1,
103 IPIPEIF_5_1_BITS9_0 = 2,
104 IPIPEIF_5_1_BITS8_0 = 3,
105 IPIPEIF_5_1_BITS7_0 = 4,
106 IPIPEIF_5_1_BITS15_4 = 5,
107};
108
109#define IPIPEIF_PAD_SINK 0
110#define IPIPEIF_PAD_SOURCE 1
111
112#define IPIPEIF_NUM_PADS 2
113
114enum ipipeif_input_entity {
115 IPIPEIF_INPUT_NONE = 0,
116 IPIPEIF_INPUT_ISIF = 1,
117 IPIPEIF_INPUT_MEMORY = 2,
118};
119
120enum ipipeif_output_entity {
121 IPIPEIF_OUTPUT_NONE = 0,
122 IPIPEIF_OUTPUT_IPIPE = 1,
123 IPIPEIF_OUTPUT_RESIZER = 2,
124};
125
126struct vpfe_ipipeif_device {
127 struct v4l2_subdev subdev;
128 struct media_pad pads[IPIPEIF_NUM_PADS];
129 struct v4l2_mbus_framefmt formats[IPIPEIF_NUM_PADS];
130 enum ipipeif_input_entity input;
131 unsigned int output;
132 struct vpfe_video_device video_in;
133 struct v4l2_ctrl_handler ctrls;
134 void __iomem *ipipeif_base_addr;
135 struct ipipeif_params config;
136 int dpcm_predictor;
137 int gain;
138};
139
140
141#define IPIPEIF_ENABLE 0x00
142#define IPIPEIF_CFG1 0x04
143#define IPIPEIF_PPLN 0x08
144#define IPIPEIF_LPFR 0x0c
145#define IPIPEIF_HNUM 0x10
146#define IPIPEIF_VNUM 0x14
147#define IPIPEIF_ADDRU 0x18
148#define IPIPEIF_ADDRL 0x1c
149#define IPIPEIF_ADOFS 0x20
150#define IPIPEIF_RSZ 0x24
151#define IPIPEIF_GAIN 0x28
152
153
154#define IPIPEIF_DPCM 0x2c
155#define IPIPEIF_CFG2 0x30
156#define IPIPEIF_INIRSZ 0x34
157#define IPIPEIF_OCLIP 0x38
158#define IPIPEIF_DTUDF 0x3c
159#define IPIPEIF_CLKDIV 0x40
160#define IPIPEIF_DPC1 0x44
161#define IPIPEIF_DPC2 0x48
162#define IPIPEIF_DFSGVL 0x4c
163#define IPIPEIF_DFSGTH 0x50
164#define IPIPEIF_RSZ3A 0x54
165#define IPIPEIF_INIRSZ3A 0x58
166#define IPIPEIF_RSZ_MIN 16
167#define IPIPEIF_RSZ_MAX 112
168#define IPIPEIF_RSZ_CONST 16
169
170#define IPIPEIF_ADOFS_LSB_MASK 0x1ff
171#define IPIPEIF_ADOFS_LSB_SHIFT 5
172#define IPIPEIF_ADOFS_MSB_MASK 0x200
173#define IPIPEIF_ADDRU_MASK 0x7ff
174#define IPIPEIF_ADDRL_SHIFT 5
175#define IPIPEIF_ADDRL_MASK 0xffff
176#define IPIPEIF_ADDRU_SHIFT 21
177#define IPIPEIF_ADDRMSB_SHIFT 31
178#define IPIPEIF_ADDRMSB_LEFT_SHIFT 10
179
180
181#define ONESHOT_SHIFT 0
182#define DECIM_SHIFT 1
183#define INPSRC_SHIFT 2
184#define CLKDIV_SHIFT 4
185#define AVGFILT_SHIFT 7
186#define PACK8IN_SHIFT 8
187#define IALAW_SHIFT 9
188#define CLKSEL_SHIFT 10
189#define DATASFT_SHIFT 11
190#define INPSRC1_SHIFT 14
191
192
193#define IPIPEIF_DPC2_EN_SHIFT 12
194#define IPIPEIF_DPC2_THR_MASK 0xfff
195
196#define IPIPEIF_DF_GAIN_EN_SHIFT 10
197#define IPIPEIF_DF_GAIN_MASK 0x3ff
198#define IPIPEIF_DF_GAIN_THR_MASK 0xfff
199
200#define IPIPEIF_DPCM_BITS_SHIFT 2
201#define IPIPEIF_DPCM_PRED_SHIFT 1
202
203#define IPIPEIF_CFG2_HDPOL_SHIFT 1
204#define IPIPEIF_CFG2_VDPOL_SHIFT 2
205#define IPIPEIF_CFG2_YUV8_SHIFT 6
206#define IPIPEIF_CFG2_YUV16_SHIFT 3
207#define IPIPEIF_CFG2_YUV8P_SHIFT 7
208
209
210#define IPIPEIF_INIRSZ_ALNSYNC_SHIFT 13
211#define IPIPEIF_INIRSZ_MASK 0x1fff
212
213
214#define IPIPEIF_CLKDIV_M_SHIFT 8
215
216void vpfe_ipipeif_enable(struct vpfe_device *vpfe_dev);
217void vpfe_ipipeif_ss_buffer_isr(struct vpfe_ipipeif_device *ipipeif);
218int vpfe_ipipeif_decimation_enabled(struct vpfe_device *vpfe_dev);
219int vpfe_ipipeif_get_rsz(struct vpfe_device *vpfe_dev);
220void vpfe_ipipeif_cleanup(struct vpfe_ipipeif_device *ipipeif,
221 struct platform_device *pdev);
222int vpfe_ipipeif_init(struct vpfe_ipipeif_device *ipipeif,
223 struct platform_device *pdev);
224int vpfe_ipipeif_register_entities(struct vpfe_ipipeif_device *ipipeif,
225 struct v4l2_device *vdev);
226void vpfe_ipipeif_unregister_entities(struct vpfe_ipipeif_device *ipipeif);
227
228#endif
229
