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19#ifndef _DAVINCI_VPFE_DM365_RESIZER_H
20#define _DAVINCI_VPFE_DM365_RESIZER_H
21
22enum resizer_oper_mode {
23 RESIZER_MODE_CONTINUOUS = 0,
24 RESIZER_MODE_ONE_SHOT = 1,
25};
26
27struct f_div_pass {
28 unsigned int o_hsz;
29 unsigned int i_hps;
30 unsigned int h_phs;
31 unsigned int src_hps;
32 unsigned int src_hsz;
33};
34
35#define MAX_PASSES 2
36
37struct f_div_param {
38 unsigned char en;
39 unsigned int num_passes;
40 struct f_div_pass pass[MAX_PASSES];
41};
42
43
44struct resizer_scale_param {
45 bool h_flip;
46 bool v_flip;
47 bool cen;
48 bool yen;
49 unsigned short i_vps;
50 unsigned short i_hps;
51 unsigned short o_vsz;
52 unsigned short o_hsz;
53 unsigned short v_phs_y;
54 unsigned short v_phs_c;
55 unsigned short v_dif;
56
57 enum vpfe_rsz_intp_t v_typ_y;
58
59 enum vpfe_rsz_intp_t v_typ_c;
60
61 unsigned char v_lpf_int_y;
62
63 unsigned char v_lpf_int_c;
64 unsigned short h_phs;
65 unsigned short h_dif;
66
67 enum vpfe_rsz_intp_t h_typ_y;
68
69 enum vpfe_rsz_intp_t h_typ_c;
70
71 unsigned char h_lpf_int_y;
72
73 unsigned char h_lpf_int_c;
74 bool dscale_en;
75 enum vpfe_rsz_down_scale_ave_sz h_dscale_ave_sz;
76 enum vpfe_rsz_down_scale_ave_sz v_dscale_ave_sz;
77
78 struct f_div_param f_div;
79};
80
81enum resizer_rgb_t {
82 OUTPUT_32BIT,
83 OUTPUT_16BIT
84};
85
86enum resizer_rgb_msk_t {
87 NOMASK = 0,
88 MASKLAST2 = 1,
89};
90
91
92struct resizer_rgb {
93 bool rgb_en;
94 enum resizer_rgb_t rgb_typ;
95 enum resizer_rgb_msk_t rgb_msk0;
96 enum resizer_rgb_msk_t rgb_msk1;
97 unsigned int rgb_alpha_val;
98};
99
100
101struct rsz_ext_mem_param {
102 unsigned int rsz_sdr_oft_y;
103 unsigned int rsz_sdr_ptr_s_y;
104 unsigned int rsz_sdr_ptr_e_y;
105 unsigned int rsz_sdr_oft_c;
106 unsigned int rsz_sdr_ptr_s_c;
107 unsigned int rsz_sdr_ptr_e_c;
108
109 unsigned int flip_ofst_y;
110
111 unsigned int flip_ofst_c;
112
113 unsigned int c_offset;
114
115 unsigned int user_y_ofst;
116
117 unsigned int user_c_ofst;
118};
119
120enum rsz_data_source {
121 IPIPE_DATA,
122 IPIPEIF_DATA
123};
124
125enum rsz_src_img_fmt {
126 RSZ_IMG_422,
127 RSZ_IMG_420
128};
129
130enum rsz_dpaths_bypass_t {
131 BYPASS_OFF = 0,
132 BYPASS_ON = 1,
133};
134
135struct rsz_common_params {
136 unsigned int vps;
137 unsigned int vsz;
138 unsigned int hps;
139 unsigned int hsz;
140
141 enum rsz_src_img_fmt src_img_fmt;
142
143 unsigned char y_c;
144
145 unsigned char raw_flip;
146
147 enum rsz_data_source source;
148 enum rsz_dpaths_bypass_t passthrough;
149 unsigned char yuv_y_min;
150 unsigned char yuv_y_max;
151 unsigned char yuv_c_min;
152 unsigned char yuv_c_max;
153 bool rsz_seq_crv;
154 enum vpfe_chr_pos out_chr_pos;
155};
156
157struct resizer_params {
158 enum resizer_oper_mode oper_mode;
159 struct rsz_common_params rsz_common;
160 struct resizer_scale_param rsz_rsc_param[2];
161 struct resizer_rgb rsz2rgb[2];
162 struct rsz_ext_mem_param ext_mem_param[2];
163 bool rsz_en[2];
164 struct vpfe_rsz_config_params user_config;
165};
166
167#define ENABLE 1
168#define DISABLE (!ENABLE)
169
170#define RESIZER_CROP_PAD_SINK 0
171#define RESIZER_CROP_PAD_SOURCE 1
172#define RESIZER_CROP_PAD_SOURCE2 2
173
174#define RESIZER_CROP_PADS_NUM 3
175
176enum resizer_crop_input_entity {
177 RESIZER_CROP_INPUT_NONE = 0,
178 RESIZER_CROP_INPUT_IPIPEIF = 1,
179 RESIZER_CROP_INPUT_IPIPE = 2,
180};
181
182enum resizer_crop_output_entity {
183 RESIZER_CROP_OUTPUT_NONE,
184 RESIZER_A,
185 RESIZER_B,
186};
187
188struct dm365_crop_resizer_device {
189 struct v4l2_subdev subdev;
190 struct media_pad pads[RESIZER_CROP_PADS_NUM];
191 struct v4l2_mbus_framefmt formats[RESIZER_CROP_PADS_NUM];
192 enum resizer_crop_input_entity input;
193 enum resizer_crop_output_entity output;
194 enum resizer_crop_output_entity output2;
195 struct vpfe_resizer_device *rsz_device;
196};
197
198#define RESIZER_PAD_SINK 0
199#define RESIZER_PAD_SOURCE 1
200
201#define RESIZER_PADS_NUM 2
202
203enum resizer_input_entity {
204 RESIZER_INPUT_NONE = 0,
205 RESIZER_INPUT_CROP_RESIZER = 1,
206};
207
208enum resizer_output_entity {
209 RESIZER_OUTPUT_NONE = 0,
210 RESIZER_OUTPUT_MEMORY = 1,
211};
212
213struct dm365_resizer_device {
214 struct v4l2_subdev subdev;
215 struct media_pad pads[RESIZER_PADS_NUM];
216 struct v4l2_mbus_framefmt formats[RESIZER_PADS_NUM];
217 enum resizer_input_entity input;
218 enum resizer_output_entity output;
219 struct vpfe_video_device video_out;
220 struct vpfe_resizer_device *rsz_device;
221};
222
223struct vpfe_resizer_device {
224 struct dm365_crop_resizer_device crop_resizer;
225 struct dm365_resizer_device resizer_a;
226 struct dm365_resizer_device resizer_b;
227 struct resizer_params config;
228 void __iomem *base_addr;
229};
230
231int vpfe_resizer_init(struct vpfe_resizer_device *vpfe_rsz,
232 struct platform_device *pdev);
233int vpfe_resizer_register_entities(struct vpfe_resizer_device *vpfe_rsz,
234 struct v4l2_device *v4l2_dev);
235void vpfe_resizer_unregister_entities(struct vpfe_resizer_device *vpfe_rsz);
236void vpfe_resizer_cleanup(struct vpfe_resizer_device *vpfe_rsz,
237 struct platform_device *pdev);
238void vpfe_resizer_buffer_isr(struct vpfe_resizer_device *resizer);
239void vpfe_resizer_dma_isr(struct vpfe_resizer_device *resizer);
240
241#endif
242
