LXR linux/drivers/staging/media/ipu3/ipu3.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (C) 2018 Intel Corporation */
   3
   4#ifndef __IPU3_H
   5#define __IPU3_H
   6
   7#include <linux/iova.h>
   8#include <linux/pci.h>
   9
  10#include <media/v4l2-ctrls.h>
  11#include <media/v4l2-device.h>
  12#include <media/videobuf2-dma-sg.h>
  13
  14#include "ipu3-css.h"
  15
  16#define IMGU_NAME                       "ipu3-imgu"
  17
  18/*
  19 * The semantics of the driver is that whenever there is a buffer available in
  20 * master queue, the driver queues a buffer also to all other active nodes.
  21 * If user space hasn't provided a buffer to all other video nodes first,
  22 * the driver gets an internal dummy buffer and queues it.
  23 */
  24#define IMGU_QUEUE_MASTER               IPU3_CSS_QUEUE_IN
  25#define IMGU_QUEUE_FIRST_INPUT          IPU3_CSS_QUEUE_OUT
  26#define IMGU_MAX_QUEUE_DEPTH            (2 + 2)
  27
  28#define IMGU_NODE_IN                    0 /* Input RAW image */
  29#define IMGU_NODE_PARAMS                1 /* Input parameters */
  30#define IMGU_NODE_OUT                   2 /* Main output for still or video */
  31#define IMGU_NODE_VF                    3 /* Preview */
  32#define IMGU_NODE_STAT_3A               4 /* 3A statistics */
  33#define IMGU_NODE_NUM                   5
  34
  35#define file_to_intel_imgu_node(__file) \
  36        container_of(video_devdata(__file), struct imgu_video_device, vdev)
  37
  38#define IPU3_INPUT_MIN_WIDTH            0U
  39#define IPU3_INPUT_MIN_HEIGHT           0U
  40#define IPU3_INPUT_MAX_WIDTH            5120U
  41#define IPU3_INPUT_MAX_HEIGHT           38404U
  42#define IPU3_OUTPUT_MIN_WIDTH           2U
  43#define IPU3_OUTPUT_MIN_HEIGHT          2U
  44#define IPU3_OUTPUT_MAX_WIDTH           4480U
  45#define IPU3_OUTPUT_MAX_HEIGHT          34004U
  46
  47struct imgu_vb2_buffer {
  48        /* Public fields */
  49        struct vb2_v4l2_buffer vbb;     /* Must be the first field */
  50
  51        /* Private fields */
  52        struct list_head list;
  53};
  54
  55struct imgu_buffer {
  56        struct imgu_vb2_buffer vid_buf; /* Must be the first field */
  57        struct imgu_css_buffer css_buf;
  58        struct imgu_css_map map;
  59};
  60
  61struct imgu_node_mapping {
  62        unsigned int css_queue;
  63        const char *name;
  64};
  65
  66/**
  67 * struct imgu_video_device
  68 * each node registers as video device and maintains its
  69 * own vb2_queue.
  70 */
  71struct imgu_video_device {
  72        const char *name;
  73        bool output;
  74        bool enabled;
  75        struct v4l2_format vdev_fmt;    /* Currently set format */
  76
  77        /* Private fields */
  78        struct video_device vdev;
  79        struct media_pad vdev_pad;
  80        struct v4l2_mbus_framefmt pad_fmt;
  81        struct vb2_queue vbq;
  82        struct list_head buffers;
  83        /* Protect vb2_queue and vdev structs*/
  84        struct mutex lock;
  85        atomic_t sequence;
  86        unsigned int id;
  87        unsigned int pipe;
  88};
  89
  90struct imgu_v4l2_subdev {
  91        unsigned int pipe;
  92        struct v4l2_subdev subdev;
  93        struct media_pad subdev_pads[IMGU_NODE_NUM];
  94        struct {
  95                struct v4l2_rect eff; /* effective resolution */
  96                struct v4l2_rect bds; /* bayer-domain scaled resolution*/
  97                struct v4l2_rect gdc; /* gdc output resolution */
  98        } rect;
  99        struct v4l2_ctrl_handler ctrl_handler;
 100        struct v4l2_ctrl *ctrl;
 101        atomic_t running_mode;
 102        bool active;
 103};
 104
 105struct imgu_media_pipe {
 106        unsigned int pipe;
 107
 108        /* Internally enabled queues */
 109        struct {
 110                struct imgu_css_map dmap;
 111                struct imgu_css_buffer dummybufs[IMGU_MAX_QUEUE_DEPTH];
 112        } queues[IPU3_CSS_QUEUES];
 113        struct imgu_video_device nodes[IMGU_NODE_NUM];
 114        bool queue_enabled[IMGU_NODE_NUM];
 115        struct media_pipeline pipeline;
 116        struct imgu_v4l2_subdev imgu_sd;
 117};
 118
 119/*
 120 * imgu_device -- ImgU (Imaging Unit) driver
 121 */
 122struct imgu_device {
 123        struct pci_dev *pci_dev;
 124        void __iomem *base;
 125
 126        /* Public fields, fill before registering */
 127        unsigned int buf_struct_size;
 128        bool streaming;         /* Public read only */
 129
 130        struct imgu_media_pipe imgu_pipe[IMGU_MAX_PIPE_NUM];
 131
 132        /* Private fields */
 133        struct v4l2_device v4l2_dev;
 134        struct media_device media_dev;
 135        struct v4l2_file_operations v4l2_file_ops;
 136
 137        /* MMU driver for css */
 138        struct imgu_mmu_info *mmu;
 139        struct iova_domain iova_domain;
 140
 141        /* css - Camera Sub-System */
 142        struct imgu_css css;
 143
 144        /*
 145         * Coarse-grained lock to protect
 146         * vid_buf.list and css->queue
 147         */
 148        struct mutex lock;
 149        /* Forbid streaming and buffer queuing during system suspend. */
 150        atomic_t qbuf_barrier;
 151        /* Indicate if system suspend take place while imgu is streaming. */
 152        bool suspend_in_stream;
 153        /* Used to wait for FW buffer queue drain. */
 154        wait_queue_head_t buf_drain_wq;
 155};
 156
 157unsigned int imgu_node_to_queue(unsigned int node);
 158unsigned int imgu_map_node(struct imgu_device *imgu, unsigned int css_queue);
 159int imgu_queue_buffers(struct imgu_device *imgu, bool initial,
 160                       unsigned int pipe);
 161
 162int imgu_v4l2_register(struct imgu_device *dev);
 163int imgu_v4l2_unregister(struct imgu_device *dev);
 164void imgu_v4l2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state);
 165
 166int imgu_s_stream(struct imgu_device *imgu, int enable);
 167
 168#endif
 169