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7#include "rtl_core.h"
8#include "r8192E_phyreg.h"
9#include "r8192E_phy.h"
10#include "r8190P_rtl8256.h"
11
12void rtl92e_set_bandwidth(struct net_device *dev,
13 enum ht_channel_width Bandwidth)
14{
15 u8 eRFPath;
16 struct r8192_priv *priv = rtllib_priv(dev);
17
18 if (priv->card_8192_version != VERSION_8190_BD &&
19 priv->card_8192_version != VERSION_8190_BE) {
20 netdev_warn(dev, "%s(): Unknown HW version.\n", __func__);
21 return;
22 }
23
24 for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
25 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
26 continue;
27
28 switch (Bandwidth) {
29 case HT_CHANNEL_WIDTH_20:
30 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
31 0x0b, bMask12Bits, 0x100);
32 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
33 0x2c, bMask12Bits, 0x3d7);
34 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
35 0x0e, bMask12Bits, 0x021);
36 break;
37 case HT_CHANNEL_WIDTH_20_40:
38 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
39 0x0b, bMask12Bits, 0x300);
40 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
41 0x2c, bMask12Bits, 0x3ff);
42 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
43 0x0e, bMask12Bits, 0x0e1);
44 break;
45 default:
46 netdev_err(dev, "%s(): Unknown bandwidth: %#X\n",
47 __func__, Bandwidth);
48 break;
49
50 }
51 }
52}
53
54bool rtl92e_config_rf(struct net_device *dev)
55{
56 u32 u4RegValue = 0;
57 u8 eRFPath;
58 bool rtStatus = true;
59 struct bb_reg_definition *pPhyReg;
60 struct r8192_priv *priv = rtllib_priv(dev);
61 u32 RegOffSetToBeCheck = 0x3;
62 u32 RegValueToBeCheck = 0x7f1;
63 u32 RF3_Final_Value = 0;
64 u8 ConstRetryTimes = 5, RetryTimes = 5;
65 u8 ret = 0;
66
67 priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
68
69 for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
70 eRFPath < priv->NumTotalRFPath; eRFPath++) {
71 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
72 continue;
73
74 pPhyReg = &priv->PHYRegDef[eRFPath];
75
76
77 switch (eRFPath) {
78 case RF90_PATH_A:
79 case RF90_PATH_C:
80 u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
81 bRFSI_RFENV);
82 break;
83 case RF90_PATH_B:
84 case RF90_PATH_D:
85 u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
86 bRFSI_RFENV<<16);
87 break;
88 }
89
90 rtl92e_set_bb_reg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
91
92 rtl92e_set_bb_reg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
93
94 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
95 b3WireAddressLength, 0x0);
96 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
97 b3WireDataLength, 0x0);
98
99 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0,
100 bMask12Bits, 0xbf);
101
102 rtStatus = rtl92e_check_bb_and_rf(dev, HW90_BLOCK_RF,
103 (enum rf90_radio_path)eRFPath);
104 if (!rtStatus) {
105 netdev_err(dev, "%s(): Failed to check RF Path %d.\n",
106 __func__, eRFPath);
107 goto fail;
108 }
109
110 RetryTimes = ConstRetryTimes;
111 RF3_Final_Value = 0;
112 while (RF3_Final_Value != RegValueToBeCheck &&
113 RetryTimes != 0) {
114 ret = rtl92e_config_rf_path(dev,
115 (enum rf90_radio_path)eRFPath);
116 RF3_Final_Value = rtl92e_get_rf_reg(dev,
117 (enum rf90_radio_path)eRFPath,
118 RegOffSetToBeCheck,
119 bMask12Bits);
120 RT_TRACE(COMP_RF,
121 "RF %d %d register final value: %x\n",
122 eRFPath, RegOffSetToBeCheck,
123 RF3_Final_Value);
124 RetryTimes--;
125 }
126
127 switch (eRFPath) {
128 case RF90_PATH_A:
129 case RF90_PATH_C:
130 rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
131 u4RegValue);
132 break;
133 case RF90_PATH_B:
134 case RF90_PATH_D:
135 rtl92e_set_bb_reg(dev, pPhyReg->rfintfs,
136 bRFSI_RFENV<<16, u4RegValue);
137 break;
138 }
139
140 if (ret) {
141 netdev_err(dev,
142 "%s(): Failed to initialize RF Path %d.\n",
143 __func__, eRFPath);
144 goto fail;
145 }
146
147 }
148
149 RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
150 return true;
151
152fail:
153 return false;
154}
155
156void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel)
157{
158 u32 TxAGC = 0;
159 struct r8192_priv *priv = rtllib_priv(dev);
160
161 TxAGC = powerlevel;
162 if (priv->bDynamicTxLowPower) {
163 if (priv->CustomerID == RT_CID_819x_Netcore)
164 TxAGC = 0x22;
165 else
166 TxAGC += priv->CckPwEnl;
167 }
168 if (TxAGC > 0x24)
169 TxAGC = 0x24;
170 rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
171}
172
173
174void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
175{
176 struct r8192_priv *priv = rtllib_priv(dev);
177 u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
178 u8 index = 0;
179 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
180 u8 byte0, byte1, byte2, byte3;
181
182 powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
183 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
184 (powerBase0 << 8) | powerBase0;
185 powerBase1 = powerlevel;
186 powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) |
187 (powerBase1 << 8) | powerBase1;
188
189 for (index = 0; index < 6; index++) {
190 writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] +
191 ((index < 2) ? powerBase0 : powerBase1));
192 byte0 = (u8)(writeVal & 0x7f);
193 byte1 = (u8)((writeVal & 0x7f00)>>8);
194 byte2 = (u8)((writeVal & 0x7f0000)>>16);
195 byte3 = (u8)((writeVal & 0x7f000000)>>24);
196 if (byte0 > 0x24)
197 byte0 = 0x24;
198 if (byte1 > 0x24)
199 byte1 = 0x24;
200 if (byte2 > 0x24)
201 byte2 = 0x24;
202 if (byte3 > 0x24)
203 byte3 = 0x24;
204
205 if (index == 3) {
206 writeVal_tmp = (byte3 << 24) | (byte2 << 16) |
207 (byte1 << 8) | byte0;
208 priv->Pwr_Track = writeVal_tmp;
209 }
210
211 if (priv->bDynamicTxHighPower)
212 writeVal = 0x03030303;
213 else
214 writeVal = (byte3 << 24) | (byte2 << 16) |
215 (byte1 << 8) | byte0;
216 rtl92e_set_bb_reg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
217 }
218
219}
220
