LXR linux/drivers/staging/rtl8712/rtl871x

   1// SPDX-License-Identifier: GPL-2.0
   2/******************************************************************************
   3 *
   4 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
   5 *
   6 * Modifications for inclusion into the Linux staging tree are
   7 * Copyright(c) 2010 Larry Finger. All rights reserved.
   8 *
   9 * Contact information:
  10 * WLAN FAE <wlanfae@realtek.com>
  11 * Larry Finger <Larry.Finger@lwfinger.net>
  12 *
  13 ******************************************************************************/
  14#define _RTL871X_MP_C_
  15
  16#include "osdep_service.h"
  17#include "drv_types.h"
  18#include "rtl871x_mp_phy_regdef.h"
  19#include "rtl8712_cmd.h"
  20
  21static void _init_mp_priv_(struct mp_priv *pmp_priv)
  22{
  23        pmp_priv->mode = _LOOPBOOK_MODE_;
  24        pmp_priv->curr_ch = 1;
  25        pmp_priv->curr_modem = MIXED_PHY;
  26        pmp_priv->curr_rateidx = 0;
  27        pmp_priv->curr_txpoweridx = 0x14;
  28        pmp_priv->antenna_tx = ANTENNA_A;
  29        pmp_priv->antenna_rx = ANTENNA_AB;
  30        pmp_priv->check_mp_pkt = 0;
  31        pmp_priv->tx_pktcount = 0;
  32        pmp_priv->rx_pktcount = 0;
  33        pmp_priv->rx_crcerrpktcount = 0;
  34}
  35
  36static int init_mp_priv(struct mp_priv *pmp_priv)
  37{
  38        int i, res;
  39        struct mp_xmit_frame *pmp_xmitframe;
  40
  41        _init_mp_priv_(pmp_priv);
  42        _init_queue(&pmp_priv->free_mp_xmitqueue);
  43        pmp_priv->pallocated_mp_xmitframe_buf = NULL;
  44        pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME *
  45                                sizeof(struct mp_xmit_frame) + 4,
  46                                GFP_ATOMIC);
  47        if (!pmp_priv->pallocated_mp_xmitframe_buf) {
  48                res = _FAIL;
  49                goto _exit_init_mp_priv;
  50        }
  51        pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
  52                         4 -
  53                         ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
  54        pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
  55        for (i = 0; i < NR_MP_XMITFRAME; i++) {
  56                INIT_LIST_HEAD(&(pmp_xmitframe->list));
  57                list_add_tail(&(pmp_xmitframe->list),
  58                                 &(pmp_priv->free_mp_xmitqueue.queue));
  59                pmp_xmitframe->pkt = NULL;
  60                pmp_xmitframe->frame_tag = MP_FRAMETAG;
  61                pmp_xmitframe->padapter = pmp_priv->papdater;
  62                pmp_xmitframe++;
  63        }
  64        pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
  65        res = _SUCCESS;
  66_exit_init_mp_priv:
  67        return res;
  68}
  69
  70static int free_mp_priv(struct mp_priv *pmp_priv)
  71{
  72        kfree(pmp_priv->pallocated_mp_xmitframe_buf);
  73        return 0;
  74}
  75
  76void mp871xinit(struct _adapter *padapter)
  77{
  78        struct mp_priv *pmppriv = &padapter->mppriv;
  79
  80        pmppriv->papdater = padapter;
  81        init_mp_priv(pmppriv);
  82}
  83
  84void mp871xdeinit(struct _adapter *padapter)
  85{
  86        struct mp_priv *pmppriv = &padapter->mppriv;
  87
  88        free_mp_priv(pmppriv);
  89}
  90
  91/*
  92 * Special for bb and rf reg read/write
  93 */
  94static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
  95{
  96        u32 cmd32 = 0, val32 = 0;
  97        u8 iocmd_class  = iocmd.cmdclass;
  98        u16 iocmd_value = iocmd.value;
  99        u8 iocmd_idx    = iocmd.index;
 100
 101        cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
 102        if (r8712_fw_cmd(pAdapter, cmd32))
 103                r8712_fw_cmd_data(pAdapter, &val32, 1);
 104        else
 105                val32 = 0;
 106        return val32;
 107}
 108
 109static u8 fw_iocmd_write(struct _adapter *pAdapter,
 110                         struct IOCMD_STRUCT iocmd, u32 value)
 111{
 112        u32 cmd32 = 0;
 113        u8 iocmd_class  = iocmd.cmdclass;
 114        u32 iocmd_value = iocmd.value;
 115        u8 iocmd_idx    = iocmd.index;
 116
 117        r8712_fw_cmd_data(pAdapter, &value, 0);
 118        msleep(100);
 119        cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
 120        return r8712_fw_cmd(pAdapter, cmd32);
 121}
 122
 123/* offset : 0X800~0XFFF */
 124u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
 125{
 126        u8 shift = offset & 0x0003;     /* 4 byte access */
 127        u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 128        u32 bb_val = 0;
 129        struct IOCMD_STRUCT iocmd;
 130
 131        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 132        iocmd.value     = bb_addr;
 133        iocmd.index     = IOCMD_BB_READ_IDX;
 134        bb_val = fw_iocmd_read(pAdapter, iocmd);
 135        if (shift != 0) {
 136                u32 bb_val2 = 0;
 137
 138                bb_val >>= (shift * 8);
 139                iocmd.value += 4;
 140                bb_val2 = fw_iocmd_read(pAdapter, iocmd);
 141                bb_val2 <<= ((4 - shift) * 8);
 142                bb_val |= bb_val2;
 143        }
 144        return bb_val;
 145}
 146
 147/* offset : 0X800~0XFFF */
 148u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
 149{
 150        u8 shift = offset & 0x0003;     /* 4 byte access */
 151        u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 152        struct IOCMD_STRUCT iocmd;
 153
 154        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 155        iocmd.value     = bb_addr;
 156        iocmd.index     = IOCMD_BB_WRITE_IDX;
 157        if (shift != 0) {
 158                u32 oldValue = 0;
 159                u32 newValue = value;
 160
 161                oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 162                oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
 163                value = oldValue | (newValue << (shift * 8));
 164                if (!fw_iocmd_write(pAdapter, iocmd, value))
 165                        return false;
 166                iocmd.value += 4;
 167                oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 168                oldValue &= (0xFFFFFFFF << (shift * 8));
 169                value = oldValue | (newValue >> ((4 - shift) * 8));
 170        }
 171        return fw_iocmd_write(pAdapter, iocmd, value);
 172}
 173
 174/* offset : 0x00 ~ 0xFF */
 175u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
 176{
 177        u16 rf_addr = (path << 8) | offset;
 178        struct IOCMD_STRUCT iocmd;
 179
 180        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 181        iocmd.value     = rf_addr;
 182        iocmd.index     = IOCMD_RF_READ_IDX;
 183        return fw_iocmd_read(pAdapter, iocmd);
 184}
 185
 186u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
 187{
 188        u16 rf_addr = (path << 8) | offset;
 189        struct IOCMD_STRUCT iocmd;
 190
 191        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 192        iocmd.value     = rf_addr;
 193        iocmd.index     = IOCMD_RF_WRIT_IDX;
 194        return fw_iocmd_write(pAdapter, iocmd, value);
 195}
 196
 197static u32 bitshift(u32 bitmask)
 198{
 199        u32 i;
 200
 201        for (i = 0; i <= 31; i++)
 202                if (((bitmask >> i) &  0x1) == 1)
 203                        break;
 204        return i;
 205}
 206
 207static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
 208{
 209        u32 org_value, bit_shift;
 210
 211        org_value = r8712_bb_reg_read(pAdapter, offset);
 212        bit_shift = bitshift(bitmask);
 213        return (org_value & bitmask) >> bit_shift;
 214}
 215
 216static u8 set_bb_reg(struct _adapter *pAdapter,
 217                     u16 offset,
 218                     u32 bitmask,
 219                     u32 value)
 220{
 221        u32 org_value, bit_shift, new_value;
 222
 223        if (bitmask != bMaskDWord) {
 224                org_value = r8712_bb_reg_read(pAdapter, offset);
 225                bit_shift = bitshift(bitmask);
 226                new_value = (org_value & (~bitmask)) | (value << bit_shift);
 227        } else {
 228                new_value = value;
 229        }
 230        return r8712_bb_reg_write(pAdapter, offset, new_value);
 231}
 232
 233static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
 234                      u32 bitmask)
 235{
 236        u32 org_value, bit_shift;
 237
 238        org_value = r8712_rf_reg_read(pAdapter, path, offset);
 239        bit_shift = bitshift(bitmask);
 240        return (org_value & bitmask) >> bit_shift;
 241}
 242
 243static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
 244              u32 value)
 245{
 246        u32 org_value, bit_shift, new_value;
 247
 248        if (bitmask != bMaskDWord) {
 249                org_value = r8712_rf_reg_read(pAdapter, path, offset);
 250                bit_shift = bitshift(bitmask);
 251                new_value = (org_value & (~bitmask)) | (value << bit_shift);
 252        } else {
 253                new_value = value;
 254        }
 255        return r8712_rf_reg_write(pAdapter, path, offset, new_value);
 256}
 257
 258/*
 259 * SetChannel
 260 * Description
 261 *      Use H2C command to change channel,
 262 *      not only modify rf register, but also other setting need to be done.
 263 */
 264void r8712_SetChannel(struct _adapter *pAdapter)
 265{
 266        struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
 267        struct cmd_obj *pcmd = NULL;
 268        struct SetChannel_parm *pparm = NULL;
 269        u16 code = GEN_CMD_CODE(_SetChannel);
 270
 271        pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC);
 272        if (!pcmd)
 273                return;
 274        pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC);
 275        if (!pparm) {
 276                kfree(pcmd);
 277                return;
 278        }
 279        pparm->curr_ch = pAdapter->mppriv.curr_ch;
 280        init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
 281        r8712_enqueue_cmd(pcmdpriv, pcmd);
 282}
 283
 284static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
 285{
 286        u16 TxAGC = 0;
 287
 288        TxAGC = TxPower;
 289        set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 290}
 291
 292static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
 293{
 294        u32 TxAGC = 0;
 295
 296        TxAGC |= ((TxPower << 24) | (TxPower << 16) | (TxPower << 8) |
 297                  TxPower);
 298        set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
 299        set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
 300        set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
 301        set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
 302        set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
 303        set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
 304}
 305
 306void r8712_SetTxPower(struct _adapter *pAdapter)
 307{
 308        u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
 309
 310        SetCCKTxPower(pAdapter, TxPower);
 311        SetOFDMTxPower(pAdapter, TxPower);
 312}
 313
 314void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
 315{
 316        u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
 317
 318        TxAGCOffset_B = ulTxAGCOffset & 0x000000ff;
 319        TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00) >> 8;
 320        TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000) >> 16;
 321        tmpAGC = TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B;
 322        set_bb_reg(pAdapter, rFPGA0_TxGainStage,
 323                        (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
 324}
 325
 326void r8712_SetDataRate(struct _adapter *pAdapter)
 327{
 328        u8 path = RF_PATH_A;
 329        u8 offset = RF_SYN_G2;
 330        u32 value;
 331
 332        value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
 333        r8712_rf_reg_write(pAdapter, path, offset, value);
 334}
 335
 336void r8712_SwitchBandwidth(struct _adapter *pAdapter)
 337{
 338        /* 3 1.Set MAC register : BWOPMODE  bit2:1 20MhzBW */
 339        u8 regBwOpMode = 0;
 340        u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
 341
 342        regBwOpMode = r8712_read8(pAdapter, 0x10250203);
 343        if (Bandwidth == HT_CHANNEL_WIDTH_20)
 344                regBwOpMode |= BIT(2);
 345        else
 346                regBwOpMode &= ~(BIT(2));
 347        r8712_write8(pAdapter, 0x10250203, regBwOpMode);
 348        /* 3 2.Set PHY related register */
 349        switch (Bandwidth) {
 350        /* 20 MHz channel*/
 351        case HT_CHANNEL_WIDTH_20:
 352                set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
 353                set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
 354                /* Use PHY_REG.txt default value. Do not need to change.
 355                 * Correct the tx power for CCK rate in 40M.
 356                 * It is set in Tx descriptor for 8192x series
 357                 */
 358                set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
 359                break;
 360        /* 40 MHz channel*/
 361        case HT_CHANNEL_WIDTH_40:
 362                set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
 363                set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
 364                /* Use PHY_REG.txt default value. Do not need to change.
 365                 * Correct the tx power for CCK rate in 40M.
 366                 * Set Control channel to upper or lower. These settings are
 367                 * required only for 40MHz
 368                 */
 369                set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
 370                           (HAL_PRIME_CHNL_OFFSET_DONT_CARE >> 1));
 371                set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
 372                           HAL_PRIME_CHNL_OFFSET_DONT_CARE);
 373                set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
 374                break;
 375        default:
 376                break;
 377        }
 378
 379        /* 3 3.Set RF related register */
 380        switch (Bandwidth) {
 381        case HT_CHANNEL_WIDTH_20:
 382                set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 383                           BIT(10) | BIT(11), 0x01);
 384                break;
 385        case HT_CHANNEL_WIDTH_40:
 386                set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 387                           BIT(10) | BIT(11), 0x00);
 388                break;
 389        default:
 390                break;
 391        }
 392}
 393/*------------------------------Define structure----------------------------*/
 394struct R_ANTENNA_SELECT_OFDM {
 395        u32     r_tx_antenna:4;
 396        u32     r_ant_l:4;
 397        u32     r_ant_non_ht:4;
 398        u32     r_ant_ht1:4;
 399        u32     r_ant_ht2:4;
 400        u32     r_ant_ht_s1:4;
 401        u32     r_ant_non_ht_s1:4;
 402        u32     OFDM_TXSC:2;
 403        u32     Reserved:2;
 404};
 405
 406struct R_ANTENNA_SELECT_CCK {
 407        u8      r_cckrx_enable_2:2;
 408        u8      r_cckrx_enable:2;
 409        u8      r_ccktx_enable:4;
 410};
 411
 412void r8712_SwitchAntenna(struct _adapter *pAdapter)
 413{
 414        u32     ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
 415        u8      ofdm_rx_ant_sel_val = 0;
 416        u8      cck_ant_select_val = 0;
 417        u32     cck_ant_sel_val = 0;
 418        struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
 419
 420        p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
 421
 422        switch (pAdapter->mppriv.antenna_tx) {
 423        case ANTENNA_A:
 424                /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
 425                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 426                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
 427                ofdm_tx_en_val = 0x3;
 428                ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
 429                p_cck_txrx->r_ccktx_enable = 0x8;
 430                break;
 431        case ANTENNA_B:
 432                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
 433                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 434                ofdm_tx_en_val = 0x3;
 435                ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
 436                p_cck_txrx->r_ccktx_enable = 0x4;
 437                break;
 438        case ANTENNA_AB:        /* For 8192S */
 439                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 440                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 441                ofdm_tx_en_val = 0x3;
 442                ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
 443                p_cck_txrx->r_ccktx_enable = 0xC;
 444                break;
 445        default:
 446                break;
 447        }
 448        /*OFDM Tx*/
 449        set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
 450        /*OFDM Tx*/
 451        set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
 452        switch (pAdapter->mppriv.antenna_rx) {
 453        case ANTENNA_A:
 454                ofdm_rx_ant_sel_val = 0x1;      /* A */
 455                p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
 456                p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
 457                break;
 458        case ANTENNA_B:
 459                ofdm_rx_ant_sel_val = 0x2;      /* B */
 460                p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
 461                p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
 462                break;
 463        case ANTENNA_AB:
 464                ofdm_rx_ant_sel_val = 0x3; /* AB */
 465                p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
 466                p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
 467                break;
 468        default:
 469                break;
 470        }
 471        /*OFDM Rx*/
 472        set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
 473                   ofdm_rx_ant_sel_val);
 474        /*OFDM Rx*/
 475        set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
 476                   ofdm_rx_ant_sel_val);
 477
 478        cck_ant_sel_val = cck_ant_select_val;
 479        /*CCK TxRx*/
 480        set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
 481}
 482
 483static void TriggerRFThermalMeter(struct _adapter *pAdapter)
 484{
 485        /* 0x24: RF Reg[6:5] */
 486        set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
 487}
 488
 489static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
 490{
 491        /* 0x24: RF Reg[4:0] */
 492        return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
 493}
 494
 495void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
 496{
 497        TriggerRFThermalMeter(pAdapter);
 498        msleep(1000);
 499        *value = ReadRFThermalMeter(pAdapter);
 500}
 501
 502void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
 503{
 504        if (bStart) { /* Start Single Carrier. */
 505                /* 1. if OFDM block on? */
 506                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 507                        /*set OFDM block on*/
 508                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 509                /* 2. set CCK test mode off, set to CCK normal mode */
 510                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 511                /* 3. turn on scramble setting */
 512                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 513                /* 4. Turn On Single Carrier Tx and off the other test modes. */
 514                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 515                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
 516                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 517        } else { /* Stop Single Carrier.*/
 518                /* Turn off all test modes.*/
 519                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 520                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 521                           bDisable);
 522                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 523                msleep(20);
 524                /*BB Reset*/
 525                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 526                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 527        }
 528}
 529
 530void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
 531{
 532        u8 rfPath;
 533
 534        switch (pAdapter->mppriv.antenna_tx) {
 535        case ANTENNA_B:
 536                rfPath = RF_PATH_B;
 537                break;
 538        case ANTENNA_A:
 539        default:
 540                rfPath = RF_PATH_A;
 541                break;
 542        }
 543        if (bStart) { /* Start Single Tone.*/
 544                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
 545                set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
 546                set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 547                           0xd4000);
 548                msleep(100);
 549                /* PAD all on.*/
 550                set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
 551                msleep(100);
 552        } else { /* Stop Single Tone.*/
 553                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 554                set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 555                set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 556                           0x54000);
 557                msleep(100);
 558                /* PAD all on.*/
 559                set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
 560                msleep(100);
 561        }
 562}
 563
 564void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
 565{
 566        if (bStart) { /* Start Carrier Suppression.*/
 567                if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 568                        /* 1. if CCK block on? */
 569                        if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 570                                /*set CCK block on*/
 571                                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
 572                                           bEnable);
 573                        }
 574                        /* Turn Off All Test Mode */
 575                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
 576                                   bDisable);
 577                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 578                                   bDisable);
 579                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
 580                                   bDisable);
 581                        /*transmit mode*/
 582                        set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 583                        /*turn off scramble setting*/
 584                        set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 585                                   bDisable);
 586                        /*Set CCK Tx Test Rate*/
 587                        /*Set FTxRate to 1Mbps*/
 588                        set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
 589                }
 590        } else { /* Stop Carrier Suppression. */
 591                if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 592                        /*normal mode*/
 593                        set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 594                        /*turn on scramble setting*/
 595                        set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 596                                   bEnable);
 597                        /*BB Reset*/
 598                        set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 599                        set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 600                }
 601        }
 602}
 603
 604static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
 605{
 606        u32 cckrate;
 607
 608        if (bStart) {
 609                /* 1. if CCK block on? */
 610                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 611                        /*set CCK block on*/
 612                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 613                }
 614                /* Turn Off All Test Mode */
 615                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 616                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 617                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 618                /*Set CCK Tx Test Rate*/
 619                cckrate  = pAdapter->mppriv.curr_rateidx;
 620                set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
 621                /*transmit mode*/
 622                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 623                /*turn on scramble setting*/
 624                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 625        } else {
 626                /*normal mode*/
 627                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 628                /*turn on scramble setting*/
 629                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 630                /*BB Reset*/
 631                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 632                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 633        }
 634} /* mpt_StartCckContTx */
 635
 636static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
 637{
 638        if (bStart) {
 639                /* 1. if OFDM block on? */
 640                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
 641                        /*set OFDM block on*/
 642                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 643                }
 644                /* 2. set CCK test mode off, set to CCK normal mode*/
 645                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 646                /* 3. turn on scramble setting */
 647                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 648                /* 4. Turn On Continue Tx and turn off the other test modes.*/
 649                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
 650                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 651                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 652        } else {
 653                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 654                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 655                           bDisable);
 656                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 657                msleep(20);
 658                /*BB Reset*/
 659                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 660                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 661        }
 662} /* mpt_StartOfdmContTx */
 663
 664void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
 665{
 666        /* ADC turn off [bit24-21] adc port0 ~ port1 */
 667        if (bStart) {
 668                r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 669                                   r8712_bb_reg_read(pAdapter,
 670                                   rRx_Wait_CCCA) & 0xFE1FFFFF);
 671                msleep(100);
 672        }
 673        if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
 674                SetCCKContinuousTx(pAdapter, bStart);
 675        else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
 676                 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
 677                SetOFDMContinuousTx(pAdapter, bStart);
 678        /* ADC turn on [bit24-21] adc port0 ~ port1 */
 679        if (!bStart)
 680                r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 681                                   r8712_bb_reg_read(pAdapter,
 682                                   rRx_Wait_CCCA) | 0x01E00000);
 683}
 684
 685void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
 686{
 687        u32 i, phyrx_set = 0;
 688
 689        for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
 690                phyrx_set = 0;
 691                phyrx_set |= (i << 28);         /*select*/
 692                phyrx_set |= 0x08000000;        /* set counter to zero*/
 693                r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 694        }
 695}
 696
 697static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
 698{
 699        /*selection*/
 700        u32 phyrx_set = 0;
 701        u32 SelectBit;
 702
 703        SelectBit = selbit << 28;
 704        phyrx_set |= (SelectBit & 0xF0000000);
 705        r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 706        /*Read packet count*/
 707        return r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
 708}
 709
 710u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
 711{
 712        u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
 713        u32 CCK_cnt  = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
 714        u32 HT_cnt   = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
 715
 716        return OFDM_cnt + CCK_cnt + HT_cnt;
 717}
 718
 719u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
 720{
 721        u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
 722        u32 CCK_cnt  = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
 723        u32 HT_cnt   = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
 724
 725        return OFDM_cnt + CCK_cnt + HT_cnt;
 726}
 727